JP2013114116A - Liquid crystal control device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To achieve color display with an inexpensive configuration.SOLUTION: Binary display data in a frame buffer RAM 204 is sequentially acquired and is transmitted to one of N bits of each of RGB dots in a display RAM 5 by a port 2 (P2 207), and gradation data is outputted to a designated display area by a port 3 (P3 208), and data is inputted to one of N bits of each pixel different from pixels to which binary display data is transmitted by the port 2, whereby color display can be performed in accordance with set values in a gradation conversion table and thus color display is achieved with an inexpensive configuration where ROM and RAM capacities are reduced.

Description

  The present invention relates to a liquid crystal control device mounted on home appliances and equipment.

  As a liquid crystal driving device for controlling a conventional dot matrix liquid crystal, Patent Document 1 is shown. The liquid crystal driving device of Patent Document 1 stores 1-dot 1-bit monochrome image data in a ROM, reads the image data, writes the image data in a DRAM in units of screens, and drives a liquid crystal element of a dot matrix liquid crystal. Configures a liquid crystal drive device that includes a liquid crystal controller that outputs a signal to the LCD driver, and further expands the data color composed of N AND circuits that expand the image data of each dot 1 bit acquired from the ROM to N bits. And a palette for gradation display, 1 dot 1 bit monochrome image data stored in the ROM is converted into N bits gradation display (or color number display) for each dot. Input to one side of the AND circuit, and simultaneously input a control signal from the CPU to the other side, 1 dot 1 bit to 1 dot N bit (2 (N-th gradation) and stored in DRAM, displaying gradation according to palette settings, reducing the amount of data stored in ROM, reducing ROM capacity, and reducing costs ing.

  In addition, the LCD controller has a register for setting, resolution, CPU interface (8bit / 16bit / serial communication), input data format (RGB8: 8: 8, RGB5: 6: 5, 8BPP gray) Set scale, look-up table (gradation conversion table) 8/16/24 BPP), liquid crystal panel interface (8 / 16-bit color, 4 / 8-bit monochrome, TFT 16/18 / 24-bit), etc. Some are used by adapting to their own system (BPP is BITS PER PIXEL, 1-bit color depth). The lookup table (gradation conversion table) converts the gradation output level for driving the LCD driver into an arbitrary set value and controls it for each input gradation code.

JP 2000-137466 A

  However, in the above-described conventional configuration, 1-bit (1 dot) 1-bit image data is stored in the ROM, and the data expansion unit configured by an N-bit AND circuit extends the data to 2 N gradations. Therefore, it is possible to reduce the data capacity stored in the ROM, reduce the ROM capacity, and reduce the cost, but the DRAM capacity for storing the image data expanded to the N-bit width cannot be reduced. There is a problem that it is necessary to provide a DRAM having a capacity and the cost increases.

  When a liquid crystal controller as described above is used and color display is performed on a color liquid crystal in the RGB 5: 6: 5 format, one frame of image data is stored in the RAM in a one-chip microcomputer with a built-in RAM. If the frame buffer RAM is configured, the required frame buffer size is frame size: (vertical dot × horizontal dot) × 16 bits (RGB5: 6: 5) / 8 [BYTE]. For example, QVGA (320 × 240 dots) ) Requires a 150 KB RAM and a large built-in RAM, which increases the cost.

  In particular, many microcomputers that control white goods and the like are often 8-bit and 16-bit general-purpose microcomputers, and not only have a small amount of RAM, but also have a low processing capacity. It was difficult to process the 6: 5 (65536 color) data format as it is.

  The present invention realizes color display without being affected by the data format (number of colors) of the display RAM of the liquid crystal controller when the frame buffer RAM is constituted by the built-in RAM of a one-chip microcomputer. An object of the present invention is to realize a color liquid crystal control device with a microcomputer having a low cost and a low processing capacity such as an 8-bit microcomputer with a small frame buffer RAM capacity.

  A liquid crystal control device that generates drawing data for display on a display unit of a dot matrix color liquid crystal including pixels composed of R (red) dots, G (green) dots, and B (blue) dots, wherein the R (red) ) N-bit display data representing the respective gradations of dots, G (green) dots, and B (blue) dots in units of pixels, and stored in units of pixels in the first storage unit. A first output unit for outputting display data of the R (red) dots, G (green) dots, and B (blue) dots by wiring corresponding to each bit, and set for each display data in pixel units A second storage unit that stores 1-bit display auxiliary data; a second output unit that outputs display auxiliary data stored in the second storage unit by wiring; R (red) dots, G (green) dots; B (blue) dot A third storage unit that stores display adjustment data for adjusting each gradation, a third output unit that outputs display adjustment data stored in the third storage unit via wiring, and the first output unit and wiring The display data of the R (red) dots, G (green) dots, and B (blue) dots input from the first output unit is converted into drawing data for display on the display unit. A gradation conversion unit, and any one of the N-bit wirings corresponding to each dot of the first output unit is connected to the wiring of the second output unit by wired OR wiring, and The liquid crystal control device is configured such that the wiring connected to the third output section is connected by wired OR wiring in a wiring different from the wiring connected to the second output section.

  By configuring the liquid crystal control device in this way, N-bit wiring corresponding to R (red) dots, G (green) dots, and B (blue) dots of the first output unit that sends display data to the first storage unit 1 pixel 1 bit display auxiliary data stored in the second storage unit can be transmitted to a predetermined wiring by wired OR wiring, so 1 pixel 1 bit display auxiliary data is R (red) dots. , G (green) dots, B (blue) dots can be converted into the form of the first storage unit configured for transmission, and R (red) dots, G (green) dots, B Display adjustment data indicating each gradation of each dot of (blue) dots is wired-OR wiring from the third output unit, and is input to any one of N bits different from the wiring connected to the second output unit, R (red) dot, G (green) Since the tone data of each dot can be transmitted to the dot and the B (blue) dot, the tone set in advance for each dot by the tone code based on the bit pattern that combines the display data, the display auxiliary data, and the display adjustment data Therefore, the color liquid crystal can be controlled by a microcomputer having a low processing capability without providing a special circuit and keeping the ROM and RAM capacities small.

  By using the liquid crystal control device of the present invention, even if the display data stored in the frame buffer RAM or ROM is expressed in binary (0 and 1), color display can be performed, and the capacity of the ROM and frame buffer RAM can be increased. There is an effect that color display is realized with an inexpensive microcomputer and system configuration.

1 is a system configuration diagram of a liquid crystal control device according to Embodiment 1 of the present invention. 1 is a block configuration diagram of a liquid crystal control device according to Embodiment 1 of the present invention. Wiring configuration diagram between microcomputer and LCD controller IC in the first embodiment of the present invention Functional block configuration diagram of a liquid crystal control device according to Embodiment 1 of the present invention Flowchart showing liquid crystal display control in Embodiment 1 of the present invention The figure which shows the address map of display RAM in Embodiment 1 of this invention The figure which shows the setting value of the gradation conversion table in Embodiment 1 of this invention.

  A first invention is a liquid crystal control device that generates drawing data to be displayed on a display unit of a dot matrix color liquid crystal including pixels composed of R (red) dots, G (green) dots, and B (blue) dots. A first storage unit that stores N-bit display data representing the respective gradations of the R (red) dots, G (green) dots, and B (blue) dots in pixel units; and the first storage unit A first output unit that outputs display data of the R (red) dots, G (green) dots, and B (blue) dots stored in pixel units by wiring corresponding to each bit; and for each display data in pixel units A second storage unit for storing 1-bit display auxiliary data set correspondingly, a second output unit for outputting the display auxiliary data stored in the second storage unit by wiring, R (red) dots, G (green) dot, B ( ) A third storage unit that stores display adjustment data for adjusting the respective gradations of the dots; a third output unit that outputs the display adjustment data stored in the third storage unit via wiring; and the first output unit. To the drawing data for displaying the display data of the R (red) dots, G (green) dots, and B (blue) dots input from the first output unit on the display unit. A gradation conversion unit for conversion, and one of the N-bit wirings corresponding to each dot of the first output unit is connected to the wiring of the second output unit by a wired OR wiring, and The liquid crystal control device is characterized in that the wiring connected to the third output section is connected by wired OR wiring in a wiring different from the wiring connected to the second output section.

  Then, the second storage unit is connected to any one of N-bit wirings corresponding to R (red) dots, G (green) dots, and B (blue) dots of the first output unit that sends display data to the first storage unit. Since the stored 1-pixel 1-bit display auxiliary data can be transmitted to a predetermined wiring by wired OR wiring, the display auxiliary data, which is 1-pixel 1-bit binary display data, includes R (red) dots, G (green). ) Dots and B (blue) dots can be transmitted after being converted to the form of the first storage unit configured in the data format, and R (red) dots, G (green) dots, and B (blue) dots Display adjustment data, which is gradation data indicating each gradation for each dot, is wired-OR wiring from the third output section and is input to one of N bits different from the wiring connected to the second output section. , R (red) dot, G ( ) Since the gradation data of each dot can be transmitted to the dot and B (blue) dot, the gradation code set in advance for each dot by the gradation code based on the bit pattern that combines the display data, the display auxiliary data, and the display adjustment data. Color conversion is possible even with low-processing microcomputers such as 8-bit microcomputers used in white goods, without providing special circuits and keeping ROM and RAM capacities small. Can be controlled.

  According to a second aspect of the present invention, there is provided the liquid crystal control device according to claim 1, wherein the third output unit has at least two wires in each of R (red), G (green), and B (blue) dots. Is.

By providing at least two third output wirings for each dot, it becomes possible to input display adjustment data indicating gradation data of 2 bit gradation or less in each dot, and R (red), G By combining (green) and B (blue), it becomes possible to express 64 colors, to reduce display auxiliary data that is gradation data, to suppress the amount of data to be processed, and to perform color display. A color liquid crystal can be controlled even by a low-processing microcomputer such as an 8-bit microcomputer.

  In the third aspect of the invention, the display adjustment data stored in the third storage unit is data for displaying at least each dot in gradation and data for setting each dot to the minimum gradation output.

  Display adjustment data indicating at least two gradation data can be input to each dot, and one wiring is used as input information (flag information) for displaying each dot in gradation, and another wiring is used. Are input information (flag information) for controlling the gradation display of the same dot to the minimum gradation output (light-off state), so that the third output unit can be used as a bit flag output, indicating gradation data. Since the amount of display adjustment data is reduced and color display is controlled, color display control is facilitated by a microcomputer with low processing capability.

  According to a fourth aspect of the present invention, the wiring of the second output section is branched and connected to one bit of each dot of R (red), G (green), and B (blue). A buffer circuit is provided.

  Then, the wiring of the second output section is branched to connect to one bit of each dot of R (red), G (green), and B (blue), and a buffer circuit is provided on the wiring and connected. The gradation of the R (red), G (green), and B (blue) dots can be simultaneously controlled by one wiring of the second output unit, and the data amount of the display auxiliary data can be reduced.

  According to a fifth aspect of the present invention, there is provided an output determination unit that determines whether or not display adjustment data is output from the third output unit. When the output determination unit determines that the pixel is a gradation output, the third output unit The display adjustment data is output from.

  Then, an output determination unit is provided, and it is determined whether or not it is a pixel that outputs display adjustment data that is gradation data from the third output unit. Thus, the gradation output area can be limited and output, and the capacity of the display adjustment data held in the third storage unit can be compressed and reduced.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. Note that the present invention is not limited to the embodiments.

(Embodiment 1)
FIG. 1 is a system configuration diagram of a liquid crystal control device according to Embodiment 1 of the present invention. FIG. 2 is a block diagram of the liquid crystal control device. FIG. 3 is a wiring configuration diagram between the microcomputer and the LCD controller IC.

  The configuration of the first embodiment will be described with reference to FIGS. 1, 2, and 3. In FIG. 1, the liquid crystal control device is composed of three components: a microcomputer 1, an LCD controller IC 2, and an LCD 3.

  The liquid crystal control device according to the present embodiment is a microcomputer having a low processing capability such as an 8-bit microcomputer, and a system that performs partial color display in an image while mainly performing binary black and white display will be described.

  The microcomputer 1 is a one-chip microcomputer incorporating a ROM, a RAM, and a CPU. A frame buffer RAM that temporarily stores display data is configured in a part of the built-in RAM.

  The microcomputer 1 transmits a control signal, a control command, and display data to the LCD controller 4 of the LCD controller IC 2, and the transmitted display data stores data to be displayed on the LCD 3 in the display RAM 5. The display RAM 5 has a capacity of the frame size (screen size) of the LCD 3 × (R (red), G (green), B (blue)) × N bits or more.

  The LCD controller 4 sends data to the LCD driver 6 in accordance with the display data stored in the display RAM 5, and the LCD driver 6 sequentially drives each liquid crystal element constituted by the dot matrix of the LCD 3. Voltage is supplied to display desired display data on the LCD 3.

  The LCD 3 is composed of liquid crystal elements having a frame size (screen size), for example, 320 × 240 = 76800 pixels (pixels) in the case of horizontal 320 × vertical 240. In addition, because of the color liquid crystal, each pixel (pixel) is composed of three dots of R (red), G (green), and B (blue), and each represents a color color by displaying a gradation.

  The LCD driver 6 continuously supplies drive voltage to the LCD 3 based on the display data of the display RAM 5, thereby displaying the display data on the LCD 3. The LCD driver 6 includes an X driver that controls the horizontal direction and a Y driver that controls the vertical direction.

  In this embodiment, a description is given of a configuration in which the LCD controller function and the LCD driver are separately provided, but the LCD controller and the LCD driver may be integrated.

  Next, the internal configuration of the liquid crystal control device according to the first embodiment will be described with reference to FIG.

  FIG. 2 is a block configuration diagram in which the internal configuration of the microcomputer 1 and the LCD controller 2 in the system configuration diagram of FIG.

  The microcomputer 1 includes a CPU 201, a ROM 202, a RAM 203, and a frame buffer RAM 204 and an I / O controller 205 in a part of the RAM 203, and the microcomputer 1 functions by cooperating them.

  The CPU 201 is a central processing unit. Program commands and data are read from a ROM 202 and a RAM 203 (to be described later), display data to be displayed on the LCD 3 is processed, calculated, and stored in the frame buffer RAM 204 of the RAM 203. Specifically, the image data and bitmap font data in the ROM 202 are read and processed by the CPU 201, and the data is written at a desired address in a frame buffer RAM 204 described later. This is repeated a plurality of times to create frame data (one screen data) on the frame buffer RAM 204.

  The ROM 202 stores program instructions, data, and image data. Also, the gradation data of the image data is stored. If necessary, the data is expanded in a RAM 203 described later. The ROM 202 may be either a flash ROM that can be written only once or a rewritable FLASH ROM.

  The RAM 203 stores setting data and display data used in the program. The RAM 203 includes a frame buffer RAM 204 configured with 1 bit per pixel (monochrome binary). For example, in the case of 320 × 240 dots, a frame buffer RAM 204 of 9600 bytes is secured. The RAM 203 may be SRAM or DRAM.

The frame buffer RAM 204 is a buffer RAM for temporarily storing frame data displayed on the LCD 3 by the microcomputer 1. The CPU 201 acquires and processes the required number of image component data stored in the ROM 202, and creates and stores frame data (one screen data) to be displayed on the frame buffer RAM. The CPU 201 continuously creates frame data (one screen data) to be displayed on the LCD 3 and causes the LCD 3 to continuously display the display data by displaying the frame data on the LCD 3.

  The I / O controller 205 is a control device that controls the IO port of the microcomputer 1. The I / O controller 205 includes five control signal outputs for RS: register select, CS: chip select, WE: write enable, RE: read enable, RST: reset, and 16 displays for controlling the LCD controller IC2. Port 1 for data output, one display auxiliary data output port 2 for outputting binary monochrome display data of the frame buffer RAM, and six display adjustment data output ports 3 for gradation data output It is connected. The output data of the three output ports cooperate to transmit display data to the LCD controller IC 2 and display the display data on the LCD 3.

  RS: register select switches whether the transmission data is a control command or control data to the LCD controller IC2. CS: Chip select is a chip selection signal to the LCD controller IC2. When L is active, it is set to L and a control command and control data are transmitted to the LCD controller IC2.

  WE: Write enable is an enable signal for latching a control command or control data to be transmitted. A control command or control data to be transmitted is written to the LCD controller IC2 in response to a falling or rising edge signal.

  RE: Read enable is an enable signal for latching control data received by the microcomputer 1. The control data to be received is read into the microcomputer 1 by the falling or rising edge signal.

  RST: Reset is a reset signal to the LCD controller IC2. When L is active, it is set to L, the register setting of the LCD controller IC2 is cleared, and resetting is performed.

  The port 1 (206) is formed by 16 signal lines P100 to P115 as shown in FIG. The 16 signal lines are connected to a total of 16 ports R4 to R0: 5, G5 to G0: 6, and B4 to B0: 5 of the LCD controller IC2, and R (red), G (green), B ( 5 bits, 6 bits, and 5 bits of gradation code are transmitted to each of the blue), and each dot is displayed in gradation.

  Port 2 (207) is formed by one signal line P27 (FIG. 3). The port 2 (207) uses one port from the most significant bit side of the output port of the microcomputer 1 and sequentially stores the frame data (one screen data: one pixel 1 bit monochrome binary) stored in the frame buffer RAM 204. While obtaining and performing bit shift processing, data is output to the LCD controller IC 2 and transmitted. Further, the signal line of the port 2 (207) branches to three signal lines, and is assigned to R (red), G (green), and B (blue) via the buffer circuit (301 in FIG. 3). Are connected to each other by wired OR wiring.

  It should be noted that at the output timing of the port 2 (207), the output terminal of the port 1 (206) that is OR-wired is switched to the input setting or the like to avoid output value collision. When outputting from the connection port side of port 1 (206), switching is performed in reverse.

  The port 3 (208) is formed by six signal lines P37 to P32 (FIG. 3). For each of R (red), G (green), and B (blue) dots, two are connected to a port different from the port to which port 2 is connected by wired OR wiring. The port 3 (208) inputs gradation data indicating a gradation code to each of the R (red), G (green), and B (blue) dots of the LCD controller IC2 when performing color display on the LCD 3. To do.

  This gradation data determines whether the display data of the dot is a gradation output. When the gradation data of port 3 is not inputted, the maximum gradation output or the minimum gradation output is controlled by a gradation conversion table described later. At the output timing of the port 3 (208), the output terminal of the port 1 (206) that is OR-wired is switched to the input setting (HI-Z: set to high impedance), thereby causing the output value to collide. To avoid.

  Reference numeral 209 denotes an I / F bus controller of the LCD controller IC2. The I / F bus controller IC 209 acquires a control signal input from the microcomputer 1, a control instruction for the control bus port, control data, and binary display data transferred from the frame buffer RAM 204. In accordance with each control signal, binary display data is sequentially obtained and stored in the display RAM 5.

  210 is a gradation conversion table. In the gradation conversion table 210, gradation data for each dot of R (red), G (green), and B (blue) stored in the display RAM 5 is set to 5 bits, 6 bits, and 5 bits, respectively. Convert to gradation output value. In the gradation conversion table, a desired value is set so that an arbitrary gradation output value can be output to the LCD 3 according to the input gradation data. In the case of R (red) dots, a desired gradation output value is set for gradation data from 0X00 to 0X1F (5-bit gradation). Similarly, G (green) dots set desired gradation output values for 0X00 to 0X3F (6-bit gradation) and B (blue) dots for 0X00 to 0X1F (5-bit gradation). Then, the LCD driver 6 converts the gradation output value into a driving voltage level for driving the liquid crystal.

  The LCD controller 4 in FIG. 1 has an I / F bus controller 209 that controls received data and control signals from the microcomputer 1 and received gradation data for each dot at an arbitrary gradation output value set in advance. A gradation conversion table 210 for controlling the LCD driver 6 is provided.

  FIG. 4 shows a functional block configuration diagram of the liquid crystal control device. In FIG. 4, the liquid crystal control device includes a display area setting unit 401, a storage unit 402, a display data control unit 403, a display area determination unit 404, an address calculation unit 405, a port 1 output unit 406, a port 2 output unit 407, and a port 3. It comprises output means 408, LCD controller means 409, LCD driver means 410, and LCD display means 411. These means cooperate to make the liquid crystal control device function. Each function block in FIG. 4 causes the circuit block in FIG. 2 and the software installed in the microcomputer 1 to function together.

  The display area setting unit 401 sets, in the storage unit 402, a display area for gradation output to pixels (R (red), G (green), and B (blue)). The display area designates an address range of a display RAM provided in the LCD controller means 409 described later.

  The storage unit 402 sets the address range of the pixel (R (red), G (green), B (blue)) designated by the display area setting unit 401 to a start vertical address, a start horizontal address, an end vertical address, and an end horizontal. Store as an address. Binary display data to be displayed on the LCD display means 411 is also stored.

  The display data control unit 403 acquires from the storage unit 402 an address range (start vertical address, start horizontal address, end vertical address, end horizontal address) for performing the above-described gradation output and display data. The binary display data is acquired from the head address of the storage means 402 stored, transmitted, and the display data for a predetermined number of bytes (one frame) is sent to the LCD via each port while incrementing the address. Transmit to controller means 409.

  When transmitting the binary display data stored in the storage means 402, the display data control means 403 outputs binary display data of 1 bit per pixel from the port 2 output means 407, and R (red), G (green) ) And B (blue) dot gradation data is output from the port 3 output means 408. The port 2 output means 407 and the port 3 output means 408 perform L output from the port of the port 1 output means 406 where the wired OR wiring is not performed.

  The display area determination unit 404 determines whether the display RAM address of the transmission destination of the binary display data transmitted by the display data control unit 403 is within the address range specified by the display area setting unit 401. The determination information is acquired by the display data control means 403, and if it is within the specified range, the gradation data output of each dot of R (red), G (green), and B (blue) is output from the port 3 output means 408. Do.

  The address calculation means 405 calculates the display RAM address of the LCD controller means 409 that transmits display data. Specifically, the display data is incremented every time a predetermined number of bytes are transmitted, and the transmission destination RAM address is calculated. The calculated transmission destination RAM address is acquired by the display data control means 403 and compared with an address range for outputting gradation data of each dot of R (red), G (green), and B (blue).

  The port 2 output means 407 outputs binary display data. The binary display data to be transmitted once by the display data control means 403 is set in the port 2 and transmitted to the LCD controller means 409 by the port 2 output means 407.

  The port 3 output means 408 outputs gradation data of each dot of R (red), G (green), and B (blue). In the case of a display area for gradation output, if gradation data is not likely to be output, L is output.

  The LCD controller means 409 is an LCD controller IC. Performs display data transmission timing control, data conversion, and the like.

  The LCD driver means 410 is composed of the LCD driver 6. The liquid crystal elements arranged in a matrix of the LCD 3 are driven and controlled.

  The LCD display means 411 is composed of the LCD 3. Display data transmitted from the display data control means 403 is displayed.

  Next, the binary display data stored in the frame buffer RAM 204 of the first embodiment in 1 pixel 1 dot binary monochrome is converted into RGB 5: 6: 5 format (16-bit color display), and a part of the display data is converted. The operation and effect of transmitting gradation data to the display data range and performing color display using the gradation conversion table 210 will be described with reference to FIG.

  FIG. 5 is a flowchart showing gradation control of each dot of R (red), G (green), and B (blue) in the color dot matrix liquid crystal of the first embodiment.

  In FIG. 5, the CPU 201 acquires image data from the ROM 202, processes the data, designates a predetermined position (address) of the frame buffer RAM 204, and sets the image data. The above process is performed a plurality of times to generate display data for one frame (one screen) of one pixel, one dot, binary monochrome (S501).

  Next, the CPU 201 controls the address range (start vertical address, start horizontal address, end vertical address, end horizontal address) of the display RAM 5 that performs gradation control of each dot of R (red), G (green), and B (blue). ) In the RAM 203 in units of pixels. Further, the head address of the display RAM 5 that transmits display data for one frame is set in the RAM 203 (S502).

  The CPU 201 reads the head address of the display RAM 5 as the transmission destination of the binary display data from the RAM 203. Further, the binary display data to be transmitted to the address is read out and acquired from the frame buffer RAM 204 (S503).

  At this time, display data is acquired in byte units. Since one display data is transmitted for one pixel, bit shift processing and transmission are performed a predetermined number of times, and binary display data is transmitted.

  Next, it is determined whether the destination display RAM address is within the address range set by the display area setting means 401 (S504).

  Specifically, in the CPU 201, the display area determination unit 404 compares and determines whether the destination display RAM address acquired from the RAM 203 is within the address range of the display RAM 5 that performs gradation control.

  An address map of the display RAM of the LCD controller IC2 is shown in FIG. X drivers are connected in the horizontal direction, and are arranged in the order of 1, 2, 3,. The X address range is 0X0000 to 0X0140. One address is configured in a 16-bit RGB 5: 6: 5 format.

  In addition, Y drivers are connected in the vertical direction, and are arranged in the order of 1, 2, 3,. The Y address range is 0X0000 to 0X00F0.

  In FIG. 6, when (X, Y) is (1, 1), the address is (0X0000, 0X0000), and when (2, 2), (0X0001, 0X0001). The range of the same address is set and determined, and gradation display is performed.

  When the determination of the display area determination unit 404 is “outside the specified range”, the most significant 1 bit of the first 1 byte of the display data of one frame (one screen data) acquired is transmitted from the port 2 output unit 407, At the same time, the port 3 output means 408 for gradation data output is OFF output (L output) (S505). Gradation data is not output.

  Specifically, in FIG. 3, the most significant bit (P27) of port 2 (P2 207) is set for one pixel, and wired OR wiring R (red), G (through the buffer 601) Display data is input to the R4, G5, and B4 ports of the most significant bit of each dot (green) and B (blue). Then, display data is transmitted from the microcomputer 1 to the LCD controller IC2.

At this time, P115, P110, and P104, which are OR-wired with port 2 (P2 207), are switched to the input setting by the setting of the microcomputer 1, and thus are in HI-Z (high impedance state), and the same wiring It avoids collision of the output port connected above. At the same time, the output terminal to which the data of P port 1 (P1 206) is not set is output L. The output terminals P26 to P20 of the port 2 (P2 207) are unconnected terminals.

  Then, after transmitting the most significant 1 bit of the acquired 1 byte, 1 bit left shift processing is performed, the next 1 bit is transmitted, 1 bit left shift is repeated, and 1 byte = 8 bits are transmitted.

  Also, with the wired OR wiring configuration, binary display data of 1 bit per pixel is converted into display data of RGB 5: 6: 5 format of 16 bits per pixel, and is displayed in the display RAM 5 via the I / F bus controller 209. Set.

  Next, the gradation code will be described. When the output of the port 2 (P2 207) is 0, the gradation code of each dot of R (red), G (green), and B (blue) of the pixel of the LCD 3 is the most significant bit by the wiring configuration of FIG. Is set to 0 and becomes the gradation output value 701 of the gradation conversion table 210 shown in FIG. 7, and each dot is controlled with the minimum gradation output. Further, when the output of port 2 (P2 207) is 1, it becomes a gradation output value 702 and is controlled by the maximum gradation output.

  Then, each of R (red), G (green), and B (blue) dots is simultaneously output with a minimum gradation or a maximum gradation, thereby expressing white or black.

  Next, when the determination by the display area determination unit 404 is “within a specified range”, the gradation is determined for each dot of R (red), G (green), and B (blue) for the specified area. In order to perform control, transmission is performed using the port 2 output means 407 from the most significant 1 bit of the first 1 byte of the acquired binary display data of one frame (one screen data), and at the same time, the port 3 output of gradation data output The means 408 outputs gradation data to each of R (red), G (green), and B (blue) dots (S506).

  At this time, in each of R (red), G (green), and B (blue) dots, port 3 (only when 1 is set in port 2 (P2 207) for the set gradation code. In P3 208), gradation data is set. Two-bit gradation data is set for each dot, and the least significant bit is a bit flag for turning off the gradation display of the dot, that is, outputting the minimum gradation. The second bit from the least significant bit is used as gradation data of the same dot (703 in FIG. 7).

  Then, the gradation code with the gradation data bit set to 1 is set in the gradation conversion table 210. In this embodiment, as shown in FIG. 7, R (red), G (green), B ( Each dot (blue) is set individually for maximum gradation output. By setting in this way, the R (red), G (green), and B (blue) dots are individually output with the maximum gradation output or the minimum gradation output by the output of the port 3 (P3 208). The light is turned on to perform color color expression (S507).

  If each of R (red), G (green), and B (blue) dots has a 2-bit gradation without being controlled as a bit flag, 64 color representations are possible.

  Each dot can be output at an intermediate gradation level by setting the gradation conversion table 210.

Then, the gradation code is input to the LCD controller means 409 by the output of the port 1 output means 406, the port 2 output means 407, and the port 3 output means 408, and the gradation output level of the set value of the gradation conversion table 210 is set. Then, the LCD driver unit 410 is driven to display white, black, and color colors (controlled by the output of the port 3) on the pixels of the LCD display unit 411 (S508).
When the binary display data for the first byte of the frame buffer RAM 204 = 8 bits = 8 pixels is transmitted to the LCD controller IC 2, the CPU 201 checks whether there is still the binary display data to be transmitted. The address value is compared with the final address of the frame buffer RAM 204 (S509).

  If it is not the final address, the CPU 201 increments the address value of the frame buffer RAM 204, which is the storage destination of the binary display data to be acquired next, by 1 and stores it in the RAM 203. At the same time, the address value of the display RAM address as the transmission destination is incremented by +1 (S510).

  Then, the display data of the second byte is acquired from the head address of the frame buffer RAM 204, and the display data of the second byte is transmitted to the LCD controller IC2 in the same manner as described above. This is repeated until the final address of the frame buffer RAM 204, one frame of display data is transmitted, and a desired display image is displayed on the LCD 3.

  As described above, according to the present embodiment, the N-bit wiring corresponding to the R (red) dot, G (green) dot, and B (blue) dot of the port 1 (P1206) that sends display data to the display RAM 5 is used. In order to transmit the 1-pixel 1-bit binary display data stored in the port 2 (P2 207) to the predetermined wiring by the wired OR wiring, the 1-pixel 1-bit binary display data is R ( The data can be converted and transmitted to the display RAM 5 configured in the RGB 5: 6: 5 format of red), G (green), and B (blue) dots, and R (red) dots, G (green) One of N bits different from the wiring connected to the second output unit by performing wired OR wiring of the gradation data indicating the gradation output for each dot, B (blue) dot from port 3 (P3 208) Enter In order to transmit the gradation data of each dot to the R (red) dot, G (green) dot, and B (blue) dot, the binary display data of 1 pixel and the gradation data are combined. By using the gradation code based on the bit pattern, gradation conversion can be performed to a gradation output value set in advance for each dot, and an 8-bit microcomputer having a small capacity of ROM and RAM can be used without providing a special circuit. A color LCD can be controlled even with a microcomputer with low processing capability.

  In addition, by providing at least two ports 3 (P3 208) for each of the R (red), G (green), and B (blue) dots, each dot has a 2-bit gradation level. Tone data can be input, and when R (red), G (green), and B (blue) are combined, 64 colors can be displayed, reducing gradation data and processing data The amount can be suppressed.

  In addition, at least two gradation data can be input to each of R (red) dots, G (green) dots, and B (blue) dots, and each dot is displayed in gradation. Port 3 (P3 208), and the other wiring is input information (flag information) for controlling the gradation display of the same dot to the minimum gradation output (light-off state). ) Can be used as a bit flag output, and color display can be controlled while reducing the amount of gradation data. In addition, since the processing information is small, color display control is facilitated by a low processing capability microcomputer such as an 8-bit microcomputer.

  The port 2 (P2 207) branch is connected to 1 bit of each dot of R (red), G (green), and B (blue), and a buffer circuit (301) is provided on the same wire. By connecting them, it is possible to simultaneously control the gradation of each dot of R (red), G (green), and B (blue) with one wiring of port 2 (P2 207), and data in the frame buffer RAM 204 The amount can be reduced.

  Further, a display area determination unit 404 is provided to determine whether the pixel outputs gradation data from the port 3 (P3 208). When the pixel is determined to output gradation, the gradation data is output. Since the gradation output area can be limited and output, and it is only necessary to have gradation data for each area, the capacity of gradation data held in the RAM 203 can be compressed and reduced.

  Note that the control level of gradation output of each dot of R (red), G (green), and B (blue) is not limited, and is between the minimum gradation and the maximum gradation that can be set by the LCD driver 6. Any setting value may be used as long as it is at a level of.

  Then, by driving the liquid crystal element of each pixel of the LCD 3 according to the control level converted by the gradation conversion table 210 from the RGB gradation codes set in the display RAM 5, white, black, and additional colors Perform color LCD control.

  In the present embodiment, the LCD controller IC 2 including the display RAM 5 in the RGB 5: 6: 5 format (16-bit color display) has been described. However, the present invention is not limited to this.

  In addition, although the output number of port 1 (P1 206) has been described as 16, it may be 8 or the like and can be configured.

  In addition, the port 3 (P3 208) is configured with six lines, and two RGB dots are wired. However, the present invention is not limited to this. Further, the bit position to be connected is not limited.

  In this embodiment, each of the RGB dots is individually output with the maximum gradation, and the color display control is performed. However, the gradation conversion is performed by increasing the number of gradation data in the port 3 (P3 208). The number of gradation codes set in the table is increased, and a large number of colors can be expressed by combining RGB.

  Further, the display RAM 5 and the liquid crystal screen size have been described as 320 × 240 dots, but are not limited thereto.

  The microcomputer 1 is mainly assumed to be a microcomputer having a low processing capability such as an 8-bit microcomputer or a 16-bit microcomputer, but a microcomputer having a high processing capability of 32 bits or more can be similarly configured.

  The gradation code of the gradation conversion table shows four settings for each dot of R (red), G (green), and B (blue), but is not limited to this.

  The liquid crystal control device according to the present invention can be applied to a liquid crystal control device using a dot matrix liquid crystal using a microcomputer having a low processing capability, such as household appliances and commercial appliances such as business and equipment.

3 LCD (display unit)
5 Display RAM (first storage)
202 ROM (third storage unit)
204 Frame buffer RAM (second storage unit)
206 Port 1 (first output)
207 Port 2 (second output section)
208 Port 3 (3rd output part)
210 Gradation conversion table (gradation conversion unit)
301 buffer circuit 404 display area determining means (output determining means)
411 LCD display means (display unit)

Claims (5)

A liquid crystal control device that generates drawing data to be displayed on a display unit of a dot matrix color liquid crystal including pixels composed of R (red) dots, G (green) dots, and B (blue) dots,
A first storage unit that stores N-bit display data representing each gradation of the R (red) dot, G (green) dot, and B (blue) dot in pixel units;
A first output unit that outputs display data of the R (red) dots, G (green) dots, and B (blue) dots stored in pixel units in the first storage unit by wiring corresponding to each bit;
A second storage unit for storing 1-bit display auxiliary data set corresponding to each display data in pixel units;
A second output unit for outputting display auxiliary data stored in the second storage unit by wiring;
A third storage unit for storing display adjustment data for adjusting the respective gradations of R (red) dots, G (green) dots, and B (blue) dots;
A third output unit for outputting the display adjustment data stored in the third storage unit by wiring;
By connecting to the first output unit by wiring, display data of the R (red) dots, G (green) dots, and B (blue) dots input from the first output unit is displayed on the display unit. A gradation conversion unit for converting into drawing data for
One of the N-bit wirings corresponding to each dot of the first output unit is connected to the second output unit by wired OR wiring, and is connected to the second output unit A liquid crystal control device, wherein the wiring is different from the wiring of the third output unit by a wired OR wiring. The liquid crystal control device according to claim 1, wherein the third output unit has at least two wires in each of R (red), G (green), and B (blue) dots. 3. The liquid crystal control device according to claim 2, wherein the display adjustment data stored in the third storage unit is data for displaying gradation of at least each dot and data for setting each dot to a minimum gradation output. The wiring of the second output section is branched and connected to one bit of each dot of R (red), G (green), and B (blue), and a buffer circuit is provided on the branched wiring. Item 4. The liquid crystal control device according to any one of Items 1 to 3. An output determination unit that determines whether or not display adjustment data is output from the third output unit is provided, and when the output determination unit determines that the pixel is a gradation output pixel, the display adjustment data is output from the third output unit. The liquid crystal control device according to any one of claims 1 to 4.

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