JP2013106022A - Semiconductor device and manufacturing method of the same - Google Patents

Semiconductor device and manufacturing method of the same Download PDF

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JP2013106022A
JP2013106022A JP2011251281A JP2011251281A JP2013106022A JP 2013106022 A JP2013106022 A JP 2013106022A JP 2011251281 A JP2011251281 A JP 2011251281A JP 2011251281 A JP2011251281 A JP 2011251281A JP 2013106022 A JP2013106022 A JP 2013106022A
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layer
portion
semiconductor device
buried layer
heterojunction
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JP5881383B2 (en
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Masakazu Kanechika
将一 兼近
Kenji Ito
健治 伊藤
Tsutomu Uesugi
勉 上杉
Masahiro Sugimoto
雅裕 杉本
Hirofumi Aoki
宏文 青木
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Toyota Central R&D Labs Inc
株式会社豊田中央研究所
Toyota Motor Corp
トヨタ自動車株式会社
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Abstract

PROBLEM TO BE SOLVED: To suppress a leakage current through a parasitic diode.
A semiconductor device includes a nitride semiconductor semiconductor layer having a c-plane as a surface, and a nitride semiconductor p-type buried layer having a thickness decreasing portion a that decreases in thickness. In the buried layer 14, there is a portion where the oxygen concentration has a peak inside the thickness reducing portion 14a, and the concentration of the p-type impurity between the peak portion and the inclined surface of the thickness reducing portion 14a is higher than the oxygen concentration. There is a part.
[Selection] Figure 8

Description

  The present invention relates to a semiconductor device having a p-type buried layer and a method for manufacturing the same.

  Development of a semiconductor device using a nitride semiconductor is in progress, and an example thereof is disclosed in Patent Document 1. An outline of the semiconductor device disclosed in Patent Document 1 is shown in FIG. The semiconductor device 4 includes a substrate 311, a gallium nitride buffer layer 312, a gallium nitride semiconductor layer 313, a p-type gallium nitride buried layer 314, a heterojunction layer 317, a drain electrode 322, a gate portion 325, a source electrode 326, a base An electrode 327 is provided. The heterojunction layer 317 includes an electron transit layer 315 of gallium nitride and an electron supply layer 316 of aluminum gallium nitride, and a two-dimensional electron gas layer is formed on the heterojunction surface of the electron transit layer 315 and the electron supply layer 316. ing. The gate portion 325 includes a gate electrode 323 and a gate insulating film 324.

  In the semiconductor device 4, conduction between the drain electrode 322 and the source electrode 326 occurs when electrons travel through the two-dimensional electron gas layer. In the semiconductor device 4, on and off are switched according to the voltage applied to the gate electrode 323 of the gate portion 325.

  The p-type buried layer 314 is provided to discharge holes generated when electrons traveling in the two-dimensional electron gas layer collide with surrounding atoms. The semiconductor device 4 is characterized in that the buried layer 314 is selectively provided on a part of the surface of the semiconductor layer 313. For example, when the buried layer 314 is provided over the entire surface of the semiconductor layer 313, electric field concentration at the junction surface between the buried layer 314 and the heterojunction layer 317 becomes a problem below the drain electrode 322. On the other hand, when the buried layer 314 is selectively provided, the hole discharging ability can be maintained while avoiding such electric field concentration.

JP 2004-260140 A

  The semiconductor device 4 is formed by crystal growth of a buffer layer 312, a semiconductor layer 313, a buried layer 314, and a heterojunction layer 317 on a silicon substrate 311 using a metal organic chemical vapor deposition method or the like. The buried layer 314 is selectively formed by etching a part after being formed on the semiconductor layer 313. The heterojunction layer 317 is crystal-grown from the surfaces of the semiconductor layer 313 and the buried layer 314 after etching a part of the buried layer 314.

  Usually, a semiconductor device using a nitride semiconductor is often employed with a c-plane as a growth surface. Therefore, the side surface 314S of the buried layer 314 that appears when a part of the buried layer 314 is etched is a surface other than the c-plane, for example, the a-plane or the m-plane.

  As a result of studies by the present inventors, it has been found that a large amount of oxygen is introduced into the side surface 314S of the buried layer 314 when the heterojunction layer 317 is crystal-grown. In a nitride semiconductor, oxygen is hardly introduced from the c-plane, but oxygen is easily introduced from a surface other than the c-plane. In the semiconductor device 4, the side surface 314S of the buried layer 314 is a surface other than the c-plane, and this is considered to be the cause.

  Oxygen functions as an n-type impurity in the nitride semiconductor. For this reason, when a large amount of oxygen is introduced into the end portion of the p-type buried layer 314, the portion becomes n-type. As a result, a parasitic pn diode is formed in the vicinity of the side surface 314S of the buried layer 314.

  When the semiconductor device 4 is turned off, a reverse bias is applied to the parasitic pn diode. When this reverse bias voltage exceeds the breakdown voltage of the parasitic pn diode, a leakage current flows through the parasitic pn diode.

  In the above, the problem of the p-type buried layer has been described by taking the semiconductor device 4 as an example. However, there are cases where it is desired to selectively form the p-type buried layer in other types of semiconductor devices. A similar problem exists in some cases.

  The technology disclosed in this specification is intended to suppress a leakage current through a parasitic pn diode in a semiconductor device having a p-type buried layer.

  In the technique disclosed in this specification, after a part of the p-type buried layer is etched, a mass transport is generated at the end of the buried layer where the side surface is exposed. Thereby, the end portion of the buried layer becomes a thickness-decreasing portion where the thickness gradually decreases. Since the inclined surface of the reduced thickness portion approaches the c-plane, the introduction of oxygen is suppressed. Thereby, the operation of the parasitic pn diode is suppressed, and the leakage current is suppressed.

  The semiconductor device disclosed in this specification includes a semiconductor layer and a p-type buried layer. The semiconductor layer is a nitride semiconductor having a c-plane as a surface. The buried layer is a nitride semiconductor that is provided on a part of the surface of the semiconductor layer and has a thickness decreasing portion in which the thickness decreases. In the buried layer, there is a portion where the oxygen concentration peaks within the thickness reduction portion, and there is a portion where the concentration of the p-type impurity is higher than the oxygen concentration between the peak portion and the inclined surface of the thickness reduction portion. To do. According to this aspect, even if the portion where the oxygen concentration is peaked is n-type, the portion between the peak portion and the inclined surface of the reduced thickness portion is p-type, and the n-type portion is in an isolated state. . Thereby, the operation of the parasitic pn diode is suppressed, and the leakage current is suppressed.

  The semiconductor device disclosed in this specification may be applied to a high electron mobility transistor. In this case, the semiconductor device further includes a heterojunction layer, a source electrode, a drain electrode, and a gate portion. The heterojunction layer is a nitride semiconductor that is provided on the semiconductor layer and the buried layer and in which the heterojunction is configured. The source electrode is provided in part on the heterojunction layer. The drain electrode is also provided on a part of the heterojunction layer. The gate portion is provided in a part on the heterojunction layer and is disposed between the source electrode and the drain electrode. Here, the gate portion may be a Schottky type or an insulated gate type.

  The heterojunction layer provided in the high electron mobility transistor may include an electron transit layer and an electron supply layer having a wider band gap than the electron transit layer. In this case, the buried layer, the electron transit layer, and the electron supply layer are preferably arranged in this order below the gate portion. In this semiconductor device, the two-dimensional electron gas layer formed on the heterojunction surface by the p-type buried layer is depleted, and can operate normally off.

  The method for manufacturing a semiconductor device disclosed in this specification may include a step of forming a thickness reduction portion of the buried layer by mass transport by heat treatment. A semiconductor device in which the operation of the parasitic pn diode is suppressed can be manufactured by using a simple manufacturing method.

  According to the technique disclosed in this specification, the operation of the parasitic pn diode formed in the p-type buried layer can be suppressed, and the leakage current can be suppressed.

A manufacturing process of a semiconductor device of Example 1 is shown (1). A manufacturing process of the semiconductor device of Example 1 is shown (2). The change of the substrate temperature of a mass trans phase and a vapor phase growth phase is shown. A manufacturing process of a semiconductor device of Example 1 is shown (3). FIG. 3 is an enlarged view of a main part of a buried layer of the semiconductor device of Example 1. 2 shows an impurity distribution in a buried layer of the semiconductor device of Example 1. A manufacturing process of a semiconductor device of Example 1 is shown (4). A manufacturing process of a semiconductor device of Example 1 is shown (5). Sectional drawing of the semiconductor device of Example 2 is shown. Sectional drawing of the semiconductor device of Example 3 is shown. Sectional drawing of the conventional semiconductor device is shown.

Some of the technical features disclosed in the examples are summarized below.
(Feature 1) The heterojunction layer preferably includes an electron transit layer made of gallium nitride as a material and an electron supply layer made of aluminum gallium nitride as a material provided on the electron transit layer. Semiconductor material of the electron transit layer, In Xa Ga Ya Al 1- Xa-Ya N (0 ≦ Xa ≦ 1,0 ≦ Ya ≦ 1,0 ≦ Xa + Ya ≦ 1) is It is desirable. The semiconductor material for the electron supply layer, In Xb Ga Yb Al 1- Xb-Yb N (0 ≦ Xb ≦ 1,0 ≦ Yb ≦ 1,0 ≦ Xb + Yb ≦ 1) is It is desirable. Here, (1-Xa-Ya) <(1-Xb-Yb).
(Feature 2) The p-type buried layer preferably has a thickness-decreasing portion whose thickness decreases from the source electrode side toward the drain electrode side.
(Feature 3) A method of manufacturing a semiconductor device includes a removal step of removing a part of the p-type buried layer, and a heat treatment step of heat-treating the buried layer after the removal step. Through the heat treatment process, the end portion of the buried layer is mass transported, and a thickness reduction portion is formed in the buried layer.
(Feature 4) In Feature 3, the method for manufacturing a semiconductor device further includes a step of crystal-growing a semiconductor on the buried layer. The heat treatment step is characterized in that the substrate temperature is set higher than that of the crystal growth step.

  A method for manufacturing a high electron mobility transistor will be described with reference to FIGS. First, as shown in FIG. 1, using a metal organic chemical vapor deposition method, a gallium nitride buffer layer 12, a gallium nitride non-doped semiconductor layer 13, and a gallium nitride p-type are formed on a substrate 11. The buried layer 14 is crystal-grown. Silicon, sapphire, or silicon carbide is used as the material of the substrate 11. The buffer layer 12 is grown at a low temperature and suppresses the propagation of strain between the substrate 11 and the semiconductor layer 13. The semiconductor layer 13 and the buried layer 14 are continuously grown, and are formed by adding p-type impurities to the source gas after crystal growth to a predetermined thickness. Magnesium is used as the p-type impurity. Note that the c-plane is adopted as the growth surface of these crystal growths.

  Next, as shown in FIG. 2, a part of the buried layer 14 is removed and a part of the semiconductor layer 13 is exposed using a dry etching technique. At this time, the side surface 14S having a plane orientation other than the c-plane is exposed at the end of the buried layer 14. In this example, only the buried layer 14 is removed, but a part of the surface portion of the semiconductor layer 13 may be removed if necessary.

  Next, crystal growth is performed from the surfaces of the semiconductor layer 13 and the buried layer 14 using metal organic vapor phase epitaxy. FIG. 3 shows an example of the substrate temperature at this stage. The present embodiment is characterized in that the mass transport phase is performed prior to the vapor phase growth phase. At time t1, the substrate temperature is raised in an ammonia atmosphere. When the substrate temperature reaches A1, the substrate temperature A1 is maintained for a predetermined period (from time t2 to time t3). The substrate temperature A1 is higher than the substrate temperature A2 in the vapor phase growth phase, specifically, preferably 1050 ° C. or higher. Further, the predetermined period (time t2 to time t3) for maintaining the substrate temperature A1 is preferably about 5 minutes or more. When the mass trans phase is completed, as shown in FIG. 4, mass transport is generated at the end of the buried layer 14, and the thickness reducing portion 14 a is formed.

  FIG. 5 shows an enlarged cross-sectional view of the thickness reducing portion 14 a of the buried layer 14. A region 14Oxy surrounded by a broken line in the figure indicates a region where oxygen is introduced. The thickness decreasing portion 14a gradually decreases in thickness from the thickness decreasing start point 14b to the thickness decreasing end point 14d, and an inclined surface 14c is formed. Before the mass transport starts, as shown in FIG. 2, the side surface 14 </ b> S is exposed at the end of the buried layer 14. The side surface 14S is a surface substantially perpendicular to the c-plane, and is, for example, an a-plane or an m-plane. In such a plane orientation, a large amount of oxygen is easily introduced. Therefore, a large amount of oxygen is introduced into the end portion of the buried layer 14 at the initial stage where the mass transport proceeds. When the mass transport progresses and the inclined surface 14c of the thickness reducing portion 14a is flattened so as to gradually approach the c-plane, the amount of oxygen introduced into the end portion of the buried layer 14 decreases.

  FIG. 6 shows an impurity concentration distribution along the line A-A ′ in FIG. 5. This impurity concentration distribution can be observed using SIMS analysis or the like. Magnesium is used for the p-type impurity of the buried layer 14. As shown in FIG. 6, the introduced oxygen concentration has a peak. This peak portion is oxygen introduced into the end portion of the buried layer 14 in the initial stage where the mass transport proceeds. The oxygen concentration in this peak portion is higher than the magnesium concentration. For this reason, a part of the buried layer 14 is n-type. In the thickness reducing portion 14a of the buried layer 14, the oxygen concentration is rapidly reduced. This indicates that the amount of oxygen introduced into the end portion of the buried layer 14 decreased in the later stage where the mass transport progressed. As a result, between the n-type portion and the inclined surface 14c, the magnesium concentration is higher than the oxygen concentration, and this portion is p-type. For this reason, in the thickness reducing portion 14a of the buried layer 14, the n-type portion is not exposed on the inclined surface 14c. Thus, the mass trans phase is continued until the inclined surface of the thickness reducing portion 14a becomes p-type.

  Returning to FIG. When the mass transport phase is completed, the substrate temperature is lowered. When the substrate temperature reaches A2 (time t4), a raw material gas necessary for vapor phase growth is supplied, and crystal growth starts. The substrate temperature A2 is preferably about 1000 to 1050 ° C.

  As shown in FIG. 7, in the vapor phase growth phase, the heterojunction layer 17 is crystal-grown on the surfaces of the semiconductor layer 13 and the buried layer 14. The heterojunction layer 17 includes an electron transit layer 15 and an electron supply layer 16. The electron transit layer 15 is non-doped gallium nitride. The electron supply layer 16 is non-doped aluminum gallium nitride. The composition ratio of aluminum (Al) contained in the electron supply layer 16 is preferably adjusted to about 0.1 to 0.3.

  Next, as shown in FIG. 8, a part of the heterojunction layer 17 on the buried layer 14 is etched to expose a part of the buried layer 14. A base electrode 27 is formed on the exposed surface of the buried layer 14, and a drain electrode 22, a gate portion 25, and a source electrode 22 are formed on the surface of the heterojunction layer 17. The base electrode 27 is in ohmic contact with the buried layer 14. The drain electrode 22 is provided on a part of the surface of the heterojunction layer 17 and is electrically connected to a two-dimensional electron gas layer formed on the heterojunction surface. The source electrode 26 is also provided on a part of the surface of the heterojunction layer 17 and is electrically connected to a two-dimensional electron gas layer formed on the heterojunction surface. The gate portion 25 is provided on a part of the surface of the heterojunction layer, and is disposed between the drain electrode 22 and the source electrode 26. The gate portion 25 has a gate electrode 23 and a gate insulating film 24. The gate electrode 23 faces the two-dimensional electron gas layer formed on the heterojunction surface with the gate insulating film 24 interposed therebetween.

  Through the above steps, the semiconductor device 1 which is a high electron mobility transistor is completed. Hereinafter, the operation of the semiconductor device 1 will be described.

  In the semiconductor device 1, the drain electrode 22 is connected to the positive polarity of the power supply through a load, and the source electrode 26 and the base electrode 27 are short-circuited and fixed to the reference potential (in this example, the ground potential). In the semiconductor device 1, the thickness portion of the buried layer 14, the electron transit layer 15, and the electron supply layer 16 are arranged in this order below the gate portion 25. The p-type buried layer 14 depletes the electron transit layer 15 when no gate-on voltage is applied to the gate electrode 23 of the gate portion 25. For this reason, the semiconductor device 1 is a normally-off type.

  When a voltage higher than the threshold voltage is applied to the gate electrode 23, the semiconductor device 1 is turned on. At this time, a current flows between the drain electrode 22 and the source electrode 26 via the two-dimensional electron gas layer formed on the heterojunction surface of the electron transit layer 15 and the electron supply layer 16. At this time, holes generated when electrons traveling in the two-dimensional electron gas layer collide with surrounding atoms are discharged to the base electrode 27 through the buried layer 14.

  When a voltage lower than the threshold voltage is applied to the gate electrode 23, the electron density in the two-dimensional electron gas layer below the gate electrode 23 decreases, the current flow is interrupted, and the semiconductor device 1 is turned off. When the semiconductor device 1 is turned off, the potential of the drain electrode 22 rises. As described with reference to FIG. 5, the n-type portion formed in the thickness reduction portion 14 a of the buried layer 14 is not exposed from the inclined surface 14 c and is configured to be covered with the buried layer 14. ing. The p-type portion existing between the n-type portion and the inclined surface 14c is electrically connected to the base electrode 27 and is fixed to the reference potential. For this reason, the potential of the n-type portion fluctuates following the potential of the buried layer 14. As a result, since a bias is not substantially applied to the parasitic diode constituted by the n-type portion, the operation of the parasitic diode is suppressed, and an increase in leakage current is suppressed.

Other features of the semiconductor device 1 will be listed.
(1) The thickness reducing portion 14a of the buried layer 14 has a corner that is smoother than that of the conventional one, and the electric field concentration in the portion is relaxed, so that it can be evaluated that the breakdown voltage is further increased.
(2) The material of the buried layer 14 may be gallium nitride containing aluminum. In this case, the concentration of aluminum contained in the buried layer 14 is preferably 1 × 10 20 cm −3 or less. In other words, the molar ratio of aluminum contained in the buried layer 14 is preferably adjusted to 0.00001 to 0.01 with respect to gallium nitride. By including aluminum in gallium nitride, the traveling speed of the mass transport can be reduced. In this case, although the time required for the mass transport phase becomes long, the controllability is greatly improved, and the thickness reducing portion 14a having a desired form can be formed.
(3) Although the semiconductor device 1 is a normally-off type, it may be a normally-on type.

FIG. 9 shows a semiconductor device 2 which is a vertical type high electron mobility transistor. The semiconductor device 2 includes an n-type gallium nitride substrate 111, an n -type gallium nitride semiconductor layer 113, a p-type gallium nitride buried layer 114, and a heterojunction layer 117. The heterojunction layer 117 includes an n -type gallium nitride electron transit layer 115 and an undoped gallium aluminum nitride electron supply layer 116.

  The semiconductor device 2 further includes a drain electrode 122 connected to the back surface of the substrate 111, a base electrode 127 connected to the surface of the buried layer 114, and a source electrode 126 connected to the surface of the heterojunction layer 117. The gate portion 125 connected to the surface of the heterojunction layer 117 is provided. The gate portion 125 includes a gate electrode 123 and a gate insulating film 124.

  Also in the semiconductor device 2, the thickness reducing portion 114 a is formed at the end portion of the buried layer 114. The thickness reducing portion 114a is also created by mass transport by heat treatment, and the portion into which oxygen is introduced at a high concentration is n-type. However, the n-type portion is covered with the p-type portion, and the operation of the parasitic diode is suppressed.

  FIG. 10 shows a JFET type semiconductor device 3. In addition, the same code | symbol is attached | subjected to the component which is common in Example 2, and the description is abbreviate | omitted. As shown in FIG. 10, the surface structure of the semiconductor device 3 is different from that of the semiconductor device 2 of FIG.

The semiconductor device 3 includes an n type high resistance layer 215 provided on the semiconductor layer 113 and the buried layer 114, and an n + type low resistance layer 216 provided on the high resistance layer 215. Yes. The semiconductor device 3 further includes a gate electrode 225 connected to the buried layer 3 and a source electrode 226 connected to the low resistance layer 216.

  Also in the semiconductor device 3, the thickness reducing portion 114 a is formed at the end portion of the buried layer 114. The thickness reducing portion 114a is also created by mass transport by heat treatment, and the portion into which oxygen is introduced at a high concentration is n-type. However, the n-type portion is covered with the p-type portion, and the operation of the parasitic diode is suppressed.

  Specific examples of the present invention have been described in detail above, but these are merely examples and do not limit the scope of the claims. The technology described in the claims includes various modifications and changes of the specific examples illustrated above. In addition, the technical elements described in the present specification or drawings exhibit technical usefulness alone or in various combinations, and are not limited to the combinations described in the claims at the time of filing. In addition, the technology exemplified in the present specification or the drawings can achieve a plurality of objects at the same time, and has technical utility by achieving one of the objects.

13, 113: Semiconductor layers 14, 114: Buried layers 14a, 114a: Thickness reducing portions 15, 115: Electron travel layers 16, 116: Electron supply layers 17, 117: Heterojunction layers

Claims (4)

  1. a nitride semiconductor layer having a c-plane surface;
    A nitride semiconductor p-type buried layer provided on a part of the surface of the semiconductor layer and having a thickness-decreasing portion with a reduced thickness;
    In the buried layer, there is a portion where the oxygen concentration peaks in the thickness reducing portion, and the concentration of the p-type impurity is higher than the oxygen concentration between the peak portion and the inclined surface of the thickness reducing portion. A semiconductor device with a part.
  2. A nitride semiconductor heterojunction layer provided on the semiconductor layer and the buried layer, and forming a heterojunction;
    A source electrode provided in a part on the heterojunction layer;
    A drain electrode provided on a part of the heterojunction layer; and
    2. The semiconductor device according to claim 1, further comprising a gate portion provided on a part of the heterojunction layer and disposed between the source electrode and the drain electrode.
  3. The heterojunction layer has an electron transit layer and an electron supply layer having a wider band gap than the electron transit layer,
    The semiconductor device according to claim 1, wherein the buried layer, the electron transit layer, and the electron supply layer are arranged in this order below the gate portion.
  4. A method for manufacturing the semiconductor device according to claim 1,
    A manufacturing method comprising a step of forming the thickness reduction portion of the buried layer by mass transport by heat treatment.
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270879A (en) * 1985-05-24 1986-12-01 Nec Corp Modulation-doped photo detector
JPH10321646A (en) * 1997-05-20 1998-12-04 Matsushita Electric Ind Co Ltd Field effect-type transistor and its manufacture
JP2000349096A (en) * 1999-06-01 2000-12-15 Matsushita Electric Ind Co Ltd Compound field effect transistor and its manufacture
JP2007103451A (en) * 2005-09-30 2007-04-19 Toshiba Corp Semiconductor device and its manufacturing method
JP2009054685A (en) * 2007-08-24 2009-03-12 Sharp Corp Nitride semiconductor device and power converter including the same
JP2011126745A (en) * 2009-12-18 2011-06-30 Hitachi Cable Ltd Group iii nitride semiconductor substrate and method for producing the same

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61270879A (en) * 1985-05-24 1986-12-01 Nec Corp Modulation-doped photo detector
JPH10321646A (en) * 1997-05-20 1998-12-04 Matsushita Electric Ind Co Ltd Field effect-type transistor and its manufacture
JP2000349096A (en) * 1999-06-01 2000-12-15 Matsushita Electric Ind Co Ltd Compound field effect transistor and its manufacture
JP2007103451A (en) * 2005-09-30 2007-04-19 Toshiba Corp Semiconductor device and its manufacturing method
JP2009054685A (en) * 2007-08-24 2009-03-12 Sharp Corp Nitride semiconductor device and power converter including the same
JP2011126745A (en) * 2009-12-18 2011-06-30 Hitachi Cable Ltd Group iii nitride semiconductor substrate and method for producing the same

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