JP2013090313A - Timing adjustment circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a timing adjustment circuit which is used to adjust timing for a difference in delay time or a deviation in that delay time on a propagation line where a plurality of signals are transferred between modules, packages or circuits, and which can be flexibly adapted to suit the arrangement, path and characteristics of the propagation line, as well as its environment conditions and passage of time.SOLUTION: The timing adjustment circuit comprises: delay means of adding a delay successively to pulse signals received via a first propagation line to generate plural N delay signals; change point discrimination means of latching instantaneous values of the plural N delay signals synchronously with a signal received via a second propagation line which is different from the first propagation line, to discriminate between the leading and the trailing edges in time sequences of the instantaneous values of the plural N delay signals; and selection means of selecting a delay signal among the plural N delay signals which corresponds in the time sequences to the leading or the trailing edge or a point of time closest to the leading or the trailing edge.

Description

  The present invention relates to a plurality of signals delivered between any of modules, packages, and circuits arranged in an electronic device, or between circuits arranged on a semiconductor chip, and propagation used to deliver these signals. The present invention relates to a timing adjustment circuit that adjusts timing in a form suitable for a difference in road delay time and a deviation of the delay time.

  By applying any of the technologies listed below between any of the modules, packages, and circuits provided in the electronic device and between the circuits arranged on the semiconductor chip, An appropriate timing can be set.

(1) When the signal to be delivered is a clock signal and data synchronized with the clock signal, the lengths of the lines (wirings) used for delivering the clock signal and data are the same in advance. Technology set to the value

(2) A technique for resynchronizing the above data with the clock signal via a PLL (Phase Locked Loop) or the like in a signal capturing circuit (hereinafter referred to as “receiving circuit”).

(3) Data is temporarily stored in a buffer memory such as FIFO (First-In First-Out), and among the clock signals with different phases, the data that is read from the buffer memory synchronously is the most probable clock. Technology for identifying signals

In addition, there exist patent document 1 thru | or patent document 6 listed below as a prior art relevant to this invention.
(1) “Two processor modules whose logical functions, physical components, and physical arrangements are substantially the same, and corresponding signals in the two processor modules are detected to detect the coincidence / mismatch of the external signals. The comparison circuit to be output to the same is formed on the same semiconductor chip. Of the two processor modules, the signal path on one processor module side provided close to the comparison circuit is connected to the other By providing a delay means that compensates for the difference in signal propagation delay time between the processor module and the comparison circuit, it is possible to achieve high reliability with an information processing device with a self-diagnosis function in a machine cycle and a simple configuration. Information processing apparatus characterized by ... Patent Document 1

(2) “n AND gates AND0 to AND (n−1) having n OR gates OR0 to OR (n−1) having the same configuration having a gate delay Dr and having the same propagation delay time Dn. ), And the n OR gates are connected to the output of the OR gate adjacent to one input, and the OR gate of the final stage is supplied with an L-level voltage to one input, and the n OR gates The output of the corresponding AND gate is connected to the other input of each of the gates, and path selection signals SEL0 to SEL for selecting a path for generating a delay amount by using a pulse input to the input terminal IN as a trigger. A control circuit that outputs (n−1), and one input of each of the n AND gates and the CLK terminal of the control circuit are commonly connected to the input terminal IN, and the n AND gates are connected. The other input of each node is connected to the corresponding path selection signal output terminal of the control circuit ”, so that“ the number of stages of the circuit element generating the OFFSET TPD is made constant regardless of the number of selected paths ”. Some variable delay circuit ... Patent Document 2

(3) “a plurality of delay elements connected in series and having a predetermined propagation delay time between input and output, and selection means for selecting an output from an arbitrary delay element among the delay elements for an input signal; A delay circuit having temperature compensation means for performing temperature compensation by controlling a delay amount of the delay circuit based on a relationship between the input signal and the output selected by the selection means. By observing changes in the signal transit time of the delay element due to fluctuations, the propagation delay time of the signal is accurately recognized, and the temperature compensation of the delay amount in the delay circuit is performed. ” Patent Document 3

(4) “A first variable delay circuit that delays the clock input to the clock input terminal Ai and applies it to the clock output terminal Ci; and the clock input terminal Di is connected to the clock output terminal Ci directly or via an external wiring. And a second variable delay circuit for giving a delay equal to the delay time of the first variable delay circuit to the clock of the clock input terminal Di, and a clock delayed in phase from the clock input to the clock input terminal Ai. The phase of the clock input terminal Bi is compared with the phase of the clock of the clock input terminal Bi and the output of the second variable delay circuit, and the delay times of the first and second variable delay circuits are set so that they are equal. It consists of a phase comparison circuit to be controlled "to reduce the variation in the phase of the clock inside or outside each IC circuit. Characteristic phase compensation circuit ... Patent Literature 4

(5) “A clock generation circuit for receiving a reference clock signal and generating an internal clock signal synchronized with the reference clock signal, coupled to the clock generation circuit, for supplying an operating power supply voltage to the clock generation circuit Provided separately from a clock power supply circuit, a clock power supply circuit, an internal power supply circuit for generating a power supply voltage, and an internal circuit for performing a predetermined function, and the internal circuit operates a power supply voltage from the internal power supply circuit By including a peripheral circuit that operates as a power supply voltage and operates in synchronization with the internal clock signal, an internal clock signal that is stably phase-synchronized with an external clock signal or a reference clock signal even when the operating environment changes is generated. Synchronous type semiconductor integrated circuit device characterized in that point ... Patent Document 5

(6) In a semiconductor test system for verifying the response output of a DUT by applying a test pattern to a device pin of a device under test (DUT) via the test channel through a plurality of test channels. A plurality of pin cards each having a plurality of pin units forming part of the test channel, and each pin card mounted on the pin card for compensating for an error factor in the pin unit provided in the pin card A non-volatile memory for storing calibration data and a microprocessor provided in each pin card to perform calibration data management and calibration process for all pin units of its corresponding pin card; Each pin unit is configured as an event tester, and the time difference based on the previous event By storing event data that defines the change point of the event in the event memory and generating a test pattern or strobe signal directly with the event data, it is possible to stably output an external clock signal or A semiconductor test system characterized by generating an internal clock signal that is phase-synchronized with a reference clock signal.

JP-A-6-161798 Japanese Patent Laid-Open No. 10-19990 JP-A-10-145198 JP 2000-56854 A JP 2000-163961 A JP 2001-311765 A

By the way, in the electronic devices and semiconductor devices to which the above-described conventional technology is applied, there is a high possibility that performance and reliability are impaired unless the following conditions (1) to (3) are established with high accuracy.
(1) Differences and deviations in propagation delay times of wirings etc. used for transferring data and clock signals are compressed with sufficient accuracy.

(2) These data and clock generation and output source characteristics are set to default values with high accuracy.
(3) The above data and clock generation and output source characteristics are consistent with both aging and fluctuations in environmental conditions such as temperature.

  In addition, these conditions (1) to (3) are factors that hinder the realization of a D / A converter that should operate at a high speed. There has been a strong demand for a technology that can eliminate or greatly alleviate the shift and the restrictions on the layout and wiring on the semiconductor chip.

  However, the above conditions (1) to (3) are actually difficult to realize easily due to restrictions such as cost, mountability, power consumption, thermal design, miniaturization, and weight reduction.

  An object of the present invention is to provide a timing adjustment circuit that can be flexibly and flexibly adapted to the arrangement, path and characteristics of propagation paths, environmental conditions and aging.

  According to the first aspect of the present invention, the delay means sequentially delays the pulse signal given through the first propagation path to generate a plurality of N delayed signals. The change point identifying means latches instantaneous values of the plurality of N delayed signals in synchronization with a signal given via a second propagation path different from the first propagation path, Identifies the leading or trailing edge of the value over time. The selection unit selects a delay signal corresponding to the time series corresponding to a time point closest to the leading edge or the trailing edge or the leading edge or the trailing edge among the plurality of N delayed signals.

  That is, there is a difference or deviation in the propagation delay time between the first propagation path and the second propagation path, and the characteristics of the delay means, change point identification means, and selection means depend on environmental conditions, power supply voltage, aging, etc. Even if the frequency may vary, the deviation on the time axis between the pulse signal and the signal delivered through the first propagation path and the second propagation path, respectively, is greatly complicated. It is stably kept low without becoming.

  In the invention according to claim 2, the delay means sequentially delays the pulse signal given through the first propagation path, and generates a plurality of N delayed signals. The change point identifying means latches the instantaneous values of the plurality of N delayed signals in synchronization with a signal given via a second propagation path different from the first propagation path, and instants the instantaneous signals of the plurality of N delayed signals. Identify the point of change in the time series of values. The selecting means includes a difference in a delay amount to be ensured between the pulse signal and the signal, and a time point closest to the leading edge or the trailing edge or the leading edge or the trailing edge among the plurality of N delay signals. And the delayed signal corresponding to the time series is selected.

  That is, there is a difference or deviation in the propagation delay time between the first propagation path and the second propagation path, and the characteristics of the delay means, change point identification means, and selection means depend on environmental conditions, power supply voltage, aging, etc. Even if the frequency may vary, the deviation on the time axis between the pulse signal and the signal delivered through the first propagation path and the second propagation path, respectively, is greatly complicated. It is stably kept low without becoming.

  In the invention according to claim 3, the delay means sequentially gives a delay in parallel to the plurality of p pulse signals given in parallel through the first propagation path, and generates a plurality of N sets of delay signals. To do. The change point identifying means latches instantaneous values of the plurality of N sets of delayed signals in synchronization with a signal given through a second propagation path different from the first propagation path, and The leading edge or the trailing edge on the time series of the instantaneous values of the N delayed signals is identified in parallel. The selection means selects one delay signal corresponding to the time series in the time point closest to the leading edge or the trailing edge or the leading edge or the trailing edge among the plurality of N sets of the delayed signals.

  That is, there are a plurality of p pulse signals delivered through the first propagation path, and there is a difference or deviation in the propagation delay time between the first propagation path and the second propagation path, and the delay means Even if the characteristics of the change point identification means and the selection means can be changed according to environmental conditions, power supply voltage, aging, etc., they are delivered via these first propagation path and second propagation path, respectively. The deviation on the time axis between the pulse signals to be generated is stably kept low without greatly complicating the configuration.

  In the invention according to claim 4, the delay means sequentially gives a delay in parallel to the plurality of p pulse signals given in parallel via the first propagation path to generate a plurality of N sets of delay signals. To do. The change point identifying means latches instantaneous values of the plurality of N sets of delayed signals in synchronization with a signal given through a second propagation path different from the first propagation path, and The change points on the time series of the instantaneous values of the N delayed signals are identified in parallel. The selection means should be secured between the pulse signal and the signal, and the time point closest to the leading edge or the trailing edge or the leading edge or the trailing edge among the plural N delay signals of the plurality of p sets. One delay signal corresponding to the sum of the difference in delay amount on the time series is selected.

  That is, there are a plurality of p pulse signals delivered through the first propagation path, and there is a difference or deviation in the propagation delay time between the first propagation path and the second propagation path, and the delay means Even if the characteristics of the change point identification means and the selection means can be changed according to environmental conditions, power supply voltage, aging, etc., they are delivered via these first propagation path and second propagation path, respectively. The deviation on the time axis between the pulse signals to be generated is stably kept low without greatly complicating the configuration.

  According to a fifth aspect of the present invention, in the timing adjustment circuit according to the third or fourth aspect, the signal is a plurality of q signals given in parallel via the second propagation path. The change point identifying means latches instantaneous values of a plurality of N delay signals of the plurality of pq sets in synchronization with a signal given via a second propagation path different from the first propagation path, and the plurality of pq A leading edge or a trailing edge on a time series of instantaneous values of a set of a plurality of N delayed signals is identified in parallel. The selection unit selects the one delay signal from the plurality of N delay signals of the plurality of pq sets.

  That is, there are a plurality of pulse signals and signals delivered through the first propagation path and the second propagation path, respectively, and the propagation between the first propagation path and the second propagation path. Even if there is a difference or deviation in the delay time and the characteristics of the delay means, change point identification means and selection means can change according to environmental conditions, power supply voltage, aging, etc., these first propagations The deviation on the time axis between the pulse signal and the signal delivered through the path and the second propagation path, respectively, is stably kept low without greatly complicating the configuration.

In systems, devices, circuits, and semiconductor devices to which the present invention is applied, desired performance, characteristics, and functions are maintained at low cost and in a favorable manner.
Therefore, in the system, apparatus, circuit, and semiconductor device to which the present invention is applied, high performance and reliability are realized without being restricted by restrictions on mounting, layout, and cost.

It is a figure which shows one Embodiment of this invention. It is an operation | movement timing chart of this embodiment. It is the other aspect of the structure of this embodiment.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
FIG. 1 is a diagram showing an embodiment of the present invention.
In the figure, the first block 10 and the second block 20 are arranged on a common semiconductor chip.

  A first circuit (hereinafter referred to as “transmission side circuit”) 11 is arranged in the first block 10, and a clock signal is input to a clock terminal of the transmission side circuit 11. Further, a data signal indicating a serial bit string synchronized with the clock signal is output to the output of the transmission side circuit 11. Such a data signal is transmitted through a first propagation path (hereinafter referred to as “data propagation path”) 31 formed on a common semiconductor chip together with the first block 10 and the second block 20. Is delivered to block 20.

  Further, like the first propagation path 31, the clock signal is supplied to a second propagation path 32 (hereinafter referred to as “clock propagation” formed on a common semiconductor chip together with the first block 10 and the second block 20. It is referred to as a “road”)) 32 and delivered to the second block 20.

On the other hand, the following elements are arranged in the second block 20.
(1) A second circuit (hereinafter referred to as “reception side circuit”) 21 that performs predetermined processing on the data signal delivered via the data propagation path 31.
(2) Non-inverting gates 22-1 to 22 -N that are cascade-connected over a predetermined number of stages N (≧ 2) and that have received a clock signal delivered via the clock propagation path 32 as the first stage.

(3) D-type flip-flops in which the D terminals are connected to the outstanding outputs of the non-inverting gates 22-1 to 22 -N, respectively, and the data signal delivered via the data propagation path 31 is commonly connected to the clock terminal 23-1 to 23-N
(4) A decoder 24 having individual input terminals connected to the non-inverted outputs Q of these D-type flip-flops 23-1 to 23-N, respectively.

(5) A control terminal connected to the output of the decoder 24, first to Nth terminals individually connected to the outputs of the non-inverting gates 22-1 to 22-N, and these first to Nth terminals. A selector 25 which can be connected to any of the terminals and has a common contact connected to the clock terminal of the receiving circuit 21.

FIG. 2 is an operation timing chart of the present embodiment.
The operation of this embodiment will be described below with reference to FIGS.
The transmission side circuit 11 generates a data signal synchronized with the clock signal and delivers the data signal to the second block 20 via the data propagation path 31. In the following, it is assumed that the data signal is generated as an RZ signal.

  Further, the clock signal is input to the second block 20 via the clock propagation path 32 while being input to the transmission side circuit 11.

  In the second block 20, the non-inverting gates 22-1 to 22-N are provided with different delay times on the time axis by sequentially giving N delays to the clock signal over N stages. Clock signals (hereinafter referred to as “first to Nth clock signals”) are generated.

The D-type flip-flops 23-1 to 23-N latch the logical values V _{1 to} V _N of the _{first to N-th} clock signals at the time of rising of the data signal input to the receiving circuit 21.

The decoder 24 decodes the combination of these logical values V _{1 to} V _N (performs correlation determination with the duty ratio and cycle of the clock signal), and rises (falls) when all of the following requirements are satisfied. Identify a specific clock signal (output by any of the non-inverting gates 22-1 through 22-N).

(1) Rise after the time point (FIG. 2 (1)) when the logical value d of the data signal changes from “0” to “1” on the time series (sequence at the rising edge of the clock signal) ( Figure 2 (2)).
(2) A setup time tsup to be secured for the reception side circuit 21 to capture the data signal with high accuracy is secured (FIG. 2 (3)).

  The selector 25 is output by any one of the non-inverting gates 22-1 to 22-N corresponding to the time point identified in this way (hereinafter referred to as “specific non-inverting gate”). The clock signal to be received (hereinafter referred to as “specific clock signal”) is selected and applied to the reception side circuit 21.

  That is, the receiving circuit 21 has a difference or deviation in the propagation delay time between the data propagation path 31 and the clock propagation path 32, or the propagation delay time varies according to temperature, power supply voltage, aging, etc. Even in this case, the clock signal synchronized with the data signal with high accuracy is stably supplied from the first block 10.

Therefore, according to the present embodiment, the reception-side circuit 21 can perform desired processing on the data signal with high accuracy and stability regardless of the following items.
(1) Arrangement of the first block 10 (transmission side circuit 11) and the second block 20 (reception side circuit 21) on the semiconductor chip
(2) Arrangement, characteristic difference and deviation between data propagation path 31 and clock propagation path 31
(3) Characteristics of circuits and elements arranged in the first block 10 and the second block 20, respectively, and deviations of these characteristics

  Further, according to the present embodiment, the restrictions on the above (1) to (3) are greatly relaxed compared to the conventional example, and the configuration is made without providing a PLL circuit or FIFO having a relatively large circuit scale. Therefore, it can be flexibly applied to various devices and systems without being restricted by cost, mountability, power consumption, thermal design, miniaturization, weight reduction, and the like as compared with the conventional example.

  It should be noted that the present invention is similarly applicable even when the above-described data signal is delivered via a plurality of p data propagation paths.

In such a case, the present embodiment is not limited to the configuration shown in FIG. 1 and may be configured as follows, for example, as shown in FIG.
(1) Instead of the timing decoder indicated by the two-dot chain line in FIG. 1, a plurality of timing decoders 20TD-1 to 20TD-p individually corresponding to the plurality of p data propagation paths are provided.

(2) A selector 25A having Np contacts individually corresponding to the “first to Nth clock signals” respectively output by the timing decoders 20TD-1 to 20TD-p is a selector 25 shown in FIG. It is provided instead of.

(3) By comprehensively considering the clock signals individually identified by the timing decoders 20TD-1 to 20TD-p, the Np clock signals (output by the timing decoders 20TD-1 to 20TD-p, respectively) Among the first to Nth clock signals), a specific clock signal to be delivered to the second circuit 21 is specified, and an overall determination unit 20TJ that instructs the selector 25A is provided.

  Further, in the present embodiment, the clock signal described above may be p synchronization signals synchronized with units of words, bytes, characters, and the like to be delivered via a plurality of p data propagation paths.

  Further, in the present embodiment, a clock signal that is synchronized with the data signal and has an appropriate rising edge is supplied to the reception side circuit 21.

  However, the present invention is not limited to such a configuration. For example, in order to provide the receiving circuit 21 with a data signal that is synchronized with a clock signal and has an appropriate time at the leading edge (rear edge). It is applicable to.

  Furthermore, the present invention is not limited to the delivery of digital signals between different circuits (blocks) arranged on a semiconductor chip, and can be applied to delivery of various digital signals between any of the following, for example. It is.

(1) Between different circuits placed on a common printed circuit board as a component of a module or package
(2) Between different modules and packages placed on a common shelf or device as a component of a shelf or rack

  In the present embodiment, the data signal is delivered from the transmission side circuit 11 to the reception side circuit 21 as an RZ signal synchronized with the clock signal.

  However, the present invention is similarly applicable even when such a data signal is an NRZ signal or a split phase signal (Manchester code) instead of the RZ signal described above.

Furthermore, this embodiment is not limited to the structure shown in FIG. 1 or FIG. 3, For example, you may be comprised so that all of the matters listed below or arbitrary ones may apply.
(1) 1 (p) sets of “first to Nth clock signals” given to the contacts of the selector 25 (25A) are individually provided in the timing decoder shown in FIG. 1 or 3 and cascaded. The N-stage non-inverting gate is provided separately from the N-stage non-inverting gate.

(2) The delay amount of each stage of “N stage non-inverted gates individually provided and cascaded in the timing decoders 20TD-1 to 20TD-p shown in FIG. 3” is set in common, and the selector 25A is replaced with the selector 25 shown in FIG. 1, and the first to Nth clock signals supplied to the selector 25 are N stages provided in any one of the timing decoders 20TD-1 to 20TD-p. Of the non-inverting gate.

(3) Any of the N-stage non-inverting gates described in (1) and (2) above has a common delay amount (not necessarily constant) in the cascade connection order.

  In the present embodiment, the target of delivery from the first block 10 to the second block 20 is the above-described data signal and a clock signal that is a reference for bit synchronization with the data signal.

  However, the present invention is not limited to such a pair of a data signal and a clock signal. The synchronization relationship between the data signal and the clock signal is ensured with a desired accuracy, and various signals to be delivered (some are analog signals). Or includes a signal in which an analog signal is superimposed on a digital signal).

  Further, in the present embodiment, the duty ratio of the clock signal may not be 50% as shown in FIG. 2, and the decoding process performed by the decoder provided in each timing decoder and the clock signal based on the decoding process are performed. As long as it is possible to identify these, any may be used.

  Further, the present invention is not limited to the above-described embodiments, and various configurations of the embodiments are possible within the scope of the present invention, and any improvements may be made to all or some of the components.

10 First block 11 First circuit (transmission side circuit)
20 Second block 20TD Timing decoder 20TJ Comprehensive determination unit 21 Second circuit (reception side circuit)
22 Non-inverting gate 23 D-type flip-flop 24 Decoder 25, 25A Selector 31 Data propagation path 32 Clock propagation path

Claims (5)

Delay means for sequentially giving a delay to the pulse signal given through the first propagation path, and generating a plurality of N delayed signals;
The instantaneous values of the N delayed signals are latched in synchronization with a signal given via a second propagation path different from the first propagation path, and the instantaneous values of the N delayed signals on the time series Change point identifying means for identifying the leading or trailing edge;
Selecting means for selecting a corresponding delay signal on the time series at a point of time closest to the leading edge or the trailing edge or the leading edge or the trailing edge among the plurality of N delayed signals. Timing adjustment circuit. Delay means for sequentially giving a delay to the pulse signal given through the first propagation path, and generating a plurality of N delayed signals;
The instantaneous values of the N delayed signals are latched in synchronization with a signal given via a second propagation path different from the first propagation path, and the instantaneous values of the N delayed signals on the time series A change point identifying means for identifying the change point;
Among the plurality of N delay signals, the sum of the leading edge or trailing edge or the time closest to the leading edge or trailing edge and the difference in delay amount to be ensured between the pulse signal and the signal. And a selection means for selecting a delay signal corresponding to the time series. Delay means for sequentially giving a delay in parallel to a plurality of p pulse signals given in parallel via the first propagation path, and generating a plurality of N sets of delay signals;
Latching instantaneous values of the plurality N of delay signals of the plurality of p sets in synchronization with a signal given via a second propagation path different from the first propagation path, and delaying the plurality of N delay signals of the plurality of p sets Change point identifying means for identifying the leading edge or the trailing edge in parallel on the time series of instantaneous values of
Selecting means for selecting one delay signal corresponding to the time series closest to the leading edge or the trailing edge or the leading edge or the trailing edge, among the plurality of N sets of the delayed signals. A timing adjustment circuit characterized by that. Delay means for sequentially giving a delay in parallel to a plurality of p pulse signals given in parallel via the first propagation path, and generating a plurality of N sets of delay signals;
Latching instantaneous values of the plurality N of delay signals of the plurality of p sets in synchronization with a signal given via a second propagation path different from the first propagation path, and delaying the plurality of N delay signals of the plurality of p sets Change point identifying means for identifying change points on the time series of instantaneous values in parallel,
The difference in delay amount to be ensured between the leading edge or trailing edge or the time point closest to the leading edge or trailing edge, and the pulse signal and the signal, among the plurality of p sets of the plurality of N delay signals And a selection means for selecting one delay signal corresponding to the time series in the sum of the timing and the timing adjustment circuit. In the timing adjustment circuit according to claim 3 or 4,
The signal is
A plurality of q signals given in parallel via the second propagation path;
The change point identifying means includes
The instantaneous values of the plurality of N delay signals of the plurality of pq sets are latched in synchronization with a signal given through a second propagation path different from the first propagation path, and the plurality of N delay signals of the plurality of pq sets are latched. Identify the leading or trailing edge of the instantaneous value of the time series in parallel,
The selection means includes
The timing adjustment circuit, wherein the one delay signal is selected from the plurality of N delay signals of the plurality of pq sets.