JP2013058947A - Clock oscillation circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock oscillation circuit which is configured to trim an oscillation frequency, and can reduce variations in the oscillation frequency due to characteristics of a CR oscillation circuit.SOLUTION: A clock oscillation circuit includes: an oscillation section 101 for generating a clock signal of an oscillation frequency depending on a frequency adjustment code; an OSC clock counter 102 for counting the oscillation frequency of the oscillation section 101; a reference clock counter 103 for counting an oscillation frequency of an externally connected crystal oscillator; a comparison circuit 104 for comparing both oscillation frequencies; and a search circuit 105 for automatically searching for the frequency adjustment code. In a frequency adjustment operation, the search circuit 105 repeatedly sets the frequency adjustment code in the oscillation section 101 and updates the frequency adjustment code in accordance with the result of comparison by the comparison circuit 104 to thereby automatically search for the frequency adjustment code.

Description

  The present invention relates to a clock oscillation circuit, and more particularly to a clock oscillation circuit having a function of trimming an oscillation frequency.

  As a device for generating an operation clock such as a CPU (Central Processing Unit), there are a ceramic resonator, a crystal oscillator, and the like. Since these devices have high frequency accuracy but are relatively large in size, they are not suitable for incorporation in small electronic devices such as digital cameras and mobile phones. Therefore, in recent years, a clock oscillation circuit using a relatively small CR oscillation circuit has been put into practical use.

  As an example of the above, an oscillation unit that outputs a clock signal, a frequency measurement circuit that measures the oscillation frequency of the oscillation unit with reference to an externally input calibration clock signal, and an oscillation frequency of the oscillation unit that is adjusted based on the measurement result A clock oscillation circuit including a trimming control circuit has been disclosed and proposed (for example, see Patent Document 1).

JP 2000-341119 A

  However, the CR oscillation circuit tends to vary in oscillation frequency due to device characteristics, temperature conditions, etc., and it cannot be said that the frequency accuracy is high. For this reason, in an electronic device that requires a high-precision oscillation frequency, for example, an adjustment element is provided outside the CR oscillation circuit, or a crystal oscillator or the like is externally connected in the manufacturing stage of the electronic device to perform the frequency adjustment operation. There was a need to go.

  In view of the above-described problems found by the inventors of the present application, the present invention is a clock oscillation circuit that performs trimming of oscillation frequency, and can reduce variations in oscillation frequency due to the characteristics of the CR oscillation circuit. An object is to provide a possible clock oscillation circuit.

  To achieve the above object, a clock oscillation circuit according to the present invention includes an oscillation unit that outputs a clock signal having an oscillation frequency corresponding to a frequency adjustment code, a first counter that measures the oscillation frequency of the clock signal, and an external A second counter for measuring an oscillation frequency of a reference clock signal applied thereto, a comparison circuit for comparing a measurement value of the first counter with a measurement value of the second counter, an oscillation frequency of the clock signal, and the reference clock A frequency adjustment code search circuit that automatically searches for the frequency adjustment code while monitoring the output of the comparison circuit so that the oscillation frequency of the signal matches, and a register that stores the frequency adjustment code that has been automatically searched; The oscillation unit is configured to perform the clock according to the frequency adjustment code stored in the register during normal operation. And an oscillation frequency of the clock signal is set according to the frequency adjustment code set by the frequency adjustment code search circuit during the frequency adjustment operation (first configuration). It is said that.

  The clock oscillation circuit having the first configuration controls the oscillation unit so that the frequency adjustment code search circuit stops the output of the clock signal to the outside of the clock oscillation circuit during the frequency adjustment operation. It is preferable to adopt a configuration (second configuration) characterized in that

  The clock oscillation circuit having the second configuration includes: an update operation in which the frequency adjustment code search circuit updates the frequency adjustment code based on an output of the comparison circuit during the frequency adjustment operation; The setting operation for setting the frequency adjustment code in the oscillation unit may be repeated a predetermined number of times (third configuration).

  Further, in the clock oscillation circuit having the third configuration, the oscillation unit sets the oscillation frequency of the clock signal according to the frequency adjustment code of m bits (m is a natural number), and the frequency adjustment code search circuit The configuration is characterized in that the updating operation and the setting operation are repeated m times, and the output of the comparison circuit is reflected in one bit of the frequency adjustment code in one updating operation (fourth operation) Configuration).

  In the clock oscillation circuit having the fourth configuration, the frequency adjustment code search circuit sets a flag that permits the frequency adjustment code to be read after the frequency adjustment code that has been automatically searched is stored in the register. It is preferable to adopt a configuration (fifth configuration).

  According to the present invention, there are two systems, an operation system for performing normal operation and an operation system for performing frequency adjustment operation for performing clock trimming of the oscillation frequency, and a clock that does not require clock trimming during normal operation. An oscillation circuit can be provided.

  Further, according to the present invention, it is possible to provide a clock oscillation circuit capable of avoiding a situation where a clock signal exceeding the operation limit is supplied to an external device of the clock oscillation circuit during the frequency adjustment operation.

1 is a block diagram showing an electronic device including a clock oscillation circuit according to the present invention. The block diagram which shows the clock oscillation circuit which concerns on this invention Schematic diagram showing count timing of oscillation frequency The block diagram which shows the clock oscillation circuit which concerns on other embodiment

<Device configuration>
FIG. 1 is a diagram illustrating an example of an internal configuration of an electronic device including the clock oscillation circuit of the present invention. The electronic device of this configuration example is assumed to be a device that is small enough to be portable and requires high-precision CPU processing, such as a mobile phone or a digital camera.

The electronic apparatus of this configuration example includes a clock oscillation circuit 100, a CPU (Central Processing Unit) 201, a ROM (Read Only Memory) 202, an external I / F 203, and an I ² C bus 204. A crystal oscillator 301 can be externally connected to the clock oscillation circuit 100 as an OSC (Oscillator) used for adjusting the oscillation frequency.

  The crystal oscillator 301 is a device that is temporarily used when the frequency of the clock oscillation circuit 100 is adjusted. Therefore, the crystal oscillator 301 is not connected to the clock oscillation circuit 100 when a general user uses the electronic device including the clock oscillation circuit 100.

  The clock oscillation circuit 100 generates and outputs a clock signal (OSC_CLK) for operating the CPU 201 using a CR oscillation circuit (not shown). The internal configuration of the clock oscillation circuit 100 will be described later.

  The CPU 201 is a logic circuit that performs data arithmetic processing. The CPU 201 transmits a predetermined command to the clock oscillation circuit 100. Receiving this, the clock oscillation circuit 100 performs a frequency adjustment operation and a clock generation operation described later based on the received command.

  The ROM 202 is a non-volatile recording medium that records a system program executed by the CPU 201, various setting information related to the operation of the clock oscillation circuit 100, and the like. Note that the ROM 202 may include a rewritable nonvolatile semiconductor memory.

The external I / F 203 (interface unit) is an interface for communicating with an external device via the I ² C bus 204.

  The crystal oscillator 301 gives EXT_CLK to the clock oscillation circuit 100 when adjusting the oscillation frequency. Note that the oscillation frequency of EXT_CLK is determined in the design stage of the electronic device or the like according to the operation accuracy required of the electronic device. In this embodiment, an oscillation frequency of 4.5 MHz is used as an example.

<Configuration of clock oscillation circuit>
Next, the internal configuration of the clock oscillation circuit 100 will be described with reference to FIG. FIG. 2 is a diagram showing an example of the internal configuration of the clock oscillation circuit of the present invention. The clock oscillation circuit 100 includes an oscillation unit 101, an OSC clock counter 102 (first counter), a reference clock counter 103 (second counter), a comparison circuit 104, a search circuit 105 (frequency adjustment code search circuit), This is a semiconductor integrated circuit device in which a register 106 is integrated.

  Further, the clock oscillation circuit 100 has external terminals T1 to T3 in order to establish an electrical connection with the outside. The external terminal T1 is an input terminal for inputting a reference clock signal (EXT_CLK) generated by the crystal oscillator 301 when adjusting the oscillation frequency. The external terminal T2 is an output terminal of OSC_CLK. The external terminal T3 is an input / output terminal for connecting the register 106 to the CPU 201.

  An input terminal of the oscillation unit 101 is connected to the search circuit 105 and the register 106. The output terminal of the oscillation unit 101 is connected to the OSC clock counter 102. Further, it is connected to the CPU 201 via the external terminal T2. The output terminal of the OSC clock counter 102 is connected to the comparison circuit 104. The input terminal of the reference clock counter 103 is connected to the external terminal T1. The output terminal of the comparison circuit 104 is connected to the search circuit 105. The output terminal of the search circuit 105 is connected to the oscillation unit 101 and the register 106. The input / output terminal of the register 106 is connected to the CPU 201 via the external terminal T3. The output terminal of the register 106 is connected to the oscillation unit 101.

  The oscillation unit 101 includes a CR oscillation circuit (not shown). The oscillation unit 101 changes the oscillation frequency by adjusting the resistance (R) portion of the CR oscillation circuit based on a frequency adjustment code described later. In this embodiment, a CR oscillation circuit composed of an 8-bit R-2R ladder is used. For this reason, 8-bit data is used as the frequency adjustment code.

  The OSC clock counter 102 receives OSC_CLK, which is a clock signal generated by the oscillation unit 101, and counts the oscillation frequency. Then, a signal (CT1) indicating the counted value is sent to the comparison circuit 104.

  The standard clock counter 103 receives EXT_CLK, which is a reference clock signal generated by the crystal oscillator 301, and counts the oscillation frequency. Then, a signal (CT 2) indicating the counted value is sent to the comparison circuit 104.

  The comparison circuit 104 compares CT1 and CT2, and sends a signal (CMP) indicating the comparison result to the search circuit 105. Note that CMP is information indicating the magnitude relationship between CT1 and CT2.

  The search circuit 105 adjusts the oscillation frequency of the oscillation unit 101 so that CT1 and CT2 coincide with each other while referring to the CMP input from the comparison circuit 104. Thus, the frequency adjustment code is searched. The searched frequency adjustment code is stored in the register 106. In this embodiment, since an 8-bit frequency adjustment code is used, search processing is performed by eight comparisons and adjustments. Details of the search process will be described later.

  The register 106 is a volatile recording medium for recording the frequency adjustment code described above. The register 106 stores the frequency adjustment code searched by the search circuit 105 and is read by the CPU 201. Further, the frequency adjustment code searched by the CPU 201 is stored and read by the oscillation unit 101. The oscillating unit 101 sets the oscillating frequency using the frequency adjustment code read from the register 106 during normal operation.

<Operation of clock oscillation circuit>
Next, the operation of the clock oscillation circuit 100 will be described. The clock oscillation circuit 100 according to the present embodiment starts the operation when the electronic device including the clock oscillation circuit 100 is turned on. The operation of the clock oscillation circuit 100 is roughly divided into a frequency adjustment operation and a normal operation. Which operation is performed is determined by, for example, a dip switch electrically connected to the CPU 201 or operation setting information recorded in advance in a flash memory (not shown). First, the frequency adjustment operation will be described.

  The frequency adjustment of the clock oscillation circuit 100 is performed before the electronic device is shipped from the factory. In performing the frequency adjustment operation, first, the crystal oscillator 301 is externally connected to the clock oscillation circuit 100.

  When the power is turned on in this state, the CPU 201 starts a temporary operation based on an unadjusted clock signal input from the oscillation unit 101. It is assumed that the oscillation frequency of the unadjusted clock signal is set in advance so that the CPU 201 does not overclock.

The CPU 201 that has started the provisional operation reads out and executes a frequency adjustment program prepared in advance from the ROM 202. After execution of this program, when an I ² C command including a frequency adjustment code search command is transmitted, the CPU 201 transmits a frequency adjustment code search command to the clock oscillation circuit 100.

  When this frequency adjustment code search command is transmitted from the CPU 201, flag information in a management register (not shown) is rewritten, and a flag indicating the start of frequency adjustment is turned ON.

  The search circuit 105 periodically monitors the management register, and starts the frequency adjustment code search process when detecting that the flag is turned on. This search process is performed by hardware logic.

  When the frequency adjustment code search process is started, the search circuit 105 transmits a setting signal (DI) indicating a test frequency adjustment code (OSC_DI) to the oscillation unit 101. OSC_DI is 8-bit information as in a normal frequency adjustment code, and its initial value is an intermediate value between the maximum value and the minimum value, that is, 0b1000_0000 in binary notation and 0d128 in decimal notation.

  The oscillation unit 101 that has received DI sets OSC_DI for the CR oscillation circuit included in the oscillation unit 101. As a result, the 8-bit R-2R ladder unit included in the CR oscillation circuit is adjusted, and the oscillation frequency of OSC_CLK is determined. The oscillation frequency is set to be higher as OSC_DI is larger and lower as OSC_DI is smaller.

  When the oscillation unit 101 generates OSC_CLK in this state, OSC_CLK is sent to the OSC clock counter 102 and the oscillation frequency is counted. CT1 indicating the count result is sent to the comparison circuit 104.

  In addition, the reference clock counter 103 counts EXT_CLK input from the crystal oscillator 301 via T1. CT 2 indicating the count result is sent to the comparison circuit 104. The timing at which the OSC clock counter 102 and the reference clock counter 103 start counting is synchronized with a trimming start signal (START) generated when the search circuit 105 starts the search process.

  The comparator 104 compares the value of CT1 with the value of CT2, and transmits CMP indicating the comparison result to the search circuit 105. Receiving this, the search circuit 105 determines the most significant bit of OSC_DI to 0 when CMP indicates “CT1> CT2.” Conversely, when CMP indicates “CT1 ≦ CT2”, the most significant bit of OSC_DI is set to 1.

  The target bits whose numerical values are changed according to CMP in this way are hereinafter referred to as comparison bits. The first comparison bit is the most significant bit of OSC_DI, and the second and subsequent comparison bits correspond to the lower bits of the previous comparison bit. That is, the second comparison bit is the sixth bit, and the eighth comparison bit is the zeroth bit.

  When the first comparison is completed, the search circuit 105 moves the comparison bit to the next lower bit. The comparison bit is first set to 1. Therefore, for example, when the first comparison result is “CT1> CT2,” the seventh bit is set to “0” and the sixth bit is set to “1”. (0d63). The search circuit 105 sets this OSC_DI in the oscillation unit 101. Then, generation, counting, and comparison of OSC_CLK are performed again.

  The above repetition is performed 8 times from the 7th bit to the 0th bit. As a result, the finally obtained OSC_DI is stored in the register 106 as a frequency adjustment code. At the same time, the search circuit 105 rewrites flag information in a management register (not shown) and turns on a flag indicating that the frequency adjustment is completed.

  An example showing specific processing timings and numerical values of the above search processing will be described with reference to FIG. 3 is a trimming start signal generated when the search circuit 105 starts the search process.

  END in the lower stage is a trimming stop signal for taking the end timing of frequency adjustment. The trimming stop signal is turned off by the search circuit 105 a predetermined time after the trimming start signal is turned on.

  REF_CNT in the lower stage of END indicates the count number of the reference clock counter 103. The lower VOC_CNT indicates the count number of the OSC clock counter 102. The lowermost OSC_DI is the above-described test frequency adjustment code.

  The reference clock counter 103 of this embodiment starts counting when START is turned on. Then, when REF_CNT reaches 2047, it is reset to 0. When the reference clock counter 103 is reset, the OSC clock counter 102 is also reset at the same timing. The reference clock counter 103 performs counting with 0 to 2047 of REF_CNT as one cycle.

  The OSC clock counter 102 resets and starts counting in synchronization with the reference clock counter 103. However, the count of the OSC clock counter 102 is stopped when REF_CNT becomes 1023, that is, when the count cycle of the reference clock counter 103 is half.

  The OSC clock counter 102 transmits the value of VOC_CNT at the time of stopping the count to the comparator 104 as CT1. At the same time, the reference clock counter 103 transmits the value of REF_CNT (1023) at this point to the comparator 104 as CT2.

  As shown in FIG. 3, a predetermined blank time occurs from when the OSC clock counter 102 is stopped until the next reset is performed. During this time, the comparison / search circuit 105 by the comparator 104 described above. The OSC_DI is updated by, the oscillation frequency of the oscillating unit 101 is set by the updated OSC_DI, and the oscillation unit 101 waits for stability.

  In the example of FIG. 3, first, when the first reset (r1 in the figure) occurs, REF_CNT and VOC_CNT increase with 0 as an initial value. The VOC_CNT at this time is obtained by counting the oscillation frequency of the clock signal generated by the unadjusted oscillation unit 101. When REF_CNT becomes 1023 in this state, counting of VOC_CNT is stopped. However, this count value is discarded because it is not used for frequency adjustment.

  When the first count of VOC_CNT is stopped, the search circuit 105 sets the most significant bit of OSC_DI as a comparison bit. As a result, as indicated by OSC_DI in FIG. 3, the OSC_DI at this time is 0b1000_0000 (0d128).

  Next, when the second reset (r2 in the figure) occurs, REF_CNT and VOC_CNT again increase from zero. When REF_CNT becomes 1023, VOC_CNT becomes 1177. For this reason, the comparison result of the comparison circuit 104 is CT1 (VOC_CNT)> CT2 (REF_CNT). As a result, the seventh bit as the comparison bit is fixed to “0”. Then, the comparison bit is shifted to the lower bit, and OSC_DI becomes 0b0100_0000 (0d64).

  Next, after the third reset (r3 in the figure) occurs, VOC_CNT becomes 1040 when REF_CNT becomes 1023. For this reason, the comparison result of the comparison circuit 104 is CT1> CT2. As a result, the sixth bit, which is the comparison bit, is fixed to “0”. Then, the comparison bit is shifted to the lower bit, and OSC_DI becomes 0b0010_0000 (0d32).

  Next, after the fourth reset (r4 in the figure) occurs, VOC_CNT becomes 982 when REF_CNT becomes 1023. For this reason, the comparison result of the comparison circuit 104 is CT1 ≦ CT2. As a result, the fifth bit, which is the comparison bit, is fixed to “1”. Then, the comparison bit is shifted to the lower bit, and OSC_DI becomes 0b0011_0000 (0d48).

  The above processing is repeated up to the 0th bit. After the ninth reset (r9 in the figure) occurs, VOC_CNT becomes 1022 when REF_CNT becomes 1023. For this reason, the comparison result of the comparison circuit 104 is CT1 ≦ CT2. As a result, the 0th bit, which is a comparison bit, is fixed to “1”. OSC_DI is 0b0011 — 0111 (0d55). This value is stored in the register 106 as the searched frequency adjustment code.

  Note that, since END is ON when REF_CNT becomes 1023 after the ninth reset, the search process is ended, and the counts of the OSC clock counter 102 and the reference clock counter 103 are also stopped.

  As described above, in this embodiment, 0 is set to the comparison bit when the comparison result is CT1> CT2, and 1 is set to the comparison bit when CT1 ≦ CT2. For this reason, it is considered that the smaller the value of the frequency adjustment code obtained by the search process is, the higher the oscillation frequency of the unadjusted oscillation unit 101 is than the target value, that is, it is necessary to lower the oscillation frequency for frequency adjustment.

The frequency adjustment code stored in the register 106 is read by an I ² C command and recorded in a flash memory (not shown) or the like. However, if the management register or the like indicates that the search for the frequency adjustment code has not been completed, reading is not performed even if an I ² C command is received.

  Next, normal operation of the clock oscillation circuit 100 will be described.

  During the normal operation of the clock oscillation circuit 100, the crystal oscillator 301 is not connected to the clock oscillation circuit 100. Further, the OSC clock counter 102, the reference clock counter 103, the comparison circuit 104, and the search circuit 105 do not operate.

When the power is turned on in this state, the CPU 201 starts a temporary operation based on an unadjusted clock signal input from the oscillation unit 101. The CPU 201 that has started the temporary operation reads a program for normal operation from the ROM 202 and executes it. After executing the program, an I ² C command including an instruction to store the searched frequency adjustment code recorded in the flash memory or the like in the register 106 is transmitted to the CPU 201.

When this I ² C command is received via the external I / F 203, the frequency adjustment code is written into the register 106. The oscillation unit 101 reads the frequency adjustment code from the register 106 and sets the frequency adjustment code.

As a result, the 8-bit R-2R ladder unit included in the oscillation unit 101 is adjusted. Then, OSC_CLK is generated in the state after adjustment, and is output to the CPU 201 via the external terminal T2. Thereafter, the CPU 201 performs a normal operation using OSC_CLK.
<Other variations>

  The configuration of the present invention can be variously modified in addition to the above-described embodiment without departing from the gist of the invention. That is, the above-described embodiment is an example in all respects and should not be considered as limiting, and the technical scope of the present invention is not the description of the above-described embodiment, but the claims. It should be understood that all modifications that come within the meaning and range of equivalents of the claims are included.

  For example, in the above-described embodiment, the oscillation unit 101 has one output terminal that outputs OSC_CLK. However, as illustrated in FIG. 4, a plurality of output terminals may be provided. As a result, it is possible to individually control whether the OSC_CLK is output to the OSC clock counter 102 and the CPU 201. The search circuit 105 controls the oscillation unit 101 to output OSC_CLK only to the CPU 201 during normal operation. Further, the search circuit 105 controls the oscillation unit 101 to output OSC_CLK only to the OSC clock counter 102 during the frequency adjustment operation. With the above configuration, for example, it is possible to avoid a situation in which OSC_CLK temporarily exceeds the operation limit clock of the CPU 201 during the frequency adjustment operation, resulting in malfunction of the apparatus.

  In the above embodiment, the 11-bit value (0-2047) is used as REF_CNT, and the intermediate value (1023) is compared with VOC_CNT. However, these specific values can be appropriately changed in the design stage. It is.

  The present invention is a useful technique for improving the accuracy of a clock signal in devices such as a microprocessor, an image processor, a multimedia processor, an IP core, a mobile device, a game machine, and a PDA.

100 Clock Oscillator 101 Oscillator 102 OSC Clock Counter (First Counter)
103 Reference clock counter (second counter)
104 comparison circuit 105 search circuit (frequency adjustment code search circuit)
106 register 201 CPU
202 ROM
203 External I / F
204 I ² C bus 301 crystal oscillator

Claims (5)

An oscillator that outputs a clock signal having an oscillation frequency corresponding to the frequency adjustment code;
A first counter for measuring an oscillation frequency of the clock signal;
A second counter for measuring the oscillation frequency of a reference clock signal applied from the outside;
A comparison circuit for comparing the measured value of the first counter with the measured value of the second counter;
A frequency adjustment code search circuit that automatically searches for the frequency adjustment code while monitoring the output of the comparison circuit so that the oscillation frequency of the clock signal and the oscillation frequency of the reference clock signal match.
A register for storing the frequency adjustment code that has been automatically searched;
Have
The oscillation unit is
During normal operation, set the oscillation frequency of the clock signal according to the frequency adjustment code stored in the register,
In the frequency adjustment operation, an oscillation frequency of the clock signal is set according to the frequency adjustment code set by the frequency adjustment code search circuit. 2. The clock oscillation according to claim 1, wherein the frequency adjustment code search circuit controls the oscillation unit to stop the output of the clock signal to the outside of the clock oscillation circuit during the frequency adjustment operation. circuit. The frequency adjustment code search circuit is configured to update the frequency adjustment code based on the output of the comparison circuit and set the updated frequency adjustment code in the oscillation unit based on the output of the comparison circuit during the frequency adjustment operation. The clock oscillation circuit according to claim 2, wherein the clock oscillation circuit is repeatedly performed a predetermined number of times. The oscillation unit sets an oscillation frequency of the clock signal according to the frequency adjustment code of m bits (m is a natural number),
The frequency adjustment code search circuit repeats the update operation and the setting operation m times, and reflects the output of the comparison circuit in one bit of the frequency adjustment code in one update operation. The clock oscillation circuit according to claim 3. 5. The clock oscillation according to claim 4, wherein the frequency adjustment code search circuit sets a flag for permitting reading of the frequency adjustment code after storing the automatically searched frequency adjustment code in the register. circuit.

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