JP2013038157A - Compound semiconductor substrate - Google Patents

Compound semiconductor substrate Download PDF

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JP2013038157A
JP2013038157A JP2011171737A JP2011171737A JP2013038157A JP 2013038157 A JP2013038157 A JP 2013038157A JP 2011171737 A JP2011171737 A JP 2011171737A JP 2011171737 A JP2011171737 A JP 2011171737A JP 2013038157 A JP2013038157 A JP 2013038157A
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layer
semiconductor
semiconductor layer
compound semiconductor
barrier layer
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Kenichi Eriguchi
健一 江里口
Jun Komiyama
純 小宮山
Koji Oishi
浩司 大石
Yoshihisa Abe
芳久 阿部
Akira Yoshida
晃 吉田
Shunichi Suzuki
俊一 鈴木
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Covalent Materials Corp
コバレントマテリアル株式会社
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Abstract

PROBLEM TO BE SOLVED: To provide a compound semiconductor substrate capable of attaining both the high performance and the high reliability of a semiconductor element while suppressing the film thickness of the entire compound semiconductor layers.SOLUTION: A compound semiconductor substrate includes: a substrate 12 of a silicon single crystal; a first semiconductor layer 16 of a compound semiconductor formed above the substrate; a barrier layer 18 of the compound semiconductor formed on the first semiconductor layer and having larger band-gap energy than the first semiconductor layer; a second semiconductor layer 20 of the compound semiconductor formed on the barrier layer and having smaller band-gap energy than the barrier layer; and a third semiconductor layer 22 of the compound semiconductor formed on the second semiconductor layer and having larger band-gap energy than the second semiconductor layer.

Description

  The present invention relates to a compound semiconductor substrate used for manufacturing a semiconductor element.

  Compound semiconductors such as gallium nitride (GaN) have a wider band gap than silicon (Si), and can be applied to various semiconductor elements, for example, high electron mobility transistors, that is, High Electron Mobility Transistor (HEMT). A great improvement in device characteristics can be expected.

  As a compound semiconductor substrate used for HEMT, for example, there is one in which a plurality of compound semiconductor layers are formed on a Si single crystal substrate. FIG. 5 is a schematic cross-sectional view of a HEMT manufactured using a compound semiconductor substrate which is an example of the prior art.

  In the HEMT shown in FIG. 5, a multilayered intermediate layer (buffer layer) 54, an electron transit layer 56, and an electron supply layer 58 are laminated in this order on a substrate 52 such as silicon (Si) to form a heterojunction structure. Is configured. On the electron supply layer 58, a source electrode 70a, a gate electrode 70b, and a drain electrode 70c are formed. If necessary, a contact layer (not shown) may be formed between the source electrode 70a and the drain electrode 70c and the electron supply layer 58 for the purpose of reducing contact resistance.

  In the HEMT having such a configuration, a two-dimensional electron gas formed immediately below the heterojunction interface between the electron transit layer 56 and the electron supply layer 58 is used as a carrier. When a voltage is applied to the source electrode 70a and the drain electrode 70c and the transistor is operated by the gate electrode 70b, electrons supplied from the source electrode 70a to the electron transit layer 56 move in the two-dimensional electron gas layer at a high speed. It reaches the electrode 70c. At this time, by controlling the voltage applied to the gate electrode 70b and changing the thickness of the depletion layer immediately below the gate electrode 70b, electrons moving from the source electrode 70a to the drain electrode 70c, that is, the drain current can be controlled.

  By the way, in the HEMT, when a high stress electric field is applied, there is a problem that the drain current amount decreases before and after the electric field stress is applied due to a phenomenon called current collapse. This current collapse is considered to be because movement of electrons in the two-dimensional electron gas layer is hindered by an electron trap and other factors when a current is passed through the semiconductor element. Accordingly, various methods have been proposed in the HEMT for effectively reducing the current collapse while maintaining the device performance.

  For example, Patent Document 1 discloses a HEMT that increases the resistance of a buffer layer without reducing current collapse and reduces leakage current generated in the buffer layer. The HEMT includes a low-temperature buffer layer, a buffer layer, an electron transit layer, and an electron supply layer, which are each made of a GaN-based compound semiconductor, stacked in this order on a substrate. Carbon for increasing the resistance is added to the buffer layer, and the added carbon concentration is equal to or lower than the concentration at which current collapse changes rapidly with respect to the carbon concentration, and the breakdown voltage of the HEMT changes rapidly. Concentration or higher. The layer thickness of the electron transit layer is set to be equal to or greater than the thickness at which the current collapse rapidly changes with respect to the layer thickness and equal to or less than the thickness at which the breakdown voltage of the HEMT is rapidly changed.

  Patent Document 2 discloses a semiconductor device having a heterojunction that realizes a normally-off operation and suppresses a current collapse phenomenon. The semiconductor device includes a semiconductor lower layer of gallium nitride (GaN), a semiconductor upper layer of gallium aluminum nitride (AlGaN) provided on the surface of the semiconductor lower layer, and an insulated gate provided on the surface of the semiconductor upper layer. The semiconductor lower layer and the semiconductor upper layer constitute a heterojunction, and the semiconductor upper layer has a δ-doped layer containing magnesium in the intermediate region.

JP 2007-251144 A JP 2009-289826 A

  The technique disclosed in Patent Document 1 optimizes the thickness of the electron transit layer as a method of suppressing current collapse that occurs when a high stress voltage is applied to the electron transit layer. However, in this case, it is inevitable that the electron transit layer becomes thicker than necessary. Therefore, it cannot be said that it is always sufficient to cope with an increase in dislocations and warping due to an increase in the film thickness of the entire compound semiconductor layer.

  The technique disclosed in Patent Document 2 forms a δ-doped layer containing magnesium in an intermediate region as a method for realizing a heterojunction in which current collapse is suppressed. Thereby, it can be said that there is a feature in that the trap that causes the current collapse disappears in the surface layer region of the heterojunction. However, with this method, there is a concern that a sufficient effect cannot be expected for current collapse caused by traps deeper than the surface region of the heterojunction existing in the electron transit layer or the buffer layer.

  The present invention has been made to solve the above technical problem, and provides a compound semiconductor substrate capable of achieving both high performance and reliability of a semiconductor element while suppressing the film thickness of the entire compound semiconductor layer. The purpose is to do.

The compound semiconductor substrate of one embodiment of the present invention includes a silicon single crystal substrate and a compound semiconductor substrate which is formed over the substrate and has a carbon concentration of 1 × 10 18 / cm 3 or more and 1 × 10 21 / cm 3 or less. 1 semiconductor layer, and a compound semiconductor barrier layer formed on the first semiconductor layer, having a carbon concentration of 5 × 10 17 / cm 3 or less and having a larger band gap energy than the first semiconductor layer A second semiconductor layer of a compound semiconductor formed on the barrier layer, having a carbon concentration of 5 × 10 17 / cm 3 or less and having a smaller band gap energy than the barrier layer, and the second semiconductor layer And a third semiconductor layer formed of a compound semiconductor having a band gap energy larger than that of the second semiconductor layer.

  In the compound semiconductor substrate of the above aspect, it is desirable that the first semiconductor layer has a higher resistance than the second semiconductor layer.

  In the compound semiconductor substrate of the above aspect, it is desirable that the first semiconductor layer and the barrier layer, and the barrier layer and the second semiconductor layer are lattice-matched at the respective boundary surfaces.

In the compound semiconductor substrate of the above embodiment, the first semiconductor layer is Al x1 In y1 Ga 1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1 + y1 ≦ 1), and the barrier layer is Al a. In b Ga 1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1), the second semiconductor layer is Al x2 In y2 Ga 1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ x2 + y2 ≦ 1), the third semiconductor layer is Al x3 In y3 Ga 1-x3-y3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1, 0 ≦ x3 + y3 ≦ The compound semiconductor represented by 1) is desirable.

  ADVANTAGE OF THE INVENTION According to this invention, it becomes possible to provide the compound semiconductor substrate which can make high performance and reliability of a semiconductor element compatible, suppressing the film thickness of the whole compound semiconductor layer.

It is a schematic sectional drawing which shows the structure of the compound semiconductor substrate of embodiment. It is a figure which shows the lattice constant and band gap energy of a nitride semiconductor. It is a schematic sectional drawing of HEMT manufactured using the compound semiconductor substrate of embodiment. It is a band figure of HEMT manufactured using the compound semiconductor substrate of an embodiment. It is a schematic sectional drawing of HEMT manufactured using the compound semiconductor substrate which is an example of a prior art.

  Hereinafter, the present embodiment will be described in more detail with reference to the drawings.

(First embodiment)
The compound semiconductor substrate of the present embodiment is a silicon single crystal substrate and a first compound semiconductor formed on the substrate and having a carbon concentration of 1 × 10 18 / cm 3 or more and 1 × 10 21 / cm 3 or less. A semiconductor layer, a barrier layer of a compound semiconductor formed on the first semiconductor layer, having a carbon concentration of 5 × 10 17 / cm 3 or less and having a band gap energy larger than that of the first semiconductor layer, and a barrier layer A second semiconductor layer formed of a compound semiconductor having a carbon concentration of 5 × 10 17 / cm 3 or less and a band gap energy smaller than that of the barrier layer; And a third semiconductor layer of a compound semiconductor having a band gap energy larger than that of the semiconductor layer. The unit of this specification levels is indicated by "/ cm 3" is synonymous with "atoms / cm 3."

  In the present embodiment, a compound semiconductor substrate particularly suitable for manufacturing a HEMT will be described as an example. By using the compound semiconductor substrate of the present embodiment, it is possible to manufacture a HEMT that achieves both high performance and reliability.

  FIG. 1 is a schematic cross-sectional view showing the structure of the compound semiconductor substrate of the embodiment. In the compound semiconductor substrate 10 of the present embodiment, for example, a nitride semiconductor intermediate layer 14 is formed on a silicon (Si) single crystal substrate 12. A first semiconductor layer 16 made of, for example, a nitride semiconductor is formed on the intermediate layer 14.

  On the first semiconductor layer 16, for example, a nitride semiconductor barrier layer 18 having a band gap energy larger than that of the first semiconductor layer 16 is formed. On the barrier layer 18, a second semiconductor layer 20 of, for example, a nitride semiconductor having a band gap energy smaller than that of the barrier layer 18 is formed.

  Further, on the second semiconductor layer 20, a third semiconductor layer 22 of, for example, a nitride semiconductor having a band gap energy larger than that of the second semiconductor layer 20 is formed.

  The intermediate layer 14 is formed for the purpose of suppressing warpage due to a difference in thermal expansion coefficient between the Si single crystal substrate 12 and the first semiconductor layer 16 and a difference in lattice constant, that is, occurrence of misfit dislocation due to lattice mismatch. Also referred to as a buffer layer.

  In general, the intermediate layer 14 has a multilayer structure in which one or more pairs of two or three nitride semiconductor layers are stacked. For example, it is formed by alternately laminating about 5 to 40 layers of a first layer made of single crystal AlN having a thickness of 10 to 50 nm and a second layer made of single crystal GaN having a thickness of 50 to 200 nm. In the present embodiment, the structure of the intermediate layer 14 is not particularly limited. However, the use of the intermediate layer 14 having a multilayer structure is preferable in terms of ease of manufacturing and controllability.

The first semiconductor layer 16 is formed of a compound semiconductor represented by, for example, Al x1 In y1 Ga 1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1 + y1 ≦ 1). For example, GaN. The film thickness is, for example, about 500 to 2000 nm.

  The first semiconductor layer 16 is a high resistance layer containing, for example, carbon (C) as an impurity. The resistance of the first semiconductor layer 16 is higher than the resistance of the second semiconductor layer 20.

And the carbon concentration is 1 × 10 18 / cm 3 or more and 1 × 10 21 / cm 3 or less. In addition to carbon, zinc (Zn), magnesium (Mg), or the like can be used as an impurity. The carbon concentration can be evaluated by using, for example, SIMS (Secondary Ion Mass Spectroscopy).

The barrier layer 18 is formed of a compound semiconductor represented by, for example, Al a In b Ga 1-ab N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1). The composition is designed so that the band gap energy is larger than that of the first semiconductor layer 16.

FIG. 2 is a diagram showing the lattice constant and band gap energy of a nitride semiconductor. For example, when the first semiconductor layer 16 is GaN, the band gap energy is larger than that of the first semiconductor layer 16 by setting Al a Ga 1-a N containing Al (0 <a ≦ 1). It becomes possible to do. The band gap energy can be theoretically obtained if the composition of the compound semiconductor is determined.

The barrier layer 18 is a so-called undoped layer that does not contain impurities, or is a low impurity layer having an impurity concentration of 5 × 10 17 / cm 3 or less. Impurities are, for example, carbon, zinc, and magnesium. The film thickness is, for example, about 5 to 50 nm.

The second semiconductor layer 20 is formed of a compound semiconductor represented by, for example, Al x2 In y2 Ga 1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ x2 + y2 ≦ 1). The composition is designed so that the band gap energy is smaller than that of the barrier layer 18. For example, when the barrier layer 18 is Al a Ga 1-a N (0 <a ≦ 1), the band gap energy can be made smaller than that of the barrier layer 18 by using GaN.

The second semiconductor layer 20 is a so-called undoped layer containing no impurities, or a low impurity layer having an impurity concentration of 5 × 10 17 / cm 3 or less. Impurities are, for example, carbon, zinc, and magnesium. The film thickness is, for example, about 100 to 1000 nm.

  The first semiconductor layer 16 and the second semiconductor layer 20 are preferably compound semiconductors having the same composition from the viewpoint of facilitating the manufacture of the compound semiconductor substrate 10.

The third semiconductor layer 22 is formed of a compound semiconductor represented by, for example, Al x3 In y3 Ga 1-x3-y3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1, 0 ≦ x3 + y3 ≦ 1). The composition is designed so that the band gap energy is larger than that of the second semiconductor layer 20. For example, when the second semiconductor layer 20 is GaN, the band gap energy is larger than that of the second semiconductor layer 20 by setting Al x3 Ga 1-x3 N (0 <x3 ≦ 1) containing Al. It becomes possible to do.

The third semiconductor layer 22 is a so-called undoped layer that does not contain impurities, or is a low impurity layer having an impurity concentration of 5 × 10 17 / cm 3 or less. Impurities are, for example, carbon, zinc, and magnesium. The film thickness is, for example, about 10 to 50 nm.

When the band gap energy of the first semiconductor layer 16 is Eg 1 , the band gap energy of the barrier layer 18 is Eg b , and the band gap energy of the second semiconductor layer 20 is Eg 2 , the difference ΔEgI of the band gap energy. = Eg b −Eg 1 and ΔEg II = Eg b −Eg 2 are desirably 0.5 eV or more, and more desirably 1.0 eV or more.

  Moreover, it is desirable that the first semiconductor layer 16 and the barrier layer 18 and the barrier layer 18 and the second semiconductor layer 20 are lattice-matched at the respective boundary surfaces. In the present specification, the term “lattice matching” does not necessarily mean that the lattice constants of the two layers completely match.

When the lattice constant of the first semiconductor layer 16 is a 1 , the lattice constant of the barrier layer 18 is a b , and the lattice constant of the second semiconductor layer 20 is a 2 , the change in lattice constant ΔaI = (a Even when b− a 1 ) / ab and ΔaII = ( ab− a 2 ) / ab are 1% or less in terms of absolute value, they are considered to be lattice matched. Even in the case of lattice matching, ΔaI = ( ab− a 1 ) / ab , ΔaII = ( ab− a 2 ) / ab is 0.5% or less, and further 0.3% The following is more desirable.

For example, when the first semiconductor layer 16 and the second semiconductor layer 20 are GaN, the first barrier layer 18 is made of Al 0.82 In 0.18 N, for example, as is apparent from FIG. The semiconductor layer 16 and the barrier layer 18, and the barrier layer 18 and the second semiconductor layer 20 can be lattice-matched at the respective boundary surfaces.

  Note that the first semiconductor layer 16 and the barrier layer 18 and the barrier layer 18 and the second semiconductor layer 20 are lattice-matched at the respective boundary surfaces, and the band gap energy of the barrier layer 18 is internal from the boundary surfaces. It is more desirable that it is larger. This structure can be realized by modulating the composition in the thickness direction in the barrier layer 18.

  FIG. 3 is a schematic cross-sectional view of a HEMT manufactured using the compound semiconductor substrate of the embodiment. A source electrode 30a, a gate electrode 30b, and a drain electrode 30c are formed on the third semiconductor layer 22 of the compound semiconductor substrate 10 of the embodiment.

  The second semiconductor layer 20 functions as a so-called electron transit layer. The third semiconductor layer 22 functions as a so-called electron supply layer.

  The first semiconductor layer 16 functions as a so-called breakdown voltage holding layer. As described above, for example, since carbon is introduced as an impurity to form a high resistance layer, the leakage current when the HEMT is turned off is reduced, and a high breakdown voltage and a normally off state are easily realized.

  However, since the impurity is introduced at a high concentration, current collapse may be reduced (deteriorated) due to an electron trap caused by the impurity generated in the first semiconductor layer 16, and the performance may be deteriorated.

FIG. 4 is a band diagram of a HEMT manufactured using the compound semiconductor substrate of the embodiment. E F represents a Fermi level, E V represents a valence band level, and E C represents a conduction band level. As shown in FIG. 4, the band gap energy of the barrier layer is larger than that of the electron transit layer and the breakdown voltage holding layer. In other words, the band gap width of the barrier layer is larger than that of the electron transit layer and the breakdown voltage holding layer.

  For this reason, in the HEMT of FIG. 3, charges such as electron traps in the electron transit layer and the breakdown voltage holding layer are quantum-chemically separated by the barrier layer. For this reason, the probability that the charge of the electron trap that causes current collapse will reach the electron transit layer from the breakdown voltage holding layer is reduced, and the influence of the charge of the electron trap in the breakdown voltage holding layer on the electron transit layer may be blocked. It becomes possible. Therefore, even if the electron transit layer is thin, the occurrence of current collapse can be suppressed. Therefore, it is possible to achieve both high performance and reliability of the HEMT while suppressing the film thickness of the entire compound semiconductor layer. And since the film thickness of the whole compound semiconductor layer can be suppressed, it becomes possible to reduce problems, such as a curvature of a board | substrate, and a manufacturing cost.

Note that, as described above, when the first semiconductor layer 16 serving as the breakdown voltage holding layer contains carbon as an impurity, the carbon concentration is 1 × 10 18 / cm 3 or more and 1 × 10 21 / cm 3 or less. It is desirable. This is because if it falls below this range, the HEMT withstand voltage may not be sufficiently secured. Moreover, it is because it will become difficult to suppress electric current collapse if it exceeds this range.

Further, as described above, the band gap energy of the first semiconductor layer 16 serving as the breakdown voltage holding layer is Eg 1 , the band gap energy of the barrier layer 18 is Eg b , and the band of the second semiconductor layer 20 serving as the electron transit layer. When the gap energy is Eg 2 , the band gap energy differences ΔEgI = Eg b −Eg 1 and ΔEg II = Eg b −Eg 2 are preferably 0.25 eV or more, and 0.5 eV or more. Is more desirable, and it is further desirable that it is 1.0 eV or more. This is because the current collapse suppression effect is improved when the HEMT is manufactured.

  Further, as described above, the first semiconductor layer 16 and the barrier layer 18 serving as the breakdown voltage holding layer, and the second semiconductor layer 20 serving as the barrier layer 18 and the electron transit layer are lattice-matched at the respective boundary surfaces. It is desirable that

  This is because when the HEMT is manufactured by lattice matching of the respective boundary surfaces, generation of electrons derived from piezo polarization at these interfaces can be suppressed, and high breakdown voltage and normally-off can be easily achieved. This is because it can be realized. In addition, the occurrence of dislocations due to lattice mismatch can be suppressed.

  Furthermore, a decrease in mobility can be suppressed. This is because the transition caused by lattice mismatch is prevented from becoming the electron scattering center.

  As described above, according to the compound semiconductor substrate of the embodiment, when a HEMT having a high resistance layer (withstand voltage holding layer) for increasing the breakdown voltage under the electron transit layer is manufactured, the high resistance layer or the like It is possible to suppress current collapse caused by a deep region without unnecessarily increasing the film thickness of the entire compound semiconductor layer. Therefore, it is possible to provide a compound semiconductor substrate that can achieve both high performance and reliability of the semiconductor element at low cost.

  The embodiments of the present invention have been described above with reference to specific examples. The above embodiment is merely given as an example, and does not limit the present invention. Further, in the description of the embodiment, the description of the compound semiconductor substrate, the semiconductor element, etc., which is not directly required for the description of the present invention is omitted, but the required compound semiconductor substrate, the semiconductor element, etc. The elements involved can be appropriately selected and used.

  For example, a spacer layer such as AlN may be formed between the second semiconductor layer serving as the electron transit layer and the third semiconductor layer serving as the electron supply layer.

  Further, for example, a silicon nitride film serving as a protective film may be provided on the third semiconductor layer serving as the electron supply layer.

  Further, in the embodiments, the case where the present invention is used particularly for manufacturing a HEMT has been described as an example. However, the compound semiconductor substrate of the present invention can be applied to manufacturing a semiconductor element other than a HEMT.

  In the embodiment, the GaN-based compound semiconductor has been described as an example. However, other compound semiconductors such as a GaAs-based compound semiconductor can also be used.

  In addition, all compound semiconductor substrates that include the elements of the present invention and that can be appropriately modified by those skilled in the art are included in the scope of the present invention. The scope of the present invention is defined by the appended claims and equivalents thereof.

  EXAMPLES Hereinafter, although this invention is demonstrated further more concretely based on an Example, this invention is not restrict | limited by the following Example.

[Example 1]
First, a compound semiconductor substrate having the layer structure shown in FIG. 1 was produced by the following steps. First, the Si (111) single crystal substrate 12 having a diameter of 4 inches was set in a Metal Organic Chemical Vapor Deposition (MOCVD) apparatus.

Next, an AlN single crystal layer having a thickness of 20 nm was formed by vapor phase growth at 1000 ° C. using trimethylaluminum (TMA) and NH 3 as raw materials. Furthermore, trimethylgallium (TMG), TMA, and NH 3 are used as raw materials, and a GaN single crystal layer having a thickness of 80 nm is stacked by vapor phase growth at 1000 ° C., and these are alternately formed in the same process. Repeatedly, 10 layers each, 20 layers in total, were laminated to form a buffer layer having a multilayer structure, and this was used as the intermediate layer 14.

On the intermediate layer 14, TMG and NH 3 were used as raw materials, and 1000 nm of GaN having a carbon concentration of 5 × 10 20 / cm 3 was deposited as the first semiconductor layer (breakdown voltage holding layer) 16. Further, TMA, trimethylindium (TMI), and NH 3 were used as raw materials, and 10 nm of Al 0.82 In 0.18 N with a carbon concentration of 1 × 10 17 / cm 3 was deposited as the barrier layer 18.

A GaN single crystal having a carbon concentration of 1 × 10 17 / cm 3 is formed on the barrier layer 18 as a second semiconductor layer (electron transit layer) 20 by vapor phase growth at 1000 ° C. using TMG and NH 3 as raw materials. Was laminated to 200 nm. Further, TMG, TMA, NH 3 are used as raw materials, and an Al 0.25 Ga 0.75 N single crystal having a carbon concentration of 1 × 10 17 / cm 3 and a thickness of 30 nm is used as the third semiconductor layer (electron supply layer) 22. The layers were laminated.

  A source electrode 30a, a gate electrode 30b, and a drain electrode 30c are formed on the compound semiconductor substrate using titanium (Ti), aluminum (Al), nickel (Ni), and gold (Au), and the structure shown in FIG. HEMTs were manufactured. The semiconductor element for evaluation of Example 1 was obtained through the above steps. The thickness of each layer formed by vapor phase growth was adjusted by adjusting the amount of raw material supplied and the supply time.

  The collapse factor was evaluated for the semiconductor element for evaluation. In the evaluation, a stress voltage was applied between the source electrode and the drain electrode in the off state, and the collapse factor was calculated from the ratio of the conduction current amount in the on state before and after the stress voltage application. The larger the collapse factor is, the closer the value is to “1.0”, the better the reproducibility of the HEMT output current characteristic and the smaller the current loss. In addition, longitudinal breakdown voltage and leakage characteristics were also evaluated. Table 1 shows the configuration of the evaluation semiconductor element and the evaluation results.

[Example 2]
Example 1 except that TMG, TMA, TMI, and NH 3 are used as raw materials for the barrier layer 18 and that Al 0.7 In 0.1 Ga 0.2 N having a carbon concentration of 1 × 10 17 / cm 3 is deposited to a thickness of 10 nm. A semiconductor element for evaluation was manufactured and evaluated in the same manner as described above. Table 1 shows the configuration of the evaluation semiconductor element and the evaluation results.

[Example 2 ']
As the barrier layer 18, except that TMG, TMA, TMI, and NH 3 are used as raw materials, and Al 0.6 In 0.2 Ga 0.2 N having a carbon concentration of 1 × 10 17 / cm 3 is deposited to 10 nm. In the same manner as in Example 1, a semiconductor element for evaluation was manufactured and evaluated. Table 1 shows the configuration of the evaluation semiconductor element and the evaluation results.

[Comparative Example 1]
An evaluation semiconductor element was manufactured and evaluated in the same manner as in Example 1 except that the barrier layer 18 was omitted. Table 1 shows the configuration of the evaluation semiconductor element and the evaluation results.

[Examples 3-6, Comparative Examples 2-5]
A semiconductor element for evaluation was manufactured and evaluated in the same manner as in Example 1 except that the carbon concentrations of the first semiconductor layer 16, the barrier layer 18, and the second semiconductor layer 20 were changed. Table 2 shows the carbon concentration and evaluation results of the evaluation semiconductor element.

  In the evaluation column of Table 1 and Table 2, ◎ indicates that the evaluation result is particularly good, ○ indicates that it is good, Δ indicates that it is acceptable, and × indicates that it is not possible.

As shown in Table 1, a good collapse factor can be realized according to the embodiment,
It became clear that the leakage characteristics were good. In addition, as shown in Table 2, it was confirmed that the device characteristics were good when the carbon concentrations of the first semiconductor layer, the barrier layer, and the second semiconductor layer were within the range of the examples.

  The present invention is suitably used as a compound semiconductor substrate for manufacturing semiconductor devices.

DESCRIPTION OF SYMBOLS 10 Compound semiconductor substrate 12 Substrate 14 Intermediate | middle layer 16 1st semiconductor layer 18 Barrier layer 20 2nd semiconductor layer 22 3rd semiconductor layer

Claims (4)

  1. A silicon single crystal substrate;
    A first semiconductor layer of a compound semiconductor formed on the substrate and having a carbon concentration of 1 × 10 18 / cm 3 or more and 1 × 10 21 / cm 3 or less;
    A compound semiconductor barrier layer formed on the first semiconductor layer, having a carbon concentration of 5 × 10 17 / cm 3 or less and having a larger band gap energy than the first semiconductor layer;
    A second semiconductor layer of a compound semiconductor formed on the barrier layer, having a carbon concentration of 5 × 10 17 / cm 3 or less and having a smaller band gap energy than the barrier layer;
    A third semiconductor layer formed on the second semiconductor layer and having a larger band gap energy than the second semiconductor layer;
    A compound semiconductor substrate comprising:
  2.   The compound semiconductor substrate according to claim 1, wherein the first semiconductor layer has a higher resistance than the second semiconductor layer.
  3.   3. The compound according to claim 1, wherein the first semiconductor layer and the barrier layer, and the barrier layer and the second semiconductor layer are lattice-matched at respective boundary surfaces. Semiconductor substrate.
  4. The first semiconductor layer is Al x1 In y1 Ga 1-x1-y1 N (0 ≦ x1 ≦ 1, 0 ≦ y1 ≦ 1, 0 ≦ x1 + y1 ≦ 1), and the barrier layer is Al a In b Ga 1-a −b N (0 ≦ a ≦ 1, 0 ≦ b ≦ 1, 0 ≦ a + b ≦ 1), the second semiconductor layer is Al x2 In y2 Ga 1-x2-y2 N (0 ≦ x2 ≦ 1, 0 ≦ y2 ≦ 1, 0 ≦ x2 + y2 ≦ 1), and the third semiconductor layer is represented by Al x3 In y3 Ga 1-x3-y3 N (0 ≦ x3 ≦ 1, 0 ≦ y3 ≦ 1, 0 ≦ x3 + y3 ≦ 1). 4. The compound semiconductor substrate according to claim 1, wherein the compound semiconductor substrate is a compound semiconductor.






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