JP2012504841A5 - - Google Patents
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- JP2012504841A5 JP2012504841A5 JP2011530194A JP2011530194A JP2012504841A5 JP 2012504841 A5 JP2012504841 A5 JP 2012504841A5 JP 2011530194 A JP2011530194 A JP 2011530194A JP 2011530194 A JP2011530194 A JP 2011530194A JP 2012504841 A5 JP2012504841 A5 JP 2012504841A5
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Claims (10)
- メモリ・デバイスの少なくとも１つの軟データ値を生成する方法であって、
少なくとも１つの硬読取値を入手するステップと、
該硬読取値を読み取るための統計に基づいて該少なくとも１つの硬読取値に関連する該軟データ値を生成するステップとを含む方法。
- 請求項１に記載の方法において、
該硬読取値は、データ・ビット、電圧レベル、電流レベル、及び抵抗レベルのうちの１つ又は複数を含む方法。
- 請求項１に記載の方法において、
該軟データ値は、（ｉ）１つ又は複数の対数尤度比を生成するのに使用される軟読取値、及び（ｉｉ）１つ又は複数の対数尤度比、のうちの１つ又は複数を含む方法。
- 請求項１に記載の方法において、
該統計は、ビット・ベースの統計、セル・ベースの統計、及びパターン依存統計のうちの１つ又は複数を含む方法。
- 請求項４に記載の方法において、
１つ又は複数の可能なレベルＬＶＬｗｒｉｔに関する該セル・ベースの統計は、該書込レベルＬＶＬｗｒｉｔが書き込まれたか復号された時にレベルＬＶＬｒｅａｄが読み取られた確率に基づく方法。
- 請求項１に記載の方法において、
該統計は、ターゲット・セルに対する少なくとも１つのアグレッサ・セルのパターン依存外乱を含む方法。
- 請求項６に記載の方法において、
１つ又は複数の識別されたパターンに関する及び１つ又は複数の可能な基準レベルＬＶＬｒｅｆに関する該パターン依存統計は、該基準レベルＬＶＬｒｅｆが復号されたか書き込まれた時にレベルＬＶＬｒｅａｄが読み取られた確率に基づく方法。
- 請求項６に記載の方法において、
１つ又は複数の識別されたパターンに関する及び１つ又は複数の可能な読取レベルＬＶＬｒｅａｄに関する該パターン依存統計は、該読取レベルＬＶＬｒｅａｄが読み取られた時に基準レベルＬＶＬｒｅｆが復号されたか書き込まれた確率に基づく方法。
- 請求項１に記載の方法において、
該統計は、位置固有統計を含み、該軟データ値は、該メモリ・デバイスの所望の位置について生成される方法。
- メモリ・デバイスの少なくとも１つの軟データ値を生成する方法であって、
軟読取値を入手するステップと、
該軟読取値を読み取るための統計に基づいて該軟読取値に関連する該軟データ値を生成するステップであって、該統計は、位置固有統計及びパターン依存統計のうちの１つ又は複数を含む、生成するステップとを含む方法。
Applications Claiming Priority (5)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US19475108P | 2008-09-30 | 2008-09-30 | |
| US61/194,751 | 2008-09-30 | ||
| PCT/US2009/049333 WO2010002948A1 (en) | 2008-07-01 | 2009-06-30 | Methods and apparatus for soft demapping and intercell interference mitigation in flash memories |
| USPCT/US2009/049333 | 2009-06-30 | ||
| PCT/US2009/059077 WO2010039866A1 (en) | 2008-09-30 | 2009-09-30 | Methods and apparatus for soft data generation for memory devices |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2012504841A JP2012504841A (ja) | 2012-02-23 |
| JP2012504841A5 true JP2012504841A5 (ja) | 2012-11-22 |
| JP5590620B2 JP5590620B2 (ja) | 2014-09-17 |
Family
ID=42073862
Family Applications (4)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011530194A Expired - Fee Related JP5590620B2 (ja) | 2008-09-30 | 2009-09-30 | メモリ・デバイスの軟データ生成の方法および装置 |
| JP2011530196A Expired - Fee Related JP5535220B2 (ja) | 2008-09-30 | 2009-09-30 | デコーダ性能フィードバックを使用するメモリ・デバイス用の軟データ生成の方法および装置 |
| JP2011530193A Pending JP2012504820A (ja) | 2008-09-30 | 2009-09-30 | 性能要因調整に基づくメモリ・デバイスの軟データ生成の方法および装置 |
| JP2011530195A Expired - Fee Related JP5535219B2 (ja) | 2008-09-30 | 2009-09-30 | 基準セルを使用する、メモリ・デバイスの軟データ生成の方法および装置 |
Family Applications After (3)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2011530196A Expired - Fee Related JP5535220B2 (ja) | 2008-09-30 | 2009-09-30 | デコーダ性能フィードバックを使用するメモリ・デバイス用の軟データ生成の方法および装置 |
| JP2011530193A Pending JP2012504820A (ja) | 2008-09-30 | 2009-09-30 | 性能要因調整に基づくメモリ・デバイスの軟データ生成の方法および装置 |
| JP2011530195A Expired - Fee Related JP5535219B2 (ja) | 2008-09-30 | 2009-09-30 | 基準セルを使用する、メモリ・デバイスの軟データ生成の方法および装置 |
Country Status (8)
| Country | Link |
|---|---|
| US (4) | US8892966B2 (ja) |
| EP (4) | EP2340539A1 (ja) |
| JP (4) | JP5590620B2 (ja) |
| KR (3) | KR101758192B1 (ja) |
| CN (4) | CN102171767A (ja) |
| IL (4) | IL211895A0 (ja) |
| TW (4) | TWI562151B (ja) |
| WO (4) | WO2010039869A1 (ja) |
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