JP2012230173A - Display apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent deterioration of continuation of a polarity inversion pattern for each split screen in the case where one liquid crystal display panel is divided in two or more screens by a plurality of video line drive circuits and is driven.SOLUTION: The number of pixels in one horizontal line of each sub-display panel is represented by PL. The number of pixels to which a video voltage of positive polarity is input subsequent to a pixel to which a video voltage of negative polarity is input on one horizontal line is represented by PP. The number of pixels to which a video voltage of negative polarity is input subsequent to a pixel to which a video voltage of positive polarity is input is represented by PN. A display apparatus includes: an inversion circuit for inverting an AC signal in the case where PL is not dividable by (PP+PN) and is dividable by (PP+PN)/2; and a selector to which an AC signal and the AC signal inverted by the inversion circuit are input. On the basis of the selector controlled by a selection signal, an AC signal or the AC signal inverted by the inversion circuit is selected, and the selected AC signal is input to a video line drive circuit that inputs a video voltage to the pixels of the sub-display panel.

Description

  The present invention relates to a display device, and more particularly to a technique effective when a liquid crystal display panel is divided and driven by a plurality of video line driving circuits.

A TFT liquid crystal display module using a thin film transistor as an active element can display a high-definition image, and is therefore used as a display device such as a television or a personal computer display.
In general, in a liquid crystal display module, an area surrounded by two adjacent scanning lines (also referred to as gate lines) and two adjacent video lines (also referred to as source lines or drain lines) is separated from the scanning lines. A so-called pixel (sub-pixel) is formed by forming a thin film transistor that is turned on by the scanning signal and a pixel electrode to which the video signal from the video line is supplied via the thin film transistor.

JP-A-5-35216

However, when one liquid crystal display panel is divided into two or more screens and driven by a plurality of video line driving circuits, the number of pixels on one horizontal line per one divided screen is the complete cycle of liquid crystal polarity inversion described later. When it is not divisible, the continuity of the polarity inversion pattern for each divided screen is impaired.
As a result, there is a problem that VCOM adjustment to be input to the counter electrode cannot be performed because a line is visible at the boundary of the divided screen, or flicker does not occur on the screen when inspecting with an existing killer pattern.
The present invention has been made to solve the problems of the prior art, and an object of the present invention is to drive one liquid crystal display panel by dividing it into two or more screens by a plurality of video line driving circuits. Another object of the present invention is to provide a technique capable of preventing the continuity of the polarity reversal pattern for each divided screen from being impaired.
The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

Of the inventions disclosed in this application, the outline of typical ones will be briefly described as follows.
(1) A display device including a display panel having a plurality of pixels, wherein the display panel is divided into at least two sub display panels, and is provided for each of the sub display panels. At least one video line driving circuit that inputs a positive video voltage and a negative video voltage to each pixel based on the AC signal, and generates the AC signal, and is provided for each sub-display panel. A sub-display panel having a first pixel on one horizontal line among the at least two sub-display panels. A, a sub display panel other than the sub display panel A is a sub display panel B, and the number of pixels of one horizontal line of each sub display panel is PL, and a negative video voltage is input on one horizontal line. PL, where PP is the number of pixels to which a positive video voltage is input continuously and PN is the number of pixels to which a negative video voltage is input continuously. Is indivisible by (PP + PN) and when PL is divisible by (PP + PN) / 2, the inverter circuit for inverting the AC signal, and the AC signal inverted by the AC signal and the inverter circuit A selector to which a signal is input, and based on the selector controlled by a selection signal, the alternating signal or the alternating signal inverted by the inverting circuit is selected, and the sub display panel B A video voltage is inputted to a pixel and inputted to a video line driving circuit.

(2) In (1), a control circuit for transferring display data to a video line driving circuit provided for each of the sub-display panels is provided. The alternating signal generating circuit, the inverting circuit, and the selector The selection signal is generated by the alternating signal generation circuit.
(3) A display device including a display panel having a plurality of pixels, wherein the display panel is divided into at least two sub display panels, and is provided for each of the sub display panels. At least one video line driving circuit that inputs a positive video voltage and a negative video voltage to each pixel based on the AC signal, and generates the AC signal, and is provided for each sub-display panel. And an alternating-current signal generation circuit for inputting to the video line driving circuit, wherein the number of pixels of one horizontal line of each sub display panel is PL, and a pixel to which a negative video voltage is input on one horizontal line When PP is the number of pixels to which a positive video voltage is input continuously and PN is the number of pixels to which a negative video voltage is input consecutively to pixels to which a positive video voltage is input, PL is ( Divided by PP + PN) If the non, wherein the AC signal generating circuit, provided the every sub-panel video line drive circuit provided for each.

(4) A display device comprising a display panel having a plurality of pixels and a plurality of video lines for inputting a video voltage to each pixel, wherein the display panel is divided into at least two sub display panels. And at least one video line that is provided for each sub display panel and supplies a positive video voltage and a negative video voltage to the plurality of video lines of each sub display panel based on an alternating signal. A driving circuit; and an AC signal generating circuit that generates the AC signal and inputs the AC signal to the video line driving circuit provided for each of the sub display panels, and includes one horizontal line of each sub display panel. The number of pixels is PL, and the number of pixels to which the positive video voltage is input is continuous to the pixels to which the negative video voltage is input on one horizontal line. Negative video voltage When PL is not divisible by (PP + PN) when the number of pixels to be applied is PN, among the at least two sub display panels, sub display panels A and B are sub-display panels that are consecutive to each other. A dummy terminal that is not electrically connected to any of the plurality of video lines of the sub display panel B is provided on the sub display panel A side of the video line driving circuit provided for each sub display panel B. A pixel to which a video voltage is supplied from a video line connected to a terminal of a video line driving circuit provided for each sub display panel A at a boundary between the sub display panel A and the sub display panel B; The polarity inversion of the video voltage input to the pixel to which the video voltage is supplied from the video line connected to the terminal of the video line driving circuit provided for each sub display panel B is continued. Determining the number of dummy terminals of the video line driver circuit provided for each of the sub-display panel B.

(5) In (3) or (4), a control circuit for transferring display data to a video line driving circuit provided for each of the sub display panels is provided, and the AC signal generation circuit is provided in the control circuit. Placed in.
(6) In (4), the video line drive circuit provided for each of the sub display panels B includes a control circuit for transferring display data to the video line drive circuit provided for each of the sub display panels. The dummy display data for the dummy terminal is inserted into the display data transferred from the control circuit.
(7) In (4), there is provided a control circuit for inputting display data to a video line driving circuit provided for each of the sub display panels, and the control circuit has a video provided for each of the sub display panels B. Dummy display data for a dummy terminal of the video line driving circuit provided for each of the sub display panels B is inserted into display data to be transferred to the line driving circuit.

The effects obtained by the representative ones of the inventions disclosed in the present application will be briefly described as follows.
According to the present invention, when one liquid crystal display panel is divided into two or more screens and driven by a plurality of video line driving circuits, it is possible to prevent the continuity of the polarity inversion pattern for each divided screen from being impaired. It becomes.

It is a block diagram which shows schematic structure of the liquid crystal display device used as the premise of this invention. It is a figure which shows the mode of the writing state of the pixel when a common symmetry method is employ | adopted as an alternating drive method. FIG. 2 is a diagram for explaining an AC signal generation circuit inside the controller of the liquid crystal display device shown in FIG. 1. It is a figure for demonstrating the point which becomes a problem of the liquid crystal display device used as the premise of this invention. It is a figure for demonstrating a mode that a streak is visible on the boundary of a split screen in the liquid crystal display device used as the premise of this invention. It is a block diagram which shows schematic structure of the liquid crystal display device of Example 1 of this invention. In the liquid crystal display device of Example 1 of this invention, it is a figure for demonstrating that a line is not visible on the boundary of a divided screen. In the liquid crystal display device which is the premise of the present invention, it is a diagram for explaining a case where the number of pixels on one horizontal line of at least one divided screen is not divisible by (polarity inversion completed number / 2). It is a block diagram which shows schematic structure of the liquid crystal display device of Example 2 of this invention. It is a figure for demonstrating inserting dummy display data in the liquid crystal display device of Example 2 of this invention. It is a block diagram which shows schematic structure of the liquid crystal display device of Example 3 of this invention. In the liquid crystal display device of Example 3 of this invention, it is a figure for demonstrating that a streak is not seen on the boundary of a split screen.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
In all the drawings for explaining the embodiments, parts having the same functions are given the same reference numerals, and repeated explanation thereof is omitted. Also, the following examples are not intended to limit the interpretation of the scope of the claims of the present invention.
[Liquid Crystal Display as a Premise of the Present Invention]
FIG. 1 is a block diagram showing a schematic configuration of a liquid crystal display device as a premise of the present invention.
As shown in the figure, the display unit 9 of the liquid crystal display panel 1 has pixels 8 arranged in a matrix. However, in FIG. 1, only one pixel 8 is shown to simplify the drawing.
Each pixel 8 is arranged in an intersecting area (an area surrounded by four signal lines) between two adjacent video lines 22 and two adjacent scanning lines 21. Each pixel 8 includes a thin film transistor (TFT) 10, a pixel electrode 11 connected to the source electrode (or drain electrode) of the thin film transistor 10, and a counter electrode 13 that faces the pixel electrode 11 across a liquid crystal layer. Note that Clc is a liquid crystal capacitance equivalently indicating a liquid crystal layer. Further, in FIG. 1, illustration of the storage capacitor formed between the counter electrode 13 and the pixel electrode 11 is omitted.

The drain electrode (or source electrode) of the thin film transistor 10 of each pixel 8 arranged in the column direction is connected to the video line 22, and each video line 22 applies a video voltage (gradation voltage) corresponding to display data. A video line driving circuit (also referred to as a drain driver) 6 to be supplied is connected.
In addition, the gate electrode of the thin film transistor 10 of each pixel 8 arranged in the row direction is connected to the scanning line 21, and each scanning line 21 scans the gate of the thin film transistor 10 with a scanning voltage (positive or negative) for one horizontal scanning time. And a scanning line driving circuit (also referred to as a gate driver) 7 for supplying a bias voltage.
When displaying an image on the liquid crystal display panel 1, the scanning line driving circuit 7 sequentially selects the plurality of scanning lines 21 from the top to the bottom or from the bottom to the top. During the selection period, the video line driving circuit 6 supplies a video voltage corresponding to the display data to the video line 22.
The voltage supplied to the video line 22 is output to the pixel electrode 11 via the thin film transistor 10, and finally, a charge is charged in the storage capacitor (not shown) and the liquid crystal capacitor (Clc), and the liquid crystal molecules An image is displayed by controlling.

In FIG. 1, reference numeral 500 denotes a timing controller (hereinafter simply referred to as a controller). Display data, control signals, and the like are input to the controller 500 from the outside (computer or the like).
The data bus line 5 is connected to the controller 500, and the controller 500 outputs display data to the data bus line 5. The controller 500 converts a control signal input from the outside and outputs a signal for controlling the video line driving circuit 6 and the scanning line driving circuit 7.
As a control signal output from the controller 500, a clock signal for the video line driving circuit 6 to capture display data and a video voltage (grayscale voltage) corresponding to the display data from the video line driving circuit 6 to the liquid crystal display panel 1 are output. There are a timing signal such as a clock signal for performing the operation, a frame start instruction signal for driving the scanning line driving circuit 7, and a gate clock signal for sequentially outputting the selection scanning signal.
The controller 500 outputs display data to the data bus line 5 according to the arrangement of pixels. Display data output from the controller 500 is transferred to the video line driving circuit 6 via the data bus line 5.
The video line driving circuit 6 takes in display data to be displayed from display data sequentially output from the controller 500. The timing at which the video line driving circuit 6 captures the display data is in accordance with a clock signal (control signal) 51 output from the controller 500.

Reference numeral 40 denotes a power supply circuit, and the power supply circuit 40 generates various drive voltages for driving the liquid crystal display panel 1. Here, the power supply circuit 40 generates and outputs a positive polarity gradation reference voltage, a negative polarity gradation reference voltage, a counter electrode voltage (VCOM), a high level voltage of a selected scanning signal, and the like.
As shown in FIG. 1, the video line driving circuit 6 is arranged in the horizontal direction (X direction) along the periphery of the display unit 9 on the first substrate (SUB1). The video line driving circuit 6 fetches display data from the data bus line 5 and outputs a gradation voltage corresponding to the display data to the video line 22. A voltage (gradation voltage) for driving the liquid crystal is supplied to the thin film transistor 10 through the video line 22. Note that although the names of the source and the drain may be reversed due to the bias relationship, the one connected to the video line 22 is referred to as the drain here.
Further, on the first substrate (SUB1), the scanning line driving circuit 7 is arranged in the vertical direction along the periphery of the display unit 9. Based on the frame start instruction signal and the shift clock sent from the controller 500, the scanning line driving circuit 7 sequentially supplies a high-level selection scanning voltage to the scanning line 21 every horizontal scanning period. The thin film transistor 10 is controlled to be turned on / off by a scanning voltage applied to the gate electrode.
A counter electrode (common electrode) 13 is disposed so as to face the pixel electrode 11, and a liquid crystal layer is provided between the pixel electrode 11 and the counter electrode 13. Therefore, as shown in FIG. A liquid crystal capacitor (Clc) is equivalently connected between the electrode 13 and the counter electrode 13.

In the liquid crystal display panel 1, the orientation of the liquid crystal layer is changed by applying a voltage between the pixel electrode 11 and the counter electrode 13. The liquid crystal display panel 1 displays an image using the fact that the light transmittance changes due to the change in the orientation of the liquid crystal layer.
An image displayed on the liquid crystal display panel 1 is composed of pixels 8. The gradation of each pixel 8 constituting the image follows the voltage supplied to the pixel electrode 11. Display data is input to the video line driving circuit 6, and the video line driving circuit 6 outputs a gradation voltage corresponding to the display data. Therefore, as the number of gradations displayed on the liquid crystal display panel 1 increases, the amount of display data and the number of data bus lines 5 also increase. In FIG. 1, FPC1 and FPC2 are flexible wiring boards.
As shown in FIG. 1, the display unit 9 is divided into further divided display areas (hereinafter referred to as sub display panels) (901, 902, 903, 904).
The liquid crystal display panel 1 includes a first substrate (SUB1) on which a pixel electrode 11, a thin film transistor 10 and the like are formed, and a second substrate (SUB1) on which a color filter and the like are stacked with a predetermined gap therebetween. In addition, the two substrates are bonded together by a seal material provided in a frame shape in the vicinity of the peripheral edge between the two substrates, and the liquid crystal is placed inside the seal material between the two substrates from the liquid crystal sealing port provided in a part of the seal material. Encapsulated and sealed, and further, a polarizing plate is attached to the outside of both substrates.
Note that the counter electrode 13 is provided on the second substrate side in the case of a TN liquid crystal display panel or a VA liquid crystal display panel. In the case of the IPS system, it is provided on the first substrate side.
Further, since the present invention is not related to the internal structure of the liquid crystal panel, a detailed description of the internal structure of the liquid crystal panel is omitted. Furthermore, the present invention can be applied to a liquid crystal panel having any structure.

In general, when the same voltage (DC voltage) is applied to the liquid crystal layer for a long time, the inclination of the liquid crystal layer is fixed, resulting in an afterimage phenomenon and shortening the life of the liquid crystal layer. In order to prevent this, in the liquid crystal display panel, the voltage applied to the liquid crystal layer is changed to AC every certain time, that is, the voltage applied to the pixel electrode 11 with reference to the voltage applied to the counter electrode 13. The voltage is changed to the positive voltage side / negative voltage side at regular intervals.
A common symmetry method is known as an AC driving method for applying an AC voltage to the liquid crystal layer. The common symmetry method is a method in which the voltage applied to the counter electrode 13 is made constant, and the voltage applied to the pixel electrode 11 is alternately inverted to positive and negative with reference to the voltage applied to the counter electrode 13. is there. As this common symmetry method, a dot inversion method or an N-line inversion method is known.
FIG. 2 shows the state of pixel writing when the common symmetry method is employed as the alternating drive method. In FIG. 2, “●” indicates a pixel in which a negative video voltage is written, and “◯” indicates a pixel in which a positive video voltage is written.
2A shows a state in which the polarity is inverted in units of two pixels in the horizontal direction in a cycle of two frames, and FIG. 2B shows a state in which the polarity is inverted in units of one pixel in the horizontal direction in a cycle of one frame. It shows how it is. For example, in FIG. 2A, a negative video voltage is written in the first pixel in 1 frame and 2 frames, and a positive video voltage is written in the first pixel in 3 frames and 4 frames. Written. Each frame data has its polarity reversed in units of two pixels in the horizontal direction from the top pixel.

FIG. 3 is a diagram for explaining an AC signal generation circuit inside the controller 500 of the liquid crystal display device shown in FIG. As shown in FIG. 3, an AC signal generation circuit 100 is built in the controller 500.
The AC signal generation circuit 100 generates an AC signal (M) and supplies it to the video line driving circuit 6 via the AC signal control line 3.
In the liquid crystal display device shown in FIG. 1, a common symmetry method is adopted as an alternating drive method. Therefore, the power supply circuit 40 generates a positive gradation reference voltage and a negative gradation reference voltage and outputs them to the video line drive circuit 6.
The video line driving circuit 6 includes a positive gradation voltage generation circuit (not shown) that generates a positive gradation voltage based on the positive gradation reference voltage, and a negative gradation level based on the negative gradation reference voltage. A negative gradation voltage generation circuit (not shown) for generating a regulated voltage.
Based on the AC signal supplied from the controller 500, the video line driving circuit 6 generates a positive gradation voltage or a negative gradation voltage even for the same display data, and displays the video line 22. To the pixel electrode 11 of each pixel 8.

Each of the sub display panels (901, 902, 903, and 904) is composed of pixels arranged in a matrix. Further, as shown in FIG. 3, the video line driving circuit 6 is provided for each of the sub display panels (901, 902, 903, 904).
The alternating signal (M) generated by the alternating signal generation circuit 100 is provided for each sub display panel (901, 902, 903, 904) via the alternating signal control line 3. Separately and simultaneously input to the line driving circuit 6.
The video line driving circuit 6 supplies a positive gradation voltage or a negative gradation voltage corresponding to the display data to the pixel electrode 11 of each pixel 8 based on the input AC signal (M). The polarity of the video voltage applied to the liquid crystal layer of each pixel is periodically reversed.
The display screen is displayed from the top pixel. In the enlarged view showing the dotted circle shown in A of FIG. 3 in an enlarged manner, the top 10 pixels that are continuous in one horizontal direction are shown as continuous display pixels 120. Here, ten rectangles (PIX in FIG. 3) of the display pixel 120 indicate one pixel, and a pixel to which a “+” symbol is attached indicates a pixel in which a positive positive video voltage is written, as a “−” symbol. Pixels marked with represent a pixel in which a negative video voltage is written.
In FIG. 3, the polarity is reversed in four consecutive pixels, that is, a pixel to which two positive video voltages are written and a pixel to which two negative video voltages are written. This is referred to as “the polarity inversion is completed with four pixels”, and the number of consecutive pixels in which the polarity is inverted is referred to as “the liquid crystal polarity inversion complete cycle”.

[Problems of the liquid crystal display device as a premise of the present invention]
When a liquid crystal display panel is divided into two or more screens and driven by a plurality of video line drive circuits, the number of pixels on one horizontal line per divided screen cannot be divided by the liquid crystal polarity inversion cycle described above. In this case, the continuity of the polarity inversion pattern for each divided screen is impaired.
For example, when the number of pixels on one horizontal line of the sub display panel (901, 903) is 398 and the number of pixels on one horizontal line of the sub display panel (902, 904) is 400, the sub display panel (902, 904) The number of pixels 400 on one horizontal line is divisible by the liquid crystal polarity inversion complete cycle (4 in FIG. 4), but the number of pixels 398 on one horizontal line of the sub display panel (901, 903) is the completion of liquid crystal polarity inversion. It is not divisible by the period (4 in FIG. 4). Therefore, as shown in the enlarged view of the dotted circle in FIG. 4, the polarity of the pixel is “−”, “−”, “+”, “+”, “+” at the boundary between the sub display panel 901 and the sub display panel 902. "" + ""-""-"And the continuity of the polarity inversion pattern is impaired.
As a result, as shown in FIG. 5, a streak is visible at the boundary between the sub display panel 901 and the sub display panel 902 and at the boundary between the sub display panel 903 and the sub display panel 904 as shown in FIG. There was a problem. Alternatively, there is a problem in that VCOM adjustment input to the counter electrode cannot be performed because flicker does not occur on the screen when inspecting with an existing killer pattern.
FIG. 4 is a diagram for explaining the problem of the liquid crystal display device which is the premise of the present invention. In FIG. 4, the pixels to which “+” symbols are attached are positive video voltages. A pixel to which “-” is added represents a pixel in which a negative video voltage is written. Further, FIG. 5 is a diagram for explaining how a streak is visible at the boundary of the sub display panel in the liquid crystal display device as a premise of the present invention.

[Example 1]
FIG. 6 is a block diagram illustrating a schematic configuration of the liquid crystal display device according to the first embodiment of the present invention.
In the present embodiment, when the liquid crystal display panel 1 is driven by dividing it into two or more screens, the number of pixels on one horizontal line of the sub display panel is not divisible by the completion cycle of the liquid crystal polarity inversion described above. This is an embodiment in the case where it is divisible by (complete cycle of reversal) / 2.
For example, as shown in FIG. 6, even in this embodiment, the number of pixels on one horizontal line of the sub display panel (901, 903) is 398, and the number of pixels on one horizontal line of the sub display panel (902, 904) is 400, the number of pixels 400 on one horizontal line of the sub display panel (902, 904) is divisible by the complete cycle of liquid crystal polarity inversion (4 in FIG. 4), but one horizontal of the sub display panel (901, 903). The number of pixels 398 on the line is not divisible by the liquid crystal polarity inversion complete cycle (4 in FIG. 4). Therefore, as shown in FIG. 7A, at the boundary between the sub display panel 901 and the sub display panel 902, the polarities of the pixels are “+”, “+”, “+”, “+”, and the polarity inversion pattern is continuous. Sexuality is impaired.
However, in the present embodiment, the number of pixels on one horizontal line of the sub display panel (901, 902, 903, 904) is divisible by (the liquid crystal polarity inversion complete cycle) / 2 (here, 2). Therefore, an AC signal input to the video line driving circuit 6 that drives each pixel of the sub display panel 902 is an inverted signal of the AC signal that is input to the video line driving circuit 6 that drives each pixel of the sub display panel 901. Accordingly, as shown in FIG. 7B, the polarities of the pixels become “+”, “+”, “−”, “−” at the boundary between the sub display panel 901 and the sub display panel 902, and the polarity inversion pattern Can be maintained.

Therefore, in the present embodiment, as shown in FIG. 6, for each sub display panel (902, 903, 904), an inverter (INV) that inverts an alternating signal output from the alternating signal generation circuit 100, and an alternating current There is provided a selector (SEL) for selecting the AC signal output from the conversion signal generation circuit 100 and the inverted AC signal output from the inverter (INV). This selector (SEL) is controlled by a selector signal (S-SEL) output from the AC signal generation circuit 100.
In this configuration, an inverted AC signal output from the inverter (INV) from the selector (SEL) is input to the video line driving circuit 6 that drives each pixel of the sub-display panels 902 and 903, whereby the sub-display panel At the boundary between 901 and the sub display panel 902, the polarities of the pixels are “+”, “+”, “−”, “−”, and the continuity of the polarity inversion pattern can be maintained.
Similarly, at the boundary between the sub display panel 902 and the sub display panel 903, the polarities of the pixels are “+”, “+”, “−”, “−”, and further, the boundary between the sub display panel 903 and the sub display panel 904. Then, the polarities of the pixels are “−”, “−”, “+”, “+”, and the continuity of the polarity inversion pattern can be maintained.
As a result, in this embodiment, the streak as shown in FIG. 5A is visible at the boundary between the sub display panel 901 and the sub display panel 902 and the boundary between the sub display panel 903 and the sub display panel 904. In addition, the VCOM adjustment to be input to the counter electrode can be performed using the existing killer pattern.

[Example 2]
When the liquid crystal display panel 1 is driven by dividing it into two or more screens, even if the number of pixels on one horizontal line of at least one sub-display panel is the liquid crystal polarity inversion complete period (the liquid crystal polarity inversion complete period) In the case where it is not divisible by / 2, the above-described first embodiment cannot be applied.
For example, as shown in FIG. 8, the number of pixels on one horizontal line of the sub display panel 901 is 399, the number of pixels on one horizontal line of the sub display panels (902, 904) is 400, and one horizontal line of the sub display panel 903 is displayed. When the number of pixels on the line is 398, the number of pixels on one horizontal line of the sub display panel (902, 903, 904) is divisible by (complete liquid crystal polarity inversion period) / 2 (here, 2). The number of pixels 399 on one horizontal line of the sub display panel 901 is not divisible by (the liquid crystal polarity inversion complete cycle) / 2. Therefore, as shown in FIG. 10A, at the boundary between the sub display panel 901 and the sub display panel 902, the polarities of the pixels are “+”, “+”, “−”, “+”, “+”, and polarity inversion is performed. The continuity of the pattern is impaired.

FIG. 9 is a block diagram showing a schematic configuration of a liquid crystal display device according to Embodiment 2 of the present invention.
In this embodiment, a part of the terminals of the video line driving circuit that drives each pixel of the sub display panel 902 is a dummy terminal (TD) that is not connected to the video line 22 so as to maintain the continuity of the polarity inversion pattern. It is a thing. In FIG. 9, TA is a terminal connected to the video line 22 of the sub display panel 902.
However, in this embodiment, since the arrangement of the display data is shifted, dummy display data is inserted into the display data by the controller 500 (or the video line driving circuit 6). That is, as shown in FIG. 9, in the video line driving circuit 6 for driving each pixel of the sub display panel 902, three terminals on the sub display panel 901 side are set as dummy terminals (TD), and the dummy terminals (T -D), as shown in FIG. 10C, a positive or negative video voltage corresponding to the dummy display data (D-DATA) is output.
In FIG. 10B, a portion indicated by an arrow EV is a pixel from which a positive or negative video voltage corresponding to actual display data (DATA) is output, and the sub display of FIG. The three pixels on the panel 901 side are pixels corresponding to dummy terminals (TD) and are not displayed on the actual liquid crystal display panel 1.

Thereby, in the liquid crystal display panel 1 of the present embodiment, the polarities of the pixels at the boundary between the sub display panel 901 and the sub display panel 902 are “+”, “+”, “−”, “−”, “+”, “+”. Thus, the continuity of the polarity inversion pattern can be maintained.
Similarly, a part of terminals of the video line driving circuit 6 (video line driving circuit for driving each pixel of the sub display panel 904) at the screen boundary between the sub display panel 903 and the sub display panel 904 is connected to the video line 22. By using the dummy terminal (TD) that is not performed, the polarity of the pixel is changed to “+”, “+”, “−”, “−”, “+”, “+” at the boundary between the sub display panel 903 and the sub display panel 904. And the continuity of the polarity reversal pattern can be maintained.
As described above, even in this embodiment, the streak as shown in FIG. 5A can be seen at the boundary between the sub display panel 901 and the sub display panel 902 and the boundary between the sub display panel 903 and the sub display panel 904. In addition, the VCOM adjustment to be input to the counter electrode can be performed using the existing killer pattern.
In this embodiment, when the liquid crystal display panel 1 is driven by dividing it into two or more screens, the number of pixels on one horizontal line of the sub display panel is not divisible by the completion period of the liquid crystal polarity inversion described above. Needless to say, the present invention can also be applied to a case where it is divisible by (complete cycle of liquid crystal polarity inversion) / 2.

[Example 3]
This embodiment is also an embodiment in which the number of pixels on one horizontal line of at least one sub display panel is not divisible by the liquid crystal polarity inversion complete cycle or (liquid crystal polarity inversion complete cycle) / 2. .
FIG. 11 is a block diagram showing a schematic configuration of a liquid crystal display device according to Embodiment 3 of the present invention.
In this embodiment, 100A, 100B, 100C, and 100D AC signal generation circuits are provided for each of the sub display panels (901, 902, 903, and 904).
As shown in FIG. 12A, in the case of the liquid crystal display panel 1 shown in FIG. 7, the polarities of the pixels at the boundary between the sub display panel 901 and the sub display panel 902 are “−”, “−”, “+”, “ “+”, “−”, “+”, “+”, “−”, “−”, And the continuity of the polarity inversion pattern is impaired.
However, as shown in FIG. 12B, in this embodiment, at the boundary between the sub display panel 901 and the sub display panel 902, the polarities of the pixels are “−”, “−”, “+”, “+”, “−”. “−”, “+”, “+”, “−”, And the continuity of the polarity inversion pattern can be maintained.
As a result, even in this embodiment, the streak as shown in FIG. 5A is visible at the boundary between the sub display panel 901 and the sub display panel 902 and the boundary between the sub display panel 903 and the sub display panel 904. In addition, VCOM adjustment to be input to the counter electrode can be performed using an existing killer pattern.
In the present embodiment, when the display panel 1 is driven by dividing it into two or more screens, the number of pixels on one horizontal line of the sub display panel is not divisible by the completion period of the liquid crystal polarity inversion described above. Needless to say, the present invention can also be applied to a case where it is divisible by the polarity reversal completion period) / 2.
As mentioned above, the invention made by the present inventor has been specifically described based on the above embodiments. However, the present invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Of course.

DESCRIPTION OF SYMBOLS 1 Liquid crystal display panel 5 Data bus line 3 AC signal control line 6 Video line drive circuit 7 Scan line drive circuit 8, PIX pixel 9 Display part 10 Thin-film transistor (TFT)
11 pixel electrode 13 counter electrode 21 scanning line 22 video line 40 power supply circuit 100, 100A, 100B, 100C, 100D AC signal generation circuit 500 timing controller 901, 902, 903, 904 sub display panel SUB1 first substrate SUB2 second Board Clc Liquid crystal capacitance FPC1, FPC2 Flexible wiring board INV Inverter SEL selector TA Terminal connected to video line TD Dummy terminal not connected to video line

Claims (7)

A display panel having a plurality of pixels, wherein the display panel is divided into at least two sub-display panels;
At least one video line driving circuit that is provided for each sub display panel and inputs a positive video voltage and a negative video voltage to each pixel of each sub display panel based on an alternating signal;
An AC signal generating circuit that generates the AC signal and inputs the AC signal to the video line driving circuit provided for each of the sub display panels;
Of the at least two sub display panels, a sub display panel having the first pixel on one horizontal line is a sub display panel A, and a sub display panel other than the sub display panel A is a sub display panel B.
The number of pixels on one horizontal line of each sub display panel is PL, the number of pixels on the horizontal line to which a negative video voltage is input is input to PP, and the positive polarity is input to PP. When PN is the number of pixels that are connected to the video voltage input pixels and the negative video voltage is input, PL is not divisible by (PP + PN) and PL is divisible by (PP + PN) / 2 In addition,
An inverting circuit for inverting the alternating signal;
A selector for inputting the AC signal and the AC signal inverted by the inverter circuit;
A video line driving circuit that selects the AC signal or the AC signal inverted by the inverting circuit based on the selector controlled by a selection signal and inputs a video voltage to the pixel of the sub display panel B. A display device characterized by inputting. A control circuit for transferring display data to a video line driving circuit provided for each sub display panel;
The alternating signal generation circuit, the inverting circuit, and the selector are arranged in the control circuit,
The display device according to claim 1, wherein the selection signal is generated by the alternating signal generation circuit. A display panel having a plurality of pixels, wherein the display panel is divided into at least two sub-display panels;
At least one video line driving circuit that is provided for each sub display panel and inputs a positive video voltage and a negative video voltage to each pixel of each sub display panel based on an alternating signal;
An AC signal generating circuit that generates the AC signal and inputs the AC signal to the video line driving circuit provided for each of the sub display panels;
The number of pixels on one horizontal line of each sub display panel is PL, the number of pixels on the horizontal line to which a negative video voltage is input is input to PP, and the positive polarity is input to PP. When PL is the number of pixels in which a negative video voltage is input continuously to a pixel to which a video voltage is input and PN is not divisible by (PP + PN),
A display device, wherein the AC signal generation circuit is provided for each video line driving circuit provided for each of the sub display panels. A display panel having a plurality of pixels and a plurality of video lines for inputting a video voltage to each pixel, wherein the display panel is divided into at least two sub-display panels;
At least one video line drive provided for each sub display panel and supplying a positive video voltage and a negative video voltage to the plurality of video lines of each sub display panel based on an AC signal. Circuit,
An AC signal generating circuit that generates the AC signal and inputs the AC signal to the video line driving circuit provided for each of the sub display panels;
The number of pixels on one horizontal line of each sub display panel is PL, the number of pixels on the horizontal line to which a negative video voltage is input is input to PP, and the positive polarity is input to PP. When PL is the number of pixels in which a negative video voltage is input continuously to a pixel to which a video voltage is input and PN is not divisible by (PP + PN),
Of the at least two sub-display panels, when sub-display panels A and B are sub-display panels that are continuous to each other, the sub-display panel of the video line driving circuit provided for each sub-display panel B A dummy terminal that is not electrically connected to any of the plurality of video lines of the sub display panel B is provided on the A side,
A pixel to which a video voltage is supplied from a video line connected to a terminal of a video line driving circuit provided for each sub display panel A at a boundary between the sub display panel A and the sub display panel B; For each sub-display panel B, the polarity inversion of the video voltage input to the pixels to which the video voltage is supplied from the video line connected to the terminal of the video line driving circuit provided for each display panel B continues. A display device that determines the number of dummy terminals of a video line driving circuit provided. A control circuit for transferring display data to a video line driving circuit provided for each sub display panel;
The display device according to claim 3, wherein the alternating signal generation circuit is disposed in the control circuit. A control circuit for transferring display data to a video line driving circuit provided for each sub display panel;
5. The display according to claim 4, wherein the video line driving circuit provided for each of the sub display panels B inserts dummy display data for the dummy terminal into display data transferred from the control circuit. apparatus. A control circuit for inputting display data to a video line driving circuit provided for each sub display panel;
The control circuit inserts dummy display data for a dummy terminal of a video line driving circuit provided for each sub display panel B into display data transferred to the video line driving circuit provided for each sub display panel B. The display device according to claim 4, wherein:

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