JP2012159759A - Electro-optical device, control method of electro-optical device and electronic apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress flicker and to cause an intensity change not to be visually recognized even when changing application time of a positive polarity voltage and application time of a negative polarity voltage.SOLUTION: A control circuit controls a voltage of a counter electrode, a period length of a positive polarity field and a period length of a negative polarity field such that an effective voltage of a voltage applied to the positive polarity field is the same as that of a voltage applied to the negative polarity field. In a case where a flicker amount becomes not less than a threshold value, the control circuit, at first, adjusts the voltage of the counter electrode such that the flicker amount becomes less than the threshold value. Next, the control circuit controls the period length of the positive polarity field and the period length of the negative polarity field such that the flicker amount gradually changes.

Description

  The present invention relates to a technique for suppressing the occurrence of flicker in an electro-optical device.

A liquid crystal element used in a liquid crystal display device has a structure in which a liquid crystal is sandwiched between two electrodes. However, when a direct current component is applied, the liquid crystal deteriorates. For this reason, in a liquid crystal display device, the liquid crystal element is generally AC driven. However, a DC component may be applied to the liquid crystal only by AC driving.
Specifically, in the liquid crystal display device, the pixel electrode substrate sandwiching the liquid crystal layer and the counter electrode substrate have different physical structures, and a positive voltage that is higher than the counter electrode is applied. The resistance value at the interface between the electrode and the alignment film or at the interface between the alignment film and the liquid crystal layer differs depending on the case where a negative polarity voltage that is low when viewed from the counter electrode is applied. As a result, in the liquid crystal display device, the current amount is different between the application of the positive voltage and the application of the negative voltage even if the effective voltage to the liquid crystal layer is the same, and the amount of charge transfer is non-targeted. Arise. In addition, due to the asymmetry of the current amount, the electric charge in the liquid crystal is biased, and an internal electric field is generated by the bias of the charge. Due to the influence of the internal electric field, the voltage actually applied to the liquid crystal layer becomes asymmetric depending on the polarity of the drive voltage, and a DC voltage component is applied to the liquid crystal layer. When this direct current component is applied to the liquid crystal layer, flicker occurs, so that the flicker is minimized, that is, the transmittance (brightness) by applying a positive voltage and the transmission by applying a negative voltage. A technique is known in which the application time of a voltage applied to one electrode of a liquid crystal element is adjusted so that the difference from the rate is minimized (see, for example, Patent Document 1).

JP 2010-79151 A

By the way, even if the application time of the voltage to the electrode is adjusted so that the flicker is minimized by the technique of Patent Document 1, a DC component may be applied to the liquid crystal element due to secular change or the like. It is possible to control flicker by detecting flicker and performing feedback. However, if the application time ratio is greatly changed during feedback control, a luminance change is caused accordingly, and this luminance change is detected by the viewer. It will be visually recognized.
The present invention has been made in view of the above-described circumstances, and one of its purposes is to suppress flicker, and even if the application time of the positive voltage and the application time of the negative voltage are changed, the luminance change is not visually recognized. Is to make it.

In order to achieve the above object, the electro-optical device according to the present invention is provided corresponding to the intersection of a plurality of scanning lines and a plurality of data lines, respectively, and when each of the scanning lines is selected, A pixel having a gradation corresponding to a voltage of a data signal supplied to the data line, the pixel including a pixel electrode to which the data signal is applied, a counter electrode facing the pixel electrode, and the pixel An electro-optical device that sandwiches an electro-optical material between an electrode and the counter electrode, wherein a positive voltage that is a voltage corresponding to a gradation of the pixel and that is higher than a predetermined potential is used as the reference voltage. A positive field supplied as a data signal to a data line corresponding to the pixel, and a negative voltage which is a voltage corresponding to the gradation of the pixel and which is lower than a predetermined potential is used as the data signal. Data corresponding to In each of the negative polarity fields to be supplied to the scanning line driving circuit for selecting the plurality of scanning lines in a predetermined order, and when one scanning line is selected in the positive polarity field, When a voltage corresponding to the gray level of the pixel is supplied to the data line corresponding to the pixel as the data signal and the one scanning line is selected in the negative polarity field, the one pixel is positioned. A data line driving circuit for supplying a voltage corresponding to the gray level of the pixel to the data line corresponding to the pixel as a data signal, and the positive polarity field for the pixel. A detection circuit for detecting a difference between an effective voltage of the applied voltage and an effective voltage of the voltage applied in the negative field, and the difference detected by the detection circuit is changed within a predetermined range. When the difference detected by the detection circuit is equal to or greater than a predetermined threshold, the voltage of the counter electrode is changed so that the difference is less than the threshold, and after the change, the positive polarity field and the negative polarity field And a control circuit for controlling the period length.
According to the present invention, since the voltage of the counter electrode is changed before changing the time of the positive polarity field and the negative polarity field, even if the time of the positive polarity field and the negative polarity field is changed, the luminance change is not visually recognized. Can be.

In the present invention, when the difference detected by the detection circuit after controlling the period length is equal to or greater than the threshold, the voltage of the counter electrode may be changed to the voltage at the time of starting the driving of the counter electrode. Good.
According to the present invention, since the voltage of the counter electrode is changed to the voltage at the start of driving, it is possible to prevent the voltage of the counter electrode from being largely biased toward the positive electrode or the negative electrode.

In the present invention, the voltage at the start of driving of the counter electrode is the difference between the effective voltage of the voltage applied in the positive polarity field and the effective voltage of the voltage applied in the negative polarity field at the start of driving. It is good also as a structure which is a voltage which does not generate | occur | produce.
According to the present invention, there is no difference between the effective voltage of the voltage applied in the positive polarity field and the effective voltage of the voltage applied in the negative polarity field at the start of driving, thereby suppressing the occurrence of flicker at the start of driving. be able to.

In the present invention, when the voltage of the counter electrode is changed, the voltage may be changed with time.
According to the present invention, since the voltage of the counter electrode is changed over time, a change in luminance is less visible.

In this invention, when changing the voltage of the said counter electrode, it is good also as a structure which changes a voltage earlier than the state of the electric charge bias in the said electro-optic material.
According to the present invention, in the electro-optic material sandwiched between the pixel electrode and the counter electrode of the pixel, the voltage is changed faster than the state of the charge bias changes, so that the luminance change is less visible. .

In the present invention, the detection circuit is applied with the brightness of the pixel located on the one scanning line when the voltage is applied in the positive polarity field and the voltage in the negative polarity field. The brightness of the pixel at the time is detected, and the effective voltage of the voltage applied to the pixel in the positive field and the voltage applied in the negative field based on the detected brightness difference. It is good also as a structure which detects the difference with an effective voltage.
According to the present invention, since the difference in effective voltage is detected based on the difference in brightness of the pixels, the difference in effective voltage can be easily obtained.

  The present invention can be conceptualized not only as an electro-optical device but also as a control method of the electro-optical device and an electronic apparatus having the electro-optical device.

1 is a block diagram illustrating a configuration of an electro-optical device according to a first embodiment. FIG. 3 is a diagram showing a configuration of a display panel of the electro-optical device. 2 is a diagram showing a configuration of a pixel in the display panel. FIG. FIG. 14 is a diagram showing an operation of a scanning line driving circuit in the display panel. The figure which shows the voltage waveform example of the data signal in the display panel. The figure which shows the voltage waveform example of the data signal in the display panel. The figure which showed the arrangement position of the optical sensor which concerns on the same embodiment. FIG. 3 is a block diagram illustrating a configuration of a data analysis unit according to the electro-optical device. The figure which shows transition of the writing of the pixel in a display area. FIG. 14 is a diagram showing an operation of a scanning line driving circuit in the display panel. The figure which shows transition of the writing of the pixel in a display area. FIG. 14 is a diagram showing an operation of a scanning line driving circuit in the display panel. The figure which shows transition of the writing of the pixel in a display area. The figure which showed the characteristic of the display panel. 5 is a flowchart showing the flow of processing of a control circuit 52. 10 is a flowchart of processing for adjusting the potential of the counter electrode. The figure which showed transition of the voltage of a counter electrode, and transition of the amount of flicker. The flowchart which shows the flow of a process of the control circuit 52 which concerns on 2nd Embodiment. The figure which showed transition of the voltage of a counter electrode, and transition of the amount of flicker. 10 is a flowchart of processing for adjusting the potential of the counter electrode in the third embodiment. The flowchart which shows the flow of a process of the control circuit 52 which concerns on 4th Embodiment. The figure which showed transition of the voltage of a counter electrode, and transition of the amount of flicker. The flowchart which shows the flow of a process of the control circuit 52 which concerns on 5th Embodiment. The figure which showed transition of the voltage of a counter electrode, and transition of the amount of flicker. FIG. 3 is a diagram illustrating a configuration of a projector using the electro-optical device according to the embodiment.

[First Embodiment]
FIG. 1 is a block diagram showing a configuration of an electro-optical device 1 according to the first embodiment of the present invention. As shown in FIG. 1, the electro-optical device 1 is roughly divided into a display panel 10, a processing circuit 50, and a detection circuit 70. Among these, the processing circuit 50 which is a circuit module for controlling the operation of the display panel 10 includes a control circuit 52, a display data processing circuit 54, and a D / A conversion circuit 56, for example, an FPC (flexible printed circuit) substrate. Is connected to the display panel 10. The detection circuit 70 includes an optical sensor 71 and a data analysis unit 72. The electro-optical device 1 is an example of a liquid crystal device that displays an image using liquid crystal.

  The control circuit 52 generates various control signals for controlling the display panel 10 in synchronization with a synchronization signal Vsync supplied from an external host device (not shown). These control signals will be described later as appropriate. The control circuit 52 generates various control signals and controls the display data processing circuit 54.

  The display data processing circuit 54 temporarily stores display data Video supplied from an external host device in an internal memory (not shown) under the control of the control circuit 52 and then reads it in synchronization with driving of the display panel 10. It is. Note that the display data Video is data that specifies the gradation of the pixels in the display panel 10, and the waveform is not particularly shown, but for one frame (period of 16.7 milliseconds (frequency 60 Hz)) (For pixel). The D / A conversion circuit 56 converts the read display data into an analog data signal Vid according to control by the control circuit 52.

  Next, the display panel 10 will be described. FIG. 2 is a diagram illustrating a configuration of the display panel 10. As shown in this figure, the display panel 10 is a peripheral circuit built-in type in which a scanning line driving circuit 130 and a data line driving circuit 140 are built around the display region 100. In the display area 100, 480 scanning lines 112 are provided so as to extend in the row (X) direction, and 640 columns of data lines 114 are provided so as to extend in the column (Y) direction. The pixels 110 are arranged so as to be electrically insulated from the scanning lines 112 and correspond to the intersections of the scanning lines 112 of 480 rows and the data lines 114 of 640 columns. Accordingly, in the present embodiment, the pixels 110 are arranged in a matrix of 480 rows × 640 columns in the display region 100, but the present invention is not limited to this arrangement.

  The configuration of the pixel 110 will be described with reference to FIG. FIG. 3 shows a total of 4 pixels of 2 × 2 corresponding to the intersection of the i row and the (i + 1) row adjacent to it by 1 row and the j column and the (j + 1) column adjacent to the right by 1 column. The structure of is shown. Note that i and (i + 1) are symbols for generally indicating the row in which the pixels 110 are arranged, and are integers of 1 to 480 in this description. J and (j + 1) are symbols for generally indicating a column in which the pixels 110 are arranged, and are integers of 1 to 640.

  As shown in FIG. 3, each pixel 110 includes an n-channel TFT 116 and a liquid crystal capacitor 120. Here, since each pixel 110 has the same configuration, the gate electrode of the TFT 116 in the pixel 110 in the i row and j column will be described as the pixel in the i row and j column. On the other hand, the source electrode is connected to the data line 114 in the j-th column, and the drain electrode is connected to the pixel electrode 118 which is one end of the liquid crystal capacitor 120. The other end of the liquid crystal capacitor 120 is connected to the counter electrode 108. The counter electrode 108 is common to all the pixels 110, and a voltage LCcom constant in time is applied.

Although not specifically shown, the display panel 10 has a configuration in which a pair of substrates of an element substrate and a counter substrate are bonded together with a certain gap therebetween, and liquid crystal is sealed in the gap. Among these, the scanning line 112, the data line 114, the TFT 116, and the pixel electrode 118 are formed on the element substrate together with the scanning line driving circuit 130 and the data line driving circuit 140, while the counter electrode 108 is formed on the counter substrate. These electrode forming surfaces are bonded together with a certain gap so as to face each other. Therefore, in this embodiment, the liquid crystal capacitor 120 is configured by sandwiching the liquid crystal 105, which is an example of an electro-optic material, between the pixel electrode 118 and the counter electrode 108.
In this embodiment, if the effective voltage value held in the liquid crystal capacitor 120 is close to zero, the transmittance of light passing through the liquid crystal capacitor is maximized to display white, while the effective voltage value increases. The normally white mode in which the amount of transmitted light decreases and finally the black display with the minimum transmittance is set.

In this configuration, a selection voltage is applied to the scanning line 112 to turn on the TFT 116, and the voltage corresponding to the gradation (brightness) is applied to the pixel electrode 118 via the data line 114 and the on-state TFT 116. When the data signal is supplied, the liquid crystal capacitor 120 corresponding to the intersection of the scanning line 112 to which the selection voltage is applied and the data line 114 to which the data signal is supplied can hold the effective voltage value corresponding to the gradation.
Therefore, the light transmitted through the liquid crystal capacitor 120 can be different for each pixel, whereby an image is formed in the display region 100. The formed image is viewed directly by the user or enlarged and projected as in a projector described later. In any case, the brightness of the pixels of the display panel 10 is detected by the optical sensor 71.

  Note that when the scanning line 112 becomes a non-selection voltage, the TFT 116 is turned off (non-conducting). However, since the off resistance at this time is not ideally infinite, the charge accumulated in the liquid crystal capacitor 120 is small. Leak. In order to reduce the influence of off-leakage, a storage capacitor 109 is formed for each pixel. One end of the storage capacitor 109 is connected to the pixel electrode 118 (the drain of the TFT 116), while the other end is commonly connected to the capacitor line 107 over all pixels. The capacitance line 107 is maintained at a constant potential, for example, the same voltage LCcom as the counter electrode 108.

  The scanning line driving circuit 130 supplies scanning signals G1, G2, G3,..., G480 to the scanning lines 112 in the 1, 2, 3,. Here, the scanning line driving circuit 130 sets the scanning signal to the selected scanning line to the H level corresponding to the voltage Vdd, and the scanning signals to the other scanning lines to L corresponding to the non-selection voltage (ground potential Gnd). Level.

FIG. 4 is a timing chart showing the scanning signals G1 to G480 output from the scanning line driving circuit 130 in relation to the start pulses Dya and Dyb and the clock signal Cly.
As shown in the figure, each scanning line 112 is selected twice in one frame period. Here, the frame means a period required to display one image on the display panel 10, but the display data Video is supplied with a period of 16.7 milliseconds as described above. Corresponds to 16.7 milliseconds of this period.
The control circuit 52 outputs a clock signal Cly having a duty ratio of 50% for 480 periods equal to the number of scanning lines over a period of one frame. In FIG. 4, a period of one cycle of the clock signal Cly is denoted as H.
The control circuit 52 outputs start pulses Dya and Dyb having a pulse width corresponding to one cycle of the clock signal Cly when the clock signal Cly rises to the H level as follows. That is, the control circuit 52 outputs the start pulse Dya at the beginning of one frame period (that is, at the beginning of the first field), while outputting the start pulse Dyb for 240 cycles of the clock signal Cly after outputting the start pulse Dyb. Is output at a timing T at which a half period of one frame has passed.
However, as will be described later, the control circuit 52 may output the start pulse Dyb with respect to the timing T to the front side or the rear side in terms of time in units of the period of the clock signal Cly.

The period from the start pulse Dya output until the start pulse Dyb is output is set as the first field in the period of one frame, and the next start pulse Dya is output after the start pulse Dyb is output. The period until is the second field.
Here, the start pulses Dya and Dyb are alternately output, and among these, the start pulse Dya is output at the start timing of one frame, that is, every 16.7 milliseconds. For this reason, when the start pulse Dya is specified, the start pulse Dyb is inevitably specified, and therefore, in FIG. 1, FIG. 2, etc., there is a case where they are described as the start pulse Dy without particularly distinguishing both.

The scanning line driving circuit 130 outputs the scanning signals G1 to G480 shown in FIG. 4 from the start pulses Dya and Dyb and the clock signal Cly. That is, when the start pulse Dya is supplied to the scanning signals G1 to G480, the scanning line driving circuit 130 sequentially sets the clock signal Cly to the H level during the L level period, while when the start pulse Dyb is supplied. The clock signal Cly is sequentially set to the H level during the H level period.
For this reason, by supplying the start pulse Dya, the scanning line extends in the order of 1, 2, 3, 4,... The clock signal Cly is selected after a half cycle period. On the other hand, when the start pulse Dyb is supplied, the scanning line moves from the second field of a certain frame to the first field of the next frame in the downward direction of the screen in the order of rows 1, 2, 3, 4,. Thus, it is selected between selections triggered by the supply of the start pulse Dya.

  The data line driving circuit 140 includes a sampling signal output circuit 142 and n-channel TFTs 146 provided corresponding to the data lines 114, respectively. As shown in FIGS. 5 and 6, the sampling signal output circuit 142 selects one of the scanning lines 112 according to the control signal Ctrl-x from the control circuit 52, and the scanning signal supplied to the scanning line is at the H level. In this period, sampling signals S1, S2, S3,..., S640 that sequentially become H level exclusively are output so as to correspond to each of the data lines 114. Note that the control signal Ctrl-x is actually a start pulse or a clock signal, but is not directly related to the present invention, so the description is omitted. Further, the period during which the scanning signal is at the H level is actually slightly narrower than the half-period period of the clock signal Cly, as shown in FIGS.

Meanwhile, the D / A conversion circuit 56 in FIG. 1 converts display data Video for one row of pixels located on the scanning line 112 selected by the scanning line driving circuit 130 into sampling signals S1 to S640 by the sampling signal output circuit 142. The data signal Vid having the following polarity is converted according to the output.
In other words, the D / A conversion circuit 56 is positive for the data signal Vid of the pixel located in the selected row when the clock signal Cly is at the L level, and is selected when the clock signal Cly is at the H level. The data signal Vid of the pixel located at is converted into a negative polarity.
Note that the positive polarity means that the voltage applied to the pixel electrode 118 is higher than the voltage applied to the counter electrode 108, and the negative polarity means that the voltage applied to the pixel electrode 118 is applied to the counter electrode 108. A case where the voltage is lower than the applied voltage.

Next, the optical sensor 71 and the data analysis unit 72 will be described. The optical sensor 71 is a sensor that detects the brightness of the pixels of the display panel 10. The optical sensor 71 includes a photodiode. When light is incident on the photodiode, a change in current flowing in the photodiode is converted into a change in voltage by a current-voltage conversion circuit, and an analog signal indicating the brightness of the pixel is obtained. The signal Sb is supplied to the control circuit 52. In the present embodiment, the signal Sb output from the optical sensor 71 represents the brightness of the pixel by the voltage value, and the voltage changes according to the detected brightness.
The optical sensor 71 is disposed in the vicinity of the display panel 10 as shown in FIG. The light transmitted through the display panel 10 is guided to the optical sensor 71 by the mirror 73 as indicated by an arrow in FIG. In the present embodiment, the light of the pixels in the 480th row is guided to the optical sensor 71 by the mirror 73, and the brightness of the pixels (detection pixels) is detected.

FIG. 8 is a block diagram showing the configuration of the data analysis unit 72. The data analysis unit 72 acquires the signal Sb supplied from the optical sensor 71 and outputs information related to the brightness of the pixel from the acquired signal Sb. The data analysis unit 72 includes an AD conversion unit 581 and a calculation unit 582.
The AD conversion unit 581 acquires the signal Sb from the optical sensor 71. In addition, the AD conversion unit 581 acquires the start pulse Dy and the clock signal Cly from the control circuit 52. The AD converter 581 counts the number of clock signals Cly from the rising edge of the start pulse Dy, and converts the signal Sb into a digital signal Sdb at a timing before the scanning signal G480 rises. The AD conversion unit 581 outputs the digital signal Sdb obtained by the conversion to the calculation unit 582.
In addition, since the pixel located in the 480th row holds the positive voltage from when the start pulse Dya is output until the scanning signal G480 is output, the pixel is obtained with the start pulse Dya as a trigger. The digital signal Sdb thus obtained represents the brightness when the pixels in the 480th row hold a positive voltage.
In addition, since the start pulse Dyb is output until the scanning signal G480 is output, the pixel located in the 480th row holds a negative voltage, and thus is obtained using the start pulse Dyb as a trigger. The digital signal Sdb thus obtained represents the brightness when the pixel in the 480th row holds a negative polarity voltage.

  The calculation unit 582 performs a fast Fourier transform process on the digital signal Sdb supplied from the AD conversion unit 581. If there is a difference between the effective voltage at the time of holding the positive voltage and the effective voltage at the time of holding the negative voltage, the pixel has a difference in brightness between holding the positive voltage and holding the negative voltage. When a difference occurs in the brightness of the pixel between when the positive voltage is held and when the negative voltage is held, the value of the digital signal Sdb also changes in accordance with this difference. For this reason, when the fast Fourier transform process is performed on the waveform indicating the change in the digital signal Sdb, the amplitude of the signal Sb can be obtained, and when the pixels in the 480th row hold the positive voltage from this amplitude. And the brightness difference when the negative polarity voltage is maintained (hereinafter referred to as flicker amount). The calculation unit 582 outputs a signal Sa1 indicating the brightness difference obtained by the fast Fourier transform process to the control circuit 52. Since the flicker amount corresponds to the difference between the effective voltage when holding the positive voltage and the effective voltage when holding the negative voltage, obtaining the flicker amount means that the effective voltage and the negative voltage when holding the positive voltage It can be said that the detection circuit 70 is a circuit that detects the difference between the effective voltage at the time of holding the positive voltage and the effective voltage at the time of holding the negative voltage.

If the brightness when the pixel holds a positive voltage is brighter than the brightness when the pixel holds a negative voltage, the value of the digital signal Sdb obtained with the start pulse Dyb is the start pulse It becomes larger than the value of the digital signal Sdb obtained with Dya as an opportunity. If the brightness when the pixel holds a negative voltage is brighter than the brightness when the pixel holds a positive voltage, the value of the digital signal Sdb obtained with the start pulse Dya is used as the start pulse. It becomes larger than the value of the digital signal Sdb obtained with Dyb.
In other words, when the change in the value of the digital signal is represented by a waveform, the brightness becomes bright when the pixel holds a positive voltage and the brightness becomes bright when the pixel holds a negative voltage. The phase of the waveform will be different. For this reason, by obtaining the phase of the waveform of the digital signal by fast Fourier transform processing, whichever is brighter when the pixel holds a positive voltage or when the pixel holds a negative voltage. You can know if it is bright.

Note that the calculation unit 582 does not obtain the phase of the waveform of the digital signal by the fast Fourier transform process, but the value of the digital signal Sdb obtained with the start pulse Dyb as a trigger is obtained with the start pulse Dya as a trigger. When the value is larger than the value of the digital signal Sdb, it is determined that the pixel is brighter when the positive voltage is held, and the value of the digital signal Sdb obtained with the start pulse Dya is used as the start pulse Dyb. When the value is greater than the value of the digital signal Sdb obtained as a trigger, it may be determined that the pixel is brighter when the negative voltage is held.
The calculation unit 582 detects which is brighter when the pixel holds a positive voltage or when the pixel holds a negative voltage by any of the above-described methods, and the pixel has a positive voltage. When the pixel is bright, the signal Sa2 is output to the control circuit 52, and when the pixel is bright when the pixel is holding the negative voltage, the signal Sa2 is output to the control circuit 52.

The control circuit 52 controls the output timing of the start pulse Dyb. Specifically, the control circuit 52 stores a predetermined first set value and second set value as set values for designating the output timing of the start pulse Dyb. In the present embodiment, the first set value is a negative integer value, and the second set value is a positive integer value.
The control circuit 52 has a register that stores a value for designating the output timing of the start pulse Dyb. The control circuit 52 changes the output timing of the start pulse Dyb according to the value stored in the register.
Hereinafter, the output timing of the start pulse Dyb will be described.

  First, the control circuit 52 stores the display data Video supplied from the external host device in the internal memory of the display data processing circuit 54, and then selects a scanning line of a row on the display panel 10, and The display signal is read out at a speed twice the storage speed, and the sampling signal output circuit 142 is connected via the control signal Ctrl-x so that the sampling signals S1 to S640 sequentially become H level in accordance with the reading of the display data. Control. The read display data is converted into an analog data signal Vid by the D / A conversion circuit 56.

Here, the control circuit 52 supplies the start pulse Dyb at timing T when the value stored in the register is “0”. When supplying the start pulse Dyb at the timing T, the control circuit 52 selects the scanning lines 112 in the order of the 241, 241, 2, 243,..., 480, 240th rows in the first field. Is done. Therefore, the control circuit 52 controls the scanning line driving circuit 130 so that the scanning line 112 in the 241st row is selected first. Further, the control circuit 52 causes the display data processing circuit 54 to read the display data Video corresponding to the 241st row stored in the memory at double speed, and causes the D / A conversion circuit 56 to read the negative data signal. The sampling signal output circuit 142 is controlled so that the sampling signals S1 to S640 are exclusively set to the H level in this order in accordance with the reading. When the sampling signals S1 to S640 are sequentially set to the H level, the TFTs 146 are sequentially turned on, and the data signals Vid supplied to the image signal lines 171 are sequentially sampled on the data lines 114 in the 1st to 640th columns.
On the other hand, when the scanning line 112 in the 241st row is selected and the scanning signal G241 becomes the H level, all the TFTs 116 in the pixels 110 located in the 241st row are turned on. Therefore, the negative voltage of the data signal Vid sampled on the data line 114 is applied to the pixel electrode 118 as it is. For this reason, the liquid crystal capacitor 120 in the pixels of the 241st row and in the columns 1, 2, 3, 4,..., 639, 640 has a negative voltage corresponding to the gradation specified by the display data Video. Will be written and held.

Next, the control circuit 52 controls the scanning line driving circuit 130 so that the scanning line 112 in the first row is selected. In addition, the control circuit 52 causes the display data processing circuit 54 to read the display data Video corresponding to the first row stored in the memory at double speed, and causes the D / A conversion circuit 56 to output a positive data signal. The sampling signal output circuit 142 is controlled so that the sampling signals S1 to S640 are exclusively set to the H level in this order in accordance with the reading.
When the scanning line 112 in the first row is selected and the scanning signal G1 becomes H level, all the TFTs 116 in the pixels 110 located in the first row are turned on, whereby the voltage of the data signal Vid sampled on the data line 114 is turned on. Is applied to the pixel electrode 118. Therefore, a positive voltage corresponding to the gradation specified by the display data Video is written and held in the liquid crystal capacitor 120 in the pixels in the first row and in the 1st to 640th columns.

Hereinafter, in the first field, the same voltage writing operation is performed in the order of the 242nd, 2nd, 24th, 3rd,..., 480th, and 240th rows. Thereby, a positive voltage corresponding to the gradation is written to the pixels in the first to 240th rows, and a negative voltage corresponding to the gradation is written to the pixels in the 241st to 480th rows. Each will be held.
If the start pulse Dyb is supplied at the timing T, the scanning lines 112 are 1, 241, 2, 242, 3, 243, 4, 244,..., 240, 480 rows in the second field. While being selected in the order of eyes, the writing polarity in the same row is inverted. Therefore, a negative voltage corresponding to the gradation is written to the pixels in the first to 240th rows, and a positive voltage corresponding to the gradation is written to the pixels in the 241st to 480th rows. Each will be held.

FIG. 5 shows an example of a voltage waveform of the data signal Vid in a period in which the (i + 240) -th scanning line and the i-th scanning line in the first field are selected.
In this figure, voltages Vb (+) and Vb (−) are positive and negative voltages corresponding to the black of the lowest gradation, respectively, and have a symmetrical relationship with respect to the reference voltage Vc. The reference voltage Vc is the center of the amplitude of the data signal Vid and is an intermediate voltage between the voltages Vb (+) and Vb (−). In the present embodiment, the ground potential Gnd is used as a voltage reference unless otherwise specified. In the present embodiment, when the decimal value of the gradation value designated by the display data Video is “0”, black of the lowest gradation is designated, and thereafter, a bright gradation is designated as the decimal value increases. Is normally white mode, so if the voltage of the data signal Vid is converted to positive polarity, it becomes a voltage swung from the voltage Vb (+) to the lower side as the gradation value increases, and the negative polarity In the case of converting to V, the voltage is swung from the voltage Vb (−) to the higher side.

In the first field, since the (i + 240) -th scanning line is selected before the i-th row, for example, the sampling signal S1 is at the H level during the period in which the scanning signal G (i + 240) is at the H level. During this period, the data signal Vid becomes a negative voltage corresponding to the gradation of the pixel in the i row and the first column, and the second, third, fourth,... It changes to a negative polarity voltage according to the gradation of the pixel.
In the i-th row that is subsequently selected, since positive polarity writing is designated, the data signal Vid is i during the period in which the scanning signal Gi is at the H level, for example, the period in which the sampling signal S1 is at the H level. It becomes a positive voltage according to the gradation of the pixel in the row 1 column, and thereafter, according to the change of the sampling signal, the positive voltage according to the gradation of the pixel in the 2, 3, 4,. Change.
In the second field, since the (i + 240) -th scanning line is selected after the i-th row, the scanning signal Gi first goes to the H level and the writing polarity is inverted, so that the data signal Vid The voltage waveform is as shown in FIG.
In FIG. 5 and FIG. 6, the vertical scale indicating the voltage of the data signal Vid is enlarged as compared with the vertical scales of other signals for convenience. In addition, the voltage corresponding to black is obtained during the period from when the sampling signal S640 changes to the L level to when the sampling signal S1 changes to the H level. This is because it does not contribute to the display even if it is written on.

Next, FIG. 9 is a diagram showing the writing state of each row with the lapse of time over successive frames when the start pulse Dyb is supplied at the timing T. FIG. As shown in this figure, in the present embodiment, negative polarity writing is performed in the pixels of 241, 242, 243,..., 480th row in the first field, and 1, 2, 3,. In the pixel on the 240th row, positive writing is performed and held until the next writing. On the other hand, in the second field, negative-polarity writing is performed on the pixels in the first, second, third,..., 240th rows, and positive-polarity writing is performed on the pixels in the 241st, 24th, 242th,. In the same manner, it is held until the next writing.
When the value of the register is “0” and the start pulse Dyb is supplied at the timing T, the period of the first and second fields is 240 periods of the clock signal Cly. The period during which the positive voltage is held and the period during which the negative voltage is held are halved.

Incidentally, as shown in FIG. 5, the voltage LCcom applied to the counter electrode 108 is set to a lower side than the reference voltage Vc at the time of factory shipment. This is because, in an active matrix type electro-optical device in which the pixel electrode is driven by a TFT, a so-called bush-down occurs, or when a liquid crystal capacitance leak holds a positive voltage and a negative voltage. It depends on what is different.
If the voltage LCcom is made to coincide with the reference voltage Vc, the effective voltage value of the liquid crystal capacitor 120 by negative polarity writing becomes slightly larger than the effective value by positive polarity writing (when the TFT 116 is n-channel). The voltage LCcom is set to an optimum value so that this difference is offset by offsetting the voltage LCcom lower than the reference voltage Vc.

In this embodiment, when the start pulse Dyb is supplied at the timing T, the first and second field periods are equal to each other, and the positive voltage and the negative voltage are held in the liquid crystal capacitor 120 in each pixel. Since the period to be performed is half of the period of the frame, a direct current component should not be applied to the liquid crystal capacitor 120. However, when the TFT push-down amount and the amount of leakage in the liquid crystal capacitance change from the time of shipment from the factory due to changes over time, the voltage LCcom is no longer the optimum value, and a DC component is applied to the liquid crystal capacitance 120, causing flicker. Will do.
In addition, the display panel 10 has different characteristics, and even if the register value is 0, a panel that needs to increase the voltage LCcom that minimizes flicker after a certain period of time and a voltage LCcom that minimizes flicker are displayed. There are panels that need to be reduced. In this case, even if the register value is 0, flicker occurs.

  Here, FIG. 14 is a diagram showing a change value of the voltage LCcom that minimizes the flicker amount with respect to the value of the register and the flicker that occurs after a predetermined time has elapsed after applying a voltage based on the value of the register. In this figure, the horizontal axis represents the register value. When the register value is positive, the positive voltage holding period is long, and when the register value is negative, the negative voltage holding period is long. ing. The vertical axis represents how much the flicker is minimized when the voltage LCcom is changed after a predetermined time has elapsed. The panel (1) in FIG. 14 is a panel that needs to increase the voltage applied to the voltage LCcom in order to minimize the flicker after a certain time has elapsed when the value of the register is 0. The panel (2) in FIG. 14 is a panel that needs to reduce the voltage applied to the voltage LCcom in order to minimize the flicker after a certain time has elapsed when the value of the register is 0. Note that the above-described second setting value, which is a setting value for designating the output timing of the start pulse Dyb, is the second setting value shown in FIG. 14, and for both the panels (1) and (2), In order to minimize the flicker after a certain period of time, the voltage LCcom needs to be reduced. Further, the first setting value described above, which is a setting value for designating the output timing of the start pulse Dyb, is the first setting value shown in FIG. 14, and for both the panels (1) and (2), In order to minimize the flicker after a certain period of time, the voltage LCcom needs to be increased.

  In the present embodiment, in order to suppress the occurrence of flicker, the timing of the start pulse Dyb is changed according to the value of the set value stored in the register, and the application of the DC component to the liquid crystal capacitor 120 is controlled. For example, when the value stored in the register is “−1”, the control circuit 52 causes the start pulse Dyb to be earlier than the timing T by one cycle of the clock signal Cly as shown in FIG. Change to (-1) and output. Then, the period of the first field is 239 periods of the clock signal Cly, while the period of the second field is 241 periods of the clock signal Cly. Accordingly, as shown in FIG. 11, the holding period of the negative voltage written by the selection triggered by the supply of the start pulse Dyb is the holding of the positive voltage written by the selection triggered by the supply of the start pulse Dya. Longer than the period. Therefore, in the pixel, the effective voltage value held at the negative voltage is increased, and the effective voltage value held at the positive voltage is lowered.

  When the voltage effective value held at the negative voltage becomes higher than the voltage effective value held at the positive voltage, the pixel becomes brighter when holding the negative voltage, and darkened when holding the positive voltage. Change. If the value stored in the register is “−2”, the control circuit 52 changes the start pulse Dyb to a timing earlier than the timing T by two cycles of the clock signal Cly and outputs the result. Then, in the pixel, the voltage effective value held at the negative voltage is further increased and the voltage effective value held at the positive voltage is further reduced as compared with the case where the value stored in the register is “−1”.

  On the other hand, if the value stored in the register is “+1”, the control circuit 52 causes the start pulse Dyb to be delayed by one cycle of the clock signal Cly from the timing T, as shown in FIG. Change to 1) and output. Then, the period of the first field is 241 periods of the clock signal Cly, while the period of the second field is 239 periods of the clock signal Cly. Thus, as shown in FIG. 13, the holding period of the negative voltage written by the selection triggered by the supply of the start pulse Dyb is the holding of the positive voltage written by the selection triggered by the supply of the start pulse Dya. Shorter than the period. Therefore, in the pixel, the effective voltage value held at the positive voltage is increased, and the effective voltage value held at the negative voltage is lowered.

  When the effective voltage value held at the positive voltage becomes higher than the effective voltage value held at the negative voltage, the pixel becomes brighter when holding the positive voltage and darker when holding the negative voltage. To do. If the value stored in the register is “+2”, the control circuit 52 changes the start pulse Dyb to a timing later than the timing T by two cycles of the clock signal Cly and outputs it. Then, in the pixel, the effective voltage value held at the positive polarity is further increased and the effective voltage value held at the negative polarity is further reduced as compared with the case where the value stored in the register is “+1”.

  By the way, in this embodiment, the electro-optical device 1 detects whether the pixel is bright (or dark) in the case where the pixel holds a positive voltage or the case where the pixel holds a negative voltage. To do. If it is detected which pixel is brighter when the positive voltage is held or when the negative voltage is held, the effective voltage value increases when the positive voltage is held or when the negative voltage is held. You can see what is being done. The electro-optical device 1 controls the voltage of the counter electrode 108, the holding period of the positive voltage, and the holding period of the negative voltage according to the detection result to suppress the appearance of flicker. Hereinafter, this operation will be described.

  First, when the drive of the display panel 10 is started, the control circuit 52 stores “0” in the register in order to specify the output timing of the start pulse Dyb. Further, the control circuit sets the voltage of the counter electrode 108 to the voltage LCcom as the voltage at the start of driving of the counter electrode 108. Next, in the electro-optical device 1, when the synchronization signal Vsync and the display data Video are supplied from the external host device to the processing circuit 50, the data signal Vid is supplied to the display panel 10. Note that the pixel on the 480th row is a detection pixel that measures the brightness of the pixel by the optical sensor 71, so the display data processing circuit 54 does not depend on the gradation specified by the display data Video. The data signal Vid is supplied so that the pixel of the eye always has an intermediate gray level between the highest white and the lowest black. Further, the control circuit 52 drives the display panel 10 in accordance with the supplied synchronization signal Vsync. Here, since the value stored in the register is “0”, the control circuit 52 outputs the start pulse Dyb at the timing T.

  When the display panel 10 is driven, the brightness of the pixels in the 480th row is measured by the optical sensor 71, and the signal Sb is supplied to the data analysis unit 72. The data analysis unit 72 detects from the signal Sb which is brighter when the pixel holds the positive voltage or the negative voltage, and sends the signal Sa2 to the control circuit 52. Output. The data analysis unit 72 converts the signal Sb into a digital signal Sdb and performs a fast Fourier transform process, so that the brightness when the pixel holds the positive voltage and the brightness when the pixel holds the negative voltage. Detect differences in brightness. The data analysis unit 72 outputs a signal Sa1 indicating the detected brightness difference to the control circuit 52.

  Thereafter, the control circuit 52 operates according to the flowchart shown in FIG. 15, and first acquires the signal Sa1 and the signal Sa2 supplied from the data analysis unit 72 (step SA1). The control circuit 52 obtains the flicker amount from the acquired signal Sa1. Next, the control circuit 52 determines whether the flicker amount is equal to or greater than a predetermined threshold value. This threshold value is set to a value that is not recognized as flicker when the user looks at the display panel 10. When the flicker amount is less than the threshold value (NO in step SA2), the control circuit 52 returns the process flow to step SA1. Note that the control circuit 52 may return the processing flow to step SA1 after a predetermined time has elapsed (for example, several seconds to several minutes).

  The display panel 10 has individual differences as shown in FIG. 14, and even if the application time ratio is the same between the positive voltage and the negative voltage, the DC component acts on the liquid crystal capacitor 120 over time. There is a difference between the effective voltage value held at the positive voltage and the effective voltage value held at the negative voltage. As described above, when a difference occurs between the effective voltage value held at the positive voltage and the effective voltage value held at the negative voltage, flicker occurs. When the time has elapsed and the flicker amount becomes equal to or greater than the threshold value (YES in step SA2), the control circuit 52 adjusts the voltage of the counter electrode 108 (step SA3).

  FIG. 16 is a flowchart of processing for adjusting the voltage of the counter electrode 108. Specifically, first, the control circuit 52 adds a predetermined voltage (for example, several mV) to the voltage of the counter electrode 108 at this time (step SB1). Note that the predetermined voltage is not limited to several mV, and may be several tens of mV. Next, the control circuit 52 acquires the signal Sa1 and the signal Sa2 (step SB2). When the voltage applied to the counter electrode 108 is changed, a difference occurs between the effective voltage value held at the positive voltage and the effective voltage value held at the negative voltage, and flicker occurs in the pixel. Here, the control circuit 52 specifies the flicker amount from the acquired signal, and when the flicker amount has not increased (NO in step SB3), the process flow returns to step SB1.

  On the other hand, when it is determined YES in step SB3, the control circuit 52 subtracts a predetermined voltage (the same voltage as the voltage in step SB1) from the voltage of the counter electrode 108 at this time (step SB4). Next, the control circuit 52 acquires the signal Sa1 and the signal Sa2 (step SB5). Here, the control circuit 52 specifies the flicker amount from the acquired signal, and when the flicker amount has not increased (NO in step SB6), the process flow returns to step SB4. On the other hand, when it is determined YES in step SB6, the control circuit 52 adjusts the voltage applied to the counter electrode 108 by adding a predetermined voltage (the same voltage as the voltage in step SB1) to the voltage of the counter electrode 108. The process ends.

  Next, the control circuit 52 determines whether or not the voltage applied to the counter electrode 108 by the process of step SA3 has increased more than before the process of step SA3. When the voltage applied to the counter electrode 108 has been increased more positively than before adjustment by the process of step SA3 (YES in step SA4), the control circuit 52 adds 1 to the value of the register (step SA5). Is returned to step SA1. Since the value of the register is 0 when driving is started, the value of the register is 1 here, and the output timing of the start pulse Dyb is later than the timing T. Here, in the pixel, the effective voltage value held at the positive voltage is increased, and the effective voltage value held at the negative voltage is lowered.

On the other hand, if the voltage applied to the counter electrode 108 has increased more negatively than before the adjustment (NO in step SA4), the control circuit 52 subtracts 1 from the register value (step SA3). SA6) The process flow is returned to step SA1. Since the value of the register is 0 when driving is started, the value of the register is −1 here, and the output timing of the start pulse Dyb is earlier than the timing T. Here, in the pixel, the effective voltage value held at the negative voltage is increased, and the effective voltage value held at the positive voltage is lowered.
Thereafter, the control circuit 52 repeats the processing of FIG. 15 and changes the voltage of the counter electrode 108 and the value of the register when the flicker amount is equal to or greater than the threshold value.

  FIG. 17 is a diagram illustrating an example of a change in the voltage of the counter electrode 108 and a change in the flicker amount when the processing of FIG. 15 is performed. Note that FIG. 17 shows changes in the voltage of the counter electrode 108 and changes in the flicker amount for a display panel in which the voltage LCcom needs to be increased when the value of the register is set to 0.

  When the value of the register is set to 0 and the display panel 10 is driven, there is a difference between the effective voltage value when the pixel holds the positive voltage and when the pixel holds the negative voltage due to the DC component applied to the liquid crystal. As a result, there is a difference in brightness between when the pixel holds a positive voltage and when the pixel holds a negative voltage. This difference increases with time, and if the control circuit 52 determines YES in step SA2, the control circuit 52 performs the process of step SA3 (time t1).

  Specifically, first, the control circuit 52 adds a predetermined voltage to the voltage applied to the counter electrode 108 (step SB1). Here, if the voltage applied to the counter electrode 108 at this time is added, the display panel is a panel having the characteristic of (1) in FIG. Here, if the flicker amount has not increased (NO in step SB3), the flow of processing is returned to step SB1, and the voltage applied to the counter electrode 108 is increased. If the voltage applied to the counter electrode 108 continues to be increased, the optimum voltage LCcom is exceeded, and this time the flicker amount increases (YES in step SB3, time t2).

  When the flicker amount increases, the control circuit 52 subtracts a predetermined voltage from the voltage applied to the counter electrode 108 (step SB4, time point t3). Thereafter, when the amount of flicker increases (YES in step SB6), the control circuit 52 adds a predetermined voltage to the voltage applied to the counter electrode 108 (step SB7, time point t4).

  Here, as shown in FIG. 17, since the voltage of the counter electrode 108 has increased more positively than before the adjustment, YES is determined in step SA4, and the value of the register becomes +1. If the value of the register is changed when there is a difference in the effective voltage value between when the pixel holds a positive voltage and when it holds a negative voltage, the negative voltage is changed when the pixel already holds the positive voltage. Since there is a difference in the brightness of the pixel from when it is held, the change in the brightness difference of the pixel becomes large. However, in this embodiment, before changing the register value, the voltage of the counter electrode 108 is changed so that the amount of flicker is minimized, and the pixel holds the positive voltage and the negative voltage. Since the value of the register is changed after the voltage effective value has been changed little with respect to time, the change in the brightness of the pixel is small when the register value is changed, and the luminance change of the pixel is less visible .

  According to this embodiment, even in a display panel in which a direct current component is applied to the liquid crystal, the voltage of the counter electrode 108, the holding period of the positive voltage, and the holding period of the negative voltage are adjusted so as to suppress the occurrence of flicker. Therefore, the occurrence of flicker can be suppressed. In addition, since the occurrence of flicker can be suppressed without the user adjusting the application time ratio, there is no need for an adjustment process before shipping the device, and the power consumed in the adjustment before shipping can be suppressed. it can.

[Second Embodiment]
Next, an electro-optical device 1 according to a second embodiment of the invention will be described. The electro-optical device 1 according to the second embodiment has the same hardware configuration as that of the first embodiment. The electro-optical device 1 according to the second embodiment is different from the electro-optical device 1 according to the first embodiment in that processing performed by the control circuit 52 is different. Therefore, in the following, this difference will be mainly described.

FIG. 18 is a flowchart showing a flow of processing performed by the control circuit 52 according to the second embodiment. In the control circuit 52 according to the present embodiment, the process from the start of driving the display panel 10 to step SC4 is the same as the process from the start of driving to step SA4 in the first embodiment. Therefore, the description thereof is omitted.
When the voltage applied to the counter electrode 108 increases more negatively than before the adjustment by the process of step SC3 (NO in step SC4), the control circuit 52 sets the first set value described above in the register (step SC6). Further, when the voltage applied to the counter electrode 108 increases more positively than before adjustment by the process of step SC3 (YES in step SC4), the control circuit 52 sets the second set value described above in the register (step SC5). ).

  Next, when the flicker amount is equal to or greater than the threshold value (YES in step SC7), the process shown in FIG. 16 is performed to adjust the voltage of the counter electrode 108 (step SC8). When the process of step SC8 ends, the control circuit 52 determines whether or not the value stored in the register after step SC4 is the first set value. If the first set value has been stored in the register after step SC4 (YES in step SC9), the control circuit 52 subtracts 1 from the value of the adjustment value that stores the value to be set in the register. If the second set value is stored in the register later (NO in step SC9), 1 is added to the value of the adjustment value. Note that the value of the adjustment value is set to 0 when driving the display panel 10 is started. When the process of step SC10 or step SC11 is completed, the control circuit 52 sets the value of the adjustment value in the register (step SC12), and returns the process flow to step SC1. Thereafter, the control circuit 52 repeats the process of FIG. 18 and changes the potential of the counter electrode 108 and the value of the register when the flicker amount becomes equal to or greater than the threshold value.

  FIG. 19 is a diagram illustrating an example of a change in the voltage of the counter electrode 108 and a change in the flicker amount when the processing of FIG. 18 is performed. Note that FIG. 19 shows changes in the voltage of the counter electrode 108 and changes in the flicker amount for the display panel having the characteristics of (1) in FIG.

  When the value of the register is set to 0 and the display panel 10 is driven, the amount of flicker increases due to the direct current component applied to the liquid crystal. When the flicker amount increases and the control circuit 52 determines YES in step SC2, the control circuit 52 performs the process in step SC3. Here, the voltage of the counter electrode 108 increases more positively than before the adjustment, and YES is determined in step SC4, and the value of the register is set to the second set value. Since the second set value is a value that requires the voltage LCcom to be reduced in order to minimize flicker, the flicker amount increases when the second set value is set in the register.

Thereafter, if YES is determined in step SC7, the process of step SC8 is performed. First, the control circuit 52 adds a predetermined voltage to the voltage applied to the counter electrode 108 at time t11 in FIG. 18 (step SB1). Here, if the voltage applied to the counter electrode 108 at this time is added, the display panel is a panel having the characteristic of (1) in FIG. Then, the control circuit 52 determines YES in Step SB3 and subtracts a predetermined voltage from the voltage applied to the counter electrode 108 (Step SB4, time t12).
If the voltage applied to the counter electrode 108 at this time is minus, the amount of flicker is reduced. If the flicker amount has not increased (NO in step SB6), the process flow returns to step SB4, and the voltage applied to the counter electrode 108 is decremented. If the voltage applied to the counter electrode 108 continues to be increased, the optimum voltage LCcom is exceeded, and this time the flicker amount increases (YES in step SB6, time t13). Here, the control circuit 52 adds a predetermined voltage to the voltage applied to the counter electrode 108 (step SB7, time t14). Thereby, the voltage of the counter electrode 108 returns to the voltage before adjusting the voltage of the counter electrode 108 in step SC3.

  Next, since the second setting value is set in the register (NO in step SC9), the control circuit 52 adds 1 to the adjustment value and sets the adjustment value in the register. In this embodiment, before changing the register value, the voltage of the counter electrode 108 is changed so that the amount of flicker is minimized, and when the pixel holds the positive voltage and when the pixel holds the negative voltage. Since the register value is changed after the voltage effective value is reduced to a small value, the change in the pixel brightness difference is small when the register value is changed, and the luminance change of the pixel is difficult to be visually recognized.

  Also in this embodiment, even in a display panel in which a direct current component is applied to the liquid crystal, the potential of the counter electrode 108 and the holding period of the positive voltage and the holding period of the negative voltage are adjusted so as to suppress the occurrence of flicker. Therefore, the occurrence of flicker can be suppressed. In addition, since the occurrence of flicker can be suppressed without the user adjusting the application time ratio, there is no need for an adjustment process before shipping the device, and the power consumed in the adjustment before shipping can be suppressed. it can.

[Third Embodiment]
Next, an electro-optical device 1 according to a third embodiment of the invention will be described. The electro-optical device 1 according to the third embodiment has the same hardware configuration as that of the first embodiment. The electro-optical device 1 according to the third embodiment is different from the electro-optical device 1 according to the first and second embodiments in that processing performed by the control circuit 52 is different. Therefore, in the following, this difference will be mainly described.

  FIG. 20 shows a process performed when the control circuit 52 according to the present embodiment adjusts the voltage of the counter electrode, that is, a process performed at step SA3 in the first embodiment and steps SC3 and SC8 in the second embodiment. It is the flowchart which showed the flow of. In the present embodiment, the process for adjusting the voltage of the counter electrode is different from the above-described embodiment.

  Specifically, first, the control circuit 52 adds a predetermined voltage (for example, several mV) to the voltage of the counter electrode 108 (step SD1). Next, the control circuit 52 counts a predetermined time (for example, 2 seconds) (step SD2). The fixed time is not limited to 2 seconds, and may be a time shorter than 2 seconds or longer than 2 seconds. When the control circuit 52 finishes counting the predetermined time, the control circuit 52 acquires the signal Sa1 and the signal Sa2 (step SD3). When the potential of the counter electrode 108 is changed, flicker occurs. Here, the control circuit 52 specifies the flicker amount from the acquired signal, and when the flicker amount has not increased (NO in step SD4), the process flow returns to step SD1.

  On the other hand, when it is determined YES in step SD4, the control circuit 52 subtracts a predetermined voltage (the same voltage as the voltage in step SD1) from the voltage of the counter electrode 108 (step SD5). Next, the control circuit 52 counts the same predetermined time as step SD2 (step SD6). When the control circuit 52 finishes counting the predetermined time, the control circuit 52 acquires the signal Sa1 and the signal Sa2 (step SD7). Here, the control circuit 52 specifies the flicker amount from the acquired signal, and when the flicker amount has not increased (NO in step SD8), the process flow returns to step SD5. On the other hand, if it is determined YES in step SB8, the control circuit 52 adjusts the potential of the counter electrode 108 by adding a predetermined voltage (the same voltage as the voltage of step SD1) to the voltage of the counter electrode 108. finish.

  According to the present embodiment, when the potential of the counter electrode 108 is adjusted, since there are Step SD2 and Step SD6, the potential of the counter electrode 108 is changed over time. As a result, the potential of the counter electrode 108 changes over time as compared with the processing in FIG. 15, and the luminance change of the pixel caused by changing the potential of the counter electrode 108 becomes difficult to be visually recognized. Note that when the voltage of the counter electrode 108 is changed, a value is set in the register and then the charge inside the liquid crystal is biased. An internal electric field is generated due to the bias of the charge, and the liquid crystal layer is affected by the influence of the internal electric field. It is preferable that the process of FIG. 20 is completed earlier than the DC component is applied.

[Fourth Embodiment]
Next, an electro-optical device 1 according to a fourth embodiment of the invention will be described. The electro-optical device 1 according to the fourth embodiment has the same hardware configuration as that of the first embodiment. The electro-optical device 1 according to the fourth embodiment is different from the electro-optical device 1 according to the first embodiment in that processing performed by the control circuit 52 is different. Therefore, in the following, this difference will be mainly described.

  FIG. 21 is a flowchart showing the flow of processing performed by the control circuit 52 according to the fourth embodiment. In the first embodiment, the driving of the display panel 10 is started after the register value is set to 0. However, in the control circuit 52 according to the present embodiment, the first set value or the first value is set. Driving is started after any of the two set values is set in the register. Further, in the present embodiment, the processing from the start of driving the display panel 10 to step SE4 is the same as the processing from the start of driving in the first embodiment to step SA4. Description is omitted.

  The control circuit 52 adjusts the voltage of the counter electrode 108 by the process of step SE3, and then determines whether the first set value or the second set value is set in the register. When the first set value is set in the register (YES in step SE4), the control circuit 52 sets the second set value in the register (step SE5), and the second set value is set in the register. (NO in step SE4), the first set value is set in the register (step SE6). Next, the control circuit 52 acquires the signal Sa1 and the signal Sa2 (step SE7). Here, the control circuit 52 specifies the flicker amount from the acquired signal, and when it is not less than the threshold value (NO in step SE8), returns the process flow to step SE7. On the other hand, if the control circuit 52 determines YES in step SE8, it returns the process flow to step SE1. Thereafter, the control circuit 52 repeats the processing of FIG. 21, and changes the potential of the counter electrode 108 and the value of the register when the flicker amount becomes equal to or greater than the threshold value.

  FIG. 22 is a diagram showing an example of changes in the voltage of the counter electrode 108 and changes in the flicker amount when the processing of FIG. 21 is performed. When the value of the register is set to the first setting value and the display panel 10 is driven, the flicker amount increases. When the amount of flicker increases and YES is determined in step SE2, processing in step SE3 is performed. Here, the voltage of the counter electrode 108 increases more positively than before the adjustment, and YES is determined in step SE4, and the value of the register is set to the second set value (time point t41). It should be noted that the flicker amount becomes less than the threshold due to the adjustment of the voltage of the counter electrode 108 in step SE3, and YES is determined in step SE8, and the process flow returns to step SE1.

  Thereafter, the second set value set in the register is a value that requires the voltage LCcom to be reduced in order to minimize the flicker, and therefore the amount of flicker increases. Then, the process of step SE3 is performed again. Here, the voltage of the counter electrode 108 returns to the initial voltage (time t42). Next, since the second setting value is set in the register, the control circuit 52 determines NO in step SE4 and sets the first setting value in the register. It should be noted that the flicker amount becomes less than the threshold due to the adjustment of the voltage of the counter electrode 108 in step SE3, and YES is determined in step SE8, and the process flow returns to step SE1. Thereafter, the voltage of the counter electrode is changed by repeating the processing of FIG. Further, the first set value and the second set value are alternately set for the register, and the flicker amount is controlled to be within a certain range.

  According to this embodiment, even in a display panel in which a DC component is applied to the liquid crystal, the potential of the counter electrode 108 and the holding period of the positive voltage and the holding period of the negative voltage are adjusted so as to suppress the occurrence of flicker. Therefore, the occurrence of flicker can be suppressed. In addition, since the occurrence of flicker can be suppressed without the user adjusting the application time ratio, there is no need for an adjustment process before shipping the device, and the power consumed in the adjustment before shipping can be suppressed. it can.

[Fifth Embodiment]
Next, an electro-optical device 1 according to a fifth embodiment of the invention will be described. The electro-optical device 1 according to the fifth embodiment has the same hardware configuration as that of the first embodiment. The electro-optical device 1 according to the fifth embodiment is that a process performed by the control circuit 52 is added to the fourth embodiment. Therefore, in the following, this difference will be mainly described.

  FIG. 23 is a flowchart showing a flow of processing performed by the control circuit 52 according to the fifth embodiment. In the embodiment, the control circuit 52 stores the voltage of the counter electrode 108 at the start of driving the display panel 10 as an initial voltage. Also in the control circuit 52 according to the present embodiment, driving is started after the first set value is set in the register. Since the processing from the start of driving the display panel 10 to step SF3 is the same as the processing from the start of driving to step SE3 in the fourth embodiment, the description thereof is omitted.

  In this embodiment, after adjusting the voltage of the counter electrode 108 in step SF3, it is determined whether the voltage of the counter electrode 108 is the above-described initial voltage. Here, when the voltage of the counter electrode 108 is the initial voltage (YES in step SF4), the control circuit 52 returns the process flow to step SF1. On the other hand, when the voltage of the counter electrode 108 is not the initial voltage (NO in step SF4), the control circuit 52 shifts the processing flow to step SF5. In addition, since the process of step SF5 to step SF9 is the same as the process of step SE4 to step SE8 of 4th Embodiment, the description is abbreviate | omitted.

  FIG. 24 is a diagram illustrating an example of a change in the voltage of the counter electrode 108 and a change in the flicker amount when the processing of FIG. 23 is performed. When the value of the register is set to the first setting value and the display panel 10 is driven, the flicker amount increases. If the amount of flicker increases and YES is determined in step SF2, the process of step SF3 is performed. Here, the voltage of the counter electrode 108 increases positively before the adjustment, and NO is determined in step SF4, and the value of the register is set to the second set value in step SF6 (time point t51). It should be noted that the flicker amount becomes less than the threshold due to the adjustment of the voltage of the counter electrode 108 in step SF3, and YES is determined in step SF9, and the process flow returns to step SF1.

  Thereafter, the second set value set in the register is a value that requires the voltage LCcom to be reduced in order to minimize the flicker, and therefore the amount of flicker increases. Then, the process of step SE3 is performed again. Here, the voltage of the counter electrode 108 returns to the initial voltage (time t52). Since the voltage of the counter electrode 108 has returned to the initial voltage, the control circuit 52 determines YES in step SF4 and returns the process flow to step SF1.

  Here, since the value of the register is the second set value, the amount of flicker increases. If YES is determined in step SF2, the voltage of the counter electrode 108 is adjusted in step SF3. Here, the voltage of the counter electrode 108 is reduced (time t53). Next, the control circuit 52 determines NO in step SF4, and sets the first set value in the register.

  Since the first setting value set in the register is a value that requires the voltage LCcom to be increased in order to minimize flicker, the amount of flicker increases. Then, the process of step SE3 is performed again. Here, the voltage of the counter electrode 108 returns to the initial voltage (time t54). Since the voltage of the counter electrode 108 has returned to the initial voltage, the control circuit 52 determines YES in step SF4 and returns the process flow to step SF1. Here, the voltage of the counter electrode 108 returns to the initial state, and the first set value is set in the register. That is, the state returns to the initial driving state, and the above-described operation is repeated thereafter.

  Also in this embodiment, even in a display panel in which a direct current component is applied to the liquid crystal, the potential of the counter electrode 108 and the holding period of the positive voltage and the holding period of the negative voltage are adjusted so as to suppress the occurrence of flicker. Therefore, the occurrence of flicker can be suppressed. In addition, since the occurrence of flicker can be suppressed without the user adjusting the application time ratio, there is no need for an adjustment process before shipping the device, and the power consumed in the adjustment before shipping can be suppressed. it can.

[Electronics]
Next, an example of an electronic apparatus using the electro-optical device according to the above-described embodiment will be described. FIG. 25 is a plan view showing a configuration of a three-plate projector using the display panel 10 of the electro-optical device 1 described above as a light valve. In this projector 2100, the light to be incident on the light valve is supplied with three primary colors of R (red), G (green), and B (blue) by three mirrors 2106 and two dichroic mirrors 2108 arranged inside. And led to the light valves 100R, 100G and 100B corresponding to the respective primary colors. Note that B light has a longer optical path than other R and G colors, and therefore, in order to prevent the loss, B light passes through a relay lens system 2121 including an incident lens 2122, a relay lens 2123, and an exit lens 2124. Led.

  Here, the configuration of the light valves 100R, 100G, and 100B is the same as that of the display panel 10 in the above-described embodiment, and image data corresponding to each color of R, G, and B supplied from an external host device (not shown). Are driven respectively. The lights modulated by the light valves 100R, 100G, and 100B are incident on the dichroic prism 2112 from three directions. In the dichroic prism 2112, the R and B light beams are refracted at 90 degrees, while the G light beam travels straight. Therefore, after the images of the respective colors are combined, they are projected in the normal rotation and enlarged by the lens unit 2114, so that a color image is displayed on the screen 2120.

  The transmitted images of the light valves 100R and 100B are projected after being reflected by the dichroic prism 2112, whereas the transmitted image of the light valve 100G is projected as it is, and thus the images formed by the light valves 100R and 100B The image formed by the light valve 100G has a left-right reversal relationship.

  In addition to the electronic device described with reference to FIG. 25, the rear projection type television or direct view type, for example, a mobile phone, a personal computer, a video camera monitor, a car navigation device, a pager, an electronic device Examples include notebooks, calculators, word processors, workstations, videophones, POS terminals, digital still cameras, and devices with touch panels. Needless to say, the electro-optical device according to the present invention is applicable to these various electronic devices.

[Modification]
As mentioned above, although embodiment of this invention was described, this invention is not limited to embodiment mentioned above, It can implement with another various form. For example, the present invention may be implemented by modifying the above-described embodiment as follows. In addition, you may combine each of embodiment mentioned above and the following modifications.

  In each of the above-described embodiments, the normally white mode in which white is displayed in a state in which no voltage is applied is used. However, a normally black mode in which black is displayed in a state in which no voltage is applied may be used.

  In the above-described embodiment, the brightness of the pixels in the 480th row is detected by the optical sensor 71, but the pixels for detecting the brightness are not limited to the 480th row and may be pixels in other rows. .

  Also in the fourth embodiment and the fifth embodiment described above, the process for adjusting the voltage of the counter electrode is not the process shown in FIG. 16 but the process shown in FIG. 20, and the voltage of the counter electrode 108 is increased over time. It may be changed.

  In the above-described embodiment, the detection circuit 70 detects the brightness of the pixel using the optical sensor 71 to thereby detect the flicker amount (difference between the effective voltage when holding the positive voltage and the effective voltage when holding the negative voltage). ) Is detected, but the method of detecting the flicker amount is not limited to the method of the above-described embodiment. For example, a sensor that detects the current flowing through the pixel is provided to detect the difference between the current that flows through the pixel when a positive voltage is applied and the current that flows through the pixel when a negative voltage is applied. The difference between the effective voltage and the effective voltage when holding the negative voltage) may be detected.

DESCRIPTION OF SYMBOLS 1 ... Electro-optical apparatus, 10 ... Display panel, 50 ... Processing circuit, 52 ... Control circuit, 54 ... Display data processing circuit, 56 ... D / A conversion circuit, 58 ... Data analysis part, 70 ... Detection circuit, 71 ... Light Sensor, 72 ... Data analysis unit, 105 ... Liquid crystal, 108 ... Counter electrode, 110 ... Pixel, 112 ... Scan line, 114 ... Data line, 116 ... TFT, 118 ... Pixel electrode, 120 ... Liquid crystal capacitance, 130 ... Scan line drive Circuit: 140 ... Data line drive circuit, 142 ... Sampling signal output circuit, 146 ... TFT, 581 ... AD converter, 582 ... Calculator, 2100 ... Projector

Claims (8)

A plurality of scanning lines and a plurality of data lines, respectively, corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, each having a gradation according to a voltage of a data signal supplied to the data line when the scanning line is selected; The pixel includes a pixel electrode to which the data signal is applied, a counter electrode facing the pixel electrode, and an electro-optical material sandwiching an electro-optical material between the pixel electrode and the counter electrode. An optical device,
A positive field that supplies a positive voltage, which is a voltage corresponding to the gray level of the pixel and is higher than a predetermined potential, to the data line corresponding to the pixel as the data signal; and the gray level of the pixel In each of the negative polarity fields that supply a negative polarity voltage that is a low voltage with reference to a predetermined potential as a data signal to the data line corresponding to the pixel, A scanning line driving circuit to select in order;
When one scanning line is selected in the positive polarity field, a voltage corresponding to the gradation of the pixel is applied to the data line corresponding to the pixel as the data signal for the pixel located on the one scanning line. When the one scanning line is selected in the negative field, the voltage corresponding to the gray level of the pixel corresponds to the pixel as the data signal for the pixel located on the one scanning line. A data line driving circuit for supplying to the data line to be
A detection circuit for detecting a difference between an effective voltage of the voltage applied to the pixel in the positive polarity field and an effective voltage of the voltage applied to the negative polarity field;
When the difference detected by the detection circuit is greater than or equal to a predetermined threshold value so that the difference detected by the detection circuit changes within a predetermined range, the difference between the counter electrode and the counter electrode is reduced so that the difference is less than the threshold value. A control circuit for changing the voltage, and controlling the period length of the positive polarity field and the negative polarity field after the change;
An electro-optical device comprising: The voltage of the counter electrode is changed to a voltage at the start of driving of the counter electrode when the difference detected by the detection circuit becomes equal to or greater than the threshold after controlling the period length. The electro-optical device according to 1. The voltage at the start of driving the counter electrode is a voltage that does not cause a difference between the effective voltage of the voltage applied in the positive polarity field and the effective voltage of the voltage applied in the negative polarity field at the start of driving. The electro-optical device according to claim 2, wherein the electro-optical device is provided.   The electro-optical device according to claim 1, wherein when the voltage of the counter electrode is changed, the voltage is changed with time. 5. The electro-optical device according to claim 4, wherein when the voltage of the counter electrode is changed, the voltage is changed earlier than the state of charge bias in the electro-optical material changes. The detection circuit is configured to detect the brightness of the pixel when the pixel located on the one scanning line is applied with a voltage in the positive polarity field and the pixel when the voltage is applied in the negative polarity field. Based on the detected brightness difference, the difference between the effective voltage of the voltage applied to the pixel in the positive polarity field and the effective voltage of the voltage applied in the negative polarity field based on the detected brightness difference. The electro-optical device according to claim 1, wherein the electro-optical device is detected. A plurality of scanning lines and a plurality of data lines, respectively, corresponding to the intersections of the plurality of scanning lines and the plurality of data lines, each having a gradation according to a voltage of a data signal supplied to the data line when the scanning line is selected; The pixel includes a pixel electrode to which the data signal is applied, a counter electrode facing the pixel electrode, and an electro-optical material sandwiching an electro-optical material between the pixel electrode and the counter electrode. An optical device control method comprising:
In each of the positive and negative fields, the plurality of scanning lines are selected in a predetermined order,
When one scanning line is selected in the positive polarity field, the voltage corresponding to the gray level of the pixel is higher than the pixel positioned on the one scanning line with reference to a predetermined potential. Supply the voltage of either the positive polarity or the negative polarity, which is lower, to the data line corresponding to the pixel as the data signal,
When the one scanning line is selected in the negative polarity field, the voltage corresponding to the gradation of the pixel is set to the positive polarity or the negative polarity with respect to the pixel located on the one scanning line. Supply the voltage of the other polarity as the data signal to the data line corresponding to the pixel,
Detecting the difference between the effective voltage of the voltage applied in the positive polarity field to the pixel and the effective voltage of the voltage applied in the negative polarity field;
When the difference is equal to or greater than a predetermined threshold so that the difference changes within a predetermined range, the voltage of the counter electrode is changed so that the difference is less than the threshold, and after the change, the positive electrode A method for controlling an electro-optical device, characterized by controlling a period length of a negative field and a negative field.   An electronic apparatus comprising the electro-optical device according to claim 1.

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