JP2012157104A - Voltage-dividing rectification circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently provide a DC voltage whose voltage is lower than a commercial AC power supply.SOLUTION: The voltage-dividing rectification circuit includes a rectification circuit which performs full-wave rectification on an AC power supply voltage, a voltage-dividing charge circuit consisting of N-pieces of voltage-dividing charging capacitors connected in series for charging the rectification output that is outputted from the rectification circuit and (N-1) pieces of capacitor separation diodes connected among the N-pieces of voltage-dividing charging capacitors, an output capacitor connected in parallel to the voltage-dividing charge circuit, a drive circuit connected in series to the output capacitor, a switching circuit which turns ON the drive circuit when the AC power supply voltage drops beyond a predetermined voltage value, and a discharge circuit which, when the drive circuit is turned ON, moves the electric charges accumulated in the N pieces of voltage-dividing charging capacitors connected in series to the output capacitor. The electric charges accumulated in the N-pieces of voltage-dividing charging capacitors are moved to the output capacitor at each predetermined timing.

Description

  The present invention relates to a voltage-dividing rectifier circuit, and more particularly to a technique suitable for use in a voltage-dividing rectifier circuit that divides and rectifies a commercial AC voltage into a DC voltage.

Conventionally, in order to obtain a DC voltage lower than that of a commercial AC power source, there are roughly the following methods.
(A) AC of commercial power supply voltage is converted into low voltage AC by a transformer and then rectified to DC. (B) A direct current obtained by rectifying the alternating current of the commercial power supply voltage is divided using a resistor to obtain a low direct current voltage. (C) After converting AC of commercial power supply voltage to high frequency, it is converted to low voltage by a small transformer using ferrite and then rectified to obtain DC.

  However, these conventional techniques have the following problems. That is, since the transformer used for the commercial AC power source of (a) uses silicon steel, it becomes heavier and larger, and loss due to iron loss and copper loss is large. Further, in (b), for example, when a 10V direct current is obtained from a 100V alternating current, the loss due to the resistance reaches 90%, and the energy loss is extremely large. Also, if the current is large, measures such as heat dissipation are required. Furthermore, (c) can be reduced in size because the capacitance of the capacitor is small. However, the circuit becomes complicated and expensive, and the power supply used at all times has a large loss.

  In order to solve the above problems, Patent Document 1 proposes a power supply voltage dividing rectifier circuit that can obtain a DC low voltage from a commercial AC power supply with a simple circuit configuration without using a transformer.

  However, in the case of the power supply voltage dividing rectifier circuit proposed in Patent Document 1, since the commercial power supply voltage is half-wave rectified, only the positive half-cycle portion of the AC voltage is extracted, and the negative half-cycle is There was a problem that the current could not pass through the diode and the efficiency was poor. Therefore, Patent Document 2 proposes a voltage dividing rectifier circuit that allows current to pass even in a negative half cycle.

Japanese Patent Laid-Open No. 10-14239 JP 11-215830 A

The voltage dividing rectifier circuit proposed in Patent Document 2 is provided separately with a circuit that divides the power supply voltage in the positive half cycle of the AC voltage and a circuit that divides the power supply voltage in the negative half cycle of the AC voltage. ing. For this reason, a large number of parts are required, and there is a disadvantage that the circuit scale becomes large.
The present invention has been made in view of the above-described problems, and an object thereof is to efficiently obtain a DC voltage having a voltage lower than that of a commercial AC power supply.

  The voltage-dividing rectifier circuit according to the present invention is a voltage-dividing rectifier circuit that divides and outputs a rectified output of an AC power supply voltage, the first rectifier circuit that full-wave rectifies the AC power supply voltage, and the first rectifier. N voltage-dividing charging capacitors connected in series to charge the rectified output output from the circuit, and N capacitors that are divided to connect the N voltage-dividing charging capacitors (N -1) a voltage dividing charging circuit composed of a plurality of capacitor isolation diodes, an output capacitor connected in parallel with the voltage dividing charging circuit, a drive circuit connected in series with the output capacitor, and the N pieces N discharge paths connected to each of the voltage dividing capacitors and the output capacitor via discharge diodes, a second rectifier circuit for full-wave rectification of the AC power supply voltage, and the first Rectification output of rectifier circuit And the rectified output of the second rectifier circuit, and when the output of the second rectifier circuit is lower than the rectified output of the first rectifier circuit by a predetermined value or more, the drive circuit is A switching circuit that is turned on, and when the drive circuit is turned on, the charge accumulated in each of the N voltage-dividing charging capacitors connected in series is supplied to the output capacitor and the discharge circuit. It is moved through the drive circuit.

  According to the voltage dividing rectifier circuit of the present invention, the configuration can be simplified because there is one voltage dividing charging circuit for dividing and charging the rectified output obtained by full-wave rectifying the AC power supply voltage by the rectifying circuit.

FIG. 3 is a block diagram illustrating a path through which a current for charging a voltage dividing capacitor flows, according to the first embodiment of this invention. It is a figure which shows the 1st Embodiment of this invention and demonstrates the path | route which moves the electric charge accumulate | stored in the partial voltage charging circuit to an output capacitor. It is a figure which shows the 1st Embodiment of this invention and demonstrates the timing which moves the electric charge currently charged by the capacitor | condenser for partial pressure charging to an output capacitor. It is a block diagram which shows the 2nd Embodiment of this invention and shows the example comprised by one rectifier circuit. It is a figure which shows the 3rd Embodiment of this invention and demonstrates schematic structure of a power line carrier communication system. It is a figure which shows the structural example of the LED circuit by which dimming control is carried out. It is a block diagram which shows the 4th Embodiment of this invention and shows what reduced the voltage drop in a discharge circuit. FIG. 10 is a diagram illustrating a path for moving charges accumulated in a divided charging circuit to an output capacitor according to a fourth embodiment of the present invention. It is a block diagram which shows the 5th Embodiment of this invention and shows what further reduced the voltage drop in a discharge circuit. FIG. 10 is a diagram illustrating a path for moving charges accumulated in a divided charging circuit to an output capacitor according to a fifth embodiment of the present invention.

Next, embodiments of the present invention will be described with reference to the drawings.
(First embodiment)
As shown in FIG. 1, in the voltage dividing rectifier circuit of this embodiment, the AC power supply 100 is full-wave rectified by a first rectifier circuit 101 and a second rectifier circuit 102. A voltage dividing charging circuit 103 is connected in parallel with the first rectifying circuit 101.

  In the present embodiment, three voltage dividing charging capacitors C1 to C3 having the same capacity are connected in series, and capacitor dividing diodes D1 and D2 are connected between the capacitors to constitute the voltage dividing charging circuit 103. is doing. The number of capacitors may be N other than three (N is an integer of 2 or more), and the rectified output voltage of the first rectifier circuit 101 is divided into voltage values corresponding to the number of connections. When three capacitors C1 to C3 are connected in series as in this embodiment, the rectified output voltage of the first rectifier circuit 101 is divided into one third. The capacitor isolation diodes D1 and D2 are connected in such a direction that the current rectified by the first rectifier circuit 101 is supplied to the three capacitors C1 to C3 as a charging current.

A load circuit 104 is connected in parallel with the divided voltage charging circuit 103. Further, an output capacitor C4 is connected in parallel with the load circuit 104. A drive circuit 105 is connected in series with the parallel circuit of the load circuit 104 and the output capacitor C4 to move the electric charge accumulated in the three capacitors C1 to C3 to the output capacitor C4. In the present embodiment, an example is shown in which the drive circuit 105 is configured using the drive transistor Q2. The driving transistor Q2 uses a field effect transistor, and its gate electrode is connected to the switching circuit 106. In the present embodiment, an example in which a plurality of light emitting diodes LED are connected in series as a load is shown. In FIG. 1, six LEDs are connected in series, but the number of connections is arbitrary. In addition, an operation stabilization resistor R _S is connected in series with the plurality of LEDs.

  The switching circuit 106 is arranged to turn on the driving transistor Q2 when the value of the rectified voltage of the first rectifier circuit 101 is lowered to a predetermined value. In the present embodiment, an example in which a PNP-type bipolar transistor Q1 is used is shown.

  In the example of FIG. 1, the connection point of the first resistance voltage dividing circuit composed of resistors R1 and R2 is connected to the base electrode of the transistor Q1. One end of the first resistance voltage dividing circuit is connected to the + terminal of the first rectifier circuit 101, and the other end is connected to the + terminal of the second rectifier circuit 102. The + terminal and the − terminal of the second rectifier circuit 102 are connected via a resistor R5. As a result, the transistor Q1 is turned on when the rectified output voltage VDD2 of the second rectifier circuit 102 becomes lower than the output voltage VDD1 of the first rectifier circuit 101 to a predetermined value.

  The emitter electrode of the transistor Q1 is connected to the + terminal of the first rectifier circuit 101. Further, the collector electrode is connected to the negative terminal of the first rectifier circuit 101 via the second resistance voltage dividing circuit composed of resistors R3 and R4, the connection point of the resistors R3 and R4 and the gate of the driving transistor Q2. The electrode is connected.

  As described above, the voltage VDD2 that is different from the output voltage VDD1 of the first rectifier circuit 101 is generated in order to create the timing for turning on the driving transistor Q2 based on the difference between VDD1 and VDD2. The resistor R5 is for reducing the potential of VDD2 without being held when the absolute value of the AC voltage of the power supply becomes small.

  The positive potential side of the first capacitor C1 is connected to the positive terminal of the first rectifier circuit 101, and the negative potential side is connected to the negative terminal of the first rectifier circuit 101 via the discharging diode D3. The positive potential side of the second capacitor C2 is connected to the positive terminal of the first rectifier circuit 101 via the discharge diode D5, and the negative potential side is connected to the negative terminal of the first rectifier circuit 101 via the discharge diode D4. It is connected to the. The positive potential side of the third capacitor C3 is connected to the positive terminal of the first rectifier circuit 101 via the discharging diode D6, and the negative potential side is connected to the negative terminal of the first rectifier circuit 101.

  As shown in FIG. 3A, the potential of the output voltage VDD1 of the first rectifier circuit 101 of the present embodiment is the charge charged in the first to third capacitors C1 to C3 and the discharge circuit discharge. Due to the diodes D 3, 4, 5, and 6, the threshold voltage SV (approximately 46 V) that is approximately 1/3 of the peak voltage PV (approximately 140 V) of the AC power supply 100 is reduced. On the other hand, the rectified output voltage VDD2 of the second rectifier circuit 102 decreases to near the reference voltage. The reason why VDD2 does not drop to the reference potential as shown in FIG. 3B is that current is supplied from VDD1 through the first resistance voltage dividing circuit.

  In a period t1, t2, t3... Where the rectified output voltage VDD2 of the second rectifier circuit 102 is lower than the output voltage VDD1 of the first rectifier circuit 101 by a predetermined voltage, the transistor Q1 is turned on. Yes. As a result, a voltage VG is generated at the connection point between the resistors R3 and R4 in the second resistance voltage dividing circuit connected to the collector electrode of the transistor Q1, and this voltage VG is applied to the gate electrode of the driving transistor Q2. As a result, the driving transistor Q2 enters an operating state.

  When the driving transistor Q2 is in an operating state, a charging current flows through the output capacitor C4. As a result, the charges charged in the three capacitors C1 to C3 are discharged, and the output capacitor C4 is charged. The discharge circuit in the present embodiment has three discharge routes (discharge routes). The discharge route of the first capacitor C1 is the route of the first capacitor C1, the output capacitor C4, the driving transistor Q2, and the discharging diode D3, as indicated by an arrow Y1 in FIG.

  Further, the discharge route of the second capacitor C2 is the route of the second capacitor C2, the discharge diode D5, the output capacitor C4, the driving transistor Q2, and the discharge diode D4 as shown by an arrow Y2 in FIG. . Further, the discharge route of the third capacitor C3 is the route of the third capacitor C3 → the discharge diode D6 → the output capacitor C4 → the driving transistor Q2, as indicated by an arrow Y3 in FIG.

  Since each capacitor C1 to C3 has accumulated electric charge that is a voltage obtained by dividing the rectified output voltage by one third, the voltage accumulated in the output capacitor C4 is 3 minutes of the peak value of the rectified output voltage. 1 of In other words, a voltage obtained by dividing the rectified output voltage of the first rectifier circuit 101 by one third can be applied to the load circuit 104 for driving.

  In the three discharge routes, two discharge diodes are inserted only in the second discharge route (arrow Y2), but there is no problem because the output capacitor C4 is delayed by that amount. Even if there is some variation in the capacitance values of the three capacitors C1, C2, and C3, the difference is that when the output capacitor C4 is charged, the capacitors that have been charged up to a high voltage are sequentially discharged from the same potential. It is absorbed during operation.

  As described above, in the present embodiment, the power supply voltage can be generated at a voltage dividing ratio corresponding to the number of smoothing capacitors with a lightweight structure using a series circuit of smoothing capacitors. As a result, high-frequency pulsed switching noise is not generated unlike a switching regulator. This is only accompanied by a loss due to the diode, and is more efficient than a transformer type or switching regulator. Furthermore, even when used as a power supply for a switching regulator, the switching circuit can be operated with a low DC power supply voltage instead of a switching operation with a high DC power supply voltage such as 100 V or 200 V, so that radiation noise from the circuit can be reduced. .

(Second Embodiment)
Next, a second embodiment of the present invention will be described.
FIG. 4 is a block diagram for explaining a second embodiment of the present invention. As shown in FIG. 4, in the present embodiment, the second rectifier circuit 102 is omitted, and the voltage VDD1 for charging the divided voltage charging circuit 103 after passing through the backflow prevention diode D7 is used as the voltage of the first rectifier circuit 101. The output is the rectified output voltage VDD2.

  That is, when the absolute value of the AC voltage of the power supply decreases, the voltage of the rectified output voltage VDD2 decreases, so that current flows from the voltage point of VDD1 to the negative electrode of the resistors R1 → R2 → R5 → first rectifier circuit 101. Q1 operates. Thereby, it is detected that the voltage VDD2 is lower than the voltage VDD1 by a predetermined value. By configuring in this way, there is an advantage that only one rectifying diode bridge is required. The backflow prevention diode D7 is for preventing the charge accumulated in the capacitors C1, C2, and C3 from flowing directly to the first rectifier circuit 101 and the resistor 5. The resistor R5 is for reducing the potential of VDD2 without being held when the absolute value of the AC voltage of the power supply becomes small, as in the examples of FIGS.

(Third embodiment)
In the first and second embodiments described above, the transistor Q1 is turned on during the periods t1, t2, t3... Where the voltage VDD2 is lower than the voltage VDD1 by a predetermined voltage. In these periods t1, t2, t3,..., No current flows through the rectifier circuit, so that the amount of noise superimposed on the power supply line is small.

Therefore, in the present embodiment, an embodiment will be described in which power line communication is performed by superimposing communication signals in periods t1, t2, t3,.
FIG. 5 is a diagram illustrating a schematic configuration of the power line carrier communication system 10 of the present embodiment. As shown in FIG. 5, the power line carrier communication system 10 of the present embodiment turns on / off the power supplied from the power supply source AC to the first load 501 and the second load 502 via the power carrier line 300. Take control. In FIG. 5, the third load 503 is connected to the power carrier line 300, but the power line carrier communication system 10 of the present embodiment does not perform power on / off control for the third load 503.

  In the power line carrier communication system 10 of the present embodiment, the power line communication control area 500 is configured, and a line filter is disposed in the power carrier line 300 that enters and exits the power line communication control area 500, thereby Noise is not superimposed on the power transfer lines 300a and 300b.

  In the example of FIG. 5, the input line filter 200 that removes noise superimposed on the power carrier line 300 that supplies power from the power supply source AC to the power line communication control region 500, and the first load 501 from the power line communication control region 500. The first line filter 201 disposed on the power supply line 301 that supplies power to the second line, and the second line disposed on the power supply line 302 that supplies power to the second load 502 from the power line communication control region 500. A filter 202 and a third line filter 203 disposed on a power line that supplies power to the third load 503 from the power line communication control area 500 are shown.

  The input line filter 200 to the third line filter 203 cut noise input via the power carrier line 300, and no malfunction occurs in data communication performed between the controller 400 and the response terminals 110 and 120. Like that. In addition, the frequency signal for data communication performed between the controller 400 and the response terminals 110 and 120 is cut to reduce the influence on the external device due to the data communication. As a configuration example of the line filter, a known filter that can cut the frequency near the control signal output from the controller 400 can be used.

A first response terminal 110, a second response terminal 120, and a controller 400 are arranged inside the power line communication control area 500 configured as described above.
The first response terminal 110 is a device for controlling the power supplied to the first load 501, and includes a responder 111 and a first switch 112. The second response terminal 120 is a device for controlling the power supplied to the second load 502, and includes a responder 121 and a second switch 122. The controller 400 transmits / receives information to / from an external computer (PC) 12 via the communication line 11 and individually controls the operations of the first response terminal 110 and the second response terminal 120.

FIG. 6 shows a configuration example of an LED circuit that is dimming controlled.
FIG. 6A shows an example in which a variable resistor is used as the operation stabilization resistor R _{S in} series with a plurality of LEDs, and the LED can be dimmed by controlling the resistance value.

In FIG. 6B, the switch SW is connected in series to the series circuit of the operation stabilization resistor R _S and the plurality of LEDs, and the dimming is possible by controlling the number of LEDs to be lit by intermittently switching the switch SW. An example is shown.

(Fourth embodiment)
A fourth embodiment of the present invention will be described with reference to FIG.
The fourth embodiment corresponds to FIG. 1 shown in the first embodiment, and the PNP-type bipolar transistor Q1 used as the driving transistor in FIG. 1 is changed to a MOS transistor (field effect transistor). is doing. Further, a MOS transistor Q3 is connected in parallel with the discharging diode D3, and a MOS transistor Q4 is connected in parallel with the discharging diode D4. The gate electrodes of the MOS transistors Q3 and Q4 are connected in common with the gate electrode of the driving transistor Q2.

  With such a configuration, when discharging the charges accumulated in the capacitors C1, C2, and C3, as shown in FIG. 8, when moving the charges accumulated in the divided charging circuit to the output capacitor, A discharge path is formed through MOS transistors Q3 and Q4. Thereby, the voltage drop in the discharge diodes D3 and D4 can be eliminated, so that the voltage drop in the discharge circuit can be reduced. Therefore, a great effect can be obtained when the partial pressure ratio is increased.

(Fifth embodiment)
FIG. 9 is a block diagram showing an embodiment in which the voltage drop in the discharge circuit is further reduced as compared with the circuit of the fourth embodiment shown in FIGS.
As shown in FIG. 9, in this embodiment, a MOS transistor Q5 is connected in parallel with the discharging diode D5, and a MOS transistor Q6 is connected in parallel with the discharging diode D6. The gate electrode is connected to the connection point between the resistors R3 and R4 of the second resistance voltage dividing circuit, and the MOS transistor Q7 is connected. The drain electrode of the MOS transistor Q7 is connected to the positive terminal of the first rectifier circuit 101 via the resistor R6, and the source electrode is connected to the negative terminal of the first rectifier circuit 101.

  With the above-described configuration, in the present embodiment, the first resistance voltage dividing circuit including the resistors R1 and R2, the second resistance voltage dividing circuit including the PMOS transistor Q1, the resistors R3 and R4, and the resistor R6. The switching circuit 106 is configured by the NMOS transistor Q7.

  The gate electrode of the driving transistor Q2 is connected to the drain electrode of the MOS transistor Q7. In the first to third embodiments described above, an NMOS transistor is used as the driving transistor Q2. However, in this embodiment, a PMOS transistor is used, and its source electrode is the first rectifier circuit 101. The drain electrode is connected to the parallel circuit of the load circuit 104 and the output capacitor C4.

  In the fifth embodiment configured as described above, as shown in FIG. 10, when the output voltage VDD1 of the first rectifier circuit 101 decreases until it can be discharged, the switching circuit 106 causes the MOS transistors Q3 and Q4 to be discharged. , Q5, Q6, and Q2 are turned on. Thereby, when discharging the electric charges charged in the first to third capacitors C1 to C3 to the output capacitor C4, it is possible to eliminate a voltage drop in the discharging diodes D3 to D6.

  In the present embodiment, the NMOS transistor Q7 and the resistor R6 are added to the switching circuit 106 in order to drive the PMOS transistors Q2, Q5, and Q6.

As described above, according to the present invention, the configuration can be simplified because there is only one voltage dividing charging circuit for dividing and charging the rectified output obtained by full-wave rectifying the AC power supply voltage by the rectifying circuit.
Further, two types of voltages VDD1 and VDD2 are generated, and the transistor Q1 is turned on during the periods t1, t2, t3,... Where VDD2 is lower than VDD1 by a predetermined voltage. Thereby, when the transistor Q2 is turned on, the charges accumulated in the capacitors C1, C2, and C3 of the voltage dividing charging circuit 103 can be reliably transferred to the output capacitor C4.

100 AC power supply,
DESCRIPTION OF SYMBOLS 101 1st rectifier circuit 102 2nd rectifier circuit 103 Voltage division charging circuit 104 Load circuit 105 Drive circuit 106 Switching circuit C1, C2, C3 Three charging capacitors D1, D2 Capacitor separation diode C4 Output capacitor

Claims (3)

A voltage dividing rectifier circuit that divides and outputs a rectified output of an AC power supply voltage,
A first rectifier circuit for full-wave rectification of the AC power supply voltage;
N voltage-dividing charging capacitors connected in series to charge the rectified output output from the first rectifying circuit and N capacitors that are divided to separate the N voltage-dividing charging capacitors. A voltage dividing charging circuit comprising (N-1) capacitor separating diodes connected;
An output capacitor connected in parallel with the voltage dividing charging circuit;
A drive circuit connected in series with the output capacitor;
N discharge paths in which each of the N divided voltage charging capacitors and the output capacitor are connected via a discharge diode;
A second rectifier circuit for full-wave rectification of the AC power supply voltage;
Comparing the rectified output of the first rectifier circuit with the rectified output of the second rectifier circuit, the output of the second rectifier circuit is lower than the rectified output of the first rectifier circuit by a predetermined value or more. A switching circuit for turning on the drive circuit in the case of
When the drive circuit is turned on, the charge accumulated in each of the N voltage-dividing charging capacitors connected in series is moved to the output capacitor via the discharge circuit and the drive circuit. A voltage dividing rectifier circuit. A voltage dividing rectifier circuit that divides and outputs a rectified output of an AC power supply voltage,
A first rectifier circuit for full-wave rectification of the AC power supply voltage;
N voltage-dividing charging capacitors connected in series to charge the rectified output output from the first rectifying circuit and N capacitors that are divided to separate the N voltage-dividing charging capacitors. A voltage dividing charging circuit comprising (N-1) capacitor separating diodes connected;
An output capacitor connected in parallel with the voltage dividing charging circuit;
A drive circuit connected in series with the output capacitor;
N discharge paths in which each of the N divided voltage charging capacitors and the output capacitor are connected via a discharge diode;
A backflow prevention diode disposed between the first rectifier circuit and the divided voltage charging circuit to prevent the charge accumulated in the divided voltage charge circuit from flowing back to the first rectifier circuit;
A switching circuit that turns on the drive circuit when the voltage on the input side is lower than the voltage on the output side than the voltage on the output side of the backflow prevention diode,
When the drive circuit is turned on, the electric charge accumulated in each of the N voltage-dividing charging capacitors connected in series is moved to the output capacitor via the discharge circuit and the drive circuit. A voltage-dividing rectifier circuit characterized by that.   3. The voltage dividing rectifier circuit according to claim 1, wherein a SW element is connected in parallel with a part or all of the discharge diodes of the discharge path, and the SW element is turned on by the switching circuit during a discharge operation. .

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