JP2012147401A - Pll circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a PLL circuit that implements improved accuracy of an output frequency in a free run at a reference frequency break.SOLUTION: A PLL circuit comprises a proportional-integral PLL circuit having an A/D conversion section 15 and a pattern generation section 16 added after an integrator 14. The A/D conversion section 15 has the function of producing a digital signal of an output voltage of the integrator 14 in a lock state and holding the lock phase digital signal in an unlocked state. At a reference frequency break in an unlocked state, the pattern generation section 16 generates a pattern in response to the held digital signal, and a selector 13 outputs it to the integrator 14. Specifically, at a reference frequency break, a pattern-generated waveform is alternatively input into the integrator 14.

Description

  The present invention relates to a PLL (Phase Locked Loop) circuit, and more particularly to a PLL circuit that improves the accuracy of a free-run output frequency when a reference frequency is interrupted.

[Conventional technology]
Conventionally, in the PLL circuit, the output frequency of the free run when the reference frequency is interrupted is switched to give a fixed value, for example, a power supply voltage / 2, to the control voltage of the voltage controlled crystal oscillator.

[Related technologies]
As related prior arts, Japanese Patent Application Laid-Open No. 2009-212995, “Phase-locked oscillation circuit” (Oki Electric Industry Co., Ltd.) [Patent Document 1], Japanese Patent Application Laid-Open No. 2003-179489, “Self-running frequency of voltage controlled oscillator” There is a phase-locked loop circuit having an automatic adjustment function ”(Sony Corporation) [Patent Document 2].

  Patent Document 1 discloses a control voltage for performing phase correction based on transient data immediately before loss of synchronization held in the transient data holding / output unit even if loss of synchronization occurs due to an abnormality of the reference standard signal in the phase synchronous oscillation circuit. After that, the control voltage is generated based on the average value calculated by the average value calculation unit and is given to the VCO.

  In Patent Document 2, in the PLL circuit, the number of pulses of the pulse signal output by the VCO during the period when the comparison result of the phase comparator is at a predetermined level is counted, and the microcomputer updates the digital data based on the count value. It is shown that the DAC converts the analog signal into an analog signal and synthesizes it with the output from the LPF to automatically adjust the free-running frequency of the VCO.

JP 2009-212995 A Japanese Patent Laid-Open No. 2003-179489

  However, the conventional method for dealing with free run in the PLL circuit has a problem that it cannot cope with fluctuations in the reference frequency at the time of lock and variations in the output frequency with respect to the control voltage of the voltage controlled crystal oscillator.

  Specifically, when the reference frequency is cut off, the power supply voltage / 2 is set as the center voltage, but the power supply voltage / 2 is not always the center voltage, and the output frequency varies. It was.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a PLL circuit that improves the accuracy of the output frequency of a free run when the reference frequency is interrupted.

  The present invention for solving the problems of the above-described conventional example is a PLL circuit including a crystal oscillator with a voltage control function, and includes a first frequency divider that receives and divides a reference frequency signal, and a crystal oscillator. A second frequency divider that divides the output of the first frequency divider, a phase comparator that compares the phases of the output from the first frequency divider and the output from the second frequency divider, and outputs a phase difference signal A low-pass filter for low-passing the output from the phase comparator, a third frequency divider for inputting and dividing the reference frequency signal, and a fourth frequency-dividing for the output from the crystal oscillator A phase which inputs the output from the frequency divider, the third frequency divider and the output from the fourth frequency divider, detects a phase advance or delay, and outputs a signal corresponding to the phase advance or delay Input the output from the lead / lag detector, the fourth divider and the reference frequency signal, and detect the reference frequency signal disconnection. Reference frequency signal disconnection detection unit, input from third frequency divider and output from fourth frequency divider, lock detection unit for detecting lock or unlock, and phase advance / delay at lock A pattern generator that generates a pattern corresponding to the signal from the detector, and a signal corresponding to the phase advance or delay from the phase advance / delay detector and a pattern from the pattern generator are input to detect a reference frequency signal loss. Selects a pattern when a signal for detecting a reference frequency signal disconnection from the unit is input, and selects a signal corresponding to a phase advance or delay when a signal for detecting a reference frequency signal disconnection is not input An integrator that integrates the signal from the selector, an adder that adds the output from the integrator to the output from the low-pass filter, and a signal that detects the reference frequency signal disconnection from the reference frequency signal disconnection detector When no signal is input and a lock detection signal is input from the lock detector, the output from the integrator is analog / digital converted and stored and output to the pattern generator to detect the reference frequency signal loss When the signal for detecting the disconnection of the reference frequency signal from the unit is input or the signal for detecting the unlock from the lock detection unit is input, the digital signal stored at the time of locking is output to the pattern generation unit A / D converter.

  In the PLL circuit according to the present invention, the phase lead / lag detection unit starts from the rise of the signal output from the third frequency divider, and the phase position of the rise of the signal from the fourth frequency divider is The logic circuit outputs a logic low (L) level if it is advanced, and outputs a logic high (H) level if it is delayed.

  According to the present invention, in the PLL circuit, the A / D conversion unit samples the output from the integrator with the output from the fourth frequency divider, and the signal for detecting the reference frequency signal disconnection is not input. When the signal for detecting the lock is input, the sampled data is temporarily stored and the sampled data is output to the pattern generation unit, and the signal for detecting the reference frequency signal disconnection is input, or When the signal for detecting unlocking is input, the stored sampled data is output to the pattern generation unit.

  According to the present invention, in the PLL circuit, the pattern generation unit counts the output from the A / D conversion unit using the output from the fourth frequency divider as a clock, and outputs from the phase advance / delay detection unit at the time of locking. An analog pattern of a signal corresponding to is generated and output to the selector.

  The present invention is characterized in that in the PLL circuit, the output of the third frequency divider and the output of the fourth frequency divider are set so as to perform frequency division until they have the same frequency.

  According to the present invention, in a PLL circuit including a crystal oscillator with a voltage control function, the first divider inputs and divides the reference frequency signal, and the second divider divides the output from the crystal oscillator. The phase comparator compares the phase of the output from the first frequency divider and the output from the second frequency divider, outputs a phase difference signal, and the low-pass filter is output from the phase comparator. The third frequency divider receives the reference frequency signal and divides it, the fourth frequency divider divides the output from the crystal oscillator, and the phase lead / lag detector Input the output from the third frequency divider and the output from the fourth frequency divider, detect the phase advance or delay, output a signal corresponding to the phase advance or delay, and disconnect the reference frequency signal The detection unit inputs the output from the fourth frequency divider and the reference frequency signal, detects the reference frequency signal disconnection, and the lock detection unit The output from the frequency divider and the output from the fourth frequency divider are input, lock or unlock is detected, and the pattern generation unit sets a pattern corresponding to the signal from the phase advance / delay detector at the time of lock. A signal for detecting a reference frequency signal disconnection from the reference frequency signal disconnection detection unit by inputting a signal corresponding to the phase advance or delay from the phase advance / delay detector and a pattern from the pattern generation unit. If it is input, select the pattern. If the signal for detecting the reference frequency signal disconnection is not input, select the signal corresponding to the phase advance or delay, and the integrator integrates the signal from the selector and adds it. The detector adds the output from the integrator to the output from the low-pass filter, and the A / D converter does not receive the signal for detecting the reference frequency signal disconnection from the reference frequency signal disconnection detection unit, and lock detection From the department When a signal for detecting a signal is input, the output from the integrator is analog / digital converted and stored, and also output to the pattern generation unit to detect the reference frequency signal disconnection from the reference frequency signal disconnection detection unit Or when a signal for detecting unlocking from the lock detection unit is input, the digital signal stored at the time of locking is output to the pattern generation unit. When the reference frequency is interrupted, the pattern generation unit By substituting the pattern from, into the integrator, the frequency accuracy during free-running can be improved.

1 is a configuration block diagram of a PLL circuit according to an embodiment of the present invention. It is a circuit diagram of an A / D converter. It is a timing chart of each signal of an A / D conversion part. 3 is a circuit diagram of a pattern generation unit 16. FIG. 4 is a timing chart showing a pattern signal of a pattern generation unit 16. It is a circuit diagram of another pattern generation unit. 3 is a timing chart showing the operation of a counter 308. 4 is a timing chart of output patterns of a selector 312.

Embodiments of the present invention will be described with reference to the drawings.
[Outline of the embodiment]
The PLL circuit according to the embodiment of the present invention uses a proportional-integral-type PLL circuit, and includes an A / D converter and a pattern generator after the integrator, and the output voltage of the integrator at the time of lock is A A digital signal is obtained by the / D conversion unit, and when it is unlocked, it has a function to hold the digital signal when it is unlocked. When the reference frequency is interrupted when unlocked, the pattern generator generates a pattern according to the held digital signal. When the reference frequency is cut off, the pattern generation waveform can be input to the integrator as an alternative to improve the frequency accuracy during free-running.

[Configuration of PLL circuit: FIG. 1]
A PLL circuit according to an embodiment of the present invention will be described with reference to FIG. FIG. 1 is a block diagram showing the configuration of a PLL circuit according to an embodiment of the present invention.
As shown in FIG. 1, a PLL circuit (this circuit) according to an embodiment of the present invention includes an input terminal 1 for inputting a reference frequency signal, a first frequency divider 2, and a phase comparator (PC) 3. A second frequency divider 4, a low-pass filter (LPF) 5, an adder 6, an operational amplifier 7, a voltage controlled crystal oscillator (VCXO) 8, and a subordinate An output terminal 9 for outputting a frequency, a third frequency divider 10, a fourth frequency divider 11, a phase advance / lag detector 12, a selector (SEL) 13, an integrator 14, an A / It has a D conversion unit (SA / D) 15, a pattern generation unit 16, a reference frequency (REF) disconnection detection unit 17, and a lock detection unit 18.

[PLL circuit connections and connections]
The input terminal 1 inputs a reference frequency signal and outputs it to the first frequency divider 2 and the third frequency divider 10.
The first frequency divider 2 divides the reference frequency signal from the input terminal 1 and outputs it to the PC 3.
The second frequency divider 4 branches and inputs the output from the VCXO 8, divides the output from the VCXO 8 and outputs it to the PC 3.
Here, the output frequencies of the first frequency divider 2 and the second frequency divider 4 do not have to be the same if there is a greatest common divisor, and are higher than the frequency obtained by the greatest common divisor. is there.

A phase comparator (PC) 3 receives a frequency-divided signal from the first frequency divider 2 and a frequency-divided signal from the second frequency divider 4, compares the phases of both, and indicates a phase difference. Is output to LPF5.
The low-pass filter (LPF) 5 receives an output from the PC 3 and passes a low-frequency band frequency signal, and is proportional to the phase difference between the first frequency divider 2 and the second frequency divider 4. Voltage to be generated and output to the adder 6.

The adder 6 adds the output from the LPF 5 and the output from the integrator 14 and outputs the result to the operational amplifier 7.
The operational amplifier 7 amplifies the output from the adder 6 and outputs the control voltage of the VCXO 8.
The VCXO 8 is a crystal oscillator with a voltage control function including a crystal resonator, and operates so as to maintain a lock as a PLL by a control voltage from the operational amplifier 7.
The output terminal 9 is an output terminal that outputs an oscillation output (dependent frequency) from the VCXO 8.

The third frequency divider 10 divides the reference frequency signal from the input terminal 1 and outputs it to the phase advance / lag detector 12.
The fourth frequency divider 11 divides and inputs the output from the VCXO 8 and divides the output from the VCXO 8 to divide the phase advance / delay detection unit 12, pattern generation unit 16, REF break detection unit 17 and lock detection. To the unit 18.
The output of the third frequency divider 10 and the output of the fourth frequency divider 11 are set so as to perform frequency division until they have the same frequency.

  The phase advance / delay detection unit 12 starts from the rising edge of the signal output from the third frequency divider 10, and if the phase position of the rising edge of the signal from the fourth frequency divider 11 has advanced, the logic low level. (L) is a logic circuit that outputs a level and outputs a logic high (H) level if delayed.

The selector 13 receives the signal from the phase advance / lag detector 12 and the signal from the pattern generation unit 16, selects one of the signals based on the REF disconnection detection signal from the REF disconnection detection unit 17, and supplies it to the integrator 14. Output.
Specifically, when the REF break detection signal from the REF break detection unit 17 is not input, the selector 13 selects the signal from the phase advance / lag detector 12 and detects the REF break detection from the REF break detection unit 17. When a signal is input, the signal from the pattern generation unit 16 is selected.
Therefore, even if this circuit is in an unlocked (unlocked) state, the selector 13 selects the signal from the phase advance / lag detector 12.

The integrator 14 integrates the output from the selector 13 and outputs a constant voltage to the adder 6 and the A / D converter 15.
The A / D conversion unit (S-A / D) 15 performs A / D (analog / digital) conversion on the output voltage of the integrator 14 when locked, and outputs a digital signal to the pattern generation unit 16.

Specifically, when the lock detection signal is input from the lock detector 18, the A / D conversion unit 15 uses the output S 2 from the fourth frequency divider 11 as a sampling clock from the integrator 14. The output voltage is digitally converted and output to the pattern generation unit 16.
In addition, the A / D conversion unit 15 holds when locked when the REF disconnection detection signal from the REF disconnection detection unit 17 is input or when the unlock detection signal is input from the lock detector 18. The digital data is output to the pattern generation unit 16.

The pattern generator 16 generates a pattern based on the digital data output from the A / D converter 15 using the output from the fourth frequency divider 11 as a clock.
The generated pattern is a signal corresponding to the output from the phase lead / lag detector 12 at the time of locking, and is substituted for the signal from the phase lead / lag detector 12 when REF is cut off.

  The reference frequency (REF) disconnection detection unit 17 inputs the reference frequency from the input terminal 1, inputs the output from the fourth frequency divider 11, and receives the output from the fourth frequency divider 11. In a state where no reference frequency is input from the input terminal 1, a reference frequency disconnection is detected, and a REF disconnection detection signal is output to the selector 13 and the A / D converter 15.

The lock detection unit 18 inputs the output from the third frequency divider 10 and the output from the fourth frequency divider 11, determines whether or not the lock state is in place, and detects a lock detection signal or an unlock detection signal. Is output to the A / D converter 15.
Specifically, the lock detection signal is at an H level when locked and at an L level when unlocked.

[Processing operation of this circuit]
The processing operation of this circuit will be described.
When the reference frequency of the reference frequency input terminal 1 is cut off, an A / D conversion unit (S-AD) 15 and a pattern generation unit 16 are added to the basic PLL circuit configuration after the integrator 14 and operated. It is.

  Specifically, the output voltage (analog voltage) of the integrator 14 at the time of locking is converted into a digital signal by the A / D converter 15, and the digital value of the digital signal is output to the pattern generator 16. The pattern generation unit 16 generates a pattern according to the digital value. This pattern corresponds to the output from the phase advance / lag detector 12 at the time of locking, and is a pattern for obtaining the analog voltage when the integrator 14 is integrated.

When the reference frequency is disconnected, the reference frequency (REF) disconnection detection unit 17 detects the REF disconnection, switches the selector 13 and inputs the pattern output of the pattern generation unit 16 to the integrator 14.
In other words, during free run, the voltage value is close to the voltage value of the integrator 14 at the time of lock, so that the frequency within the error of about 10 to 15 ppm from the time of lock can be obtained.

[A / D converter (S-AD) 15: FIG. 2]
Next, the A / D converter 15 will be described with reference to FIG. FIG. 2 is a circuit diagram of the A / D converter. This configuration shows an embodiment that does not depend on an expensive A / D converter.
The output of the integrator 14 is input to the comparator input terminal 101, and the output S109 of a simple integrator composed of a diode 107, a resistor 108, and a capacitor 109 is input to the comparator (CMP) 102.

The output S102 of the comparator 102 outputs a logic H level when the output S109 of the simple integrator becomes higher than the voltage of the comparator input terminal 101, and outputs a logic L level when it becomes lower.
The sampling clock terminal 110 to which the sampling clock is input is connected to the input of the inverter 111, and the inverted clock is input to the clock terminals of the flip-flops 103 and 104 as the output S111.

  The flip-flop 103, the flip-flop 104, the inverter gate 105, and the AND gate 106 detect the change point of the H level from the L level of the output S102 from the CMP 102, and the output S111 from the inverter gate 111 has the H level for one clock. An output S106 (output from the AND gate 106) is obtained.

  This output S106 is input to the CLR (frequency division clear) terminal of the frequency divider (1 / n) 112, the CLR (count clear) terminal of the counter (CNT) 114, and the AND gate 121 and serves as a reset signal. It is.

  The output S112 of the frequency divider 112 is input to the resistor 108 of the simple integrator by the output S111 from the inverter gate 111, the electric charge is accumulated in the capacitor 109, and integration is started. The integration is performed until the comparator 102 becomes higher than a specific voltage. When the voltage becomes higher than a specific voltage, the integration is terminated by the H level of one clock from the output S106, the frequency divider 112 is cleared, and the output S112 of the frequency divider 112 becomes the L level. The electric charge of the capacitor 109 is released by 107 and the initial state is restored.

  By changing the output S112 of the frequency divider 112 from the L level to the H level, the 4-bit counter 114 counts until the output S106 becomes the H level. / D conversion result.

  The CLR (count clear) terminal, EN (count enable) terminal, and CI (carry-in) terminal of the counter 114 are clock synchronous. When the EN terminal is at the L level, the count value when the EN terminal is at the H level is held. Further, it is assumed that the count clear operation at the CLR terminal has the highest priority regardless of the logic state of the EN terminal.

When the count value in the counter 114 becomes the maximum, the CY (carry) terminal becomes H level, the inverted L level is input to the CI terminal by the inverter gate 113, and the count is stopped.
The output S114 of the counter 114 is passed through the flip-flop 115 to obtain A / D conversion data at the data output terminal 116. It is assumed that the EN terminal of the flip-flop 115 holds the value at the H level at the L level.

The reference disconnection state input terminal 117 is connected to the input of the inverter gate 119, and the inverted output of the inverter gate 119 is input to one input terminal of the AND gate 120. The lock state input terminal 118 is connected to the other input terminal of the AND gate 120.
Then, the logical product output of the AND gate 120 and the output S106 of the AND gate 106 are input to the AND gate 121, and the logical product output S121 is input to the EN terminal of the flip-flop 115.

  That is, when the logic of the reference disconnection state input terminal 117 is H level (when the reference frequency is disconnected), or when the logic of the lock state input terminal 118 is L level (when unlocked), the output S120 of the AND gate 120 is L. The output S121 of the AND gate 121 is also at the L level, the EN terminal of the flip-flop 115 is at the L level, and the digital data at the data output terminal 116 continues to output the data at the time of locking.

  When the logic of the reference disconnection state input terminal 117 is L level (when the reference frequency is input) and the logic of the lock state input terminal 118 is H level (when locked), the output S120 of the AND gate 120 is At the H level, the output S121 of the AND gate 121 outputs the output S106. Every time the H level of the output S106 is input to the EN terminal of the flip-flop 115, the digital data at the H level is stored (held), and the digital data held at the H level (the data at the time of lock) is stored at the L level. The data is output from the data output terminal 116.

[Timing chart of A / D converter: FIG. 3]
Next, FIG. 3 shows states of various signals in the A / D conversion unit shown in FIG. FIG. 3 is a timing chart of each signal of the A / D conversion unit.
When the output S120 from the AND gate 120 is at the H level, that is, when the reference frequency is input and in the locked state, the output S1 (output S101) from the integrator 14 is accumulated in the simple integrator (output S109). ).

  When the EN terminal of the counter 114 is at the H level, the counter 114 outputs the value obtained by counting the sampling clock inverted output to the flip-flop 115. When the EN terminal is at the L level, the counter 114 has the EN terminal at the H level. Is output to the flip-flop 115 (output S114). When the output S106 of the AND gate 106 becomes H level, the flip-flop 115 outputs the count value that has been input and held (b3_0).

  When the output S120 from the AND gate 120 is at L level, that is, when the reference frequency is disconnected or unlocked, the EN terminal of the flip-flop 115 is at L level and the EN terminal is at H level. In this case, the count value that was held at that time (the count value at the time of lock) is output.

[Pattern generator 16: FIG. 4]
Next, the circuit configuration of the pattern generation unit 16 will be described with reference to FIG. FIG. 4 is a circuit diagram of the pattern generation unit 16.
As shown in FIG. 4, the pattern generation unit 16 inputs the lower 3 bits of the 4 bits of the output b3_0 from the output terminal 116 of the A / D conversion unit 15 to the exclusive ORs 203 to 205, respectively. The most significant bit is inverted by the inverter gate 202 and input to the other of the exclusive ORs 203 to 205.

The counter (CNT) 207 is a 4-bit counter, and the initial value of load data (D, C, B, A from the upper side) at the start of counting is 0H to 7H in C_A with the upper D terminal fixed at the L level. input.
As for the load data, the output of the inverter gate 206 becomes the L level every time the CY terminal is at the H level, that is, the count value becomes the maximum, and the load data (D_A) is taken in synchronization with the clock S2 of the sampling clock input terminal 210. Return the count value to the initial value.

If b3 is at L level, the load data operates as an inverter until an inverted H level is input to each of the exclusive ORs 203 to 205 by the inverter gate 202. Furthermore, the exclusive OR 208 also operates as an inverter.
Further, when b3 is at the H level, the L level is input to each of the exclusive ORs 203 to 205, so that it simply operates as a buffer. Furthermore, the exclusive OR 208 also operates as a buffer.

[Pattern signal of pattern generator 16: FIG. 5]
FIG. 5 is a timing chart showing the pattern signal of the pattern generator 16.
As a result, as shown in FIG. 5, a pattern can be generated corresponding to the data of b3_0. In the pattern of FIG. 5, the pattern is the same just by reversing the pattern at b3_0 = 0111 and b3_0 = 1000. However, since the frequency error at the time of free run is set to 10 to 15 ppm, there is no problem. In order to dislike this and make all the patterns different, it can be avoided by providing an addition circuit for adding “0001” to b2_0 of the load data when b3 is at the H level. However, bit processing is required when all the bits of b3_0 at the time of carry become L level.

[Other pattern generation units: FIGS. 6 and 7]
Next, the configuration of another pattern generation unit will be described with reference to FIG. FIG. 6 is a circuit diagram of another pattern generation unit, and FIG. 7 is a timing chart showing the operation of the counter 308.
In the counter (CNT) 308, the A terminal is fixed at the L level, and the data of b3_0 is input to the D_B terminal by the inverter gate 303 and the exclusive ORs 304 to 306.
The output S308 of the CY terminal of the counter 308 is input to one of the AND gates 310 through the inverter gate 309, and the output S308 is input to one of the OR gates 311. The other of the gates 310 and 311 has a sampling clock. S2 is input.

  The output of the AND gate 310 and the output of the OR gate 311 are input to the selector (SEL) 312, and b3 is L level and the output S310 of the AND gate 310 is selected, and b3 is H level and the output S311 of the OR gate 311 is selected. And output.

When the input D_A of the counter 308 is 0000, the output S308 of the CY (carry) terminal becomes H level once in 16 sampling clocks S302.
Further, when D_A = 0010, the output S308 becomes H level once in 14 sampling clocks S2.
Similarly, the output S308 becomes H level once for D_A = 0100, once every 12 times for D_A = 0110, once every 10 times for D_A = 1110, and once for every two times.

In FIG. 6, when b3 = L level, the output S310 of the AND gate 310 is a logical product of the clock of the sampling clock input terminal 302 and the inverted output S309 of the CY terminal output S308, and the inverted output S309. The L level is periodically set by the logic of b2, b1, and b0.
When b3 = H level, a different pattern can be generated corresponding to b3_0 by periodically setting H level to the CY terminal output S308 by the output S311 of the OR gate 311.

[Pattern generation: Fig. 8]
When the selector 312 is at b3 = L level, the output S310 is selected. When b3 = H level, the output S311 is selected to obtain the pattern S5 at the output terminal 313. FIG. 8 shows pattern generation based on the logic of b3_b0. FIG. 8 is a timing chart of the output pattern of the selector 312.

[Effect of the embodiment]
According to this circuit, the A / D conversion unit 15 and the pattern generation unit 16 are added after the integrator 14 using a proportional-integration type PLL circuit, and the A / D conversion unit 15 is configured to perform integration at the time of locking. The output voltage of the device 14 is obtained as a digital signal, and has a function of holding the digital signal at the time of unlocking when the lock is released. This is generated and output to the integrator 14. When the reference frequency is interrupted, the pattern generation waveform is alternatively input to the integrator 14, so that the frequency accuracy during free run can be improved.

  The present invention is suitable for a PLL circuit that improves the accuracy of the free-run output frequency when the reference frequency is interrupted.

  DESCRIPTION OF SYMBOLS 1 ... Input terminal, 2 ... 1st frequency divider, 3 ... Phase comparator (PC), 4 ... 2nd frequency divider, 5 ... Low-pass filter (LPF) ), 6 ... adder, 7 ... operational amplifier, 8 ... voltage controlled crystal oscillator (VCXO), 9 ... output terminal, 10 ... third frequency divider, 11 ... first 4 divider, 12 ... phase advance / lag detector, 13 ... selector (SEL), 14 ... integrator, 15 ... A / D converter (SA / D), 16 ... Pattern generation unit, 17 ... Reference frequency (REF) break detection unit, 18 ... Lock detection unit

Claims (5)

A PLL circuit including a crystal oscillator with a voltage control function,
A first frequency divider for inputting and dividing a reference frequency signal;
A second divider for dividing the output from the crystal oscillator;
A phase comparator that compares the phase of the output from the first frequency divider and the output from the second frequency divider and outputs a phase difference signal;
A low-pass filter for low-passing the output from the phase comparator;
A third frequency divider for inputting and dividing a reference frequency signal;
A fourth divider for dividing the output from the crystal oscillator;
An output from the third frequency divider and an output from the fourth frequency divider are input, a phase advance / delay is detected, and a signal corresponding to the phase advance or delay is output. A delay detector;
A reference frequency signal disconnection detection unit that receives an output from the fourth frequency divider and a reference frequency signal and detects a reference frequency signal disconnection;
A lock detection unit that inputs an output from the third frequency divider and an output from the fourth frequency divider, and detects lock or unlock;
A pattern generator for generating a pattern corresponding to a signal from the phase advance / delay detector at the time of locking;
A signal corresponding to a phase advance or delay from the phase advance / delay detector and a pattern from the pattern generation unit are input, and a signal for detecting a reference frequency signal disconnection from the reference frequency signal disconnection detection unit is input. A selector that selects the pattern, and when a signal for detecting the reference frequency signal disconnection is not input, a signal that selects a signal corresponding to the advance or delay of the phase;
An integrator for integrating the signal from the selector;
An adder for adding the output from the integrator to the output from the low-pass filter;
When the signal for detecting the reference frequency signal disconnection from the reference frequency signal disconnection detection unit is not input and the signal for detecting the lock from the lock detection unit is input, the output from the integrator is analog. / Digitally converted and stored and output to the pattern generation unit, a signal for detecting a reference frequency signal disconnection from the reference frequency signal disconnection detection unit is input, or an unlock from the lock detection unit is detected A PLL circuit comprising: an A / D converter that outputs a digital signal stored at the time of locking to the pattern generation unit when a signal is input.   The phase advance / delay detection unit starts from the rising edge of the signal output from the third divider, and if the phase position of the rising edge of the signal from the fourth divider is advanced, the logic low (L) 2. The PLL circuit according to claim 1, wherein the PLL circuit outputs a level and outputs a logic high (H) level if delayed. The A / D converter samples the output from the integrator with the output from the fourth frequency divider, and the signal for detecting the lock is inputted without the signal for detecting the reference frequency signal interruption being inputted. The sampled data is temporarily stored, and the sampled data is output to the pattern generator,
The stored sampled data is output to the pattern generation unit when a signal for detecting the reference frequency signal disconnection is input or when a signal for detecting unlock is input. Item 3. The PLL circuit according to Item 1 or 2.   The pattern generation unit counts the output from the A / D conversion unit using the output from the fourth frequency divider as a clock, and outputs an analog pattern of a signal corresponding to the output from the phase advance / delay detection unit when locked. 4. The PLL circuit according to claim 1, wherein the PLL circuit is generated and output to a selector.   5. The PLL circuit according to claim 1, wherein the output of the third frequency divider and the output of the fourth frequency divider are set so as to perform frequency division until they have the same frequency. .

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