JP2012084853A - 半導体装置の作製方法 - Google Patents
半導体装置の作製方法 Download PDFInfo
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- JP2012084853A JP2012084853A JP2011195553A JP2011195553A JP2012084853A JP 2012084853 A JP2012084853 A JP 2012084853A JP 2011195553 A JP2011195553 A JP 2011195553A JP 2011195553 A JP2011195553 A JP 2011195553A JP 2012084853 A JP2012084853 A JP 2012084853A
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- film
- transistor
- insulating film
- oxide semiconductor
- oxide
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- 229910052720 vanadium Inorganic materials 0.000 description 1
- 229910052724 xenon Inorganic materials 0.000 description 1
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 description 1
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Abstract
【解決手段】絶縁膜上にマスクを形成し、該マスクを微細化する。微細化されたマスクを用いて凸部を有する絶縁層を形成し、これを用いて、微細なチャネル長(L)を有するトランジスタを形成する。また、トランジスタを作製する際に、微細化された凸部の上面と重なるゲート絶縁膜の表面に平坦化処理を行う。これにより、トランジスタの高速化を達成しつつ、信頼性を向上させることが可能となる。また、絶縁膜を凸部を有する形状とすることで、自己整合的にソース電極及びドレイン電極を形成することができ、製造工程の簡略化、また生産性を向上させることが可能となる。
【選択図】図1
Description
本実施の形態では、半導体装置の作製方法の一例について、図1乃至図4を参照して説明する。
本実施の形態では、実施の形態1と異なる半導体装置の作製方法の一例について、図5乃至図7を参照して説明する。本実施の形態と実施の形態1の主な相違点は、酸化物半導体膜140、ソース電極またはドレイン電極130a及びソース電極またはドレイン電極130bの積層順及び構造にあるので、本実施の形態では主にこの点について説明する。
本実施の形態では、半導体装置の一形態に相当する液晶表示パネルの外観及び断面について、図8を用いて説明する。図8に示す液晶表示パネルは、実施の形態1または実施の形態2で示したトランジスタを含む。図8(A)及び図8(C)は、トランジスタ4010、4011、及び液晶素子4013を、第1の基板4001と第2の基板4006との間にシール材4005によって封止した、パネルの平面図であり、図8(B)は、図8(A)または図8(C)のM−Nにおける断面図に相当する。
本実施の形態では、半導体装置の一形態として電子ペーパーの例を示す。
本実施の形態では、半導体装置の一例として、記憶媒体(メモリ素子)を示す。本実施の形態では、実施の形態1で示す酸化物半導体を用いたトランジスタと、酸化物半導体以外の材料を用いたトランジスタとを同一基板上に形成する。
本明細書に開示する半導体装置は、さまざまな電子機器(遊技機も含む)に適用することができる。電子機器としては、例えば、テレビジョン装置(テレビ、またはテレビジョン受信機ともいう)、コンピュータ用などのモニタ、デジタルカメラ、デジタルビデオカメラ、デジタルフォトフレーム、携帯電話機(携帯電話、携帯電話装置ともいう)、携帯型ゲーム機、携帯情報端末、音響再生装置、パチンコ機などの大型ゲーム機などが挙げられる。
上記実施の形態1乃至6において、トランジスタの半導体層に用いることのできる酸化物半導体膜の一形態を、図12を用いて説明する。
101 絶縁膜
106 素子分離絶縁層
108 ゲート絶縁層
109 ゲート電極
110 導電膜
111 ゲート電極
112 導電膜
116 チャネル形成領域
118 不純物領域
120 ゲート絶縁膜
124 金属化合物領域
126 電極
128 絶縁層
129 導電膜
130 導電膜
130a ソース電極またはドレイン電極
130b ソース電極またはドレイン電極
140 酸化物半導体膜
150 絶縁層
154 配線
156 絶縁層
157 絶縁層
158 導電層
160 トランジスタ
164 容量素子
200 マスク
210 マスク
300 領域
301 基板
400 トランジスタ
401 トランジスタ
402 トランジスタ
403 トランジスタ
404 トランジスタ
410 トランジスタ
411 トランジスタ
412 トランジスタ
413 トランジスタ
414 トランジスタ
420 絶縁層
437 絶縁層
450a 結晶性酸化物半導体膜
450b 結晶性酸化物半導体膜
453 酸化物半導体膜
500 基板
580 基板
581 トランジスタ
583 絶縁層
585 絶縁層
587 第1の電極層
588 第2の電極層
589 球形粒子
590a 黒色領域
590b 白色領域
595 充填材
596 基板
2700 電子書籍
2701 筐体
2703 筐体
2705 表示部
2707 表示部
2711 軸部
2721 電源
2723 操作キー
2725 スピーカー
2800 筐体
2801 筐体
2802 表示パネル
2803 スピーカー
2804 マイクロフォン
2805 操作キー
2806 ポインティングデバイス
2807 カメラ用レンズ
2808 外部接続端子
2810 太陽電池セル
2811 外部メモリスロット
3001 本体
3002 筐体
3003 表示部
3004 キーボード
3021 本体
3022 スタイラス
3023 表示部
3024 操作ボタン
3025 外部インターフェイス
3051 本体
3053 接眼部
3054 操作スイッチ
3055 表示部(B)
3056 バッテリー
3057 表示部(A)
4001 第1の基板
4002 画素部
4003 信号線駆動回路
4004 走査線駆動回路
4005 シール材
4006 第2の基板
4008 液晶層
4010 トランジスタ
4011 トランジスタ
4013 液晶素子
4015 接続端子電極
4016 端子電極
4018 FPC
4019 異方性導電膜
4021 絶縁層
4030 画素電極層
4031 対向電極層
4032 絶縁層
4033 絶縁層
4035 スペーサ
4040 導電層
4041 絶縁層
4042 保護絶縁層
Claims (5)
- 第1の絶縁膜上に導電膜を形成し、
前記導電膜上に第1のマスクを形成し、
前記第1のマスクにプラズマ処理によるスリミングを行って第2のマスクを形成し、
前記第2のマスクを用いて前記第1の絶縁膜及び前記導電膜をエッチング処理することで、凸部を有する第2の絶縁膜、及び前記第2の絶縁膜の凸部上面にゲート電極を形成し、
前記第2の絶縁膜及び前記ゲート電極上に、前記ゲート電極を覆うようにゲート絶縁膜を形成し、
前記第2の絶縁膜の凸部上面と重なる前記ゲート絶縁膜の表面に平坦化処理を行った後、
前記ゲート絶縁膜上に酸化物半導体膜を形成し、
前記第2の絶縁膜の凸部上面と重ならないように、前記酸化物半導体膜上にソース電極及びドレイン電極を形成する、半導体装置の作製方法。 - 第1の絶縁膜上に導電膜を形成し、
前記導電膜上に第1のマスクを形成し、
前記第1のマスクにプラズマ処理によるスリミングを行って第2のマスクを形成し、
前記第2のマスクを用いて前記第1の絶縁膜及び前記導電膜をエッチング処理することで、凸部を有する第2の絶縁膜、及び前記第2の絶縁膜の凸部上面にゲート電極を形成し、
前記第2の絶縁膜及び前記ゲート電極上に、前記ゲート電極を覆うようにゲート絶縁膜を形成し、
前記第2の絶縁膜の凸部上面と重ならないように、前記ゲート絶縁膜上にソース電極及びドレイン電極を形成し、
前記第2の絶縁膜の凸部上面と重なる前記ゲート絶縁膜の表面に平坦化処理を行い、
前記ソース電極またはドレイン電極及び前記ソース電極またはドレイン電極を覆うように、前記ゲート絶縁膜上に酸化物半導体膜を形成する、半導体装置の作製方法。 - 前記プラズマ処理は、アッシング処理を用いる、請求項1または請求項2に記載の半導体装置の作製方法。
- 前記平坦化処理は、化学的機械研磨処理とプラズマ処理の少なくとも一方を用いる、請求項1乃至請求項3のいずれか一に記載の半導体装置の作製方法。
- 前記ソース電極またはドレイン電極及び前記ソース電極またはドレイン電極の形成方法は、エッチング処理と前記化学的機械研磨処理の少なくとも一方を用いる、請求項1乃至4のいずれか一に記載の半導体装置の作製方法。
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KR20210146877A (ko) * | 2014-12-09 | 2021-12-06 | 엘지디스플레이 주식회사 | 산화물 반도체층의 결정화 방법, 이를 적용한 반도체 장치 및 이의 제조 방법 |
KR102334986B1 (ko) * | 2014-12-09 | 2021-12-06 | 엘지디스플레이 주식회사 | 산화물 반도체층의 결정화 방법, 이를 적용한 반도체 장치 및 이의 제조 방법 |
KR102450341B1 (ko) * | 2014-12-09 | 2022-10-04 | 엘지디스플레이 주식회사 | 산화물 반도체층의 결정화 방법, 이를 적용한 반도체 장치 및 이의 제조 방법 |
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US8592879B2 (en) | 2013-11-26 |
US20140051209A1 (en) | 2014-02-20 |
US8969144B2 (en) | 2015-03-03 |
US20120061670A1 (en) | 2012-03-15 |
KR20120028271A (ko) | 2012-03-22 |
JP5844583B2 (ja) | 2016-01-20 |
KR101890564B1 (ko) | 2018-08-23 |
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