JP2012080488A - Gate drive circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a gate drive circuit capable of reducing a response time to the convergence of a gate voltage to a clamp value, without causing the increase of a circuit area and manufacturing cost.SOLUTION: When abnormality of an overcurrent flow occurs in a transistor Q11, an abnormality detection signal Sa becomes an H level, so that a switch S11 is switched on. In this state, when a potential difference between signal lines L13 and L12 rises to almost exceed a clamp value, a Zener diode D11 breaks down, and the most breakdown current thereof becomes the base current of an amplification transistor T12. A current amplified from the breakdown current by the amplification action of the amplification transistor T12 is supplied to the base of a clamping transistor T11. The clamping transistor T11 produces a collector current flowing between signal lines L11 and L12 in accordance with the supplied base current. By this, a potential difference between the signal lines L11, L12 is decreased.

Description

  The present invention relates to a gate drive circuit for driving a gate of an insulated gate bipolar transistor by supplying a gate signal through a pair of signal lines.

  For example, a gate drive circuit that drives the gate of an IGBT (insulated gate bipolar transistor) used as a switching element of a motor drive circuit is provided with a protection circuit for protecting the element from an overcurrent caused by a short circuit or the like. As such a protection circuit, for example, when an abnormal state in which an overcurrent flows in the IGBT is detected, a voltage between the gate and the emitter of the IGBT (gate voltage) is clamped to a predetermined clamp value to reduce the current flowing through the IGBT. There is something. Patent Documents 1 and 2 disclose a clamp circuit that clamps a voltage between a pair of signal lines to a predetermined clamp value.

  FIG. 10 shows a configuration example of a clamp circuit used in such a protection circuit. 10 includes a transistor 4 which is an N-channel MOSFET connected between signal lines 2 and 3, and a Zener diode 5 which is connected between the signal line 2 and the gate of the transistor 4 with the illustrated polarity. And a resistor 6 connected between the gate of the transistor 4 and the signal line 3.

  With such a configuration, when the voltage between the signal lines 2 and 3 tries to increase beyond the Zener voltage of the Zener diode 5, the Zener diode 5 breaks down and the transistor 4 is turned on. A current corresponding to the ON state of the transistor 4 flows between the signal lines 2 and 3, whereby the voltage between the signal lines 2 and 3 is clamped to a predetermined clamp value. In this case, the clamp value is a value obtained by adding the threshold voltage Vt of the transistor 4 to the Zener voltage.

JP 2002-084174 A JP 2005-223399 A

  In the conventional clamp circuit 1 described above, the time (response time) until the voltage between the signal lines 2 and 3 converges to the clamp value during the clamp operation is determined according to the element characteristics of the Zener diode 5 and the transistor 4. Further, the response time is preferably as short as possible for the purpose of reducing the loss in the IGBT due to the overcurrent flowing due to the short circuit. In order to shorten the response time, the driving current supplied to the transistor 4 at the time of clamping, that is, the charging current for charging the gate-source capacitance is increased, or the on-resistance of the transistor 4 is reduced to reduce the current capability. Need to be increased. In order to increase the charging current at the time of clamping, the breakdown current (zener current) of the Zener diode 5 may be increased. However, since the Zener current of the Zener diode is generally relatively low, the charging current cannot be increased so much. On the other hand, when the on-resistance of the transistor 4 is to be reduced, there arises a problem that the element size (circuit area) of the transistor 4 is increased and the manufacturing cost is increased accordingly.

  The present invention has been made in view of the above circumstances, and an object thereof is gate driving capable of shortening the response time until the gate voltage is converged to the clamp value without causing an increase in circuit area and manufacturing cost. It is to provide a circuit.

  According to the first aspect of the present invention, there is provided a gate drive circuit for driving a gate of an insulated gate bipolar transistor (hereinafter referred to as IGBT) by supplying a gate signal through a pair of signal lines. A clamping transistor, clamping means and driving current amplification means connected between the signal lines. The clamp means includes a Zener diode and a switch means. The Zener diode is connected so as to be in a reverse bias state between a pair of signal lines, and has a characteristic of breakdown when a potential difference between the pair of signal lines tries to exceed a clamp value. The switch means is interposed in a connection path between the Zener diode and the signal line, and is turned on in a state where an abnormality detection signal is given, and is turned off in a state where no abnormality detection signal is given. The abnormality detection signal is given when an abnormality in which an overcurrent flows through the IGBT due to a short circuit or the like is detected.

  In such a configuration, when there is no abnormality in which overcurrent flows in the IGBT, no abnormality detection signal is given. Therefore, the switch means is turned off and the Zener diode is electrically disconnected from the pair of signal lines. In this state, since the Zener diode does not break down, no driving current is output from the clamping means. Therefore, the clamping transistor is in an off state, and no limitation is imposed on the potential difference between the signal lines. Therefore, the IGBT is driven as usual based on the supplied gate signal.

  On the other hand, when an abnormality occurs in which an overcurrent flows in the IGBT, an abnormality detection signal is given. For this reason, the switch means is turned on, and the Zener diode is electrically connected between the pair of signal lines. At this time, when the potential difference is about to exceed the clamp value, the drive current is output from the clamp means by the breakdown of the Zener diode. The drive current is for driving the clamping transistor to the on state. When the clamping transistor is turned on, a current flows between the signal lines, and the potential difference between the signal lines decreases. The clamp means outputs a drive current so as to fix (clamp) the potential difference to a clamp value. In other words, the clamp means controls the driving state of the clamping transistor so that the potential difference between the signal lines matches the clamp value.

  The drive current output from the clamp means is amplified by the drive current amplifying means, and the amplified drive current is supplied to the control terminal of the clamping transistor. In addition, the supply mentioned here means both the case where current flows into the control terminal and the case where current flows out from the control terminal. When the clamping transistor is a bipolar transistor, the drive current corresponds to the base current. In the bipolar transistor, the collector current increases as the base current increases. As the collector current of the clamping transistor increases, the decrease rate of the potential difference increases (the gradient of the decrease becomes steep). When the clamping transistor is a MOSFET, the driving current corresponds to a charging current for the gate-source capacitance. In the MOSFET, the gate-source voltage increases as the charging current increases. In the MOSFET, the drain current increases as the gate-source voltage increases. The decreasing rate of the potential difference increases as the drain current of the clamping transistor increases.

  For this reason, when the clamping transistor is turned on by a current with an increased driving current as in this means, the clamping transistor having the same size and characteristics as that of this means is turned on by the driving current that is not amplified. Compared with the case of driving, the reduction rate of the potential difference between the signal lines becomes higher. In this means, the added drive current amplifying means flows the current supplied to the control terminal of the clamping transistor, so it may have a lower current capability than the clamping transistor, and its size is relatively small. Therefore, the circuit area occupied by the components added in this means is relatively small as compared with the circuit area required for improving the current capability of the clamping transistor. For this reason, according to this means, the time until the potential difference between the signal lines is fixed to the clamp value without increasing the circuit area and the manufacturing cost, that is, the gate-emitter voltage (gate voltage) of the IGBT. It is possible to shorten the response time until the value converges to the clamp value. As a result, when an abnormality occurs in which the overcurrent flows through the IGBT due to a short circuit or the like, the IGBT gate voltage can be quickly reduced to the clamp value to eliminate the abnormality (overcurrent). It is possible to reduce the loss generated in the IGBT as it flows.

  The Zener diode provided in the clamp means has a characteristic that it breaks down when the potential difference between the signal lines exceeds the clamp value. That is, the value of the Zener voltage of the Zener diode is a value corresponding to the voltage applied between the terminals of the Zener diode when the potential difference between the signal lines reaches the clamp value. For this reason, when the potential difference between the signal lines exceeds the clamp value, the Zener diode breaks down and a breakdown current flows. The voltage between the terminals of the Zener diode in the breakdown state is equal to the Zener voltage. The clamp means outputs the breakdown current as a drive current. That is, the clamping transistor is driven to the on state by a current obtained by amplifying the breakdown current of the Zener diode. According to such a configuration, the potential difference (clamp value) between the signal lines during the clamping operation is determined according to the Zener voltage. Therefore, it is possible to easily change the clamp value only by changing the breakdown characteristics of the Zener diode to be used.

  The switch means provided in the clamp means is provided in a connection path between the Zener diode and the signal line. The switch means is turned on in a state where an abnormality detection signal indicating that an abnormality in which an overcurrent flows in the IGBT is detected, and is turned off in a state where the abnormality detection signal is not provided. When the above abnormality occurs, it is necessary to temporarily reduce the current flowing through the IGBT by lowering the gate voltage of the IGBT. According to such a configuration, when it is necessary to lower the gate voltage (voltage between the signal lines) of the IGBT, that is, when it is necessary to perform the above-described clamping operation, a state in which the Zener diode is connected between the signal lines. It becomes possible to. On the other hand, when it is not necessary to reduce the gate voltage of the IGBT, even if the Zener diode malfunctions due to, for example, noise, no current is supplied to the control terminal of the clamping transistor. It is never driven. Therefore, it is possible to prevent problems such as a decrease in voltage (gate voltage) between signal lines and wasteful power consumption due to a malfunction of the Zener diode.

  According to the means described in claim 2, the drive current amplifying means includes an amplifying transistor. The amplifying transistor is connected between one signal line of the pair of signal lines and the control terminal of the clamping transistor. A drive current output from the clamping means is supplied to the control terminal of the amplifying transistor. The supply here also means both the case where current is supplied to the control terminal and the case where current is supplied from the control terminal, as in the case of the supply described above in claim 1.

  When the amplifying transistor is a bipolar transistor, a driving current is supplied as its base current. A collector current of the clamping transistor, which is a current obtained by amplifying the base current, is supplied to the control terminal of the clamping transistor. When the amplifying transistor is a MOSFET, a driving current is supplied as a charging current for the gate-source capacitance. A drain current corresponding to the gate-source voltage of the MOSFET is supplied to the control terminal of the clamping transistor. The drain current corresponds to a current obtained by amplifying the charging current. By such a current amplifying action by the amplifying transistor, a current obtained by amplifying the driving current can be supplied to the control terminal of the clamping transistor.

  According to the means described in claim 3, the drive current amplifying means includes the off-fixing operation means. The off-fixing operation means is configured to be able to execute an off-fixing operation that maintains the clamping transistor in the off state regardless of the output state of the drive current from the clamping means. The off-fixing operation means becomes inoperative when the abnormality detection signal is applied, and operates when no abnormality detection signal is applied.

  According to such a configuration, when it is necessary to lower the gate voltage of the IGBT, that is, when it is necessary to clamp the voltage of the signal line, the clamping transistor is set according to the output state of the drive current from the clamping means. Driven. When there is no need to clamp the voltage between the signal lines, the clamping transistor is maintained in the off state. In this way, when it is not necessary to clamp the voltage between the signal lines, the clamping transistor can be reliably maintained in an off state, and the malfunction caused by noise superimposed on the control terminal can be prevented. Can be prevented.

  According to a fourth aspect of the present invention, the clamp means includes a diode connected so as to be in a forward bias state between the pair of signal lines. The diode is connected in series with the Zener diode. According to such a configuration, the potential difference (clamp value) between the signal lines during the clamping operation is determined according to the Zener voltage of the Zener diode and the forward voltage of the diode. Therefore, the clamp value can be easily changed in units of the forward voltage of the diode only by changing the number of diodes used.

  According to the means described in claim 5, since the amplifying transistor is constituted by a plurality of bipolar transistors, the amplifying effect of the driving current is further increased. Accordingly, the rate of decrease in the potential difference between the signal lines is further increased during the clamping operation, and the response time of the clamping operation can be further shortened. Alternatively, if the response time of the clamping operation is made approximately the same as the case where this means is not adopted, the size of the clamping transistor can be reduced correspondingly, and the circuit area can be reduced.

  According to the means described in claim 6, the drive current amplifying means includes current limiting means for limiting the drive current after amplification. If the reduction rate of the potential difference between the signal lines is too high during the clamping operation, a so-called undershoot occurs in which the potential difference between the signal lines temporarily decreases beyond the clamp value. If such an undershoot occurs, the operation of the circuit to which each signal line is connected may be adversely affected. In the present means, since the current limiting means limits the drive current after amplification, the occurrence of the undershoot is suppressed. However, since the effect of suppressing the undershoot and the effect of shortening the response time of the clamping operation are in a trade-off relationship, it is preferable to appropriately set the drive current limit value by the current limiting means so as to satisfy each required specification. .

1 is a partial configuration diagram of a motor drive circuit showing a first embodiment of the present invention. FIG. 1 equivalent diagram showing a second embodiment of the present invention FIG. 1 equivalent view showing a third embodiment of the present invention FIG. 1 equivalent view showing a fourth embodiment of the present invention FIG. 1 equivalent view showing a fifth embodiment of the present invention FIG. 1 equivalent view showing a sixth embodiment of the present invention The figure which shows the verification result of undershoot suppression action The figure which shows the constitution of the verification circuit of undershoot suppression action FIG. 1 equivalent view showing a seventh embodiment of the present invention Configuration diagram of clamp circuit showing conventional technology

(First embodiment)
Hereinafter, a first embodiment of the present invention will be described with reference to FIG.
FIG. 1 shows a circuit configuration of a part of a motor driving circuit including a switching element that forms a bridge connection form. That is, the motor drive circuit is an H-bridge circuit or the like if the motor to be driven is a brushed DC motor, and a three-phase full-bridge circuit or the like if the motor is a three-phase motor (such as an AC motor or a brushless DC motor). is there. FIG. 1 shows a transistor Q11 that is one of the switching elements and a gate drive circuit 11 that drives the gate thereof.

  The transistor Q11 is one of the switching elements that constitute the motor drive circuit, and constitutes, for example, a lower arm. The transistor Q11 is a multi-emitter type IGBT (Insulated Gate Bipolar Transistor). That is, the transistor Q11 includes a first emitter for flowing a supply current to a motor that is a load, and a second emitter for current detection for detecting an overcurrent described later. A relatively small current corresponding to the current flowing through the first emitter flows through the second emitter.

  The collector of the transistor Q11 is connected to the signal line L11, and the first emitter is connected to the signal line L12. Although not shown in FIG. 1, the signal line L11 is connected to a terminal of the motor and is connected to a power supply line of the motor drive circuit via a transistor constituting the upper arm. The signal line L12 is connected to the ground line (0 V) of the motor drive circuit. When the transistor Q11 constitutes the upper arm of the motor drive circuit, the signal line L11 is connected to the power supply line of the motor drive circuit, and the signal line L12 is connected to the motor terminal and through the transistor constituting the lower arm. Thus, it is connected to the ground line of the motor drive circuit.

  The second emitter of the transistor Q11 is connected to the signal line L12 via the resistors R11 and R12. The interconnection point Na between the resistors R11 and R12 is connected to the non-inverting input terminal of the comparator 12. The voltage Vdet at the interconnection point Na corresponds to the current output from the second emitter of the transistor Q11 and consequently the current (load current) output from the first emitter. The comparator 12 detects a load current flowing through the transistor Q11, and outputs an abnormality detection signal Sa having a level (voltage value) corresponding to the load current. The comparator 12 operates by being supplied with a power supply voltage VDD (for example, +5 V) via the power supply terminal 13 and the ground terminal 14.

  A reference voltage Vref output from a reference voltage generation circuit (not shown) is input to the inverting input terminal of the comparator 12. The comparator 12 compares the voltage Vdet at the interconnection point Na with the reference voltage Vref. Each resistance value (voltage division ratio) of the resistors R11 and R12 is such that the current flowing through the first emitter of the transistor Q11 (first emitter current) is a threshold current (threshold for detecting an overcurrent state). The value of the voltage Vdet at the time when they become equal is set to be equal to the value of the reference voltage Vref.

  Thereby, the abnormality detection signal Sa output from the output terminal of the comparator 12 becomes L level (level of the ground terminal 14 = 0V) when the first emitter current of the transistor Q11 is less than the threshold current. On the other hand, when the first emitter current of the transistor Q11 exceeds the threshold current, that is, when an abnormality occurs in which an overcurrent flows in the transistor Q11, the abnormality detection signal Sa is at the H level (power supply terminal 13 Level = + 5V). In short, the abnormality detection signal Sa becomes H level when an abnormality in which an overcurrent flows in the transistor Q11 is detected, and becomes L level when no abnormality is detected. The abnormality detection signal Sa output from the comparator 12 is given to the clamp circuit 15. In the present embodiment, the state of “abnormality detection signal Sa = H level” corresponds to the state where the abnormality detection signal is given, and the state of “abnormality detection signal Sa = L level” is given by the abnormality detection signal. It corresponds to a state that cannot be performed.

  The drive control circuit 16 outputs a gate signal Sg based on a command value for motor driving given from a higher-level control circuit (not shown). The gate signal Sg output from the drive control circuit 16 is applied to the gate of the transistor Q11 via the signal line L13 and the signal line L12 which is a reference potential line. Transistor Q11 is driven in accordance with gate signal Sg applied to the gate. In this case, since the gate signal Sg is a positive voltage, a positive voltage is applied between the signal lines L13 and L12 (between the gate and emitter of the transistor Q11).

  A clamp circuit 15 is provided between the signal line L13 connected to the gate of the transistor Q11 and the signal line L12 connected to the emitter of the transistor Q11. The clamp circuit 15 is in a state where the clamp operation can be executed in a state where the abnormality detection signal Sa of H level is given. The clamping operation means that the potential difference between the signal lines L13 and L12, that is, the potential difference between the signal lines L13 and L12 when the gate-emitter voltage (gate voltage) of the transistor Q11 increases beyond a predetermined clamp value Vcp. Is fixed to a predetermined clamp value Vcp. The clamp circuit 15 can be provided not only between the transistor Q11 constituting the lower arm but also between the gate and emitter of a transistor (not shown) constituting the upper arm.

  The clamp circuit 15 includes a clamp transistor T11, an amplification transistor T12, resistors R13 and R14, a Zener diode D11, and a switch S11. The clamping transistor T11 is an NPN bipolar transistor and can flow a relatively large collector current. The collector of the clamping transistor T11 is connected to the signal line L13, and the emitter of the clamping transistor T11 is connected to the signal line L12. That is, the clamping transistor T11 is connected between the signal lines L13 and L12. Between the base and emitter of the clamping transistor T11, a resistor R13 for stabilizing the operation at the OFF time is connected. The base (corresponding to the control terminal) of the clamping transistor T11 is connected to the collector of the amplifying transistor T12.

  The amplifying transistor T12 is a PNP-type bipolar transistor and has a smaller collector current that can be flowed than the clamping transistor T11. Therefore, the size of the amplifying transistor T12 is smaller than that of the clamping transistor T11. The emitter of the amplifying transistor T12 is connected to the signal line L13. Between the emitter and base of the amplifying transistor T12, a resistor R14 for stabilizing the operation at the off time is connected. The base of the amplifying transistor T12 (corresponding to the control terminal) is connected to the cathode of the Zener diode D11. The anode of the Zener diode D11 is connected to the signal line L12 via the switch S11.

  On / off of the switch S11 provided in series in the connection path between the Zener diode D11 and the signal line L12 is controlled according to the abnormality detection signal Sa. The switch S11 is turned on when the abnormality detection signal Sa becomes H level. As a result, the Zener diode D11 is connected to the signal lines L13 and L12 via the resistor R14 so as to be in a reverse bias state. For this reason, the clamp circuit 15 is in a state in which a clamp operation can be performed. The switch S11 is turned off when the abnormality detection signal Sa becomes L level. As a result, the Zener diode D11 is electrically disconnected from the signal lines L13 and L12. For this reason, the clamp circuit 15 is in a state in which the clamp operation cannot be executed.

The zener diode D11 has a zener voltage (breakdown voltage) Vz as expressed in the following equation (1). However, the clamp value is Vcp, and the forward voltage of the amplifying transistor T12 is Vf.
Vz = Vcp-Vf (1)

Due to the above configuration and the characteristics of the Zener diode D11, the clamp value Vcp at the time of the clamp operation by the clamp circuit 15 is expressed by the following equation (2).
Vcp = Vz + Vf (2)
As shown in the above equation (2), the clamp value Vcp of the clamp circuit 15 is determined by the Zener voltage Vz and the forward voltage Vf.

  In this embodiment, the clamping means 17 is comprised by the Zener diode D11 and switch S11. When the potential difference between the signal lines L13 and L12 tries to exceed the clamp value Vcp, the clamp means 17 outputs a drive current to drive the clamping transistor T11 to the on state, and fixes the potential difference to the clamp value Vcp. It is. The amplifying transistor T12 and the resistor R14 constitute drive current amplifying means 18. The drive current amplifying means 18 amplifies the drive current output from the clamp means 17 and supplies the amplified drive current to the base of the clamping transistor T11. Further, the breakdown current that flows when the Zener diode D11 breaks down corresponds to the drive current for driving the clamping transistor T11 to the ON state.

Next, the operation and effect of the above configuration will be described.
When the overcurrent state does not occur in the load current flowing through the transistor Q11, the abnormality detection signal Sa output from the comparator 12 is at the L level. For this reason, the clamp circuit 15 is in a state in which the clamp operation cannot be executed. Thus, when the overcurrent state is not generated in the load current, that is, when the motor drive circuit is operating normally, it is not necessary to perform the clamp operation by the clamp circuit 15. Therefore, in the present embodiment, in a state where the motor drive circuit is considered to be operating normally, the clamp circuit 15 cannot perform the clamp operation.

  That is, in the above state, since the Zener diode D11 is electrically disconnected from the signal lines L13 and L12, the breakdown current of the Zener diode D11 does not flow, and the amplifying transistor T12 is in the off state. Therefore, no limitation is imposed on the potential difference between the signal lines L13 and L12, and the transistor Q11 is driven as usual based on the gate signal Sg output from the drive control circuit 16.

  On the other hand, when an overcurrent state occurs in the load current flowing through the transistor Q11, the abnormality detection signal Sa output from the comparator 12 is at the H level. For this reason, the clamp circuit 15 is in a state in which a clamp operation can be performed. Thus, when an abnormality occurs in the motor drive circuit and an excessive load current flows, a protective operation such as temporarily reducing the current flowing through the transistor Q11 by reducing the gate voltage of the transistor Q11 is required. . Therefore, it is necessary to perform a clamping operation by the clamping circuit 15. Therefore, in this embodiment, when the load current flowing through the transistor Q11 exceeds the threshold current (overcurrent state), the clamp circuit 15 can perform the clamping operation.

  In the above state, when the potential difference between the signal lines L13 and L12 tries to rise beyond the clamp value Vcp, a clamp operation is performed by the clamp circuit 15, and the potential difference between the signal lines L13 and L12 is clamped (fixed) to the clamp value Vcp. ) Since the gate-emitter voltage of the transistor Q11 is suppressed to the clamp value Vcp, the load current flowing through the transistor Q11 decreases. That is, the overcurrent state can be eliminated by clamping the gate-emitter voltage of the transistor Q11.

  Specifically, the above clamping operation is performed as follows. That is, when the potential difference between the signal lines L13 and L12 tends to rise beyond the clamp value Vcp, the Zener diode D11 breaks down. As a result, a current flows from the signal line L13 to the signal line L12 via the resistor R14 and the Zener diode D11. Then, a potential difference is generated between the emitter and base of the amplifying transistor T12, and a base current is supplied. That is, a base current flows out from the base of the amplifying transistor T12 toward the signal line L12.

  As a result, the amplification transistor T12 is turned on. A collector current obtained by amplifying the base current with a predetermined amplification rate flows from the collector of the amplifying transistor T12. The collector current is supplied to the base of the clamping transistor T11. That is, a base current flows from the collector of the amplifying transistor T12 toward the base of the clamping transistor T11. As a result, the clamping transistor T11 is turned on. The clamping transistor T11 passes a collector current obtained by amplifying the base current with a predetermined amplification factor. When a current flows between the signal lines L13 and L12 via the clamping transistor T11, the voltage between the signal lines L13 and L12 decreases.

  When the voltage between the signal lines L13 and L12 decreases and falls below the clamp value Vcp, the breakdown state of the Zener diode D11 is released, and thus the amplifying transistor T12 and the clamping transistor T11 are turned off. Then, the potential difference between the signal lines L13 and L12 rises again. Thereafter, when the voltage between the signal lines L13 and L12 again exceeds the clamp value Vcp, the Zener diode D11 breaks down. As a result, the clamping transistor T11 is turned on, and the potential difference between the signal lines L13 and L12 decreases. By repeating such an operation, the voltage between the signal lines L13 and L12 is clamped (fixed) to the clamp value Vcp. That is, the drive state of the clamping transistor T11 is controlled according to the breakdown current of the Zener diode D11, whereby the potential difference between the signal lines L13 and L12 is clamped to the clamp value Vcp. The clamp value Vcp at this time is obtained by adding the forward voltage Vf of the amplifying transistor T12 to the Zener voltage Vz as represented by the above equation (2).

  Most of the breakdown current of the Zener diode D11 is the base current of the amplifying transistor T12. That is, the base current of the amplifying transistor T12 is substantially equal to the breakdown current. The current obtained by amplifying the breakdown current (the collector current of the amplifying transistor T12) is supplied to the base of the clamping transistor T11 by the amplifying action of the amplifying transistor T12. The collector current of the clamping transistor T11 increases as the base current increases. As the collector current of the clamping transistor T11 increases, the decrease rate of the potential difference between the signal lines L13 and L12 increases (the gradient of the decrease becomes steep). That is, the time (response time) required for the voltage between the signal lines L13 and L12 to converge to the clamp value Vcp during the clamp operation is shortened.

  For this reason, the clamp circuit 15 according to the present embodiment is compared with a clamp circuit that turns on a transistor having the same size and characteristics as the clamp transistor T11 according to the present embodiment by the breakdown current itself of the Zener diode D11. The reduction rate of the potential difference between the signal lines during operation increases. Further, the amplifying transistor T12 that constitutes the drive current amplifying means 18 may have a lower current capability than the clamping transistor T11. Therefore, the size of the amplifying transistor T12 can be made smaller than the size of the clamping transistor T11. Therefore, in the clamp circuit 15 of the present embodiment, the circuit area occupied by the drive current amplifying means 18 which is a component added from the conventional clamp circuit is the circuit area required for improving the current capability of the clamping transistor T11. Smaller than that. Therefore, according to the clamp circuit 15 of the present embodiment, the response time until the potential difference between the pair of signal lines L13 and L12 is fixed to the clamp value Vcp is shortened without increasing the circuit area and the manufacturing cost. be able to.

  According to the gate drive circuit 11 including such a clamp circuit 15, when the load current flowing through the transistor Q11 is in an overcurrent state, the gate voltage of the transistor Q11 can be quickly reduced to the clamp value Vcp. It becomes possible. As described above, according to the present embodiment, when an overcurrent occurs, the state can be quickly eliminated. Therefore, the loss generated in the transistor Q11 as the overcurrent flows can be reduced. Can do.

  In addition, the potential difference (clamp value Vcp) between the signal lines L13 and L12 during the clamping operation is determined by the Zener voltage Vz of the Zener diode D11 and the forward voltage Vf of the amplifying transistor T12. Therefore, since the clamp value Vcp can be easily changed by changing the Zener voltage Vz (characteristic regarding breakdown) of the Zener diode D11 to be used, the degree of freedom in circuit design is increased.

  When it is not necessary to perform the clamping operation, the clamp circuit 15 electrically disconnects the Zener diode D11 from the signal lines L13 and L12, and the clamping operation cannot be performed. Therefore, when the clamping operation is not necessary, for example, the malfunction of the Zener diode D11 due to the influence of noise or the like is suppressed, and the voltage between the signal lines L13 and L12 due to the malfunction of the clamping transistor T11 (the gate voltage of the transistor Q11). It is possible to prevent problems such as a decrease in power consumption and wasteful power consumption.

(Second Embodiment)
Hereinafter, the second embodiment of the present invention in which the type of transistors constituting the clamp circuit is changed will be described with reference to FIG.
FIG. 2 is a view corresponding to FIG. 1 in the first embodiment, and the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The clamp circuit 22 included in the gate drive circuit 21 according to the present embodiment illustrated in FIG. 2 includes a clamp transistor M21 instead of the clamp transistor T11 as compared with the clamp circuit 15 according to the first embodiment illustrated in FIG. The difference is that an amplifying transistor M22 is provided instead of the amplifying transistor T12.

  The clamping transistor M21 is an N-channel LDMOS (Laterally Diffused MOS) FET, and can flow a relatively large drain current. The amplifying transistor M22 is a P-channel type MOSFET, and the magnitude of the drain current that can flow is smaller than that of the clamping transistor M21. Therefore, the size of the amplifying transistor M22 is smaller than that of the clamping transistor M21. The clamping transistor M21 and the amplifying transistor M22 are connected in the same manner as the clamping transistor T11 and the amplifying transistor T12 in the first embodiment.

  The clamping operation by the clamping circuit 22 having the above configuration is as follows. That is, when the potential difference between the signal lines L13 and L12 tries to increase beyond the clamp value Vcp, the Zener diode D11 breaks down and a breakdown current flows. Then, a charging current corresponding to the breakdown current flows between the gate and source of the amplifying transistor M22, whereby the gate-source capacitance is charged. Then, the voltage between the gate and the source of the amplifying transistor M22 increases and is turned on. A drain current corresponding to the gate-source voltage flows through the amplifying transistor M22 that is turned on.

  The drain current of the amplifying transistor M22 is supplied to the gate (corresponding to the control terminal) of the clamping transistor M21. That is, a current flows from the drain of the amplifying transistor M22 toward the gate of the clamping transistor M21. This drain current flows between the gate and source of the clamping transistor M21, whereby the gate-source capacitance is charged. Then, the gate-source voltage of the clamping transistor M21 increases and is turned on. A drain current corresponding to the gate-source voltage flows through the clamp transistor M21 that is turned on. When a current flows between the signal lines L13 and L12 via the clamping transistor M21, the voltage between the signal lines L13 and L12 decreases.

The clamp value Vcp at this time is obtained by adding the threshold voltage Vt of the amplifying transistor M22 to the Zener voltage Vz as represented by the following expression (3).
Vcp = Vz + Vt (3)
Even with the configuration of the present embodiment in which the clamping transistor M21 and the amplifying transistor M22, both of which are MOSFETs, are used as the clamping transistor and the amplifying transistor, the breakdown current (drive current) is obtained by the current amplifying action of the amplifying transistor M22. Since the clamp transistor M21 is driven on by the amplified current, the same operation and effect as the first embodiment can be obtained.

(Third embodiment)
Hereinafter, a third embodiment of the present invention in which the configuration of the drive current amplification means is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 3 is a view corresponding to FIG. 1 in the first embodiment, and the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The clamp circuit 32 provided in the gate drive circuit 31 of this embodiment shown in FIG. 3 is different from the clamp circuit 15 of the first embodiment shown in FIG. It has different points.

  The drive current amplifying unit 33 further includes an amplifying transistor T31 and a resistor R31 in addition to the components included in the drive current amplifying unit 18. The amplification transistor T31 is an NPN bipolar transistor. The amplification transistors T12 and T31 are connected in two stages. That is, the base of the clamping transistor T11 is connected to the emitter of the amplifying transistor T31. The collector of the amplifying transistor T31 is connected to the signal line L13. A resistor R31 is connected between the base of the amplifying transistor T31 and the signal line L12 to stabilize the off-time operation. The base of the amplifying transistor T31 is connected to the collector of the amplifying transistor T12.

  The clamp circuit 32 of the present embodiment includes a drive current amplifying unit 33 configured by amplification transistors T12 and T31 connected in two stages. Thus, the current amplification effect is improved by configuring the amplifying transistors in two stages. For this reason, since the amplification factor of the current supplied to the base of the clamping transistor T11 is increased, the response time of the clamping operation can be further shortened. Further, if the response time of the clamping operation is set to the same level as that of the first embodiment, the size of the clamping transistor T11 can be reduced correspondingly, and the circuit area can be reduced.

(Fourth embodiment)
Hereinafter, a fourth embodiment of the present invention in which the configuration of the clamping means is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 4 is a view corresponding to FIG. 1 in the first embodiment, and the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The clamp circuit 42 provided in the gate drive circuit 41 of the present embodiment shown in FIG. 4 is provided with a clamp means 43 instead of the clamp means 17 with respect to the clamp circuit 15 of the first embodiment shown in FIG. Is different.

  The clamp unit 43 includes a diode D41 in addition to the configuration of the clamp unit 17. The diode D41 is connected in series with the Zener diode D11. The cathodes of the diode D41 and the Zener diode D11 are connected in common. The anode of the diode D41 is connected to the base of the amplifying transistor T12 and is connected to the signal line L13 via the resistor R14. That is, the diode D41 is connected between the pair of signal lines L13 and L12 so as to be in a forward bias state.

The Zener diode D11 of this embodiment has a Zener voltage Vz as expressed in the following equation (4). However, the forward voltage of the diode D41 is Vf.
Vz = Vcp−2 · Vf (4)
Due to the above configuration and the characteristics of the Zener diode D11, the clamp value Vcp at the time of the clamp operation by the clamp circuit 42 is expressed by the following equation (5).
Vcp = Vz + 2 · Vf (5)

  As shown in the above equation (5), in the clamp circuit 42 of the present embodiment, the clamp value Vcp at the time of the clamp operation is determined by the Zener voltage Vz of the Zener diode D11 and the forward voltage Vf of the amplification transistor T12 and the diode D41. . Accordingly, the clamp value Vcp can be easily changed in units of the forward voltage Vf by appropriately changing the number of diodes D41 inserted between the base of the amplifying transistor T12 and the signal line L12. The degree of freedom is further increased.

(Fifth embodiment)
Hereinafter, a fifth embodiment of the present invention in which the configuration of the drive current amplification means is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 5 is a view corresponding to FIG. 1 in the first embodiment, and the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The clamp circuit 52 provided in the gate drive circuit 51 of this embodiment shown in FIG. 5 is different from the clamp circuit 15 of the first embodiment shown in FIG. It has different points.

  The drive current amplifying unit 53 includes diodes D51 and D52 instead of the resistor R14 included in the drive current amplifying unit 18. The anode of the diode D51 is connected to the emitter of the amplifying transistor T12. The cathode of the diode D51 is connected to the anode of the diode D52. The cathode of the diode D52 is connected to the base of the amplifying transistor T12. That is, a series circuit of diodes D51 and D52 is connected between the emitter and base of the amplifying transistor T12.

  The clamp circuit 52 of this embodiment in which a series circuit of diodes D51 and D52 is connected between the emitter and base of the amplifying transistor T12 instead of the resistor R14 also amplifies the Zener diode D11 in the off state (the state where it does not break down). It is possible to prevent the operation transistor T12 from malfunctioning due to the influence of noise or the like. That is, the operational stability when the amplification transistor T12 is off can be improved.

(Sixth embodiment)
Hereinafter, the sixth embodiment of the present invention in which the configuration of the drive current amplifying means is changed with respect to the first embodiment will be described with reference to FIGS.
FIG. 6 is a view corresponding to FIG. 1 in the first embodiment, and the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The clamp circuit 62 provided in the gate drive circuit 61 of the present embodiment shown in FIG. 6 is different from the clamp circuit 15 of the first embodiment shown in FIG. It has different points.

  The drive current amplifying unit 63 includes a resistor R61 in addition to the components included in the drive current amplifying unit 18. The resistor R61 is connected between the signal line L13 and the emitter of the amplifying transistor T12. With such a configuration, the resistor R61 functions as current limiting means for limiting the drive current after amplification, that is, the collector current of the amplifying transistor T12.

  During the clamping operation, the amplifying transistor T12 allows a collector current corresponding to the base current to flow from the signal line L13 toward the clamping transistor T11. The resistor R61 is interposed in series with the path through which the collector current flows. For this reason, the collector current is limited according to the resistance value of the resistor R61.

  In the clamp operation, if the rate of decrease in the potential difference between the signal lines L13 and L12 is too high, so-called undershoot occurs in which the potential difference temporarily decreases beyond the clamp value Vcp. When undershoot occurs, there is a possibility that the operation of the transistor Q11 to which the signal lines L13 and L12 are connected is adversely affected. In such a case, undershooting can be suppressed by limiting the collector current of the amplifying transistor T12 during the clamping operation as in this embodiment.

  FIG. 7 shows the confirmation result of the undershoot suppression effect by the above configuration, and FIG. 8 shows the configuration of the verification circuit used for the confirmation. The verification circuit shown in FIG. 8 simulates the operation of increasing the potential difference between the gate and the emitter of the transistor Q11, and includes a current source 64 and a capacitor 65. The current source 64 and the capacitor 65 are connected in series between the power supply terminal 66 and the ground terminal 67. An interconnection point between the current source 64 and the capacitor 65 is connected to the signal line L13. The signal line L12 is connected to the ground terminal 67. With such a configuration, the capacitor 65 is charged according to the output current of the current source 64, and the charging voltage is applied between the signal lines L13 and L12. In this verification circuit, the switch S11 of the clamp circuit 62 is fixed to the on state.

  The result of confirming the clamp operation by applying an overvoltage exceeding the clamp value Vcp between the signal lines L13 and L12 using the verification circuit having the above configuration is as follows. That is, the voltage waveform between the signal lines L13 and L12 during the clamping operation by the verification circuit is as shown in FIG. In FIG. 7, when the resistance value of the resistor R61 is 1 kΩ, it is indicated by A (solid line), when 2 kΩ is indicated by B (two-dot chain line), when 3 kΩ is indicated by C (one-dot chain line), and when 5 kΩ is indicated This is indicated by D (broken line). As shown in FIG. 7, the higher the resistance value of the resistor R61, the lower the occurrence of undershoot when converging to the clamp value Vcp. Note that the amount of undershoot generated depends on the characteristics of each component constituting the clamp circuit 62, such as the characteristics of each transistor. Therefore, the resistance value of the resistor R61 in this verification result is merely an example, and it is necessary to set as appropriate for each applied clamp circuit.

Further, the clamp value Vcp changes according to the resistance value of the resistor R61. That is, in the present embodiment in which the resistor R61 is inserted, the clamp value Vcp is increased by the voltage drop in the resistor R61 as compared with the case in which the resistor R61 is not inserted. Accordingly, the clamp value Vcp at the time of the clamp operation by the clamp circuit 62 is expressed by the following equation (6). However, the voltage drop in the resistor R61 is Vr.
Vcp = Vz + Vf + Vr (6)

  The current flowing through the resistor R61 during the clamping operation is a minimum current that can maintain the on state (breakdown state) of the Zener diode D11, and is substantially constant even when the voltage between the signal lines L13 and L12 changes. This is because the change in the current flowing from the signal line L13 to the signal line L12 is sufficiently larger than the current flowing in the resistor R61 due to the voltage change between the signal lines L13 and L12. It is because it is absorbed by. However, when the current capability of the clamping transistor T11 is insufficient, care must be taken because the current flowing through the resistor R61 may change with the voltage change between the signal lines L13 and L12.

  Thus, according to the clamp circuit 62 of this embodiment in which the resistor R61 is inserted between the signal line L13 and the emitter of the amplification transistor T12, the collector current of the amplification transistor T12 during the clamping operation is limited. The occurrence of undershoot during the clamping operation can be suppressed. However, since the effect of suppressing undershoot and the effect of shortening the response time of the clamping operation are in a trade-off relationship, the resistance value of the resistor R61, that is, the drive current by the current limiting means, is considered in consideration of the required specifications. The limit value should be set appropriately.

(Seventh embodiment)
Hereinafter, the seventh embodiment of the present invention in which the configuration of the drive current amplifying means is changed with respect to the first embodiment will be described with reference to FIG.
FIG. 9 is a view corresponding to FIG. 1 in the first embodiment, and the same parts as those in the first embodiment are denoted by the same reference numerals and description thereof is omitted. The clamp circuit 72 provided in the gate drive circuit 71 of this embodiment shown in FIG. 9 is different from the clamp circuit 15 of the first embodiment shown in FIG. 1 in that a drive current amplification means 73 is used instead of the drive current amplification means 18. It has different points.

  The drive current amplifying unit 73 includes a switch S71 (corresponding to an off-fixing operation unit) and an inverter circuit 74 in addition to the configuration provided in the drive current amplifying unit 18. The switch S71 is connected between the base of the clamping transistor T11 and the signal line L12. The inverter circuit 74 inverts the abnormality detection signal Sa and supplies the inverted signal to the switch S71. The on / off of the switch S71 is controlled according to the inverted signal.

  Specifically, the switch S71 is turned off when the inverted signal becomes L level (the abnormality detection signal Sa is H level). As a result, the clamping transistor T11 becomes drivable according to the output state of the driving current from the clamping means 17. For this reason, the clamp circuit 72 is in a state in which a clamp operation can be performed. The switch S71 is turned on when the inverted signal becomes H level (the abnormality detection signal Sa is L level). Thus, the clamping transistor T11 is maintained in the off state regardless of the output state of the driving current from the clamping means 17 (corresponding to the off-fixing operation). For this reason, the clamp circuit 72 is in a state where the clamp operation cannot be executed.

  The clamp circuit 72 according to the present embodiment is in a state where the clamp operation can be executed when it is necessary to perform the clamp operation. For this reason, when a clamping operation is necessary, it is possible to execute the same clamping operation as in the first embodiment, and the same operations and effects as in the first embodiment can be obtained.

  When the clamping circuit 72 does not need to perform the clamping operation, the clamping transistor T11 is maintained in the OFF state regardless of the output state of the driving current from the clamping means 17, and the clamping operation cannot be performed. To. Therefore, when the clamping operation is not necessary, the clamping transistor T11 can be surely maintained in the off state, and malfunction can be prevented when noise is superimposed on the base.

(Other embodiments)
The present invention is not limited to the embodiments described above and illustrated in the drawings, and the following modifications or expansions are possible.
In each of the above embodiments, the NPN bipolar transistor (T11) or the N-channel LDMOSFET (M21) is used as the clamping transistor, and the PNP bipolar transistor (T12) or the P-channel MOSFET (M22) is used as the amplifying transistor. However, instead of this, a PNP bipolar transistor or a P-channel LDMOSFET is used as a clamping transistor, and an NPN bipolar transistor or an N-channel MOSFET is used as an amplifying transistor. A circuit in which the connection state is changed may be used.

In the third embodiment, bipolar transistors (T12, T31) connected in two stages are used as amplification transistors, but the number of stages may be three or more.
In the sixth embodiment, instead of the resistor R61, a resistor interposed in series between the base of the amplifying transistor T12 and the Zener diode D11 may be provided. According to such a configuration, the base current of the amplifying transistor T12 is limited during the clamping operation. If the base current is limited, the collector current is also limited accordingly, so that the resistor functions as a current limiting means for limiting the drive current after amplification.

  In each of the embodiments described above, the switch S11 provided in series in the connection path between the Zener diode D11 and the signal line L12 has an abnormality detection output from the comparator 12 that compares the voltage Vdet with the reference voltage Vref. Although the configuration is such that the signal Sa is turned on / off according to the level of the signal Sa, the present invention is not limited thereto. That is, a circuit that outputs an abnormality detection signal when an abnormality that causes an overcurrent to flow through the transistor Q11 is detected is configured using, for example, a comparator, and the switch S11 is turned on when the abnormality detection signal is given, What is necessary is just to comprise so that it may turn off in the state where a signal is not given.

  In the drawing, 11, 21, 31, 41, 51, 61, 71 are gate drive circuits, 17, 43 are clamping means, 18, 33, 53, 63, 73 are drive current amplification means, D11 is a Zener diode, and D41 is Diodes, L12 and L13 are signal lines, R61 is a resistor (current limiting means), Q11 is a transistor (insulated gate bipolar transistor), S11 is a switch (switch means), S71 is a switch (off-fixing operation means), and T11 and M21 are Clamping transistors T12, T31, and M22 indicate amplification transistors.

Claims (6)

A gate drive circuit for driving a gate of an insulated gate bipolar transistor by supplying a gate signal via a pair of signal lines,
A clamping transistor connected between the pair of signal lines;
When the potential difference between the pair of signal lines exceeds a clamp value, a drive current is output to drive the clamping transistor to an on state, and the clamp that fixes the potential difference between the pair of signal lines to the clamp value Means,
Drive current amplification means for amplifying the drive current output from the clamping means and supplying the amplified drive current to the control terminal of the clamping transistor;
With
The clamp means is connected so as to be in a reverse bias state between the pair of signal lines, and has a characteristic that a breakdown occurs when a potential difference between the pair of power supply lines exceeds the clamp value; and Switch means interposed in a connection path between the Zener diode and the signal line, and outputs a breakdown current that flows when the Zener diode breaks down as the drive current;
The switch means is turned on in a state where an abnormality detection signal indicating that an abnormality in which an overcurrent flows in the insulated gate bipolar transistor is detected and is turned off in a state where the abnormality detection signal is not provided. A characteristic gate drive circuit. The drive current amplifying means includes an amplifying transistor connected between one signal line of the pair of signal lines and a control terminal of the clamping transistor,
2. The gate drive circuit according to claim 1, wherein a drive current output from the clamp means is supplied to a control terminal of the amplifying transistor. The drive current amplifying unit includes an off-fixing operation unit capable of performing an off-fixing operation for maintaining the clamping transistor in an off state regardless of an output state of the driving current from the clamp unit,
3. The off-fixing operation means is in an inoperative state when the abnormality detection signal is applied, and is in an operational state when the abnormality detection signal is not applied. Gate drive circuit.   The clamp means includes a diode connected in series with the Zener diode so as to be in a forward bias state between the pair of signal lines. The gate drive circuit described.   The gate drive circuit according to claim 2, wherein the amplifying transistor includes a plurality of bipolar transistors.   6. The gate driving circuit according to claim 1, wherein the driving current amplifying unit includes a current limiting unit that limits the amplified driving current.

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