JP2012064286A - Nonvolatile semiconductor storage device and method for controlling nonvolatile semiconductor storage device - Google Patents

Nonvolatile semiconductor storage device and method for controlling nonvolatile semiconductor storage device Download PDF

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JP2012064286A
JP2012064286A JP2010209650A JP2010209650A JP2012064286A JP 2012064286 A JP2012064286 A JP 2012064286A JP 2010209650 A JP2010209650 A JP 2010209650A JP 2010209650 A JP2010209650 A JP 2010209650A JP 2012064286 A JP2012064286 A JP 2012064286A
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JP5351863B2 (en
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Masaru Kawabata
優 川端
Nobuo Yamazaki
信夫 山崎
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PROBLEM TO BE SOLVED: To effectively prevent a deterioration in a variable resistive element of an RRAM by suppressing variations of resistive states.SOLUTION: A memory cell array 10 provided with a plurality of memory cells M provided with a variable resistive element R whose electric resistance changes to two or more different resistive states, a determination circuit for partitioning the range of resistance values, which the variable resistive element R can take, into a plurality of target ranges and a plurality of middle ranges and determining whether the resistance value of the memory cell M is within any range among the plurality of target ranges and the plurality of middle ranges, and a write circuit 13 for applying a voltage pulse to the variable resistive element R so as to make a resistance value be within one range among the target ranges and writing information in the memory cells M are provided. Two or more middle ranges exist between two adjacent target ranges. In the determination circuit, a voltage pulse is applied to a memory cell M in which the resistance value of the memory cell M is not determined to be within a predetermined target range on a first application condition set differently at least in each middle range.

Description

本発明は、電圧パルスの印加により電気抵抗が２以上の異なる抵抗状態に変化し、前記抵抗状態を不揮発的に保持することにより情報を記憶可能な可変抵抗素子を備えるメモリセルを複数備えてなるメモリセルアレイを備える不揮発性半導体記憶装置に関する。   The present invention includes a plurality of memory cells including variable resistance elements capable of storing information by changing an electric resistance to two or more different resistance states by application of a voltage pulse and holding the resistance state in a nonvolatile manner. The present invention relates to a nonvolatile semiconductor memory device including a memory cell array.

従来、大容量で安価な不揮発性メモリとしてフラッシュメモリが広く使用されている。しかし近年、フラッシュメモリの微細化限界が見えてきており、フラッシュメモリに代わる高速動作可能な次世代不揮発性ランダムアクセスメモリ（ＮＶＲＡＭ：Ｎｏｎｖｏｌａｔｉｌｅ Ｒａｎｄｏｍ Ａｃｃｅｓｓ Ｍｅｍｏｒｙ）として、ＦｅＲＡＭ（Ｆｅｒｒｏｅｌｅｃｔｒｉｃ ＲＡＭ）、ＭＲＡＭ（Ｍａｇｎｅｔｉｃ ＲＡＭ）、ＯＵＭ（Ｏｖｏｎｉｃ Ｕｎｉｆｉｅｄ Ｍｅｍｏｒｙ）、ＲＲＡＭ（抵抗変化メモリ：ＲＲＡＭは登録商標）等の不揮発性メモリの開発が盛んに行われている。   Conventionally, flash memories have been widely used as large-capacity and inexpensive nonvolatile memories. However, in recent years, the miniaturization limit of the flash memory has been seen, and as a next-generation non-volatile random access memory (NVRAM) capable of high-speed operation instead of the flash memory, FeRAM (Ferroelectric RAM), MRAM (Magnetic RAM) ), OUM (Ovonic Unified Memory), RRAM (resistance change memory: RRAM is a registered trademark), etc., are actively developed.

これらの不揮発性メモリの中でもＲＲＡＭは、高速書き換えが可能であり、材料に単純な二元系の遷移金属酸化物が使用可能なため作製が容易であり、既存のＣＭＯＳプロセスとの親和性が高いことに利点があることから注目されている。   Among these nonvolatile memories, the RRAM can be rewritten at high speed, and can be easily manufactured because a simple binary transition metal oxide can be used as a material, and has high compatibility with an existing CMOS process. It is attracting attention because of its advantages.

ＲＲＡＭは、図７に示すように、第１電極１０１と、第２電極１０２と、第１電極１０１と第２電極１０３の間に介装された可変抵抗体１０２を備える可変抵抗素子Ｒで構成されている。第１電極１０１と第２電極１０２との間に電気的ストレスとして電圧パルスを印加することにより、可変抵抗体１０２の電気抵抗を可逆的且つ不揮発的に２以上の抵抗状態に変化させる（スイッチング動作）ことができ、これにより情報を不揮発的に記憶させることができる。   As shown in FIG. 7, the RRAM is composed of a variable resistance element R including a first electrode 101, a second electrode 102, and a variable resistor 102 interposed between the first electrode 101 and the second electrode 103. Has been. By applying a voltage pulse as an electrical stress between the first electrode 101 and the second electrode 102, the electric resistance of the variable resistor 102 is reversibly and non-volatilely changed to two or more resistance states (switching operation) This allows information to be stored in a nonvolatile manner.

可変抵抗体１０２の材料としては、例えば、超巨大磁気抵抗効果で知られるペロブスカイト材料がある（例えば、特許文献１、非特許得文献１参照）。尚、ペロブスカイト材料としては、例えば、ペロブスカイト型酸化物である結晶性プラセオジウム・カルシウム・マンガン酸化物Ｐｒ１−ＸＣａＸＭｎＯ３（ＰＣＭＯ）膜がある（特許文献１参照）。また、可変抵抗体１０２の他の材料としては、例えば、遷移金属の酸化物である酸化チタン（ＴｉＯ２）膜、ニッケル酸化（ＮｉＯ）膜、酸化亜鉛（ＺｎＯ）膜、酸化ニオブ（Ｎｂ２Ｏ５）膜がある（例えば、特許文献２、非特許得文献２参照）。尚、可変抵抗体１０２として酸化チタンや酸化ニッケル等の遷移金属酸化物を用いた場合、可変抵抗素子Ｒに流れ込む電流による熱上昇によって酸化物中に局所的に抵抗率が低下した領域（以下、適宜「フィラメントパス」と称す）が形成されたり、分解されたりすることによって、抵抗変化が発生していると考えられている（非特許文献３参照）。 As a material of the variable resistor 102, for example, there is a perovskite material known for its supergiant magnetoresistance effect (see, for example, Patent Document 1 and Non-Patent Document 1). As the perovskite material, for example, there is a crystalline praseodymium / calcium / manganese oxide Pr 1-X Ca X MnO 3 (PCMO) film which is a perovskite oxide (see Patent Document 1). Examples of other materials of the variable resistor 102 include a titanium oxide (TiO 2 ) film, a nickel oxide (NiO) film, a zinc oxide (ZnO) film, and niobium oxide (Nb 2 O), which are transition metal oxides. 5 ) There is a film (for example, see Patent Document 2 and Non-Patent Document 2). Note that when a transition metal oxide such as titanium oxide or nickel oxide is used as the variable resistor 102, a region in which the resistivity is locally reduced in the oxide due to a heat increase due to a current flowing into the variable resistance element R (hereinafter, referred to as “the variable resistor 102”). It is considered that a resistance change is caused by forming or disassembling (referred to as “filament path” as appropriate) (see Non-Patent Document 3).

米国特許第６２０４１３９号明細書US Pat. No. 6,204,139 特表２００２−５３７６２７号公報JP 2002-537627 A

Ｌｉｕ，Ｓ．Ｑ．他、“Ｅｌｅｃｔｒｉｃ−ｐｕｌｓｅ−ｉｎｄｕｃｅｄ ｒｅｖｅｒｓｉｂｌｅ Ｒｅｓｉｓｔａｎｃｅ ｃｈａｎｇｅ ｅｆｆｅｃｔ ｉｎ ｍａｇｎｅｔｏｒｅｓｉｓｔｉｖｅ ｆｉｌｍｓ”，Ａｐｐｌｉｅｄ Ｐｈｙｓｉｃｓ Ｌｅｔｔｅｒｓ，２０００年，Ｖｏｌ．７６，ｐ．２７４９−２７５１Liu, S .; Q. Et al., “Electric-pulse-induced reversible resistance change effect in magnetosensitive films”, Applied Physics Letters, 2000, Vol. 76, p. 2749-2751 Ｈ．Ｐａｇｎｉａ他、“Ｂｉｓｔａｂｌｅ Ｓｗｉｔｃｈｉｎｇ ｉｎ Ｅｌｅｃｔｒｏｆｏｒｍｅｄ Ｍｅｔａｌ−Ｉｎｓｕｌａｔｏｒ−Ｍｅｔａｌ Ｄｅｖｉｃｅｓ”，Ｐｈｙｓ．Ｓｔａｔ．Ｓｏｌ．（ａ），１９８８年，ｖｏｌ．１０８，ｐ．１１−６５H. Pagna, et al., “Bistable Switching in Electroformed Metal-Insulator-Metal Devices”, Phys. Stat. Sol. (A), 1988, vol. 108, p. 11-65 G. Dearnaley他, ”Electrical phenomena in amorphous oxide films”, Rep. Prog. Phys., 1970年, Vol. 33, p.1129-1191G. Dearnaley et al., “Electrical phenomena in amorphous oxide films”, Rep. Prog. Phys., 1970, Vol. 33, p.1129-1191

ここで、図８は、可変抵抗素子Ｒが２つの抵抗状態、即ち、高抵抗状態及び低抵抗状態の間で変化する場合におけるＩＶ特性を示している。   Here, FIG. 8 shows IV characteristics when the variable resistance element R changes between two resistance states, that is, a high resistance state and a low resistance state.

より具体的には、図８（ａ）は、高抵抗状態への書き込み処理を行った場合に、抵抗状態が目標となる抵抗値の範囲である目標範囲にある場合のＩＶ特性を、図８（ｂ）は、低抵抗状態への書き込み処理を行った場合に、抵抗状態が目標範囲にある場合のＩＶ特性を、図８（ｃ）は、高抵抗状態への書き込み処理を行った場合に、抵抗状態が目標範囲にない場合のＩＶ特性を、図８（ｄ）は、低抵抗状態への書き込み処理を行った場合に、抵抗状態が目標範囲にない場合のＩＶ特性を夫々示している。   More specifically, FIG. 8A shows the IV characteristics when the resistance state is in the target range which is the target resistance value range when the writing process to the high resistance state is performed. FIG. 8B shows the IV characteristics when the resistance state is in the target range when the writing process to the low resistance state is performed, and FIG. 8C shows the case when the writing process to the high resistance state is performed. FIG. 8D shows the IV characteristics when the resistance state is not within the target range when the writing process to the low resistance state is performed, respectively. .

高抵抗状態に書き込まれたメモリセルの場合、抵抗状態が目標範囲にある場合は、図８（ａ）のように、非線形性が強い特性を示すが、抵抗状態が目標範囲に無い場合は、即ち、書き込みが不十分の場合は、図８（ｃ）のように、非線形性が弱い特性を示すことになる。同様に、低抵抗状態に書き込まれたメモリセルの場合、図８（ｂ）のように、抵抗状態が目標範囲にある場合は、線形性の強い特性を示し、抵抗状態が目標範囲にない場合、即ち、書き込みが不十分の場合は、図８（ｄ）のように、線形性が弱い特性を示すことになる。   In the case of a memory cell written in a high resistance state, when the resistance state is in the target range, as shown in FIG. 8A, the non-linearity is strong, but when the resistance state is not in the target range, That is, when the writing is insufficient, the nonlinear characteristic is weak as shown in FIG. Similarly, in the case of the memory cell written in the low resistance state, as shown in FIG. 8B, when the resistance state is in the target range, the characteristic exhibits strong linearity, and the resistance state is not in the target range. That is, when the writing is insufficient, as shown in FIG. 8D, a characteristic with low linearity is exhibited.

このような書き込み処理後の抵抗状態のばらつきは、可変抵抗素子Ｒの劣化に影響する。例えば、図８（ｃ）のように、高抵抗状態への書き込みで抵抗状態が目標範囲にないメモリセルに対し、抵抗状態が目標範囲にある他のメモリセルと同じ電圧条件で低抵抗状態への書き込み処理を行うと、書き込み過剰になり、可変抵抗素子Ｒを劣化させる可能性がある。ここで、図９及び図１０は、高抵抗状態と低抵抗状態の間で抵抗状態を遷移させた場合の抵抗状態の変化を示しており、ＲＥＳＥＴは高抵抗状態への書き込み処理を行った場合の抵抗状態を、ＳＥＴは低抵抗状態への書き込み処理を行った場合の抵抗状態を夫々示している。図９は、抵抗状態が目標範囲内のメモリセル、即ち、劣化していないメモリセルの遷移を示しており、図１０は、劣化したメモリセルの遷移を２つのサンプルについて示している。図９と比較して、図１０では、一方のサンプルについては、ＳＥＴ２の低抵抗状態への書き込み処理以降、特に、ＲＥＳＥＴ３の高抵抗状態への書き込み処理において、所望の抵抗状態を得られなくなっていることが分かる。同様に、他方のサンプルについては、ＳＥＴ３の低抵抗状態への書き込み処理以降、特に、ＲＥＳＥＴ４の高抵抗状態への書き込み処理において、所望の抵抗状態を得られなくなっていることが分かる。   Such variation in the resistance state after the writing process affects the deterioration of the variable resistance element R. For example, as shown in FIG. 8C, a memory cell whose resistance state is not in the target range when writing to the high resistance state is changed to the low resistance state under the same voltage condition as other memory cells whose resistance state is in the target range. When the above writing process is performed, writing becomes excessive and the variable resistance element R may be deteriorated. Here, FIG. 9 and FIG. 10 show changes in the resistance state when the resistance state is transitioned between the high resistance state and the low resistance state, and RESET is when the writing process to the high resistance state is performed. , SET indicates the resistance state when the writing process to the low resistance state is performed. FIG. 9 shows a transition of a memory cell whose resistance state is within a target range, that is, a non-degraded memory cell, and FIG. 10 shows a transition of a degraded memory cell for two samples. Compared to FIG. 9, in FIG. 10, one sample cannot obtain a desired resistance state after the writing process to the low resistance state of SET 2, especially in the writing process to the high resistance state of RESET 3. I understand that. Similarly, for the other sample, it can be seen that a desired resistance state cannot be obtained after the writing process to the low resistance state of SET3, especially in the writing process to the high resistance state of RESET4.

従って、ＲＲＡＭにおいてメモリセルの抵抗状態のばらつきを抑えることは、不揮発性半導体記憶装置の信頼性等の観点から、重要であり、メモリセルの抵抗状態のばらつきを抑えることができる不揮発性半導体記憶装置が望まれている。   Accordingly, it is important to suppress variations in the resistance state of the memory cell in the RRAM from the viewpoint of the reliability of the nonvolatile semiconductor memory device, and the nonvolatile semiconductor memory device capable of suppressing the variation in the resistance state of the memory cell. Is desired.

尚、メモリセルの抵抗状態のばらつきを抑える方法としては、例えば、高抵抗状態への書き込み処理で抵抗状態が目標範囲内に到達しないメモリセルに対し、再度高抵抗状態への書き込み処理を行うことが考えられる。しかし、書き込み処理の電圧パルスの電圧値及びパルス幅の設定によっては、目標範囲からの抵抗値の差異の小さいメモリセルが書き込み過剰になる可能性がある。図１１は、オーバーライトの回数と可変抵抗素子Ｒの劣化の関係を示しており、オーバーライトが可変抵抗素子Ｒの劣化に繋がり、誤書き込みの要因になる可能性があることを示している。   As a method for suppressing variation in the resistance state of the memory cell, for example, the writing process to the high resistance state is performed again on the memory cell whose resistance state does not reach the target range in the writing process to the high resistance state. Can be considered. However, depending on the setting of the voltage value and the pulse width of the voltage pulse of the writing process, there is a possibility that the memory cell having a small difference in resistance value from the target range becomes overwritten. FIG. 11 shows the relationship between the number of times of overwriting and the deterioration of the variable resistance element R, and shows that the overwriting may lead to the deterioration of the variable resistance element R and cause erroneous writing.

本発明は上記の問題に鑑みてなされたものであり、その目的は、抵抗状態のばらつきを抑えてＲＲＡＭの可変抵抗素子の劣化を効果的に防止する点にある。   The present invention has been made in view of the above problems, and an object of the present invention is to effectively prevent deterioration of the variable resistance element of the RRAM by suppressing variation in resistance state.

上記目的を達成するための本発明に係る不揮発性半導体記憶装置は、電圧パルスの印加により電気抵抗が２以上の異なる抵抗状態に変化し、前記抵抗状態を不揮発的に保持することにより情報を記憶可能な可変抵抗素子を備えるメモリセルを複数備えてなるメモリセルアレイと、前記可変抵抗素子の取り得る抵抗値の範囲を、複数の目標範囲と複数の中間範囲に区分し、前記メモリセルの抵抗値が、複数の前記目標範囲と複数の前記中間範囲の内の何れの範囲内にあるかを判定する判定処理を行う判定回路と、前記可変抵抗素子に対し抵抗値が前記目標範囲の中の１つの範囲内となるように電圧パルスを印加して、前記メモリセルに情報を書き込む書き込み回路と、を備え、隣接する２つの前記目標範囲間に前記中間範囲が２以上存在し、前記判定回路において抵抗値が前記中間範囲にあると判定された前記メモリセルに対し、前記中間範囲別に設定された第１印加条件で電圧パルスを印加することを特徴とする。   In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention changes its electric resistance to two or more different resistance states by applying a voltage pulse, and stores information by holding the resistance state in a nonvolatile manner. A memory cell array including a plurality of memory cells each including a variable resistance element, and a resistance value range of the variable resistance element is divided into a plurality of target ranges and a plurality of intermediate ranges; Is a determination circuit that performs a determination process for determining which one of the plurality of target ranges and the plurality of intermediate ranges is within, and a resistance value of the variable resistance element is 1 in the target range. And a writing circuit for writing information to the memory cell by applying a voltage pulse so as to be within one range, wherein there are two or more intermediate ranges between two adjacent target ranges, To said memory cell resistance is determined to be in the intermediate range in the determination circuit, and applying a voltage pulse in the first application condition set by the intermediate range.

更に、上記特徴の不揮発性半導体記憶装置は、前記可変抵抗素子の抵抗値が、複数の前記目標範囲と複数の前記中間範囲の内の何れの前記範囲内にあるかを判定するための複数のリファレンスレベルを備えたリファレンス回路を備え、前記判定回路が、前記可変抵抗素子の抵抗値またはその換算値を前記リファレンスレベルの夫々と比較して、前記判定処理を行うことが好ましい。   Furthermore, the nonvolatile semiconductor memory device having the above characteristics includes a plurality of resistance values for determining whether the resistance value of the variable resistance element is within the plurality of the target ranges or the plurality of the intermediate ranges. Preferably, a reference circuit having a reference level is provided, and the determination circuit compares the resistance value of the variable resistance element or its converted value with each of the reference levels to perform the determination process.

更に、上記特徴の不揮発性半導体記憶装置は、前記書き込み回路が、書き込み動作時において、書き込み対象の選択メモリセルの前記可変抵抗素子に対し所定の第２印加条件で電圧パルスを印加して書き込み処理を行い、前記判定回路が、前記書き込み処理後、前記選択メモリセルに対し前記判定処理を行い、前記書き込み回路が、前記書き込み動作における前記判定処理後、抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルの前記可変抵抗素子に対し、前記第１印加条件で電圧パルスを印加することが好ましい。   Further, in the nonvolatile semiconductor memory device having the above characteristics, the write circuit applies a voltage pulse to the variable resistance element of the selected memory cell to be written under a predetermined second application condition during a write operation. The determination circuit performs the determination process on the selected memory cell after the write process, and the write circuit has a resistance value in one of the intermediate ranges after the determination process in the write operation. Preferably, a voltage pulse is applied to the variable resistance element of the selected memory cell determined to be under the first application condition.

更に、上記特徴の不揮発性半導体記憶装置は、前記判定回路が、読み出し動作時において、読み出し対象の選択メモリセルに対し前記判定処理を行い、前記可変抵抗素子の抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルについて、前記中間範囲に最も近い前記目標範囲に対応する情報値を出力し、前記書き込み回路が、前記読み出し動作における前記判定処理後、抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルの前記可変抵抗素子に対し、前記第１印加条件で電圧パルスを印加することが好ましい。   Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, the determination circuit performs the determination process on a selected memory cell to be read during a read operation, and the resistance value of the variable resistance element is one in the intermediate range. Output the information value corresponding to the target range closest to the intermediate range, and the write circuit has a resistance value after the determination process in the read operation, for the selected memory cell determined to be in the intermediate range Preferably, a voltage pulse is applied to the variable resistance element of the selected memory cell determined to be in one of the above conditions under the first application condition.

更に、上記特徴の不揮発性半導体記憶装置は、前記判定回路が、リフレッシュ動作時において、リフレッシュ対象の選択メモリセルに対し前記判定処理を行い、前記書き込み回路が、前記リフレッシュ動作における前記判定処理後、抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルの前記可変抵抗素子に対し、前記第１印加条件で電圧パルスを印加することが好ましい。   Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, the determination circuit performs the determination process on the selected memory cell to be refreshed during the refresh operation, and the write circuit performs the determination process in the refresh operation, Preferably, a voltage pulse is applied under the first application condition to the variable resistance element of the selected memory cell that has been determined to have a resistance value in one of the intermediate ranges.

上記目的を達成するための本発明に係る不揮発性半導体記憶装置は、電圧パルスの印加により電気抵抗が２以上の異なる抵抗状態に変化し、前記抵抗状態を不揮発的に保持することにより情報を記憶可能な可変抵抗素子を備えるメモリセルを複数備えてなるメモリセルアレイを備える不揮発性半導体記憶装置の制御方法であって、前記可変抵抗素子の取り得る抵抗値の範囲を、複数の目標範囲と複数の中間範囲に区分し、隣接する２つの前記目標範囲間に前記中間範囲が２以上存在し、前記メモリセルの抵抗値が、複数の前記目標範囲と複数の前記中間範囲の内の何れの範囲内にあるかを判定する判定処理を行う判定工程と、前記判定工程において抵抗値が前記中間範囲にあると判定された前記メモリセルに対し、前記中間範囲別に設定された第１印加条件で電圧パルスを印加する電圧印加工程と、を実行することを特徴とする。   In order to achieve the above object, a nonvolatile semiconductor memory device according to the present invention changes its electric resistance to two or more different resistance states by applying a voltage pulse, and stores information by holding the resistance state in a nonvolatile manner. A method for controlling a nonvolatile semiconductor memory device including a memory cell array including a plurality of memory cells each including a variable resistance element, wherein a resistance value range that the variable resistance element can take is set to a plurality of target ranges and a plurality of target ranges. The intermediate range is divided into two or more intermediate ranges between two adjacent target ranges, and the resistance value of the memory cell is within any range of the plurality of target ranges and the plurality of intermediate ranges. A determination step for performing a determination process for determining whether or not the resistance value is in the intermediate range for the memory cell in which the resistance value is determined to be in the intermediate range in the determination step. And executes a voltage applying step of applying a voltage pulse in the first application condition.

上記特徴の不揮発性半導体記憶装置によれば、可変抵抗素子の抵抗値が中間範囲内にある場合に、中間範囲別に設定された第１印加条件で電圧パルスを印加するので、目標範囲の下限値または上限値に対応する抵抗値と可変抵抗素子の抵抗値の差異に応じた電圧パルスを印加できる。これによって、可変抵抗素子が過剰書き込みになる可能性が低くなるので、可変抵抗素子の劣化をより効果的に防止することが可能になる。   According to the nonvolatile semiconductor memory device having the above characteristics, when the resistance value of the variable resistance element is in the intermediate range, the voltage pulse is applied under the first application condition set for each intermediate range. Alternatively, a voltage pulse corresponding to the difference between the resistance value corresponding to the upper limit value and the resistance value of the variable resistance element can be applied. As a result, the possibility that the variable resistance element is overwritten is reduced, so that the deterioration of the variable resistance element can be more effectively prevented.

更に、上記特徴の不揮発性半導体記憶装置において、読み出し動作時に、可変抵抗素子の抵抗値が中間範囲にある選択メモリセルについて、最も近い目標範囲に対応する情報値を出力するように構成すれば、可変抵抗素子の抵抗値が目標範囲外の選択メモリセルについても、読み出し動作をより適切に行うことができる。更に、上記特徴の不揮発性半導体記憶装置において、読み出し動作時に、可変抵抗素子の抵抗値が中間範囲にある選択メモリセルに対し第１印加条件で電圧パルスを印加するように構成すれば、読み出しディスターブにより可変抵抗素子の抵抗値が目標範囲外となった選択メモリセルの抵抗値を目標範囲内にすることができるので、可変抵抗素子の劣化をより効果的に防止することが可能になる。   Furthermore, in the nonvolatile semiconductor memory device having the above characteristics, when configured to output an information value corresponding to the closest target range for a selected memory cell in which the resistance value of the variable resistance element is in the intermediate range during a read operation, The read operation can be performed more appropriately for the selected memory cell whose resistance value of the variable resistance element is outside the target range. Further, in the nonvolatile semiconductor memory device having the above characteristics, if the voltage pulse is applied to the selected memory cell having the resistance value of the variable resistance element in the intermediate range during the read operation, the read disturb is achieved. Thus, the resistance value of the selected memory cell in which the resistance value of the variable resistance element is out of the target range can be set within the target range, so that deterioration of the variable resistance element can be more effectively prevented.

また、上記特徴の不揮発性半導体記憶装置において、例えば、書き込み動作や読み出し動作を行わない期間に、リフレッシュ動作として、可変抵抗素子の抵抗値が目標範囲内にない選択メモリセルに対し第１印加条件で電圧パルスを印加するように構成すれば、経時劣化により可変抵抗素子の抵抗値が目標範囲外となった選択メモリセルの抵抗値を目標範囲内にすることができるので、可変抵抗素子の劣化をより効果的に防止することが可能になる。   In the nonvolatile semiconductor memory device having the above characteristics, for example, the first application condition is applied to a selected memory cell in which the resistance value of the variable resistance element is not within the target range as a refresh operation during a period in which no write operation or read operation is performed. If the voltage pulse is applied at the same time, the resistance value of the selected resistance memory cell whose resistance value is outside the target range due to deterioration over time can be set within the target range. Can be more effectively prevented.

本発明に係る不揮発性半導体記憶装置の概略構成例を示す概略ブロック図である。1 is a schematic block diagram illustrating a schematic configuration example of a nonvolatile semiconductor memory device according to the present invention. 本発明に係る不揮発性半導体記憶装置のメモリセルアレイの概略構成例を示す概略ブロック図である。1 is a schematic block diagram showing a schematic configuration example of a memory cell array of a nonvolatile semiconductor memory device according to the present invention. 目標範囲と中間範囲の設定の一例について示す概略構成図である。It is a schematic block diagram shown about an example of the setting of a target range and an intermediate range. 本発明に係る不揮発性半導体記憶装置の制御方法の一例を示すフローチャートである。3 is a flowchart showing an example of a method for controlling a nonvolatile semiconductor memory device according to the present invention. 本発明に係る不揮発性半導体記憶装置の制御方法の一例を示すフローチャートである。3 is a flowchart showing an example of a method for controlling a nonvolatile semiconductor memory device according to the present invention. 本発明に係る不揮発性半導体記憶装置の制御方法の一例を示すフローチャートである。3 is a flowchart showing an example of a method for controlling a nonvolatile semiconductor memory device according to the present invention. ＲＲＡＭのメモリセルの概略構成例を示す概略ブロック図である。It is a schematic block diagram which shows the schematic structural example of the memory cell of RRAM. ＲＲＡＭの可変抵抗素子のＩＶ特性を示すグラフである。It is a graph which shows the IV characteristic of the variable resistance element of RRAM. ＲＲＡＭの可変抵抗素子の抵抗状態を高抵抗状態と低抵抗状態の間で遷移させた場合の抵抗状態の変化を示すグラフである。It is a graph which shows the change of a resistance state at the time of changing the resistance state of the variable resistance element of RRAM between a high resistance state and a low resistance state. ＲＲＡＭの可変抵抗素子の抵抗状態を高抵抗状態と低抵抗状態の間で遷移させた場合の抵抗状態の変化を示すグラフである。It is a graph which shows the change of a resistance state at the time of changing the resistance state of the variable resistance element of RRAM between a high resistance state and a low resistance state. ＲＲＡＭの可変抵抗素子のオーバーライトの回数と劣化の関係を示すグラフである。It is a graph which shows the relationship between the frequency | count of overwriting and deterioration of the variable resistance element of RRAM.

以下、本発明に係る不揮発性半導体記憶装置及び不揮発性半導体記憶装置の制御方法（以下、適宜「本発明装置」、「本発明方法」と略称する）の実施形態を図面に基づいて説明する。   DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a nonvolatile semiconductor memory device and a method for controlling the nonvolatile semiconductor memory device according to the present invention (hereinafter simply referred to as “device of the present invention” and “method of the present invention” as appropriate) will be described below with reference to the drawings.

先ず、本発明装置の構成について、図１及び図２を基に説明する。   First, the configuration of the device of the present invention will be described with reference to FIGS. 1 and 2.

本発明装置１は、図１及び図２に示すように、電圧パルスの印加により電気抵抗が２以上の異なる抵抗状態に変化し、抵抗状態を不揮発的に保持することにより情報を記憶可能な可変抵抗素子Ｒを備えるメモリセルＭを複数備えてなるメモリセルアレイ１０と、本発明装置１の動作制御を行う制御回路１１と、メモリセルＭに印加する複数種類の電圧または複数種類の電流を発生させる電圧発生回路１２と、メモリセルアレイ１０からの出力をリファレンス回路１７を用いて比較するセンス回路１６と、ワード線デコーダ１４及びビット線デコーダ１５を介して処理対象の選択メモリセルＭに電圧パルスを印加して書き込み動作を行う書き込み回路１３を備えて構成されている。   As shown in FIG. 1 and FIG. 2, the device 1 of the present invention changes its electric resistance to two or more different resistance states by applying a voltage pulse, and can store information by holding the resistance state in a nonvolatile manner. A memory cell array 10 including a plurality of memory cells M each including a resistance element R, a control circuit 11 for controlling the operation of the device 1 of the present invention, and a plurality of types of voltages or a plurality of types of currents applied to the memory cells M. A voltage pulse is applied to the selected memory cell M to be processed through the voltage generation circuit 12, the sense circuit 16 that compares the output from the memory cell array 10 using the reference circuit 17, and the word line decoder 14 and the bit line decoder 15. Thus, a write circuit 13 for performing a write operation is provided.

メモリセルアレイ１０は、図２に示すように、ｍ×ｎ個のメモリセルＭを備えて構成されている。ただし、ｍ、ｎは１以上の整数である。メモリセルＭｉｊ（ｉ＝１〜ｍ、ｊ＝１〜ｎ）は、ゲート端子がワード線ＷＬｊに、ソース端子がソース線ＳＬｊに夫々接続されたＭＯＳトランジスタＴと、一端がビット線ＢＬｉに、他端がＭＯＳトランジスタＴのドレイン端子に夫々接続された可変抵抗素子Ｒを備えて構成されている。   As shown in FIG. 2, the memory cell array 10 includes m × n memory cells M. However, m and n are integers of 1 or more. The memory cell Mij (i = 1 to m, j = 1 to n) includes a MOS transistor T having a gate terminal connected to the word line WLj, a source terminal connected to the source line SLj, and one end connected to the bit line BLi. The variable resistor element R is connected to the drain terminal of the MOS transistor T.

可変抵抗素子Ｒの構成は、図７に示す従来の可変抵抗素子Ｒの構成と同じであり、本実施形態では、可変抵抗体１０２がＨｆＯｘ、第１電極１０１及び第２電極１０３が共にＴｉＮで構成されており、可変抵抗素子Ｒの抵抗値が高抵抗状態と低抵抗状態の２つの抵抗状態の間で変化する場合について説明する。尚、本実施形態では、可変抵抗素子Ｒの抵抗値が高抵抗状態と低抵抗状態の２つの抵抗状態の間で変化する場合を想定しているが、これに限るものではなく、３以上の抵抗状態の間で変化する可変抵抗素子Ｒであっても良い。   The configuration of the variable resistance element R is the same as that of the conventional variable resistance element R shown in FIG. 7. In this embodiment, the variable resistance body 102 is HfOx, and the first electrode 101 and the second electrode 103 are both TiN. A case where the resistance value of the variable resistance element R is configured and changes between two resistance states of a high resistance state and a low resistance state will be described. In the present embodiment, it is assumed that the resistance value of the variable resistance element R changes between two resistance states, ie, a high resistance state and a low resistance state. It may be a variable resistance element R that changes between resistance states.

更に、本実施形態では、可変抵抗体１０２がＨｆＯｘ、第１電極１０１及び第２電極１０３が共にＴｉＮで構成されている場合を想定して説明するが、これに限るものではない。可変抵抗体１０２の材料としては、ＨｆＯｘだけでなく、例えば、ＣｏＯ、ＮｉＯ、ＴａＯｘ、ＴｉＯｘ、ＺｒＯｘ、ＡｌＯｘ、ＣｕＯｘ、ＮｂＯｘ等の金属酸化物で電圧印加によって抵抗が変化する公知の可変抵抗材料が使用できる。また、第１電極１０１の材料は、可変抵抗体１０２を構成する金属酸化物がｎ型半導体であるかｐ型半導体であるかによって変わる。可変抵抗体１０２がＴｉＯｘ、ＴａＯｘのようなｎ型半導体の場合は、第１電極１０１の材料として、ＰｔやＴｉＮのような仕事関数が４．５ｅＶより大きな金属を用い、可変抵抗体１０２がＣｏＯ、ＮｉＯのようなｐ型半導体の場合は、仕事関数が４．５ｅＶより小さなＴｉやＴａのような金属を用い、第１電極１０１と可変抵抗体１０２を構成する金属酸化物の間にショットキー障壁ができるような組み合わせとすることで、可変抵抗素子Ｒとして良好なスイッチング特性（高抵抗状態と低抵抗状態間の抵抗状態の遷移特性）を得ることができ、望ましい。第２電極１０３の材料としては、例えば、Ｔｉ、Ｔａ、Ｈｆ、又はＺｒから選択される金属の何れかを含む金属酸化物または金属窒化物が考えられる。   Furthermore, in the present embodiment, the case where the variable resistor 102 is composed of HfOx and the first electrode 101 and the second electrode 103 are both composed of TiN will be described. However, the present invention is not limited to this. As a material of the variable resistor 102, not only HfOx but also a known variable resistance material whose resistance is changed by voltage application with a metal oxide such as CoO, NiO, TaOx, TiOx, ZrOx, AlOx, CuOx, and NbOx, for example. Can be used. The material of the first electrode 101 varies depending on whether the metal oxide constituting the variable resistor 102 is an n-type semiconductor or a p-type semiconductor. When the variable resistor 102 is an n-type semiconductor such as TiOx or TaOx, a metal having a work function larger than 4.5 eV such as Pt or TiN is used as the material of the first electrode 101, and the variable resistor 102 is CoO. In the case of a p-type semiconductor such as NiO, a metal such as Ti or Ta having a work function smaller than 4.5 eV is used, and a Schottky is interposed between the first electrode 101 and the metal oxide constituting the variable resistor 102. By using a combination that can provide a barrier, it is desirable that the variable resistance element R can obtain good switching characteristics (transition characteristics of a resistance state between a high resistance state and a low resistance state). As a material of the second electrode 103, for example, a metal oxide or a metal nitride containing any of metals selected from Ti, Ta, Hf, or Zr can be considered.

制御回路１１は、図示しないが、外部入力されたアドレス信号を記憶するアドレスバッファと、書き込み動作時に外部入力されたデータ信号を記憶し、読み出し動作時に外部出力するデータ信号を記憶するデータバッファを備えて構成されており、外部から書き込み動作または読み出し動作を示す制御信号を受け付けて、後述する書き込み動作、書き込みベリファイ動作、読み出し動作及びセルフリフレッシュ動作の制御を行う。また、内部指示に基づいて、リフレッシュ動作の制御を行う。尚、内部指示による書き込み動作及び読み出し動作の制御を行えるように構成しても良い。   Although not shown, the control circuit 11 includes an address buffer that stores an externally input address signal, and a data buffer that stores an externally input data signal during a write operation and stores a data signal output externally during a read operation. In this configuration, a control signal indicating a write operation or a read operation is received from the outside, and a write operation, a write verify operation, a read operation, and a self-refresh operation, which will be described later, are controlled. Also, the refresh operation is controlled based on the internal instruction. Note that the writing operation and the reading operation may be controlled by an internal instruction.

ワード線デコーダ１４は、ワード線ＷＬ１〜ＷＬｎと接続し、選択ワード線と非選択ワード線に分離して、後述する書き込み動作、書き込みベリファイ動作、読み出し動作、セルフリフレッシュ動作、及び、リフレッシュ動作の各動作別に、選択ワード線電圧ＶＷＬ１と非選択ワード線電圧ＶＷＬ０を印加する。選択ワード線電圧ＶＷＬ１が印加されたワード線に接続するメモリセルＭのＭＯＳトランジスタＴはＯＮ状態となり、非選択ワード線電圧ＶＷＬ０が印加されたワード線に接続するメモリセルＭのＭＯＳトランジスタＴはＯＦＦ状態となる。   The word line decoder 14 is connected to the word lines WL1 to WLn and separated into a selected word line and a non-selected word line, and each of a write operation, a write verify operation, a read operation, a self-refresh operation, and a refresh operation described later is performed. For each operation, the selected word line voltage VWL1 and the unselected word line voltage VWL0 are applied. The MOS transistor T of the memory cell M connected to the word line to which the selected word line voltage VWL1 is applied is turned on, and the MOS transistor T of the memory cell M connected to the word line to which the unselected word line voltage VWL0 is applied is turned off. It becomes a state.

ビット線デコーダ１５は、ビット線ＢＬ１〜ＢＬｍと接続し、選択ビット線と非選択ビット線に分離して、後述するメモリセルＭに対する書き込み動作、書き込みベリファイ動作、読み出し動作、セルフリフレッシュ動作、及び、リフレッシュ動作の各動作別に、後述する第１印加条件で、選択ビット線電圧ＶＢＬ１と非選択ビット線電圧ＶＢＬ０を印加する。選択ビット線電圧ＶＢＬ１が印加されたビット線が選択され、非選択ビット線電圧ＶＢＬ０が印加されたビット線が非選択となる。   The bit line decoder 15 is connected to the bit lines BL1 to BLm and separated into a selected bit line and a non-selected bit line, and a write operation, a write verify operation, a read operation, a self-refresh operation, For each refresh operation, the selected bit line voltage VBL1 and the unselected bit line voltage VBL0 are applied under a first application condition described later. The bit line to which the selected bit line voltage VBL1 is applied is selected, and the bit line to which the unselected bit line voltage VBL0 is applied is not selected.

電圧発生回路１２は、後述するメモリセルＭに対する書き込み動作、書き込みベリファイ動作、読み出し動作、セルフリフレッシュ動作、及び、リフレッシュ動作の各動作別に設定された第１印加条件で、選択ワード線電圧ＶＷＬ１、非選択ワード線電圧ＶＷＬ０、選択ビット線電圧ＶＢＬ１及び非選択ビット線電圧ＶＢＬ０等の電圧を発生させる。   The voltage generation circuit 12 is configured to select the selected word line voltage VWL1 and non-voltage under a first application condition set for each of a write operation, a write verify operation, a read operation, a self-refresh operation, and a refresh operation for a memory cell M to be described later. Voltages such as a selected word line voltage VWL0, a selected bit line voltage VBL1, and a non-selected bit line voltage VBL0 are generated.

書き込み回路１３は、電圧発生回路１２、ワード線デコーダ１４、ビット線デコーダ１５、後述するセンス回路１６及びリファレンス回路１７に接続され、電圧発生回路１２で生成された電圧をワード線デコーダ１４及びビット線デコーダ１５に供給し、後述するセンス回路１６から選択メモリセルＭの可変抵抗素子Ｒの抵抗値の情報を受け付けるように構成されている。   The write circuit 13 is connected to the voltage generation circuit 12, the word line decoder 14, the bit line decoder 15, a sense circuit 16 and a reference circuit 17 which will be described later, and the voltage generated by the voltage generation circuit 12 is transferred to the word line decoder 14 and the bit line. The information is supplied to the decoder 15 and receives information on the resistance value of the variable resistance element R of the selected memory cell M from a sense circuit 16 to be described later.

センス回路１６（判定回路）は、ソース線ＳＬ１〜ＳＬｎと接続し、後述するメモリセルＭに対する書き込みベリファイ動作、読み出し動作、セルフリフレッシュ動作、及び、リフレッシュ動作での読み出し処理において、ソース線ＳＬ１〜ＳＬｎに流れる電流を選択ソース線と非選択ソース線に分離して検知し、当該電流の電流値を電圧に換算したレベル（可変抵抗素子Ｒの抵抗値の換算値）を、複数のリファレンス回路１７のリファレンスレベル（ここでは、電圧値）と比較して、選択メモリセルＭの可変抵抗素子Ｒの抵抗値を検出する。尚、本実施形態のセンス回路１６は、電圧の差動センス回路である場合を想定しているが、電流値を可変抵抗素子Ｒの抵抗値の換算値とし、電流の差動センス回路で構成しても良い。また、本実施形態のリファレンス回路１７は、可変抵抗素子Ｒの抵抗値に対応する抵抗値を持つ抵抗素子で構成されている。   The sense circuit 16 (determination circuit) is connected to the source lines SL1 to SLn, and the source lines SL1 to SLn are read in a write verify operation, a read operation, a self-refresh operation, and a refresh operation for a memory cell M described later. Is detected separately for the selected source line and the non-selected source line, and the level (converted value of the resistance value of the variable resistance element R) obtained by converting the current value of the current into a voltage is determined by the plurality of reference circuits 17. Compared with a reference level (here, a voltage value), the resistance value of the variable resistance element R of the selected memory cell M is detected. The sense circuit 16 of the present embodiment is assumed to be a voltage differential sense circuit. However, the current value is a converted value of the resistance value of the variable resistance element R, and the current differential sense circuit is configured. You may do it. Further, the reference circuit 17 of the present embodiment is configured by a resistance element having a resistance value corresponding to the resistance value of the variable resistance element R.

より具体的には、本実施形態のセンス回路１６は、可変抵抗素子Ｒの取り得る抵抗値の範囲を、複数の目標範囲と複数の中間範囲に区分し、メモリセルＭの抵抗値が、複数の目標範囲と複数の中間範囲の内の何れの範囲内にあるかを判定する判定処理を行う。   More specifically, the sense circuit 16 of the present embodiment divides the range of resistance values that can be taken by the variable resistance element R into a plurality of target ranges and a plurality of intermediate ranges, and the resistance values of the memory cells M are plural. A determination process for determining which of the target range and the plurality of intermediate ranges are within the range is performed.

ここで、図３は、目標範囲と中間範囲の設定の一例について示しており、隣接する２つの目標範囲間に中間範囲が２以上存在するように構成されている。本実施形態では、上述したように、可変抵抗素子Ｒの抵抗値が高抵抗状態と低抵抗状態の２つの抵抗状態の間で変化するので、高抵抗状態に対応する目標範囲Ａ１、低抵抗状態に対応する目標範囲Ａ６、及び、目標範囲Ａ１と目標範囲Ａ６の間を４分割した中間範囲Ａ２〜Ａ５が設定されている。リファレンス回路１７ａ〜１７ｅには、夫々、目標範囲Ａ１及びＡ６、中間範囲Ａ２〜Ａ５夫々の境界の抵抗値Ｒｅｆ１〜Ｒｅｆ５に対応するリファレンスレベル、ここでは、抵抗値の換算値としての電圧値が設定されている。センス回路１６は、可変抵抗素子Ｒの抵抗値を示すメモリセルアレイ１０からの出力をリファレンスレベルＲｅｆ１〜Ｒｅｆ５の夫々と比較して、判定処理を行う。   Here, FIG. 3 shows an example of setting of the target range and the intermediate range, and there are two or more intermediate ranges between two adjacent target ranges. In the present embodiment, as described above, since the resistance value of the variable resistance element R changes between the two resistance states of the high resistance state and the low resistance state, the target range A1 corresponding to the high resistance state, the low resistance state And an intermediate range A2 to A5 obtained by dividing the range between the target range A1 and the target range A6 into four. In the reference circuits 17a to 17e, reference levels corresponding to the resistance values Ref1 to Ref5 at the boundaries of the target ranges A1 and A6 and the intermediate ranges A2 to A5, respectively, are set here as voltage values as converted resistance values. Has been. The sense circuit 16 performs a determination process by comparing the output from the memory cell array 10 indicating the resistance value of the variable resistance element R with each of the reference levels Ref1 to Ref5.

次に、本発明方法について、図４〜図６を基に説明する。   Next, the method of the present invention will be described with reference to FIGS.

〈書き込み動作時の制御方法〉
書き込み動作時の本発明方法について、図４を基に説明する。 <Control method during write operation>
The method of the present invention during the write operation will be described with reference to FIG.

外部から書き込み動作を指示する制御信号が入力されると、制御回路１１が、アドレス信号及びデータ信号を受け付け、書き込み回路１３が、アドレス信号によって特定される書き込み対象の選択メモリセルＭの可変抵抗素子Ｒに対し、ワード線デコーダ１４及びビット線デコーダ１５を介して、所定の第２印加条件で電圧パルスを印加して書き込み処理を行う（ステップ＃１００）。ここでは、データ信号によって示される選択メモリセルＭの期待値が高抵抗状態に対応する値であり、選択メモリセルＭを低抵抗状態から高抵抗状態に書き込む場合（ＲＥＳＥＴ動作）について説明する。   When a control signal instructing a write operation is input from the outside, the control circuit 11 receives an address signal and a data signal, and the write circuit 13 is a variable resistance element of the selected memory cell M to be written that is specified by the address signal. A write process is performed on R by applying a voltage pulse under a predetermined second application condition via the word line decoder 14 and the bit line decoder 15 (step # 100). Here, the case where the expected value of the selected memory cell M indicated by the data signal is a value corresponding to the high resistance state, and the selected memory cell M is written from the low resistance state to the high resistance state (RESET operation) will be described.

引き続き、本発明装置１は、書き込みベリファイ処理を行う（ステップ＃１１０）。詳細には、書き込みベリファイ処理では、先ず、センス回路１６が、メモリセルアレイ１０からの出力信号のレベルをリファレンス回路１７のリファレンスレベルと比較して、選択メモリセルＭに対する判定処理を行う（ステップ＃１１１）。   Subsequently, the device 1 of the present invention performs a write verify process (step # 110). Specifically, in the write verify process, first, the sense circuit 16 compares the level of the output signal from the memory cell array 10 with the reference level of the reference circuit 17 and performs a determination process on the selected memory cell M (step # 111). ).

ここで、出力信号のレベルは、選択メモリセルの抵抗値に応じて流れる電流値を電圧に換算したレベルであり、抵抗値が大きいと出力信号の電圧レベルも高くなる。また、リファレンスレベルは、中間範囲の上限値及び下限値に対応する抵抗値を、同様に電圧値に換算した値となっている。   Here, the level of the output signal is a level obtained by converting the current value flowing according to the resistance value of the selected memory cell into a voltage, and the voltage level of the output signal increases as the resistance value increases. The reference level is a value obtained by converting resistance values corresponding to the upper limit value and the lower limit value of the intermediate range into voltage values in the same manner.

また、ここでの判定処理は、メモリセルアレイ１０からの出力信号のレベルを、図３に示すＲｅｆ１〜Ｒｅｆ５の５つのリファレンスレベルと比較して行う。メモリセルアレイ１０からの出力信号のレベルがリファレンスレベルＲｅｆ１〜Ｒｅｆ５より高い場合をＨ、低い場合をＬとすると、判定結果が（ＨＨＨＨＨ）の場合は選択メモリセルＭの可変抵抗素子Ｒの抵抗値が目標範囲Ａ１にあると判定できる。同様に、判定結果が（ＬＨＨＨＨ）の場合は中間範囲Ａ２に、判定結果が（ＬＬＨＨＨ）の場合は中間範囲Ａ３に、判定結果が（ＬＬＬＨＨ）の場合は中間範囲Ａ４に、判定結果が（ＬＬＬＬＨ）の場合は中間範囲Ａ５に、判定結果が（ＬＬＬＬＬ）の場合は目標範囲Ａ６にあると判定できる。   The determination process here is performed by comparing the level of the output signal from the memory cell array 10 with the five reference levels Ref1 to Ref5 shown in FIG. When the level of the output signal from the memory cell array 10 is higher than the reference levels Ref1 to Ref5, and H when the level is low, the resistance value of the variable resistance element R of the selected memory cell M is determined when the determination result is (HHHHH). It can be determined that the target range is A1. Similarly, if the determination result is (LHHHH), it is in the intermediate range A2, if the determination result is (LLHHH), it is in the intermediate range A3, if the determination result is (LLLLHH), it is in the intermediate range A4, and the determination result is (LLLLH). ) Can be determined to be in the intermediate range A5, and if the determination result is (LLLLLL), it can be determined to be in the target range A6.

引き続き、本発明装置１は、判定処理の結果、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が目標範囲Ａ１にあると判定した場合は（ステップ＃１１２で「ＹＥＳ」分岐）、書き込み処理が正常に完了したと判定して、書き込みベリファイ処理を終了する。   Subsequently, when the device 1 of the present invention determines that the resistance value of the variable resistance element R of the selected memory cell M is within the target range A1 as a result of the determination processing (“YES” branch in step # 112), the write processing is performed. It is determined that the processing has been completed normally, and the write verify process is terminated.

更に、本発明装置１は、判定処理の結果、抵抗値が期待値に対応する目標範囲以外の範囲にあると判定された選択メモリセルＭの前記可変抵抗素子Ｒに対し、第１印加条件で電圧パルスを印加する。尚、本実施形態では、中間範囲Ａ２〜Ａ５の夫々に加え、目標範囲Ａ６についても第１印加条件が設定されている。具体的には、本発明装置１は、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が目標範囲Ａ１にないと判定した場合は（ステップ＃１１２で「ＮＯ」分岐）、書き込み処理が正常に完了しなかったと判定し、書き込み回路１３が、当該選択メモリセルＭの可変抵抗素子Ｒに対し、中間範囲Ａ２〜Ａ５、目標範囲Ａ６別に設定された第１印加条件で電圧パルスを印加する（ステップ＃１１３）。ここでは、第１印加条件として、電圧パルスの電圧値が中間範囲Ａ２〜Ａ５、目標範囲Ａ６別に設定されている。より具体的には、中間範囲Ａ２の場合に電圧Ｖ１パルス幅Ｔ１の電圧パルスを、中間範囲Ａ３の場合に電圧Ｖ２パルス幅Ｔ２の電圧パルスを、中間範囲Ａ４の場合に電圧Ｖ３パルス幅Ｔ３の電圧パルスを、中間範囲Ａ５の場合に電圧Ｖ４パルス幅Ｔ４の電圧パルスを、目標範囲Ａ６の場合に電圧Ｖ５パルス幅Ｔ５の電圧パルスを夫々用いるとすると、目標範囲Ａ１からの抵抗値の差異が大きいほど電圧パルスの電圧値が大きくなるように、｜Ｖ１｜＜｜Ｖ２｜＜｜Ｖ３｜＜｜Ｖ４｜＜｜Ｖ５｜に設定されている。尚、第１印加条件としては、目標範囲Ａ１からの抵抗値の差異が大きいほど電圧パルスのパルス幅が大きくなるように、｜Ｔ１｜＜｜Ｔ２｜＜｜Ｔ３｜＜｜Ｔ４｜＜｜Ｔ５｜に設定しても良いし、パルス幅及び電圧値の両方を中間範囲Ａ２〜Ａ５、目標範囲Ａ６別に設定しても良い。尚、目標範囲Ａ６の第１印加条件は、第２印加条件と同じであっても良い。   Furthermore, as a result of the determination process, the device 1 of the present invention applies a first application condition to the variable resistance element R of the selected memory cell M in which the resistance value is determined to be in a range other than the target range corresponding to the expected value. Apply a voltage pulse. In the present embodiment, the first application condition is set for the target range A6 in addition to each of the intermediate ranges A2 to A5. Specifically, when the device 1 of the present invention determines that the resistance value of the variable resistance element R of the selected memory cell M is not within the target range A1 (“NO” branch at step # 112), the writing process is performed normally. The write circuit 13 determines that it has not been completed, and applies a voltage pulse to the variable resistance element R of the selected memory cell M under the first application condition set for each of the intermediate ranges A2 to A5 and the target range A6 (step) # 113). Here, as the first application condition, the voltage value of the voltage pulse is set for each of the intermediate ranges A2 to A5 and the target range A6. More specifically, a voltage pulse having a voltage V1 pulse width T1 in the intermediate range A2, a voltage pulse having a voltage V2 pulse width T2 in the intermediate range A3, and a voltage pulse having a voltage V3 pulse width T3 in the intermediate range A4. If the voltage pulse is a voltage pulse having a voltage V4 pulse width T4 in the case of the intermediate range A5 and a voltage pulse having a voltage V5 pulse width T5 in the case of the target range A6, then the difference in resistance value from the target range A1 is It is set to | V1 | <| V2 | <| V3 | <| V4 | <| V5 | so that the voltage value of the voltage pulse increases as the value increases. The first application condition is that | T1 | <| T2 | <| T3 | <| T4 | <| T5 so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A1 increases. It may be set to |, or both the pulse width and the voltage value may be set for each of the intermediate ranges A2 to A5 and the target range A6. Note that the first application condition of the target range A6 may be the same as the second application condition.

引き続き、本発明装置１は、第１印加条件で電圧パルスを印加した選択メモリセルＭに対し、再度、ステップ＃１１１から書き込みベリファイ処理を実行する（ステップ＃１１０）。   Subsequently, the device 1 of the present invention again executes the write verify process from step # 111 on the selected memory cell M to which the voltage pulse has been applied under the first application condition (step # 110).

尚、ここでは、外部から書き込み指示があった場合について説明したが、内部で書き込み指示があった場合についても同様に、書き込み動作時の本発明方法を適用できる。   Here, the case where a write instruction is given from the outside has been described, but the method of the present invention at the time of a write operation can be similarly applied to the case where a write instruction is given internally.

また、選択メモリセルＭを低抵抗状態から高抵抗状態に書き込む場合（ＲＥＳＥＴ動作）について説明したが、高抵抗状態から低抵抗状態に書き込む場合（ＳＥＴ動作）についても同様に適用できる。具体的には、目標範囲Ａ１の場合に電圧Ｖ０パルス幅Ｔ０の電圧パルスを用いるとすると、目標範囲Ａ６となるように書き込むので、目標範囲Ａ６からの抵抗値の差異が大きいほど電圧パルスの電圧値が大きくなるように｜Ｖ０｜＞｜Ｖ１｜＞｜Ｖ２｜＞｜Ｖ３｜＞｜Ｖ４｜に設定する。尚、目標範囲Ａ６からの抵抗値の差異が大きいほど電圧パルスのパルス幅が大きくなるように｜Ｔ０｜＞｜Ｔ１｜＞｜Ｔ２｜＞｜Ｔ３｜＞｜Ｔ４｜に設定しても良いし、電圧値及びパルス幅の両方を中間範囲Ａ２〜Ａ５、目標範囲Ａ１別に設定しても良い。   Further, the case where the selected memory cell M is written from the low resistance state to the high resistance state (RESET operation) has been described, but the same applies to the case where the selected memory cell M is written from the high resistance state to the low resistance state (SET operation). Specifically, if a voltage pulse having a voltage V0 pulse width T0 is used in the case of the target range A1, writing is performed so as to become the target range A6. Therefore, as the difference in resistance value from the target range A6 increases, the voltage pulse voltage It is set to | V0 |> | V1 |> | V2 |> | V3 |> | V4 | Note that | T0 |> | T1 |> | T2 |> | T3 |> | T4 | may be set so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A6 increases. Both the voltage value and the pulse width may be set separately for the intermediate range A2 to A5 and the target range A1.

〈読み出し動作時の制御方法〉
読み出し動作時の本発明方法について、図５を基に説明する。 <Control method during read operation>
The method of the present invention during the read operation will be described with reference to FIG.

外部から読み出し動作を指示する制御信号が入力されると、制御回路１１が、アドレス信号を受け付け、当該アドレスが示す選択メモリセルＭのデータを読み出す読み出し処理を行う（ステップ＃２００）。   When a control signal for instructing a read operation is input from the outside, the control circuit 11 receives an address signal and performs a read process of reading data in the selected memory cell M indicated by the address (step # 200).

具体的には、本発明装置１は、読み出し処理を開始すると、センス回路１６が、メモリセルアレイ１０からの出力信号のレベルをリファレンス回路１７のリファレンスレベルと比較して、選択メモリセルＭに対する判定処理を行う（ステップ＃２０１）。ここでは、書き込み処理の場合と同様に、メモリセルアレイ１０からの出力信号のレベルを、図３に示すＲｅｆ１〜Ｒｅｆ５の５つのリファレンスレベルと比較して、判定処理を行う。   Specifically, when the device 1 of the present invention starts the reading process, the sense circuit 16 compares the level of the output signal from the memory cell array 10 with the reference level of the reference circuit 17 to determine the selected memory cell M. Is performed (step # 201). Here, as in the case of the writing process, the level of the output signal from the memory cell array 10 is compared with the five reference levels Ref1 to Ref5 shown in FIG.

引き続き、本発明装置１は、センス回路１６により、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ２〜Ａ５にあると判定された場合（ステップ＃２０２で「中間範囲」分岐）、制御回路１１が、選択メモリセルＭの情報値として、判定された中間範囲に最も近い目標範囲に対応する情報値を出力する（ステップ＃２０３）。ここでは、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が、図３に示すＲｅｆ０（＝Ｒｅｆ３）より大きい場合は高抵抗状態と判定して高抵抗状態に対応する情報値を出力し、Ｒｅｆ０より小さい場合は低抵抗状態と判定して低抵抗状態に対応する情報値を出力する。即ち、センス回路１６により選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ２及びＡ３にあると判定された場合は、制御回路１１が目標範囲Ａ１に対応する情報値を外部出力し、センス回路１６により選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ４及びＡ５にあると判定された場合は、制御回路１１が目標範囲Ａ６に対応する情報値を外部出力する。   Subsequently, when it is determined by the sense circuit 16 that the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate range A2 to A5 (the “intermediate range” branch in step # 202), the device 1 of the present invention. The control circuit 11 outputs an information value corresponding to the target range closest to the determined intermediate range as the information value of the selected memory cell M (step # 203). Here, if the resistance value of the variable resistance element R of the selected memory cell M is larger than Ref0 (= Ref3) shown in FIG. 3, it is determined as the high resistance state, and an information value corresponding to the high resistance state is output. If it is smaller, it is judged as a low resistance state and an information value corresponding to the low resistance state is output. That is, if the sense circuit 16 determines that the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A2 and A3, the control circuit 11 outputs an information value corresponding to the target range A1 to the outside, When the sense circuit 16 determines that the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A4 and A5, the control circuit 11 outputs an information value corresponding to the target range A6 to the outside.

更に、本発明装置１は、センス回路１６により、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が目標範囲Ａ１にあると判定された場合は（ステップ＃２０２で「目標範囲」分岐）、制御回路１１が目標範囲Ａ１に対応する情報値を外部出力し（ステップ＃２０４）、センス回路１６により抵抗値が目標範囲Ａ６に在ると判定された場合は（ステップ＃２０２で「目標範囲」分岐）目標範囲Ａ６に対応する情報値を外部出力し（ステップ＃２０４）、当該選択メモリセルＭに対する読み出し処理（ステップ＃２００）を終了する。   Further, when the sense circuit 16 determines that the resistance value of the variable resistive element R of the selected memory cell M is within the target range A1 (the “target range” branch in step # 202), the device 1 of the present invention performs control. When the circuit 11 outputs the information value corresponding to the target range A1 to the outside (step # 204) and the sense circuit 16 determines that the resistance value is in the target range A6 ("target range" branch in step # 202) ) The information value corresponding to the target range A6 is externally output (step # 204), and the reading process (step # 200) for the selected memory cell M is completed.

引き続き、本発明装置１は、前回の判定処理で抵抗値が中間範囲の１つにあると判定された選択メモリセルＭに対するセルフリフレッシュ処理を行う（ステップ＃２１０）。詳細には、本発明装置１の書き込み回路１３が、抵抗値が中間範囲の１つにあると判定された選択メモリセルＭの可変抵抗素子Ｒに対し、第１印加条件で電圧パルスを印加する（ステップ＃２１１）。   Subsequently, the device 1 of the present invention performs a self-refresh process for the selected memory cell M in which the resistance value is determined to be in one of the intermediate ranges in the previous determination process (step # 210). Specifically, the write circuit 13 of the device 1 of the present invention applies a voltage pulse under the first application condition to the variable resistance element R of the selected memory cell M whose resistance value is determined to be in one of the intermediate ranges. (Step # 211).

より詳細には、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ２及びＡ３にある場合は、目標範囲Ａ１となるように設定された第１印加条件で電圧パルスを印加する。ここで、第１印加条件は、中間範囲Ａ２の場合に電圧Ｖ６パルス幅Ｔ６の電圧パルスを、中間範囲Ａ３の場合に電圧Ｖ７パルス幅Ｔ７の電圧パルスを夫々用いるとすると、目標範囲Ａ１からの抵抗値の差異が大きいほど電圧パルスの電圧値が大きくなるように、｜Ｖ６｜＜｜Ｖ７｜に設定されている。尚、第１印加条件としては、目標範囲Ａ１からの抵抗値の差異が大きいほど電圧パルスのパルス幅が大きくなるように、｜Ｔ６｜＜｜Ｔ７｜に設定しても良いし、パルス幅及び電圧値の両方を中間範囲Ａ２及びＡ３別に設定しても良い。   More specifically, when the resistance value of the variable resistance element R of the selected memory cell M is in the intermediate ranges A2 and A3, the voltage pulse is applied under the first application condition set to be the target range A1. Here, the first application condition is that when a voltage pulse having a voltage V6 pulse width T6 is used in the case of the intermediate range A2, and a voltage pulse having a voltage V7 pulse width T7 is used in the case of the intermediate range A3, | V6 | <| V7 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T6 | <| T7 | so that the pulse width of the voltage pulse increases as the resistance value difference from the target range A1 increases. Both voltage values may be set separately for the intermediate ranges A2 and A3.

更に、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ４及びＡ５にある場合は、目標範囲Ａ６となるように設定された第１印加条件で電圧パルスを印加する。ここで、第１印加条件は、中間範囲Ａ４の場合に電圧Ｖ８パルス幅Ｔ８の電圧パルスを、中間範囲Ａ５の場合に電圧Ｖ９パルス幅Ｔ９の電圧パルスを夫々用いるとすると、目標範囲Ａ６からの抵抗値の差異が大きいほど電圧パルスの電圧値が大きくなるように、｜Ｖ８｜＞｜Ｖ９｜に設定されている。尚、第１印加条件としては、目標範囲Ａ６からの抵抗値の差異が大きいほど電圧パルスのパルス幅が大きくなるように、｜Ｔ８｜＞｜Ｔ９｜に設定しても良いし、パルス幅及び電圧値の両方を中間範囲Ａ４及びＡ５別に設定しても良い。   Further, when the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A4 and A5, the voltage pulse is applied under the first application condition set to be the target range A6. Here, if the first application condition is to use a voltage pulse with a voltage V8 pulse width T8 in the case of the intermediate range A4 and a voltage pulse with a voltage V9 pulse width T9 in the case of the intermediate range A5, respectively, | V8 |> | V9 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T8 |> | T9 | so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A6 increases. Both voltage values may be set separately for the intermediate ranges A4 and A5.

引き続き、本発明装置１は、第１印加条件で電圧パルスを印加した選択メモリセルＭに対し、判定処理を行う（ステップ＃２１２）。可変抵抗素子Ｒの抵抗値が目標範囲Ａ１またはＡ６にある場合は、処理を終了し（ステップ＃２１３で「目標範囲」分岐）、可変抵抗素子Ｒの抵抗値が中間範囲Ａ２〜Ａ５にある場合は、再度ステップ＃２１１からセルフリフレッシュ処理を実行する（ステップ＃２１３で「中間範囲」分岐）。   Subsequently, the device 1 of the present invention performs a determination process on the selected memory cell M to which the voltage pulse has been applied under the first application condition (step # 212). When the resistance value of the variable resistance element R is in the target range A1 or A6, the process ends (the “target range” branch in step # 213), and the resistance value of the variable resistance element R is in the intermediate range A2 to A5 Performs the self-refresh process again from step # 211 ("intermediate range" branch in step # 213).

尚、ここでは、外部から読み出し指示があった場合について説明したが、内部で読み出し指示があった場合についても同様に、読み出し動作時の本発明方法を適用できる。   Here, the case where a read instruction is given from the outside has been described, but the method of the present invention at the time of a read operation can be similarly applied to the case where a read instruction is given internally.

〈リフレッシュ動作時の制御方法〉
リフレッシュ動作時の本発明方法について、図６を基に説明する。 <Control method during refresh operation>
The method of the present invention during the refresh operation will be described with reference to FIG.

本発明装置１は、本実施形態では、書き込み動作及び読み出し動作が一定時間指示されない場合に、一定時間毎に、自動的にリフレッシュ動作を実行するように構成されている。   In the present embodiment, the device 1 of the present invention is configured to automatically perform a refresh operation at regular time intervals when a write operation and a read operation are not instructed for a constant time.

本発明装置１は、リフレッシュ動作を開始すると、センス回路１６が、リフレッシュ対象の選択メモリセルＭを読み出して判定処理を行う（ステップ＃３０１）。   In the device 1 of the present invention, when the refresh operation is started, the sense circuit 16 reads the selected memory cell M to be refreshed and performs a determination process (step # 301).

本発明装置１は、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が目標範囲Ａ１またはＡ６にあると判定された場合は（ステップ＃３０２で「目標範囲」分岐）、当該選択メモリセルＭに対するリフレッシュ処理を終了する。   When it is determined that the resistance value of the variable resistive element R of the selected memory cell M is within the target range A1 or A6 (the “target range” branch in Step # 302), the device 1 of the present invention 1 applies to the selected memory cell M. The refresh process ends.

本発明装置１は、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ２〜Ａ５の１つにあると判定された場合は（ステップ＃３０２で「中間範囲」分岐）、書き込み回路１３が、当該選択メモリセルＭの可変抵抗素子Ｒに対し、第１印加条件で電圧パルスを印加する。より詳細には、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ２及びＡ３にある場合は、目標範囲Ａ１となるように設定された第１印加条件で電圧パルスを印加する。ここで、第１印加条件は、中間範囲Ａ２の場合に電圧Ｖ１０パルス幅Ｔ１０の電圧パルスを、中間範囲Ａ３の場合に電圧Ｖ１１パルス幅Ｔ１１の電圧パルスを夫々用いるとすると、目標範囲Ａ１からの抵抗値の差異が大きいほど電圧パルスの電圧値が大きくなるように、｜Ｖ１０｜＜｜Ｖ１１｜に設定されている。尚、第１印加条件としては、目標範囲Ａ１からの抵抗値の差異が大きいほど電圧パルスのパルス幅が大きくなるように、｜Ｔ１０｜＜｜Ｔ１１｜に設定しても良いし、パルス幅及び電圧値の両方を中間範囲Ａ２及びＡ３別に設定しても良い。   When it is determined that the resistance value of the variable resistive element R of the selected memory cell M is in one of the intermediate ranges A2 to A5 (the “intermediate range” branch in step # 302), the device 1 of the present invention 1 However, a voltage pulse is applied to the variable resistance element R of the selected memory cell M under the first application condition. More specifically, when the resistance value of the variable resistance element R of the selected memory cell M is in the intermediate ranges A2 and A3, the voltage pulse is applied under the first application condition set to be the target range A1. Here, when the first application condition is that a voltage pulse having a voltage V10 pulse width T10 is used in the case of the intermediate range A2, and a voltage pulse having a voltage V11 pulse width T11 is used in the case of the intermediate range A3, | V10 | <| V11 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T10 | <| T11 | so that the pulse width of the voltage pulse increases as the difference in resistance value from the target range A1 increases. Both voltage values may be set separately for the intermediate ranges A2 and A3.

更に、選択メモリセルＭの可変抵抗素子Ｒの抵抗値が中間範囲Ａ４及びＡ５にある場合は、目標範囲Ａ６となるように設定された第１印加条件で電圧パルスを印加する。ここで、第１印加条件は、中間範囲Ａ４の場合に電圧Ｖ１２パルス幅Ｔ１２の電圧パルスを、中間範囲Ａ５の場合に電圧Ｖ１３パルス幅Ｔ１３の電圧パルスを夫々用いるとすると、目標範囲Ａ６からの抵抗値の差異が大きいほど電圧パルスの電圧値が大きくなるように、｜Ｖ１２｜＞｜Ｖ１３｜に設定されている。尚、第１印加条件としては、目標範囲Ａ６からの抵抗値の差異が大きいほど電圧パルスのパルス幅が大きくなるように、｜Ｔ１２｜＞｜Ｔ１３｜に設定しても良いし、パルス幅及び電圧値の両方を中間範囲Ａ４及びＡ５別に設定しても良い。   Further, when the resistance value of the variable resistive element R of the selected memory cell M is in the intermediate ranges A4 and A5, the voltage pulse is applied under the first application condition set to be the target range A6. Here, if the first application condition is to use a voltage pulse having a voltage V12 pulse width T12 in the case of the intermediate range A4 and a voltage pulse having a voltage V13 pulse width T13 in the case of the intermediate range A5, respectively, | V12 |> | V13 | is set so that the voltage value of the voltage pulse increases as the difference in resistance value increases. The first application condition may be set to | T12 |> | T13 | so that the pulse width of the voltage pulse increases as the resistance value difference from the target range A6 increases. Both voltage values may be set separately for the intermediate ranges A4 and A5.

引き続き、本発明装置１は、第１印加条件で電圧パルスを印加した選択メモリセルＭに対し、ステップ＃３０１の判定処理を実行する。   Subsequently, the device 1 of the present invention executes the determination process of step # 301 for the selected memory cell M to which the voltage pulse is applied under the first application condition.

尚、ここでは、リフレッシュ動作について説明したが、読み出し動作及びリフレッシュ動作以外の動作であって、期待値が不明の場合に適用しても良い。また、リフレッシュ動作を内部指示に基づいて実行する場合を想定して説明したが、外部指示に基づいて実行可能に構成しても良い。   Although the refresh operation has been described here, it may be applied to an operation other than the read operation and the refresh operation and the expected value is unknown. Further, although the case where the refresh operation is executed based on the internal instruction has been described, the refresh operation may be executed based on the external instruction.

〈別実施形態〉
尚、上記実施形態では、リファレンス回路１７を複数備える場合について説明したが、これに限るものではない。例えば、リファレンスレベルを任意に変更可能なリファレンス回路１７を備える場合に、リファレンスレベルを適宜変更して、複数の目標範囲と複数の中間範囲の内の何れの範囲内にあるかを判定するように構成しても良い。 <Another embodiment>
In the above embodiment, the case where a plurality of reference circuits 17 are provided has been described. However, the present invention is not limited to this. For example, when the reference circuit 17 capable of arbitrarily changing the reference level is provided, the reference level is appropriately changed to determine which of the plurality of target ranges and the plurality of intermediate ranges are within the range. It may be configured.

１ 本発明に係る不揮発性半導体記憶装置
１０ メモリセルアレイ
１１ 制御回路
１２ 電圧発生回路
１３ 書き込み回路
１４ ワード線デコーダ
１５ ビット線デコーダ
１６ センス回路（判定回路）
１７ リファレンス回路
１０１ 第１電極
１０２ 可変抵抗体
１０３ 第２電極
Ｍ メモリセル
Ｒ 可変抵抗素子
Ｔ ＭＯＳトランジスタ
ＷＬ ワード線
ＢＬ ビット線
ＳＬ ソース線 DESCRIPTION OF SYMBOLS 1 Nonvolatile semiconductor memory device 10 concerning this invention Memory cell array 11 Control circuit 12 Voltage generation circuit 13 Write circuit 14 Word line decoder 15 Bit line decoder 16 Sense circuit (determination circuit)
Reference circuit 101 First electrode 102 Variable resistor 103 Second electrode M Memory cell R Variable resistance element T MOS transistor WL Word line BL Bit line SL Source line

Claims (6)

電圧パルスの印加により電気抵抗が２以上の異なる抵抗状態に変化し、前記抵抗状態を不揮発的に保持することにより情報を記憶可能な可変抵抗素子を備えるメモリセルを複数備えてなるメモリセルアレイと、
前記可変抵抗素子の取り得る抵抗値の範囲を、複数の目標範囲と複数の中間範囲に区分し、前記メモリセルの抵抗値が、複数の前記目標範囲と複数の前記中間範囲の内の何れの範囲内にあるかを判定する判定処理を行う判定回路と、
前記可変抵抗素子に対し抵抗値が前記目標範囲の中の１つの範囲内となるように電圧パルスを印加して、前記メモリセルに情報を書き込む書き込み回路と、を備え、
隣接する２つの前記目標範囲間に前記中間範囲が２以上存在し、
前記判定回路において抵抗値が前記中間範囲にあると判定された前記メモリセルに対し、前記中間範囲別に設定された第１印加条件で電圧パルスを印加することを特徴とする不揮発性半導体記憶装置。 A memory cell array including a plurality of memory cells each including a variable resistance element capable of storing information by changing the electrical resistance to two or more different resistance states by applying a voltage pulse and holding the resistance state in a nonvolatile manner;
A range of resistance values that the variable resistance element can take is divided into a plurality of target ranges and a plurality of intermediate ranges, and the resistance value of the memory cell is any one of the plurality of target ranges and the plurality of intermediate ranges. A determination circuit for performing a determination process for determining whether or not it is within a range;
A write circuit that writes information into the memory cell by applying a voltage pulse so that the resistance value of the variable resistance element is within one of the target ranges, and
There are two or more intermediate ranges between two adjacent target ranges,
A nonvolatile semiconductor memory device, wherein a voltage pulse is applied to the memory cell whose resistance value is determined to be in the intermediate range by the determination circuit under a first application condition set for each intermediate range. 前記可変抵抗素子の抵抗値が、複数の前記目標範囲と複数の前記中間範囲の内の何れの前記範囲内にあるかを判定するための複数のリファレンスレベルを備えたリファレンス回路を備え、
前記判定回路が、前記可変抵抗素子の抵抗値またはその換算値を前記リファレンスレベルの夫々と比較して、前記判定処理を行うことを特徴とする請求項１に記載の不揮発性半導体記憶装置。 A reference circuit having a plurality of reference levels for determining which of a plurality of the target ranges and a plurality of intermediate ranges the resistance value of the variable resistance element is in;
The nonvolatile semiconductor memory device according to claim 1, wherein the determination circuit performs the determination process by comparing a resistance value of the variable resistance element or a converted value thereof with each of the reference levels. 前記書き込み回路が、書き込み動作時において、書き込み対象の選択メモリセルの前記可変抵抗素子に対し所定の第２印加条件で電圧パルスを印加して書き込み処理を行い、
前記判定回路が、前記書き込み処理後、前記選択メモリセルに対し前記判定処理を行い、
前記書き込み回路が、前記書き込み動作における前記判定処理後、抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルの前記可変抵抗素子に対し、前記第１印加条件で電圧パルスを印加することを特徴とする請求項１または２に記載の不揮発性半導体記憶装置。 The write circuit performs a write process by applying a voltage pulse to the variable resistance element of the selected memory cell to be written under a predetermined second application condition during a write operation,
The determination circuit performs the determination process on the selected memory cell after the write process,
After the determination process in the write operation, the write circuit applies a voltage pulse to the variable resistance element of the selected memory cell in which the resistance value is determined to be in one of the intermediate ranges under the first application condition. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied. 前記判定回路が、読み出し動作時において、読み出し対象の選択メモリセルに対し前記判定処理を行い、前記可変抵抗素子の抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルについて、前記中間範囲に最も近い前記目標範囲に対応する情報値を出力し、
前記書き込み回路が、前記読み出し動作における前記判定処理後、抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルの前記可変抵抗素子に対し、前記第１印加条件で電圧パルスを印加することを特徴とする請求項１〜３の何れか１項に記載の不揮発性半導体記憶装置。 The determination circuit performs the determination process on a selected memory cell to be read during a read operation, and the selected memory cell in which the resistance value of the variable resistance element is determined to be in one of the intermediate ranges. Outputting an information value corresponding to the target range closest to the intermediate range;
After the determination process in the read operation, the write circuit applies a voltage pulse under the first application condition to the variable resistance element of the selected memory cell determined to have a resistance value in one of the intermediate ranges. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied. 前記判定回路が、リフレッシュ動作時において、リフレッシュ対象の選択メモリセルに対し前記判定処理を行い、
前記書き込み回路が、前記リフレッシュ動作における前記判定処理後、抵抗値が前記中間範囲の１つにあると判定された前記選択メモリセルの前記可変抵抗素子に対し、前記第１印加条件で電圧パルスを印加することを特徴とする請求項１〜４の何れか１項に記載の不揮発性半導体記憶装置。 The determination circuit performs the determination process on a selected memory cell to be refreshed during a refresh operation,
After the determination process in the refresh operation, the write circuit applies a voltage pulse under the first application condition to the variable resistance element of the selected memory cell in which the resistance value is determined to be in one of the intermediate ranges. The nonvolatile semiconductor memory device according to claim 1, wherein the nonvolatile semiconductor memory device is applied. 電圧パルスの印加により電気抵抗が２以上の異なる抵抗状態に変化し、前記抵抗状態を不揮発的に保持することにより情報を記憶可能な可変抵抗素子を備えるメモリセルを複数備えてなるメモリセルアレイを備える不揮発性半導体記憶装置の制御方法であって、
前記可変抵抗素子の取り得る抵抗値の範囲を、複数の目標範囲と複数の中間範囲に区分し、
隣接する２つの前記目標範囲間に前記中間範囲が２以上存在し、
前記メモリセルの抵抗値が、複数の前記目標範囲と複数の前記中間範囲の内の何れの範囲内にあるかを判定する判定処理を行う判定工程と、
前記判定工程において抵抗値が前記中間範囲にあると判定された前記メモリセルに対し、前記中間範囲別に設定された第１印加条件で電圧パルスを印加する電圧印加工程と、を実行することを特徴とする不揮発性半導体記憶装置の制御方法。

A memory cell array including a plurality of memory cells each including a variable resistance element capable of storing information by changing an electric resistance to two or more different resistance states by applying a voltage pulse and holding the resistance state in a nonvolatile manner. A method for controlling a nonvolatile semiconductor memory device, comprising:
A range of resistance values that the variable resistance element can take is divided into a plurality of target ranges and a plurality of intermediate ranges,
There are two or more intermediate ranges between two adjacent target ranges,
A determination step of performing a determination process for determining which of the plurality of target ranges and the plurality of intermediate ranges the resistance value of the memory cell is within;
Performing a voltage application step of applying a voltage pulse to the memory cells determined to have a resistance value in the intermediate range in the determination step under a first application condition set for each of the intermediate ranges. A method for controlling a nonvolatile semiconductor memory device.

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