JP2012032275A - Receiver circuit for radio time piece - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a receiver circuit for a radio time piece capable of remarkably reducing influences of noise upon a received signal by making a passband of a frequency selection filter narrow by compensating for initial deviation or temperature characteristics of a crystal oscillator or the filter and obtaining an intermediate frequency signal of a fine adjusted stable frequency by performing a fine adjustment of a frequency of a local signal.SOLUTION: In a receiver circuit for a radio time piece which produces a demodulation signal from a long standard radio wave selected from among a plurality of frequencies and including time information received by an external antenna 1, a local oscillation circuit 8 for producing a local signal from a reference frequency signal of a horizontal oscillation circuit 5 comprises a PLL circuit 6 and a DDS circuit 7, and a fine adjustment of a frequency of the local signal is performed by the DDS circuit 7.

Description

  The present invention relates to a superheterodyne type multi-frequency radio wave receiver for receiving a plurality of standard radio waves and correcting the time.

  2. Description of the Related Art Conventionally, a superheterodyne radio timepiece receiver circuit is known. The standard radio wave including time information is different for each transmission region. For example, it is set to 40 kHz or 60 kHz in Japan, and is set to 77.5 kHz in Germany (DCF-77). The radio clock receiver circuit is a PLL (Phase Locked Loop) circuit using a signal of a predetermined frequency received from these transmission waves and an oscillation signal having a frequency of 32.768 kHz generated by a crystal oscillator as a reference signal source. The local oscillation frequency signal output from the local oscillation circuit is mixed with a mixing circuit, then an intermediate frequency signal is output with an intermediate frequency circuit equipped with a crystal filter, and this intermediate frequency signal is demodulated with a detection circuit. (Patent Document 1).

Japanese Patent Laid-Open No. 6-214054

  However, this conventional superheterodyne radio clock receiver circuit has the following problems. First, there is an initial deviation and temperature characteristic of the reference signal frequency of 32.768 kHz due to the crystal resonator of the crystal oscillator, but no countermeasure is taken for this. Second, the crystal filter of the intermediate frequency circuit also has an initial deviation and temperature characteristics due to the crystal resonator, but no countermeasure is taken for this. Thirdly, in connection with the second point, in the crystal filter, the frequency correction of about several hundred ppm can be performed by the additional circuit. However, in the correction by the additional circuit, the Q value (equivalent to the half bandwidth of the frequency) can be obtained. ) And the passage loss greatly changes, so it is not an effective measure. Fourth, in the superheterodyne system, a local oscillation circuit that can produce the same intermediate frequency for all receivable frequencies is ideal, and the output frequency of the PLL circuit is 32.768 kHz × N ÷ R ( Where N is the frequency division number of the main counter provided on the oscillation unit side, and R is the frequency division number of the reference counter provided on the reference signal side). By increasing the values of N and R, the total reception frequency However, in this case, there is a problem that the lock time of the PLL circuit becomes longer and the stability of the output frequency is deteriorated. SUMMARY OF THE INVENTION An object of the present invention is to provide a multi-frequency radio timepiece receiver circuit using a superheterodyne system that solves such problems.

  In order to achieve this object, a radio clock receiver circuit according to the present invention is a radio clock receiver circuit that generates a demodulated signal from a long wave standard radio wave including time information received from an external antenna selected from a plurality of frequencies. A tuning frequency adjusting circuit having a tuning frequency adjusting capacitive element for switching the tuning capacity value of the antenna according to the frequency of the received long wave standard radio wave, and a tuning capacity value adjusted by the tuning frequency adjusting circuit. Therefore, an amplifier that amplifies the received radio signal and a reference frequency signal input from an external crystal oscillation circuit are multiplied, and a local signal is generated from the multiplied reference frequency signal by a DDS (Direct Digital Synthesizer) circuit. A local oscillation circuit, a radio signal amplified by the amplifier, and a local signal generated by the local oscillation circuit And a frequency conversion circuit that generates an intermediate frequency signal and a single frequency selection filter that removes noise other than a predetermined frequency using the intermediate frequency signal as an input signal, such as a crystal filter or a switched capacitor filter. It has an intermediate frequency circuit and a detection circuit that generates a demodulated signal including time information by detecting an output signal of the intermediate frequency circuit.

The operation of multiplying the reference frequency signal in the local oscillator circuit is VCO (Voltage Controlled).
The VCO includes a feedback resistor connected between input and output terminals, an even number of first inverter circuit strings connected in series in order from the input terminal side, and current control. It is preferable to have a possible second inverter circuit and a capacitive element connected between the input and output terminals of the first inverter circuit row.

  According to the radio clock receiver circuit according to the present invention, the local oscillation circuit is provided with the DDS circuit, so that the frequency of the local signal can be finely adjusted. And temperature characteristics can be compensated, and an intermediate frequency signal with a finely-tuned stable frequency can be obtained, so that the passband of the frequency selection filter is narrowed to greatly influence the noise on the received signal. There is an effect that it can be reduced.

1 is a block diagram showing a preferred embodiment of the present invention. The block diagram of a PLL circuit. The block diagram which shows the more concrete structure of VCO in a PLL circuit. The block diagram of a DDS circuit.

  DESCRIPTION OF EXEMPLARY EMBODIMENTS Hereinafter, a preferred embodiment of the invention will be described with reference to FIGS. As shown in FIG. 1, the radio clock receiving circuit includes an external antenna 1, a tuning frequency adjustment circuit 3 that is controlled by the control means 2 and tunes to the frequency of the radio signal received by the antenna 1, and this tuning circuit. An amplifier 4 for amplifying the output of the frequency adjusting circuit 3 and a reference frequency signal generated by the crystal oscillation circuit 5 and inputted from the outside are multiplied by a PLL circuit 6 and the control means is derived from the multiplied reference frequency signal by a DDS circuit 7. 2 generates a local frequency signal by synthesizing the local oscillation circuit 8 that generates the local signal having the frequency set in 2 and the radio signal amplified by the amplifier 4 and the local signal generated by the local oscillation circuit 8. The frequency conversion circuit 9 and an external one that is a frequency selection filter that removes noise other than a predetermined frequency using the intermediate frequency signal as an input signal An intermediate frequency circuit 11 having a crystal filter 10 and a detection circuit 12 for generating a demodulated signal containing time information by detecting an output signal of the intermediate frequency circuit 11.

  As shown in FIG. 1, the tuning frequency adjustment circuit 3 includes a switch element 32 connected to each of a plurality of capacitor elements 31 connected in parallel, and each switch element 32 is controlled to be turned on and off by the control means 2 to receive signals. The tuning capacity value of the antenna 1 is switched and adjusted so as to be tuned to the frequency of the long wave standard radio wave to be tuned. The received radio wave signal is amplified by the amplifier 4 and input to the frequency conversion circuit 9. The output of the local oscillation circuit 8 is also input to the frequency conversion circuit 9.

  The local oscillation circuit 8 receives the reference frequency signal of 32.768 kHz generated by the external crystal oscillation circuit 5 and multiplies the reference frequency signal by 16 and the 524 output from the PLL circuit 6. The DDS circuit 7 generates a local signal from an output signal of 288 kHz.

  As shown in FIG. 2, the PLL circuit 6 includes a phase comparison circuit 61 that compares phases of a reference frequency signal and an output signal of a frequency divider 65 that divides an oscillation signal of a VCO 64, which will be described in detail later, by 1/16. A charge pump circuit 62 that outputs a current corresponding to the output of the phase comparison circuit 61; a low-pass filter 63 that attenuates the high-frequency component of the output signal of the charge pump circuit 62 and outputs only the low-frequency component; The VCO 64 outputs an oscillation signal having a frequency corresponding to the voltage level of the output signal of the filter 63. With this configuration, the PLL circuit 6 multiplies the reference frequency signal having a frequency of 32.768 kHz by 16 to obtain an output signal having a frequency of 524.288 kHz.

  Here, the configuration of the VCO 64 will be described in more detail. The VCO 64 includes a control circuit 641 to which the output signal of the low pass filter 63 is input, and includes inverters 642, 643, and 644 connected in series in three stages. The two-stage inverters 642 and 643 on the input terminal side constitute a first inverter circuit row, and the last-stage inverter 644 constitutes a second inverter circuit. The output terminal of the final stage inverter 644 is connected to the input terminal of the first stage inverter 642 via a feedback resistor 645, and the input terminal of the first stage inverter 642 is grounded via a capacitive element 646. In addition, it is connected to the input terminal of the inverter 644 in the final stage through a capacitive element 647. The feedback resistor 645 and the capacitive element 647 constitute a time constant circuit. The control signal output from the control circuit 641 is input to the inverter 644 at the final stage to control the current flowing through the inverter 644, and mainly adjust the charge / discharge time to the capacitor 647 to change the output frequency. To do. With this configuration, the oscillation amplitude is increased (CMOS level), and phase noise can be reduced.

  As shown in FIG. 3, each of inverters 642, 643, 644 is composed of P channel MOS transistors P1, P2, P3 and N channel MOS transistors N1, N2, N3, respectively, and has the same configuration. The inverter 644 has a P-channel MOS transistor P3 which is connected to a P-channel MOS transistor P3 in order to apply a control voltage, which is a control signal output from the control circuit 641, to the P-channel MOS transistor P3 and the N-channel MOS transistor N3. P4 is connected, and an N-channel MOS transistor N4 is connected to the N-channel MOS transistor N3.

  As shown in FIG. 4, the DDS circuit 7 includes a phase accumulator (address calculator) 73 composed of an adder 71 and a latch 72, a SIN waveform memory 74 in which waveform data for a quarter period is written, a DA It consists of a converter 75 and a low-pass filter 76. The phase accumulator 73 accumulates the frequency set value M in synchronization with the reference clock, thereby generating a sawtooth wave having a speed proportional to the frequency set value M. Since the sawtooth wave data corresponds to the phase of the output waveform, it is used as the address of the SIN waveform memory 74 and the written waveform data is called to obtain the SIN waveform. The SIN waveform is converted into an analog signal by a DA converter 75, and a clock component is removed from the stepped output waveform by a low-pass filter 76, thereby obtaining a clean analog output. The frequency setting value M is set by inputting data to the control means 2.

Here, if the number of bits of the adder 71 is n, the oscillation frequency is
Oscillation frequency = frequency set value M x clock frequency ÷ 2 ⁿ
For example, if the clock frequency is 524.288 kHz and the number of bits of the adder 71 is 21, the clock frequency is divided by 2 ⁿ = 0.25 (Hz), and the frequency setting value M is set appropriately. The desired oscillation frequency with a frequency change step of 0.25 Hz can be output from the DDS circuit 7.

  Thus, according to the above-described embodiment, since the output frequency of the DDS circuit 7 can be changed in steps of 0.25 Hz, the initial deviation of the reference frequency of 32.768 kHz caused by the crystal resonator of the crystal oscillator 5 and Temperature characteristics can be compensated. Similarly, the initial deviation and temperature characteristics caused by the crystal resonator of the crystal filter 10 can also be compensated.

  Subsequently, the operation of the above-described embodiment will be described. First, the frequency of the standard radio wave to be received, for example, 40 kHz is designated by the control means 2, and the tuning frequency adjustment circuit 3 sets the tuning frequency of the antenna 1 to the designated frequency of 40 kHz by the control signal of the control means 2. In parallel with this, the control unit 2 sets a frequency setting value M, for example, 284000, and sends the frequency setting value 284000 from the control unit 2 to the DDS circuit 7 of the local oscillation circuit 8.

  The standard radio wave signal of 40 kHz received by the antenna 1 is sent from the tuning frequency adjustment circuit 3 to the amplifier 4 to be amplified and sent to the frequency conversion circuit 9. On the other hand, a reference signal having a frequency of 32.768 kHz from the crystal oscillation circuit 5 is sent to the DDS circuit 7 as a clock signal having a frequency of 524.288 kHz multiplied by 16 by the PLL circuit 6 of the local oscillation circuit 8.

  In the DDS circuit 7, the frequency accumulator 73 synchronizes with the clock signal and accumulates the frequency setting value 284000 set by the control means 2 to generate sawtooth data having a speed proportional to the frequency setting value 284000. SIN waveform data corresponding to the SIN waveform memory 74 is output using the generated data as an address. The SIN waveform data is analog-converted by the AD converter 75, the clock component is removed by the low-pass filter 76, and is sent to the frequency conversion circuit 9 as a clean analog local signal having a frequency of 71 kHz.

  The frequency conversion circuit 9 frequency-converts (mixes) the amplified standard radio signal and the local signal output from the local oscillation circuit 8 to generate an intermediate frequency signal having a frequency of 31 kHz, and the intermediate frequency circuit 11 generates the intermediate frequency signal. Is extracted and sent to the detection circuit 12. The detection circuit 12 detects the extracted intermediate frequency signal and generates and outputs a demodulated signal including time information. This demodulated signal is sent to a control unit (not shown) and converted into time information, and this time information is used to correct the time of the radio timepiece.

  The present invention is not limited to the above-described embodiment. For example, the configuration of the VCO 64 in the PLL circuit 6 is not limited to the above-described one, and the PLL circuit 6 may not be provided. That is, when the external crystal oscillation circuit 5 supplies a frequency signal sufficient for causing the DDS circuit 7 to perform a desired operation instead of the fundamental frequency of 32.768 kHz, the PLL circuit may be directly input to the DDS circuit. The circuit 6 becomes unnecessary. Further, the crystal filter 10 externally attached to the intermediate frequency circuit 11 can be replaced by incorporating an IC having a frequency selection function for removing noise other than a predetermined frequency, such as an SCF (switched capacitor filter). Furthermore, the frequency changing step at the output frequency of the DDS circuit 7 is not limited to 0.25 Hz, and can be set as appropriate depending on the clock frequency and the number of bits of the adder 71.

DESCRIPTION OF SYMBOLS 1 Antenna 2 Control means 3 Tuning frequency adjustment circuit 4 Amplifier 5 Crystal oscillation circuit 6 PLL circuit 7 DDS circuit 8 Local oscillation circuit 9 Frequency conversion circuit 10 Crystal filter 11 Intermediate frequency circuit 12 Detection circuit

Claims (2)

A radio clock receiving circuit that generates a demodulated signal from a long-wave standard radio wave including time information received by an external antenna selected from a plurality of frequencies, and tuning the antenna according to the frequency of the long-wave standard radio wave to be received A tuning frequency adjusting circuit having a tuning frequency adjusting capacitive element for switching a capacitance value, an amplifier for amplifying a radio signal received according to the tuning capacitance value adjusted by the tuning frequency adjusting circuit, and an external crystal by a DDS circuit An intermediate frequency signal is generated by combining a local oscillation circuit that generates a local signal based on a reference frequency signal input from an oscillation circuit, and a radio signal amplified by the amplifier and a local signal generated by the local oscillation circuit. And a frequency selection circuit for removing noise other than a predetermined frequency using the intermediate frequency signal as an input signal. An intermediate frequency circuit having a filter, radio clock receiver circuit, characterized in that it comprises a detection circuit for generating a demodulated signal containing time information by detecting an output signal of the intermediate frequency circuit. The local oscillation circuit includes a PLL circuit including a voltage controlled oscillator for multiplying the reference frequency signal, and the voltage controlled oscillator is connected in series in order from the input terminal side with a feedback resistor connected between the input and output terminals. An even-numbered first inverter circuit array and a second inverter circuit capable of current control, and a capacitive element connected between input and output terminals of the first inverter circuit array. Item 1. A radio timepiece receiver circuit according to Item 1.

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