JP2012010542A - Serial multiple inverter device and control method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a serial multiple inverter device capable of continuously supplying power to an AC load with the same output voltage as the voltage before a failure even when a short-circuit failure and the like occurred in at least one of a plurality of unit inverters.SOLUTION: The serial multiple inverter device receives DC power from a rectifier and a smoothing capacitor, forms a serially connected unit inverter group by serially connecting output sides of a plurality of unit inverters in which semiconductor switch elements are bridge-connected, controls opening and closing of the semiconductor switches, and connects a plurality of serially connected unit inverter groups to an AC load. When operation error detection means detects a unit inverter error, a bypass circuit short-circuits an output side of the unit inverter, and circuit protection means opens and protects the unit inverter. In addition, output voltage margin supply means makes up for deficient voltage and continues power supply.

Description

  The present invention relates to a series multiple inverter device for supplying a high voltage output obtained by connecting the output sides of a plurality of unit inverters in series to an AC load.

As a series multiple inverter device as a power converter, a configuration in which outputs of a plurality of unit inverters are connected in series to perform high voltage output is known. In such a serial multiple inverter device, when the unit inverter fails, the unit inverter is connected in series to the circuit, so that there is no current path and no current can flow. For this reason, when the unit inverter fails, the entire apparatus is stopped.
Moreover, as a method for avoiding the stop of the entire apparatus, there is Patent Document 1, and a bypass circuit that bypasses the output of a unit inverter is provided, and a current path is created by operating the bypass circuit when the unit inverter fails, The operation was continued even when the unit inverter failed.

JP 11-196578 A

  However, when the unit inverter has a short circuit failure or an open failure shown in Patent Document 1, the output of the unit inverter is short-circuited, the failed unit inverter is disconnected from the circuit, and the operation is continued. Since the output voltage of the unit inverter is lowered, there is a problem that the output voltage is insufficient and the operation in accordance with the output condition before the failure cannot be performed.

  Therefore, the present invention solves such problems, and the object of the present invention is to operate the remaining healthy unit inverters even if a failure occurs in at least one of the plurality of unit inverters. It is to provide a series multiple inverter device capable of continuing the operation of an AC load at the same output voltage as before the failure without stopping the operation.

In order to solve the above-described problems and achieve the object of the present invention, the present invention is configured as follows.
That is, a rectifier that converts AC power into DC power, and DC power that is the output of the rectifier is converted into AC power, and a plurality of unit inverters formed by bridge-connecting a plurality of semiconductor switch elements are provided, A unit inverter series connection group in which the input side of each unit inverter is connected in parallel to the output of the rectifier via a smoothing capacitor, the output side of each unit inverter is connected in series and connected to an AC load, and the unit inverter Unit inverter control means for giving an open / close control command in a predetermined order to the semiconductor switch elements constituting the unit, an operation abnormality detection means for detecting an operation abnormality state of the unit inverter, and the operation abnormality detection means is the unit When an abnormality in the inverter is detected, the unit corresponding to the corresponding unit inverter is opened to open the unit. Corresponding to circuit protection means for protecting the inverter, bypass switch connected in parallel to the unit inverter and forming a flow path for circulating load current when electrically closed, and corresponding unit inverter when the operation abnormality is detected The bypass switch control means for short-circuiting the output of the unit inverter by giving a closing command to the bypass switch, and the function of compensating for the output voltage that is insufficient when bypassing the unit inverter, Output voltage margin supply means provided in series.

  With this configuration, when the operation abnormality detecting means detects an abnormality of the unit inverter, the output side of the unit inverter is short-circuited by the bypass switch corresponding to the corresponding unit inverter, and at the same time, the unit inverter is protected. The unit inverter is opened by the circuit protection means to perform protection. At this time, the output voltage shortage caused by the bypass circuit short-circuiting the output of the unit inverter is compensated by the output voltage margin supply means, and the power supply equivalent to that before the failure to the AC load is continuously performed. .

  According to the present invention, even if a failure or the like occurs in at least one of the plurality of unit inverters, the operation of the AC load is performed with the same output voltage as before the failure without stopping the operation of the remaining healthy unit inverters. Can be provided.

It is a circuit diagram which shows the main structures of 1st Embodiment of the serial multiple inverter apparatus of this invention. The structure of the alternating current power contained in embodiment of this invention is shown, (a) is a figure which shows the structure of the secondary side coil | winding of a transformer output, (b) shows the voltage waveform of a three-phase alternating current. FIG. It is a circuit diagram which shows the structure of the 1st DC unit which consists of a rectifier, a capacitor | condenser, and unit inverter contained in embodiment of this invention. It is a figure which shows the functional operation | movement of the unit inverter contained in embodiment of this invention. It is a figure which shows the example of the output voltage operation | movement waveform of the unit inverter contained in embodiment of this invention. It is a figure which shows the output voltage operation waveform example of the phase voltage of the unit inverter serial connection group which is embodiment of this invention. It is a figure which shows the output voltage operation waveform example of the line voltage of the unit inverter serial connection group which is embodiment of this invention. It is a circuit diagram which shows the structure of the 2nd DC unit of the 1st Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the structure of the 2nd DC unit of the 2nd Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the structure of the 2nd DC unit of the 3rd Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the structure of the 2nd DC unit of the 4th Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the structure of the 2nd DC unit of the 5th Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the structure of the 2nd DC unit of the 6th Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the structure of the 2nd DC unit of the 7th Embodiment of this invention, and each main means relevant to it. It is a circuit diagram which shows the main structures of the 8th Embodiment of this invention. It is a figure which shows the structure of the circuit which generates the output voltage margin of the 9th Embodiment of this invention, and the output voltage waveform of a unit inverter. It is a circuit diagram which shows the main structures of the 9th Embodiment of this invention. It is a circuit diagram which shows the main structures of the 10th Embodiment of this invention. It is an output voltage vector diagram for demonstrating control of the 11th Embodiment of this invention. It is a control block diagram for demonstrating the control method of the 11th Embodiment of this invention. It is a circuit diagram which shows the main structures of the 12th Embodiment of this invention. It is a circuit diagram which shows the main structures of the 13th Embodiment of this invention. It is a circuit diagram which shows the main structures of the 14th Embodiment of this invention. It is a circuit diagram which shows the various connection methods of the circuit protection means of this invention. It is a figure which shows the element used for the circuit protection means of this invention. It is a circuit diagram which shows the 1st structure of the bypass switch of this invention. It is a circuit diagram which shows the 2nd structure of the bypass switch of this invention. It is a circuit diagram which shows the 3rd structure of the bypass switch of this invention. It is a circuit diagram which shows the 4th structure of the bypass switch of this invention. It is a circuit diagram which shows the 5th structure of the bypass switch of this invention.

  Embodiments of the present invention will now be described. The overall configuration of the embodiment and individual elements constituting the embodiment will be described.

(First embodiment)
FIG. 1 is a circuit diagram showing a main configuration of a first embodiment of a serial multiple inverter device of the present invention.
In FIG. 1, AC power 1 (1 ₁₁ to ₁ 1 _m ,..., 1 _n1 to 1 _nm ), rectifier 2 (2 ₁₁ to 2 _{1 m} ,..., 2 _n1 to 2 _nm ), smoothing capacitor 4 ( Output of unit inverter 5 (5 _{11 to} 51 _m ,..., 5 _{n1 to} 5 _nm ) for converting a DC voltage supplied through 4 ₁₁ to 41 _m ,..., 4 _n1 to 4 _nm to an AC voltage m pieces connected in series, the second unit inverter series group _{9 (9} 1 to 9 _n) configured to connect the second unit inverter series group _{9 (9} 1 to 9 _n) into n parallel The output terminal is connected to an AC load 7 to supply AC power. The output voltage margin supply means 8 is connected in series to the second unit inverter series connection group 9 (9 _{1 to} 9 _n ), and ensures a voltage that is insufficient when the inverter fails.
In FIG. 1, the output voltage margin supply means 8 is connected to the neutral point (NP) 901 side of the apparatus, but is connected to the AC load (ACLLoad) 7 side or between the series connection of the unit inverters 5. May be.

In addition, in the above, AC power 1 (1 ₁₁ to ₁ 1 _m ,..., 1 _n1 to 1 _nm ), rectifier 2 (2 ₁₁ to 2 _{1 m} ,..., 2 _n1 to 2 _nm ), smoothing capacitor 4 ( _{4 11 ~4 1m, ···, 4} n1 ~4 nm), unit inverters _{5 (5 11 ~5 1m, ···} , 5 n1 ~5 nm), the second unit inverter series group 9 ₍₉ 1 - 9 _n ), these may be simplified and expressed as AC power 1, rectifier 2, smoothing capacitor 4, unit inverter 5, and second unit inverter series connection group 9, respectively.
The second unit inverter series connection group 9 includes the AC power 1, the rectifier 2, and the smoothing capacitor 4 in addition to the unit inverter 5. However, the AC power 1, the rectifier 2, and the smoothing capacitor 4 are not included, and only the unit inverter 5 is focused, and, for example, m outputs of the unit inverter 5 are connected in series (5 ₁₁ +5 ₁₂ +... +5 _1m ) is referred to as a unit inverter series connection group, and is distinguished from the second unit inverter series connection group 9.

In order to describe the details of the operation and function of the main circuit of the series multiple inverter device of FIG. 1, the configuration, function, and operation of each circuit shown in FIG. 1 will be described first.
The components included in the second unit inverter series connection group 9 will be described in order.

<AC power>
A specific configuration of AC power 1 (FIG. 1) is shown in FIG.
FIG. 2A shows the configuration of the secondary side of the three-phase AC transformer 1. The transformer secondary winding 104, 105, 106 of the transformer 1 is a three-phase alternating current of a combination of the transformer output terminals (u) 101, (v) 102, (w) 103 to (u, v, w). Is output.
Although the primary side of the transformer 1 is not shown in FIG. 2A, the AC power 1 (1 ₁₁ to ₁ 1 _m , 1 _n1 to 1 _nm ) is shown in FIG. It is written. In addition, although Fig.2 (a) showed the case where the structure of a transformer was (DELTA) connection (delta connection), it may be a Y connection (star connection). Even when transformers having the same Δ connection configuration are used, there may be combinations in which the phases of the three phases are different between the AC powers 1 (1 ₁₁ to ₁ 1 _m , 1 _n1 to 1 _nm ).

  FIG. 2B shows a well-known three-phase AC voltage waveform. The voltage of each phase is a sinusoidal alternating current, and each of the three phases (phase 1, phase 2, and phase 3) is configured by a combination having a phase difference of 120 degrees. In addition, each phase which consists of said 3 phase respond | corresponds to the three-phase alternating current of the combination of (u, v, w) in Fig.2 (a).

<First DC unit, part 1>
FIG. 3 is a circuit diagram showing a configuration of a first DC unit 500 including the rectifier 2, the smoothing capacitor 4 and the unit inverter 5. The circuit of the first DC unit 500 shown in FIG. 3 is shown for explaining the basic operation of the second unit inverter series connection group 9 or the serial multiple inverter device of the present embodiment. The circuit protection means 3 (FIG. 1) and the bypass switch 6 (FIG. 1) to be described later are excluded from the second unit inverter series connection group 9 of FIG.
Below, the diode rectifier 401, the smoothing capacitor 4, and the unit inverter 5 which are the main components of the first DC unit 500 will be described in order.

<Rectifier and smoothing capacitor>
The rectifier 2 includes diodes 211, 212, 221, 222, 231, and 232. The cathode of the diode 211 is connected to the positive terminal 501, and the anode is connected to the cathode of the diode 212. The anode of the diode 212 is connected to the negative terminal 502. Further, one phase of three-phase alternating current is input from the first direct current unit terminal (u) 111 to the connection point between the anode of the diode 211 and the cathode of the diode 212. If the voltage of the sine wave input to the connection point between the anode of the diode 211 and the cathode of the diode 212 is positive, the voltage reaches the positive terminal 501 through the diode 211. If it is negative, it passes through the diode 212 and reaches the negative terminal 502.
From the above, the input for one phase of the three-phase alternating current from the first direct current unit terminal (u) 111 is full-wave rectified by the diode 211 and the diode 212 and reaches the positive terminal 501 and the negative terminal 502, and the smoothing capacitor (C) 4 is accumulated and smoothed.

The cathode of the diode 221 is connected to the positive terminal 501, and the anode is connected to the cathode of the diode 222. The anode of the diode 222 is connected to the negative terminal 502. Further, one phase of three-phase alternating current is input from the first direct current unit terminal (v) 112 to the connection point between the anode of the diode 221 and the cathode of the diode 222. If the voltage of the sine wave input to the connection point between the anode of the diode 221 and the cathode of the diode 222 is positive, the voltage passes through the diode 221 and reaches the positive terminal 501. If it is negative, it passes through the diode 222 and reaches the negative terminal 502.
From the above, the input for one phase of the three-phase alternating current from the first DC unit terminal (v) 112 is full-wave rectified by the diode 221 and the diode 222 and reaches the positive terminal 501 and the negative terminal 502, and the smoothing capacitor (C). 4 is accumulated and smoothed.

  The cathode of the diode 231 is connected to the positive terminal 501, and the anode is connected to the cathode of the diode 232. The anode of the diode 232 is connected to the negative terminal 502. Further, one phase of three-phase alternating current is input from the first direct current unit terminal (w) 113 to the connection point between the anode of the diode 231 and the cathode of the diode 232. If the voltage of the sine wave input to the connection point between the anode of the diode 231 and the cathode of the diode 232 is positive, it passes through the diode 231 and reaches the positive terminal 501. If it is negative, it passes through the diode 232 and reaches the negative terminal 502. From the above, the input for one phase of the three-phase AC from the first DC unit terminal (w) 103 is full-wave rectified by the diode 231 and the diode 232 and reaches the positive terminal 501 and the negative terminal 502, and the smoothing capacitor (C) 4 is accumulated and smoothed.

Since the rectifier 2 is input with each phase having different three-phase AC phases from the first DC unit terminals (u) 111, (v) 112, and (w) 113, it is further averaged, and the positive terminal 501 and the negative terminal The smoothing capacitor 4 connected between the terminals 502 accumulates more smoothed DC power (voltage Vdc).
Note that the transformer output terminals (u) 101, (v) 102, and (w) 103 of the transformer 1 in FIG. 2A are respectively the first DC unit terminals (u) 111 and (v) 112 in FIG. , (W) 113.

<Configuration of unit inverter>
In FIG. 3, the unit inverter 5 includes insulated gate bipolar transistors (IGBTs: hereinafter abbreviated as IGBTs) 511 to 514 serving as semiconductor switching elements.
IGBT (S1) 511 has a collector connected to positive terminal 501 and an emitter connected to unit inverter output terminal (a) 503. The IGBT (S3) 513 has an emitter connected to the negative terminal 502 and a collector connected to the unit inverter output terminal (a) 503. IGBT (S2) 512 has a collector connected to positive terminal 501 and an emitter connected to unit inverter output terminal (b) 504. The IGBT (S4) 514 has an emitter connected to the negative terminal 502 and a collector connected to the unit inverter output terminal (b) 504. The control signals of the unit inverter control means 10 (FIG. 8) are connected to the input terminals (gate terminals) of the IGBTs 511 to 514, respectively.
The configuration of the above semiconductor switch elements (IGBT 511 to IGBT 514) is referred to as bridge connection.

At this time, when the ON (ON) and OFF (OFF) control of the IGBTs (S1, S3, S2, S4) is performed as shown in FIG. 4, the unit inverter output terminal (a) 503 and the unit inverter output terminal (B) Between +504, + Vdc, 0, -Vdc can be generated intentionally. The unit inverter control means 10 (FIG. 8) collectively controls the IGBTs (S1, S3, S2, S4) to be turned on (ON) and off (OFF).
The semiconductor switch element is not necessarily composed of an IGBT, but the IGBT is relatively excellent in insulation and pressure resistance, and is used as the unit inverter 5 (FIG. 3) or the second unit inverter series connection group 9 (FIG. 1). ), Or as a series multiple inverter device of this embodiment, it is easy to obtain a high voltage.

<Example of output waveform of unit inverter>
FIG. 5 shows output voltages according to respective periods when the output between the unit inverter output terminal (a) 503 and the unit inverter output terminal (b) 504 of the unit inverter 5 (FIG. 3) is generated between 0 and + Vdc. It is a figure which shows the difference. The vertical axis represents voltage and the horizontal axis represents time.
FIG. 5A shows the output voltage waveform when the generation period of 0 and + Vdc is equal, and shows the output voltage waveform when the generation period of + Vdc is longer than the generation period of 0. This is shown in FIG. As the absolute value of the output voltage, only 0 and + Vdc are output, but the average value of the output voltage is higher in FIG. 5B.
Therefore, the control of the unit inverter 5 (FIG. 3) by the unit inverter control means 10 (FIG. 8) can be controlled not only simply on (ON) and off (OFF) but also on (ON) and off (OFF) periods. For example, when the voltage value is set as the average value of the output voltage, the degree of freedom of selection is further increased.

<First DC unit, part 2>
Since the rectifier 2, the smoothing capacitor 4, and the unit inverter 5 have been described as elements constituting the first DC unit 500 in FIG. 3, the operation as the first DC unit 500 will be described.
In FIG. 3, three-phase alternating current is input from the first direct current unit input terminals (u) 111, (v) 112, and (w) 113. The input three-phase alternating current is input to the rectifier 2 including a plurality of diodes. The rectifier 2 performs full-wave rectification on the input three-phase alternating current, and converts the alternating current into direct current (average voltage is Vdc). The output of the rectifier 2 is supplied to the unit inverter 5 through the smoothing capacitor (C) 4, and the unit inverter control means supplies DC voltages of + Vdc, 0, and −Vdc between the unit inverter output terminals (a) 503 and (b) 504. 10 (FIG. 8) according to the control status.

<Configuration of unit inverter series connection group>
In order to increase the output voltage or increase the number of types of output voltage, a plurality of first DC units 500 (FIG. 3) in which the outputs of the unit inverters 5 are connected in series are unit inverter series connection groups (5 ₁₁ +5 ₁₂ + ... + 5 _{1 m} ) (FIG. 1).
Further, since the first DC unit 500 (FIG. 3) is further provided with the circuit protection means 3, the bypass switch 6, and the AC power 1, the second DC unit 600 (FIG. 15) is configured.
In FIG. 1, the second unit inverter series connection group 9 includes the unit inverter output terminals (a) and (b) of the unit inverter 5 (FIG. 3) in the second DC unit 600 (FIG. 15) continuously connected in series. Connected and configured. With this configuration, from the output terminal of the second unit inverter series connection group 9, it is possible to synthesize and output a higher voltage or various voltages.

Since the second unit inverter series connection group 9 is configured by connecting the second DC units 600 (FIG. 15) continuously in series, the “DC unit series connection group” or the “second DC unit series connection group”. However, since the unit inverter 5 directly synthesizes the output voltage and directly outputs the output voltage, it is referred to as a “second unit inverter series connection group”.
Further, as described above, focusing on only the unit inverter 5 excluding the AC power 1, the rectifier 2, the circuit protection means 3, the smoothing capacitor 4, and the bypass switch 6 from the second unit inverter series connection group 9, the unit inverter 5 is also expressed as a unit inverter series connection group (5 ₁₁ +5 ₁₂ +... +5 _{1 m} ,..., 5 _n1 +5 _n2 +... +5 _nm ) (FIG. 1). .

Further, the unit inverter 5 (FIG. 3) of one first DC unit 500 (FIG. 3) is provided with one unit inverter control means 10 (FIG. 8), and the opening / closing thereof is controlled. Therefore, as shown in FIG. 1, as the second unit inverter series connection group 9, there are a plurality of second DC units 600 (FIG. 15), and a plurality of second unit inverter series connection groups (9 _{1 to} 9 _n ). There are a large number of unit inverter control means 10 (FIG. 8). In order to operate these many unit inverter control means 10 (FIG. 8) included in the circuit of FIG. 1 in cooperation with each other, there is a general inverter control means (not shown) that controls them.

<Example of output voltage waveform of unit inverter series connection group>
FIG. 6 shows an example of an output waveform in the case where the number m of series stages is 3 in the second unit inverter series connection group 9 (FIG. 1). The vertical axis represents voltage and the horizontal axis represents time.
FIG. 6 shows that the voltage waveform of the second unit inverter series connection group 9 ₁ phase is generated between +2 Vdc and +3 Vdc. In this case, the output voltage of two unit inverters of three unit inverters connected in series is + Vdc, and the other one is changed between 0 and + Vdc.

Also, stepped waveforms (not shown) of 0, + Vdc, + 2Vdc, + 3Vdc, and negative voltages thereof can be generated.
The control for generating these voltages is performed by the unit inverter control means 10 (FIG. 8).
Further, from the second unit inverter series group 9, not only the second unit inverter series group 9 ₁ 9 ₁ phase is output by, the output of the second unit inverter series group 9 ₂ 9 ₂ phase, The same control can be applied to the 9 _n phase output from the second unit inverter series connection group 9 _n to generate a stepped waveform.

FIG. 7 shows unit inverter series connection groups (5 ₁₁ +5 ₁₂ +... +5 _1m ) when the number of stages of unit inverter 5 (or second DC unit 600 (FIG. 15)) is further increased from three. ) Shows an example of an output voltage waveform. As described above, the output of the unit inverter 5 can be selected from + Vdc, 0, and −Vdc. In the second unit inverter series connection group 9, the number of series stages of the unit inverter 5 can be configured to exceed three, and the unit When the output period of the inverter 5 is controlled by the unit inverter control means 10 (FIG. 8), the average value as shown in FIG. 7A is close to a curve, and the maximum value generates a high voltage voltage waveform. Can do.

Incidentally, whereas the output voltage waveform of the single-phase in FIG. 7 (a) _{9 1} phase to 9 _n-phase, FIG. 7 (b) example _{9 1-phase} and phase line voltage between _{9 2} phases It shows an example. Considering not only the phase voltage but also the line voltage, the degree of freedom is high, so that the step size is further reduced, and a voltage waveform more approximate to a sine wave can be formed.

<Three-phase output and motor load>
In FIG. 1, when the AC load (ACLLoad) 7 is a three-phase AC motor, n sets of second unit inverter series connection groups 9 _n include three sets of second unit inverter series connection groups of n = 3. 9 ₁ consists second unit inverter series group 9 _3, and the output voltage 3-phase (u, v, w) is ultimately desired is AC.
If the unit inverter control means 10 (FIG. 8) or the overall inverter control means (not shown) changes the frequency for opening and closing the semiconductor switch elements (S1 to S4) of the unit inverter, a more approximate three-phase AC waveform can be obtained. The frequency as three-phase alternating current can also be changed.

Even if the number of stages of the unit inverter 5 (or the second DC unit 600 (FIG. 15)) is increased, the step of the voltage waveform is not completely eliminated, but when the load is an electric motor, the winding ( The inductance of the coil) is large and the current changes smoothly, so the rotation of the motor is not affected by the step of the voltage waveform.
Further, as will be described later, an AC reactor (coil) is connected in series between the inverter and the load to smooth the voltage / current waveform.

Further, in FIG. 1, the first DC unit 500 in the second unit inverter series group _{9 1} (FIG. 3) of the rectifier ₍₂ 11 _{to 2 1 m)} is the AC power ₍₁ 11 _{to 1 1 m),} respectively separately 3 Receiving phase AC power. Even if this is the same three-phase AC, if the wiring is simply divided and connected to a plurality of first DC units 500 (FIG. 3) from the same AC power, unit inverter 5 (or first DC unit 500) is connected in series. This is because a high voltage cannot always be generated. Therefore, it is necessary to use another AC power (1 ₁₁ to _{1 1m} ) that is isolated at least in the DC direction for each first DC unit 500, that is, each rectifier (2 ₁₁ to 2 _1m ) in FIG. There is.

<Output voltage abnormality detection and compensation>
FIG. 8 is a partial circuit block diagram showing only the following related elements for explaining the first embodiment of the present invention.
8 mainly shows a circuit related to one unit inverter 5 in the second unit inverter series connection group 9 of FIG. The AC power 1, the rectifier 2, the circuit protection means 3, the smoothing capacitor 4, the unit inverter 5, and the bypass switch 6 constitute a second DC unit 600 (FIG. 15).
The AC power 1, the rectifier 2, and the smoothing capacitor 4 are as described above.
The basic operations of the unit inverter 5 and the unit inverter control means 10 have been described. However, the operation at the time of abnormality according to the present embodiment will be described below.
The circuit protection means 3, the bypass switch 6, the output voltage margin supply means 8, the operation abnormality detection means 11, and the bypass switch control means 12 will be described later.

In FIG. 8, when the unit inverter 5 is in a state in which it can operate normally, the unit inverter control means 10 controls the semiconductor switch elements S1 to S4 of the unit inverter 5 to open / close (OFF, ON) so that an appropriate output voltage is obtained. Is supplied. Then, when all of the plurality of unit inverters 5 in FIG. 1 are in a normally operable state, AC power is supplied to the AC load 7.
In this case, since each unit inverter 5 is normal, an abnormality detection signal is not output from the operation abnormality detection means 11, and therefore no closing command is given to the bypass switch 6 from the bypass switch control means 12. For this reason, the bypass switch 6 remains in an OFF state.

The operation abnormality detecting means 11 detects an AC output side voltage / current abnormality, a DC input side voltage drop, or the like when a short circuit failure or the like occurs in each unit inverter 5. Then, the operation abnormality detection means 11 outputs an operation abnormality detection signal to the bypass switch control means 12.
By this operation abnormality detection signal, the bypass switch control means 12 outputs a closing command to the bypass switch 6.
The bypass switch 6 is turned on (ON), and the current flowing through the semiconductor switch elements S1 to S4 to the AC load 7 flows through the bypass switch.

The operation abnormality detection signal is also output to the circuit protection means 3 and the output voltage margin supply means 8.
The circuit protection means 3 prevents the damaged unit inverter 5 and the AC power 1 from being damaged by opening the power supply side circuit by the operation abnormality detection signal.
The output voltage margin supply means 8 outputs, instead of the failed unit inverter 5, the output voltage that is insufficient due to the failure of the unit inverter 5 by detecting the operation abnormality detection signal.
As a result, the AC load 7 (FIG. 1) can be operated with the same output voltage as before the failure by the sound unit inverter 5 in which no failure occurs and the AC voltage supplied from the output voltage margin supply means 8. Can continue.
The specific configuration and operation of the output voltage margin supply means 8 will be described later.

(Second embodiment, fuse)
FIG. 9 is a partial circuit diagram showing only the following related elements for explaining the second embodiment of the present invention.
FIG. 9 has the same configuration as the circuit of FIG. 8 except for signals related to the fuse 13. Therefore, description of the same configuration and operation as in FIG. 8 is omitted as appropriate.
In FIG. 9, when an abnormality occurs in the circuit of the second DC unit 600 (FIG. 15) including the unit inverter 5 and an overcurrent flows, the fuse 13 is blown or cut off to protect the circuit.

In FIG. 9, the circuit protection means 3 and the fuse 13 are separated, but the fuse 13 may also serve as the circuit protection means 3. Further, in FIG. 9, the circuit protection means 3 and the fuse 13 are connected between the rectifier 2 and the smoothing capacitor 4, but may be between the smoothing capacitor 4 and the unit inverter 5.
In addition, due to the operating contact that operates in conjunction with the fusing of the fuse 13, the fusing becomes an electric signal, and the operation abnormality detecting means 11 detects the operation abnormality. The bypass switch 6 is closed due to the operation abnormality detection as in FIG.

(Third embodiment, level determination <1>)
FIG. 10 is a partial circuit diagram showing only the following related elements for explaining the third embodiment of the present invention.
FIG. 10 has the same configuration as the circuit of FIG. 8 except for the voltage detection means 14, the level determination means 15, and signals related thereto. Therefore, description of the same configuration and operation as in FIG. 8 is omitted as appropriate.
In FIG. 10, the voltage detection means 14 is provided at both ends of the output terminals (positive terminal 501 and negative terminal 502 (FIG. 3)) of the rectifier 2. Further, a level determination unit 15 is connected so as to determine the signal of the voltage detection unit 14.

  With this configuration, the DC voltage applied to the unit inverter 5 is detected by the voltage detection means 14, and the level determination means 15 indicates that the detected value by the voltage detection means 14 has become an overvoltage or undervoltage with respect to the reference value. Hold it and detect it. The level determination means 15 sends the detection signal to the operation abnormality detection means 11. The operation abnormality detection means 11 sends an operation abnormality detection signal to the bypass switch control means 12, and the bypass switch 6 is closed.

(Fourth embodiment, level determination <2>)
FIG. 11 is a partial circuit diagram showing only the following related elements for explaining the fourth embodiment of the present invention.
FIG. 11 has the same configuration as the circuit of FIG. 8 except for the current detection means 16, the level determination means 17, and signals related thereto. Therefore, description of the same configuration and operation as in FIG. 8 is omitted as appropriate.
In FIG. 11, the current detection means 16 is provided between the output terminal (positive terminal 501 (FIG. 3)) of the rectifier 2 and the circuit protection means 3. Further, a level determination means 17 is connected so as to determine the signal of the current detection means 16.

  With this configuration, the level determination means 17 detects the current flowing through the rectifier 2 or the smoothing capacitor 4 by the current detection means 16, and detects an abnormality of the unit inverter 5 when the detected voltage exceeds a predetermined range with respect to the reference value. To do. The level determination means 17 sends a signal of the detection signal to the operation abnormality detection means 11. The operation abnormality detection means 11 sends an operation abnormality detection signal to the bypass switch control means 12, and the bypass switch 6 is closed.

(Fifth embodiment, level determination <3>)
FIG. 12 is a partial circuit diagram showing only the following related elements for explaining the fifth embodiment of the present invention.
FIG. 12 has the same configuration as the circuit of FIG. 8 except for the voltage detection means 18 and the level determination means 19 and signals related thereto. Therefore, description of the same configuration and operation as in FIG. 8 is omitted as appropriate.
In FIG. 12, the voltage detection means 18 is provided between the output terminals ((a) 503, (b) 504 (FIG. 3)) of the unit inverter 5. Further, a level determination means 19 is connected so as to determine the signal of the voltage detection means 18.

  With this configuration, the level determination means 19 detects the output AC voltage of the unit inverter 5 by the voltage detection means 18, detects the voltage output by the unit inverter 5 by the voltage detection means 18, and the level determination means 19 detects the voltage detection. When the detected value by the means 18 exceeds a predetermined range with respect to the reference value, an abnormality of the unit inverter 5 is detected. The level determining means 19 sends a signal to the operation abnormality detecting means 11. The operation abnormality detection means 11 sends an operation abnormality detection signal to the bypass switch control means 12, and the bypass switch 6 is closed.

(Sixth embodiment, level determination <4>)
FIG. 13 is a partial circuit diagram showing only the following related elements for explaining the sixth embodiment of the present invention.
FIG. 13 has the same configuration as the circuit of FIG. 8 except for the voltage detection means 20, the level determination means 21, and signals related thereto. Therefore, description of the same configuration and operation as in FIG. 8 is omitted as appropriate.
In FIG. 13, the voltage detection means 20 is provided between the input AC voltages of the rectifier 2. Further, a level determination unit 21 is connected so as to determine the signal of the voltage detection unit 20.

  With this configuration, the input AC voltage of the rectifier 2 is detected by the voltage detection means 20, and the level determination means 21 has that the value detected by the voltage detection means 20 has become an overvoltage or undervoltage with respect to the reference value. To detect. The level determination means 21 sends the detection signal to the operation abnormality detection means 11. The operation abnormality detection means 11 sends an operation abnormality detection signal to the bypass switch control means 12, and the bypass switch 6 is closed.

(Seventh embodiment, level determination <5>)
FIG. 14 is a partial circuit diagram showing only the following related elements for explaining the seventh embodiment of the present invention.
FIG. 14 has the same configuration as the circuit of FIG. 8 except for the output detectors 22 to 25, the voltage detection means 26, and signals related thereto. Therefore, description of the same configuration and operation as in FIG. 8 is omitted as appropriate.
In FIG. 14, output detectors 22 to 25 are provided between the emitters and gates of the semiconductor switch elements S <b> 1 to S <b> 4 of the unit inverter 5. The voltage detection means 26 is provided between the output terminals ((a) 503, (b) 504 (FIG. 3)) of the unit inverter. Further, the output detectors 22 to 25 and the voltage detection means 20 are connected to send signals to the operation abnormality detection means 11.

  In this configuration, the voltage waveform detected by the output detectors 22 to 25 of the unit inverter control means 10 is input to the operation abnormality detection means 11, and the voltage waveform and the reference voltage waveform, or the unit detected by the voltage detection means 26. By comparing with the output AC voltage waveform of the inverter 5, an abnormality due to an external factor is determined. The operation abnormality detection means 11 sends an operation abnormality detection signal to the bypass switch control means 12, and the bypass switch 6 is closed.

(Eighth embodiment, output voltage margin supply means <1>)
FIG. 15 is a circuit diagram showing a main configuration of the eighth embodiment.
As the output voltage margin supply means 8 (FIGS. 1 and 8), the second DC unit 600 including the unit inverter 5 that generates the output voltage margin is connected to each second unit inverter series connection group 9.
In FIG. 15, the output voltage margin supply means 8 includes a second DC unit 600 ₁₀ (AC power 1 ₁₀ + rectifier 2 ₁₀ + circuit protection means 3 ₁₀ + smoothing capacitor 4 ₁₀ + unit inverter 5 ₁₀ + bypass switch 6 ₁₀ ). The second DC unit 600 _n0 (AC power 1 _n0 + rectifier 2 _n0 + circuit protection means 3 _n0 + smoothing capacitor 4 _n0 + unit inverter 5 _n0 + bypass switch 6 _n0 ) is a second unit inverter series connection group 9 (9 ₁ to 9 9 _n ).

In Figure 15, the second DC unit 600 which is an output voltage margin supply means only shows two second DC unit 600 ₁₀ and the second DC unit 600 _n0, a three or more plural It is also possible to provide n total numbers.

  Further, in FIG. 15, the second DC unit 600 serving as the output voltage margin supply means is connected to only one stage in the series direction with respect to each second unit inverter series connection group 9. , May be connected. At this time, the output voltage margin becomes a large value according to the number of stages, and the range of voltage adjustment is expanded.

15, in the normal case, the unit inverter 5 (5 ₁₀ , 5 _n0 ) of the output voltage margin supply means 8 outputs a zero voltage (see FIG. 4) or the bypass switch 6 (6 ₁₀ , 6 _n0 ). Turn on and keep bypassing.
Further, there is a second unit inverter series group _{9 (9} 1 ~9 _n) unit inverters 5 in case of failure at _{(5 11} to 5 _{1 m,} · · ·, either _{5 n1} to 5 _nm) is An operation abnormality detection signal is transmitted from the operation abnormality detection means 11 shown in FIG. 8 to the bypass switch control means 12 and the output voltage margin supply means 8.

Upon receipt of the operation abnormality detection signal, the bypass switch control means 12 bypasses the bypass switch 6 (6 ₁₁ to 5 _{1m to} 5 _{n1 to} 5 _nm ) corresponding to the unit inverter 5 (5 _{11 to} 51 _m ,. 6 _1m ,..., 6 _{n1 to} 6 _nm ) are turned on (ON) and bypassed.

In response to the operation abnormality detection signal, the output voltage margin supply means 8 includes a second unit inverter series connection group including unit inverters 5 (any of 5 _{11 to} 51 _m ,..., 5 _{n1 to} 5 _nm ) in which a failure has occurred. The unit inverter 5 (5 ₁₀ , 5 _n0 ) of the output voltage margin supply means 8 corresponding to 9 (9 _{1 to} 9 _n ) is operated to cause the unit inverter 5 (5 _{11 to} 51 _m ,... By generating a predetermined output voltage instead of any one of 5 _{n1 to} 5 _nm , the operation of the AC load is continued at the same output voltage as before the failure.
When the unit inverter 5 (5 ₁₀ , 5 _n0 ) of the output voltage margin supply means 8 is operated, the corresponding bypass switch 6 (6 ₁₀ , 6 _n0 ) is turned off.

(Ninth embodiment, output voltage margin supply means <2>)
The ninth embodiment of the present invention will be described with reference to FIGS.
FIG. 16 shows the configuration of the circuit for generating the output voltage margin of the ninth embodiment, the output voltage margin, and the waveform of each output voltage indicating the relationship between the unit inverter rated output voltage and the load rated output voltage. Yes.
In the ninth embodiment of FIG. 16, as the output voltage margin supply means 8 shown in FIG. 1, the rated output voltage of each unit inverter 5 is made larger than the load rated output voltage, and the voltage for the rated output operation of the load is set. There is a margin.

That is, in the ninth embodiment, the extra second DC unit 600 ₁₀ (AC power 1 ₁₀ + rectifier 2 ₁₀ + circuit protection means 3 shown in FIG. 15 is used as the output voltage margin supply means 8 shown in FIG. ₁₀ + smoothing capacitor 4 ₁₀ + unit inverter 5 ₁₀ + bypass switch 6 ₁₀ ) or 600 _n0 , instead of providing unit inverter 5 (5 _{11 to} 51 _m ,..., 5 _{n1 to} 5 _nm ) of FIG. Control is performed to adjust individual output voltages to compensate for the voltage drop at the time of failure.

This is illustrated in FIG. 17, which is a circuit diagram showing a main configuration of the ninth embodiment.
When a failure occurs in the unit inverter 5 in a certain second unit inverter series connection group 9, an operation abnormality detection signal is transmitted from the operation abnormality detection means 11 shown in FIG. 8 to the unit inverter control means, and the output voltage By using the margin supply means 8 to increase the output voltage from each unit inverter 5 that has not failed, the output voltage that becomes insufficient due to the failure is compensated, and the operation of the AC load is continued with the same output voltage as before the failure. To do.

17, in the second unit inverter series connection groups (9 ₁ +8 ₁ ), (9 ₂ +8 ₂ ),..., (9 _n +8 _n ), (9 ₁ ), (9 ₂ ),. , (9 _n ) means a circuit for generating an output of the second unit inverter series connection group 9 and control corresponding to the normal state, and (8 ₁ ), (8 ₂ ) _,. ) Means a circuit corresponding to the circuit and control to be generated when the unit inverter 5 fails.
In this case, the maximum output voltage is originally larger than the load rated output voltage in the normal case, and the voltage adjusted as a margin is used when a failure occurs. This method will be described below.

  In FIG. 5, the unit inverter 5 outputs two values of 0 and + Vdc in both FIGS. 5 (a) and 5 (b). In FIG. 5A, the time (period) during which 0 and + Vdc are output is the same, so the average output voltage is approximately + (0.5) Vdc. On the other hand, in FIG. 5B, the period during which + Vdc is output is longer than 0 (approximately 6 times), and the average output voltage is approximately + (0.85) Vdc. Therefore, although the unit inverter 5 has a binary output of 0 and + Vdc, the average output voltage can be adjusted by controlling the on / off of the unit inverter 5.

This method is used in the ninth embodiment shown in FIG. Normally, as described above, a method of suppressing the ON (ON) and OFF (OFF) control of the unit inverter 5 so that the output voltage has a margin is set to the load rated output voltage. The control method of the other unit inverter 5 is changed so as to compensate for the voltage of the failed unit inverter 5.
The control of the unit inverter 5 is not performed solely by the individual unit inverter control means 10, but the overall inverter control means (not shown) that controls the plurality of unit inverters 5 in an integrated manner and the operation abnormality detection means 11 are linked. To do.

(Tenth embodiment, output voltage margin supply means <3>)
FIG. 18 is a diagram illustrating the tenth embodiment. As the output voltage margin supply means 8 in the eighth embodiment, an extra unit inverter 5 is connected to all the second unit inverter series connection groups 9. Since this is a limited circuit in the eighth embodiment, detailed description thereof is omitted.

(Eleventh embodiment, output voltage margin supply means <4>)
19 and 20 are diagrams for explaining an eleventh embodiment of the present invention, and are a vector diagram of output voltages and a control block diagram when performing control, respectively.
FIG. 19 is a vector diagram of the output voltage when supplying a three-phase alternating current in the main circuit as shown in FIG. When a unit inverter breaks down in a certain phase, the output phase voltage is lowered from before the failure due to the bypass, and if it is left as it is, an output line voltage equivalent to that before the failure cannot be secured. Therefore, in the other phases, by increasing the phase voltage in the opposite direction to the voltage that is insufficient in the failure phase by the output voltage margin, it is possible to maintain the same output line voltage after the failure as before the failure.

As described above with reference to FIG. 7, there are a method in which the output voltage is controlled only in a single phase, and a method in which a voltage between lines between phases is used. This indicates that the second unit inverter series connection group 9 (9 _{1 to} 9 _n ) can be controlled even between lines in addition to the method of controlling the output voltage independently in the second unit inverter series connection group 9. .

FIG. 20 is a control block diagram illustrating an example when the above control is performed.
In FIG. 20, the voltage limit means 81V _{1 to} 81V _n have a function of suppressing the voltage command values V _{1 to} V _n before control to a prescribed maximum voltage value that can be output. In phase was bypassed in the event of a fault, because the maximum voltage value that can be output than at the normal time decreases, the voltage limit means _81V 1 _{~81V n} receives failure information from the abnormal operation detecting means _11V 1 _{~11V n,} it appropriately outputs It has the role of changing the maximum voltage value. The voltage command values V _{1 to} V _n in the voltage limit means 81 V _{1 to} 81 V _n are the ratios at which 0 or + Vdc of the unit inverter 5 (FIG. 8) is output as described above with reference to FIG. (a), (b) as described above with reference to the second unit inverter series group 9 collaboration and the unit inverter 5 (FIG. 8) in (FIG. 1), the second unit inverter series group 9 (9 ₁ ˜9 _n ) (FIG. 1) is adjusted by cooperation in the mutual line voltage. This adjustment is performed by the control of the unit inverter control means 10 (FIG. 8) and the overall inverter control means (not shown).

Therefore, when there is no failure, the voltage command values V _{1 to} V _n have a relatively large margin and are lower than the specified maximum voltage value. The voltage limit means 81V _{1 to} 81V _n suppress the voltage command values V _{1 to} V _n before the control to the specified maximum voltage value that can be output. Voltage command value _V 1 ~V _n If there is no fault and the becomes lower than the output voltage of the voltage limit means _81V 1 _{~81V n} voltage.
The output of the voltage limit means _81V 1 _{~81V n,} the voltage command value _V 1 ~V _n are both input to respective comparing means _82V 1 _{~82V n.} Comparing means _82V 1 _{~82V n} sends the comparison result to the aggregator 83V _s. Tallying unit 83V _s sums the comparison result sent from the comparator means _82V 1 _{~82V n.}

Each A terminal of the output voltage regulator _84V 1 _{~84V n,} the output voltage of the voltage limit means _81V 1 _{~81V n} respectively input.
Each B terminals of the output voltage regulator _84V 1 _{~84V n,} the output voltage of the aggregator 83V _s inputs.
Voltage command values V _{1 to} V _n are respectively input to the C terminals of the output voltage adjusting means 84V _{1 to} 84V _n .

In the output voltage adjusting means 84V _{1 to} 84V _n , the input voltage at the A terminal and the input voltage at the C terminal are compared, and if A = C, the input voltage at the A terminal is subtracted from the input voltage at the A terminal. , Respectively, as output voltages of the output voltage adjusting means 84V _{1 to} 84V _n .
If A = C, the input voltage at the A terminal is output as the output voltage of the output voltage adjusting means 84V _{1 to} 84V _n .
This is because the voltage command values V _{1 to} V _n before control are limited by the maximum voltage value V * limit (* is 1 to n) that can be output, and when there is no limit, the limit over value of the other phase Are subtracted, and output voltage commands V ₁ ′ to V _n ′ are obtained.
By this process, the voltage that could not be output due to the limit in the failed phase is compensated for by other phases, and the line voltage can be maintained at the same value as before the failure.

20, the voltage limit means 81V _{1 to} 81V _n , the comparison means 82V _{1 to} 82V _n , the totaling means 83V _s , and the output voltage adjustment means 84V _{1 to} 84V _n shown in FIG. The output voltage margin supply means 8, the unit inverter control means 10 (FIG. 8), the overall inverter control means (not shown), the operation abnormality detection means 11 (FIG. 8), etc. in FIG. Can be shared.

(Twelfth embodiment, output voltage margin supply means <5>)
FIG. 21 is a circuit diagram showing the main configuration of the twelfth embodiment.
In FIG. 21, the second DC unit 600 ₂₀ ,..., 600 _{n0 of} the output voltage margin supply means 8 is respectively provided for the second unit inverter series connection group 9 (9 ₁ , 9 _{2 to} 9 _n ). Correspondingly, not all are prepared.
If the control shown in the eleventh embodiment is used, the output voltage margin supply means 8 need not be provided in all the second unit inverter series connection groups 9. When bypassing in a group where an extra unit inverter exists, the phase voltage that is deficient is compensated by the extra unit inverter, and when bypassing in a group where no extra unit inverter exists, By using the control shown in the eleventh embodiment, a line voltage equivalent to that before the failure can be secured. Since this embodiment can reduce the number of unit inverters, the cost is reduced.

(Thirteenth embodiment, output voltage margin supply means <6>)
FIG. 22 is a circuit diagram showing the main configuration of the thirteenth embodiment.
In Figure 22, as the output voltage margin supply means 8, the second DC unit _{600 10} is provided with only one. Switch _S 1A _{to S nA} is connected between the respective one of the terminals and an output terminal of the second unit inverter series group ₉ 1 to 9 _n of unit inverter _{5 10} in the second DC unit _{600 10.} The switch _S 1B _{to S nB} each other terminal of unit inverter _{5 10} in the second DC unit _{600 10,} i.e. the neutral point (NP) 901 and the output terminal of the second unit inverter series group ₉ 1 to 9 _n Connected between and.

Before the failure of the unit inverter, which is a normal case, the switches S _{1B to} S _nB composed of semiconductor switch elements or the like are turned on (ON), and the failure is caused by a signal from the operation abnormality detecting means 11 at the time of failure. By turning off the switch S _{* B of the} circuit having the unit inverter 5 and turning on the switch S _{* A} , the excess unit inverter can be used to compensate for the failed unit inverter. In S _{* B} and S _{* A} , * corresponds to a number corresponding to _{1 to n} second unit inverter series connection group 9 (9 _{1 to} 9 _n ).
Further, the switches S _{1A to} S _nA are referred to as ON switches when a failure occurs, and the switches S _{1B to} S _nB are referred to as ON switches when a failure _does not occur. The switches S _{1A to} S _nA and the switches S _{1B to} S _nB are referred to as failure changeover switches.

By constructing such a switch circuit comprising ON switches S _{1A to} S _nA at the time of failure and ON switches S _{1B to} S _nB at the time of non-failure, the unit inverter necessary for the output voltage margin supply means 8 can be reduced. I can do it.
Moreover, in FIG. 22, although the case where only the 2nd DC unit 600 was one was shown, you may provide with two or more. However, at this time, it is necessary to further include a switch and wiring for this switching.

(Fourteenth embodiment, output voltage margin supply means <7>)
FIG. 23 is a circuit diagram showing the main configuration of the fourteenth embodiment.
In FIG. 23, a transformer 27 (27 _{1 to} 27 _n ) is connected in series to the output of the second unit inverter series connection group 9 (9 _{1 to} 9 _n ), and an output voltage is connected to the other winding of the transformer 27. The outputs of the second DC units 600 (600 ₁₀ to 600 _n0 ) corresponding to the surplus are connected to compensate for the output voltage shortage due to bypass at the time of failure through the transformer 27.
In FIG. 23, the transformer 27 is connected to the neutral point (NP) 901 side, but may be the AC load (ACLLoad) 7 side.

An AC reactor may be connected to the load side of the series multiple inverter for the purpose of a filter or impedance. Even with the step-like output voltage waveform shown in FIGS. 7A and 7B, the current can be smoothly changed by this reactor.
Since the transformer 27 in FIG. 23 has a configuration similar to that of an AC reactor, it can be further connected that it can be connected for the same purpose.

(Other embodiments)
As mentioned above, although embodiment as a whole structure as a serial multiple inverter apparatus to which the present invention is applied has been described, the individual circuits and means are not limited to those described above. In the following, embodiments of the individual elements are described.

<Embodiment of Circuit Protection Means>
FIG. 24 shows an example of the position of the circuit protection means 3. The circuit protection means 3 in each of the above embodiments may be between the AC power 1 and the rectifier 2 as shown in FIG.
Further, the circuit protection means 3 may be provided between the rectifier 2 and the smoothing capacitor 4 as shown in FIG. This positional relationship is the same as the relationship between the circuit protection means 3, the rectifier 2 and the smoothing capacitor 4 shown in FIG.
The circuit protection means 3 may be provided between the smoothing capacitor 4 and the unit inverter 5 as shown in FIG.
Further, the circuit protection means 3 may be any one between the unit inverter 5 and the bypass switch 6 as shown in FIG.

Further, as an element used for the circuit protection means 3, there are various embodiments as shown in FIG.
FIG. 25A shows a configuration in which semiconductor switch elements, which are self-extinguishing semiconductor elements (for example, IGBTs) that can be turned on and off by input signals, are connected in parallel with opposite polarities. .
FIG. 25B shows a fuse that is blown by an overcurrent exceeding a specified value.
FIG. 25 (c) shows a circuit breaker that is interrupted by an overcurrent exceeding a specified value.
Moreover, it is good also as an alternative of a circuit protection means by opening the semiconductor switch element of the unit inverter 5 at the time of failure. However, in that case, the circuit cannot be protected from a short circuit failure of the semiconductor switch element.

<Embodiment of Bypass Switch>
FIG. 26 (FIGS. 26A, 26B, 26C, 26D, and 26E) shows an embodiment of a bypass switch.
FIG. 26A shows a self-extinguishing semiconductor device. The semiconductor switch elements (6A1, 6A2), which are self-extinguishing semiconductor elements, are connected in parallel in the reverse direction. This circuit is connected to the output terminal of the unit inverter 5. At this time, the gate terminals of the semiconductor switch elements (6A1, 6A2) are controlled.
As described above, there is an IGBT as a self-extinguishing semiconductor element. In the case of this circuit, a reverse voltage blocking IGBT (reverse blocking IGBT) is used as the IGBT so as not to be destroyed by the reverse voltage.

  FIG. 26B shows a self-extinguishing semiconductor device. The semiconductor switch elements (6B1, 6B2), which are self-extinguishing semiconductor elements, are connected in series with opposite polarities. Diodes (6B3, 6B4) are connected in parallel to the semiconductor switch elements (6B1, 6B2) in order to allow a reverse current to flow to the semiconductor switch elements (6B1, 6B2). This circuit is connected to the output terminal of the unit inverter 5. At this time, the gate terminals of the semiconductor switch elements (6B1, 6B2) are controlled.

  In FIG. 26C, diodes 6C1, 6C2, 6C3, and 6C4 are bridge-connected, and a thyristor 6C5 is connected to the DC output thereof. This circuit is connected to the output terminal of the unit inverter 5. At this time, the gate terminal of the thyristor 6C5 is controlled.

  In FIG. 26D, diodes 6D1, 6D2, 6D3, and 6D4 are bridge-connected, and a thyristor 6D5 is connected to a DC output thereof. This circuit is connected in parallel between the power supplies of the unit inverter 5 (between the positive terminal 501 and the negative terminal 502 (FIG. 3)), that is, the smoothing capacitor 4 (FIG. 3). At this time, the gate terminal of the thyristor 6D5 is controlled. This circuit has the same configuration as the circuit of FIG. 26C, but the path for bypassing is different.

  In FIG. 26E, one thyristor 6E5 is connected in parallel between the power supplies of the unit inverter 5 (between the positive terminal 501 and the negative terminal 502 (FIG. 3)), that is, the smoothing capacitor 4 (FIG. 3). At this time, the gate terminal of the thyristor 6E5 is controlled.

In addition, since the bypass circuit of FIG. 26D and FIG. 26E also performs a short circuit on the DC side (both ends of the smoothing capacitor 4 (FIG. 3)), DC circuit protection by the circuit protection means 3 is essential.
As for FIG. 26E, a load-side current is passed using a free wheel diode that is normally used in an IGBT that is often used as a semiconductor switch element of the unit inverter 5. Since the capacity is smaller than the current, care must be taken when selecting the element.

  In addition to the bypass switch described above, bypassing is also possible by switching at a mechanical contact such as a knife switch or an electromagnetic contactor. However, it is desirable to use the semiconductor switch element as described above because of the problem of time response.

<AC power>
1 and 2, the AC power 1 has been described as being a three-phase AC, but it may be composed of a single phase, two phases, or four or more phases. The greater the number of phases, the lower the output voltage ripple after passing through the rectifier 2 (FIGS. 1 and 2).

Further, FIGS. 1, 15, 17, 18, in FIGS. 21 to 23, the AC power _{1 (1 11 ~1 1m, ···} , 1 n1 ~1 nm) has been described, three-phase When the alternating current itself is supplied, the present embodiment does not need to include the alternating current power 1 (1 ₁₁ to _{11 m} ,..., 1 _n1 to 1 _nm ) as a device.

<Unit inverter control means>
8 to 14, it is shown that the unit inverter control means 10 is provided for each unit inverter 5, and overall unit inverter control means (not shown) that controls the plurality of unit inverter control means 10 in an integrated manner. ) Explained that it is further provided. However, the unit inverter control means 10 described above is not necessarily provided for each unit inverter 5, and may be shared. Further, the overall unit inverter control means (not shown) may directly control the plurality of unit inverters 5.

<Bypass switch control means>
8 to 14, the bypass switch control means 12 controls the bypass switch 6 provided for each unit inverter 5. At this time, the bypass switch control means 12 may be provided for each of the bypass switches 6, or one bypass switch control means 12 may control a plurality of bypass switches 6 at once.

  As mentioned above, this embodiment converts the direct current power of a rectifier into alternating current power, prepares several unit inverters, the input side is connected in parallel to a rectifier via a smoothing capacitor, and the output of each unit inverter In the series multiplex inverter connected in series and connected to an AC load, when the operation abnormality detecting means detects an abnormality, the output side of the unit inverter is short-circuited by a bypass circuit corresponding to the corresponding unit inverter, The protection circuit that protects the unit inverter opens the unit inverter and protects it. At this time, the output voltage becomes insufficient because the bypass circuit short-circuits the output of the unit inverter, but the insufficient output voltage is compensated for by the output voltage margin of the device, and power supply equivalent to that before the failure is supplied to the AC load. It will be done continuously.

Therefore, even if a failure or the like occurs in at least one of the plurality of unit inverters, the series of AC loads can be continuously operated with the same output voltage as before the failure without stopping the remaining healthy unit inverters. A multiple inverter device is provided.
Further, not only the configuration of the serial multiple inverter device but also a control method of the serial multiple inverter is shown.

1, 1 ₁₀ to 1 _n0 , 1 ₁₁ to ₁ 1 _m , 1 _n1 to 1 _nm AC power, transformer 2, 2 ₁₀ to 2 _n0 , 2 ₁₁ to 2 _{1 m} , 2 _n1 to 2 _nm rectifier 3, 3 _{10 to} 3 _{n0, 3 11 ~3 1m, 3} n1 ~3 nm circuit protection _{4,4 10 ~4 n0, 4 11 ~4} 1m, 4 n1 ~4 nm smoothing capacitor _{5,5 10 ~5 n0, 5 11 ~5} 1m 5 _{n1 to} 5 _nm unit inverter 6, 6 _{10 to} 6 _n0 , 6 _{11 to} 6 _1m , 6 _{n1 to} 6 _nm Bypass switch 6A1, 6A2, 6B1, 6B2 Semiconductor switch element 6B3, 6B4, 6C1 to 6C4, 6D1 to 6D4 Diode 6C5, 6D5, 6E5 Thyristor, short-circuited semiconductor element with control pole 7 AC load, ACLLoad
8, 8 ₁ to 8 _n Output voltage margin supply means 9, 9 _{1 to} 9 _n Second unit inverter series connection group 10 Unit inverter control means 11, 11 _{1 to} 11 _n Operation abnormality detection means 12 Bypass switch control means 13 Fuse The circuit protection device 14,18,20,26 voltage detecting means 15, 17, 19, 21 level determination unit 16 current detecting means 22 to 25 output detector 27, 27 ₁ ~ 27 _n transformer 81V ₁ ~81V _n voltage limit Means 82V _{1 to} 82V _n Comparison means 83V _s Total means 84V _{1 to} 84V _n Output voltage adjustment means 101 to 103 Transformer output terminals ((u), (v), (w))
104, 105, 106 Transformer secondary winding 111-113 First DC unit terminal ((u), (v), (w))
211, 212, 221, 222, 231, 232 Diode 500 First DC unit 501 Positive terminal 502 Negative terminal
503 unit inverter output terminal (a)
504 Unit inverter output terminal (b)
511-514, S1-S4 Semiconductor switch element, IGBT
600, 600 ₂₀ to 600 _n0 second DC unit 901 Neutral point (NP)
V ₁ ~V _n control before the voltage command V ₁ '~V _n' post-control voltage command S _1A to S _nA switches, fault-ON switch, the failure-time change-over switch S _1B to S _nB switches, non-failure-time ON switch failure Time selector switch

Claims (29)

A rectifier that converts AC power into DC power;
DC power that is the output of the rectifier is converted to AC power, and a plurality of unit inverters are formed by bridge-connecting a plurality of semiconductor switch elements, and the input side of each unit inverter is connected to the above-mentioned via a smoothing capacitor. Unit inverter series connection group connected in parallel to the output of the rectifier, connecting the output side of each unit inverter in series, and connecting to an AC load;
Unit inverter control means for giving an open / close control command in a predetermined order to the semiconductor switch elements constituting the unit inverter;
An operation abnormality detecting means for detecting an operation abnormality state of the unit inverter;
Circuit protection means for protecting the unit inverter by opening a circuit corresponding to the corresponding unit inverter when the operation abnormality detection means detects an abnormality of the unit inverter;
A bypass switch connected in parallel to the unit inverter and forming a flow path for circulating load current when electrically closed;
A bypass switch control means for short-circuiting the output of the unit inverter by giving a closing command to the bypass switch corresponding to the corresponding unit inverter when the operation abnormality is detected;
An output voltage margin supply means provided in series with the output of the unit inverter;
A serial multiple inverter device comprising: A rectifier that converts AC power into DC power;
A smoothing capacitor connected between the output terminals of the rectifier;
A unit inverter formed by bridge-connecting a plurality of semiconductor switch elements;
And the DC input side of the unit inverter is connected in parallel to both terminals of the smoothing capacitor and the output of the rectifier to constitute a first DC unit,
Outputs of the plurality of unit inverters included in the plurality of first DC units are connected in series to form a unit inverter series connection group,
A plurality of unit inverter series connection groups are connected to an AC load in parallel.
further,
A plurality of unit inverter control means for respectively controlling the opening and closing of the plurality of unit inverters;
A plurality of operation abnormality detecting means for detecting operation abnormality states of the plurality of unit inverters;
When any one of the plurality of operation abnormality detection means detects an operation abnormality state of the unit inverter, the unit of the first DC unit corresponding to the unit inverter corresponding to the operation abnormality state is opened, thereby the unit Circuit protection means for protecting the inverter;
A plurality of bypass switches that are connected in parallel to the outputs of the plurality of unit inverters and that each form a flow path for circulating a load current when electrically closed;
When any one of the plurality of operation abnormality detecting means detects an operation abnormality state of the unit inverter, a bypass switch control means for giving a closing instruction to the bypass switch corresponding to the unit inverter corresponding to the operation abnormality state;
An output voltage margin supply means connected in series to the unit inverter series connection group, and the bypass switch is closed to compensate for an insufficient output voltage of the unit inverter corresponding to the bypass switch;
A serial multiple inverter device comprising:   3. The serial multiple inverter device according to claim 1, wherein the operation abnormality detection unit detects a DC abnormality when a fuse connected to the unit inverter is blown. 4.   3. The serial multiplexing according to claim 1, wherein the operation abnormality detecting unit detects that the DC voltage applied to the unit inverter is an overvoltage or an undervoltage with respect to a reference value. Inverter device.   The said operation abnormality detection means detects that the electric current which flows into the rectifier or the smoothing capacitor of the said unit inverter became an overcurrent or an insufficient current with respect to a reference value, The Claim 1 or Claim 2 characterized by the above-mentioned. Series multiple inverter device.   2. The operation abnormality detecting means detects an output AC voltage of the unit inverter and detects an abnormality of the unit inverter when the detected voltage exceeds a predetermined range with respect to a reference value. The serial multiple inverter device according to claim 2.   The said operation abnormality detection means detects that the alternating voltage input into the rectifier of the said unit inverter became an overvoltage or an undervoltage with respect to a reference value, The Claim 1 or Claim 2 characterized by the above-mentioned. Series multiple inverter device.   3. The serial multiple inverter device according to claim 1, wherein the operation abnormality detection unit makes a determination based on a relationship between an output voltage of the unit inverter and an output voltage of the unit inverter control unit.   The output voltage margin supply means includes an extra unit inverter connected in series to the rated output voltage. Normally, the extra unit inverter outputs zero voltage or is bypassed by a bypass switch. The output voltage of the unit inverter provided in excess is compensated for the insufficient output voltage by bypassing the unit inverter corresponding to the abnormality by the bypass switch when an operation abnormality is detected. The serial multiple inverter device according to claim 2.   The output voltage margin supply means is provided with output voltage margin supply means for each of the unit inverters for the rated output voltage in a normal state, and the unit inverter corresponding to an abnormality at the time of detecting an operation abnormality is detected by the bypass switch. 3. The serial multiple inverter device according to claim 1, wherein the output voltage that has been bypassed and is insufficient is compensated by the output voltage of the output voltage margin supply means of another unit inverter.   The serial multiple inverter device according to claim 9, wherein the output voltage margin supply means includes an extra unit inverter in all unit inverter series connection groups.   The output voltage margin supply means bypasses the unit inverter corresponding to an abnormality when a unit inverter in a unit inverter series connection group detects an operation abnormality by the bypass switch, and reduces an output phase voltage component that decreases 10. The control for securing the rated voltage of the output line voltage and ensuring the rated operation of the AC load is performed by increasing the output phase voltage of the unit inverter series connection group by the shortage. The serial multiple inverter device according to 10.   The output voltage margin supply means includes a unit inverter series connection group in which an extra unit inverter exists only in some of the unit inverter series connection groups provided in the apparatus, and the extra unit inverter exists. When bypassing with the bypass switch, the phase voltage that is insufficient with the extra unit inverter is compensated, and when bypassing with the bypass switch in the unit inverter series connection group in which the extra unit inverter does not exist, 3. The serial multiple inverter device according to claim 1, wherein a line voltage equivalent to that before the failure is secured by increasing the output phase voltage of the other unit inverter series connection group by the shortage.   The voltage margin of the output voltage margin supply means is calculated by adding an extra unit inverter with a failure time changeover switch to the unit inverter series connection group when the unit inverter of a unit inverter series connection group is bypassed by the bypass switch. 3. The serial multiple inverter device according to claim 1, wherein the output is short-circuited by connecting in series and the output of the extra unit inverter is supplemented. In addition, with multiple transformers,
The output voltage margin supply means serially connects the secondary side windings of the plurality of transformers to the outputs of the plurality of unit inverter series connection groups, and outputs the output voltage to the primary side windings of the plurality of transformers. Consists of multiple unit inverters connected to each other,
When the unit inverter in any one of the unit inverter series connection groups is bypassed by the bypass switch, the unit inverter that is insufficient with the output voltage of the plurality of unit inverters connected to the primary winding of the transformer The series multiple inverter device according to claim 1, wherein the output voltage of the serial multiple inverter device is supplemented.   The series circuit according to claim 1, wherein the circuit protection unit is a protection circuit that is connected in series to a supply line of AC power supplied to the rectifier and has a function of interrupting the circuit. Multiple inverter device.   3. The series multiple inverter according to claim 1, wherein the circuit protection means is a protection circuit that is connected in series between the rectifier and the smoothing capacitor and has a function of interrupting the circuit. apparatus.   The circuit protection means is a protection circuit that is connected in series between the smoothing capacitor and the unit inverter formed of a bridge circuit of the semiconductor switch element and has a function of interrupting the circuit. The serial multiple inverter device according to claim 1 or 2.   3. The serial multiple inverter device according to claim 1, wherein the circuit protection means is a protection circuit connected in series to the output of the unit inverter and having a function of interrupting the circuit.   The serial multiple inverter device according to any one of claims 16 to 19, wherein the circuit protection means uses a self-extinguishing semiconductor element.   The serial multiple inverter device according to any one of claims 16 to 19, wherein the circuit protection means is a fuse that is blown by an overcurrent exceeding a specified value.   20. The series multiple inverter device according to claim 16, wherein the circuit protection unit is a circuit breaker that is interrupted by an overcurrent that is equal to or greater than a specified value.   3. The serial multiple inverter device according to claim 1, wherein the circuit protection unit interrupts the circuit by opening the semiconductor switch element of the unit inverter. 4.   2. The bypass switch according to claim 1, wherein the bypass switch is a semiconductor element, and two or more semiconductor elements are used between the outputs of the unit inverter, and the characteristics are reversed and connected in parallel. Item 3. The serial multiple inverter device according to Item 2.   25. The serial multiple inverter device according to claim 24, wherein a self-extinguishing semiconductor element is used as the semiconductor element used for the bypass switch.   As the bypass switch, a diode is bridge-connected, a semiconductor element with a short-circuit control pole is connected to a DC output of the bridge circuit, and a DC input of the bridge circuit is connected between outputs of the unit inverter. The serial multiple inverter device according to claim 1 or 2.   As the bypass switch, a diode is bridge-connected, a short-circuited control element with a control electrode is connected to a DC output of the bridge circuit, and a DC input of the bridge circuit is connected between power supplies of the unit inverters. The serial multiple inverter device according to claim 1 or 2.   3. The series according to claim 1, wherein the bypass switch includes a semiconductor element with a short-circuiting control pole connected in parallel to a smoothing capacitor between the rectifier and the semiconductor switch element of the unit inverter. Multiple inverter device. A rectifier that converts AC power into DC power;
DC power that is the output of the rectifier is converted to AC power, and a plurality of unit inverters are formed by bridge-connecting a plurality of semiconductor switch elements, and the input side of each unit inverter is connected to the above-mentioned via a smoothing capacitor. Unit inverter series connection group connected in parallel to the output of the rectifier, connecting the output side of each unit inverter in series, and connecting to an AC load;
Unit inverter control means for giving an open / close control command in a predetermined order to the semiconductor switch elements constituting the unit inverter;
An operation abnormality detecting means for detecting an operation abnormality state of the unit inverter;
Circuit protection means for protecting the unit inverter by opening a circuit corresponding to the corresponding unit inverter when the operation abnormality detection means detects an abnormality of the unit inverter;
A bypass switch connected in parallel to the unit inverter and forming a flow path for circulating load current when electrically closed;
A bypass switch control means for short-circuiting the output of the unit inverter by giving a closing command to the bypass switch corresponding to the corresponding unit inverter when the operation abnormality is detected;
An output voltage margin supply means provided in series with the output of the unit inverter, having a function of compensating for an output voltage component that is insufficient at the time of bypassing the unit inverter;
When an abnormality occurs in any of the plurality of unit inverters, the operation abnormality detection unit detects an abnormality, the operation abnormality detection unit outputs an operation abnormality detection signal to the bypass switch control unit, and the bypass switch The control means issues a closing command to the bypass switch, short-circuits the output of the unit inverter in which an abnormality has occurred,
Moreover, the unit inverter is opened by the circuit protection means for protecting the unit inverter, and protection is performed.
Further, the operation abnormality detection means outputs an operation abnormality detection signal to the output voltage margin supply means so as to compensate for an output voltage that is insufficient when the unit inverter is bypassed.

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