JP2011211097A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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JP2011211097A
JP2011211097A JP2010079571A JP2010079571A JP2011211097A JP 2011211097 A JP2011211097 A JP 2011211097A JP 2010079571 A JP2010079571 A JP 2010079571A JP 2010079571 A JP2010079571 A JP 2010079571A JP 2011211097 A JP2011211097 A JP 2011211097A
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layer
plane
surface
gan
semiconductor
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Naoki Hirao
Yuya Miura
祐哉 三浦
直樹 平尾
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Sony Corp
ソニー株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/005Processes
    • H01L33/0062Processes for devices with an active region comprising only III-V compounds
    • H01L33/0079Processes for devices with an active region comprising only III-V compounds wafer bonding or at least partial removal of the growth substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/30625With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/40Materials therefor
    • H01L33/405Reflective materials
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor element, including a nitride semiconductor layer having a high-precision thickness.SOLUTION: The manufacturing method includes a step for forming a semiconductor film 20A, comprising GaN having a +c plane as a main surface on a substrate; a step for forming a groove 29 by selectively graving a part of region on the +c plane, in the semiconductor film 20A; a step for forming a metal layer 38 so as to fill the groove 29; and a step for removing a part in thickness direction by polishing a -c plane of the semiconductor layer 20 as a whole so that the metal layer 38 is exposed. Thus, the semiconductor layer 20, having a predetermined thickness corresponding to the depth of the groove 29, is obtained.

Description

  The present invention relates to a method for manufacturing a semiconductor element including a semiconductor layer made of gallium nitride (GaN).

  Nitride semiconductors such as gallium nitride (GaN) have been put into practical use for semiconductor light emitting devices such as light emitting diodes (LEDs) and semiconductor devices such as high speed transistors capable of high temperature operation.

  In manufacturing a semiconductor device using such a nitride semiconductor, a nitride semiconductor layer is grown to a predetermined thickness on a base material substrate such as a sapphire substrate, and then the nitride semiconductor A nitride semiconductor substrate is obtained by peeling off the interface between the layer and the base material substrate. For example, the interface between the nitride semiconductor layer and the base material substrate is irradiated with a laser beam having a predetermined intensity, and the irradiated portion of the laser beam is locally heated and sublimated to separate the two. By using such a sublimation effect by laser light irradiation, an efficient semiconductor device can be manufactured.

  However, when the nitride semiconductor layer and the base material substrate are separated by such a laser beam, only the portion irradiated with the laser beam is peeled off during the process, and the other portion is bonded. A state will remain. For this reason, stress concentration occurs at the joint portion between the two, and there is a high possibility that a crack will occur on the surface of the nitride semiconductor layer.

  The surface layer in which such a crack has occurred is called a so-called damaged layer (or damaged layer). The presence of the damaged layer not only causes deterioration of physical strength and characteristics, but may cause adhesion of dirt and impurities during the manufacturing process of the semiconductor element. Moreover, when manufacturing a semiconductor light emitting element, it is necessary to attach an electrode to the nitride semiconductor layer. When the surface layer of the nitride semiconductor layer is a damaged layer, the contact resistance of the electrode tends to increase. Furthermore, when dry etching is performed on a damaged layer on the surface for processing such an electrode, there arises a problem that a fine columnar structure called a pillar is generated.

  Therefore, the present applicant has already developed a technique for removing the damaged layer as described above by performing a chemical mechanical polishing (CMP) process after growing the nitride semiconductor layer (for example, , See Patent Document 1).

JP 2006-86388 A

  By the way, when the nitride semiconductor layer is a GaN layer, when the CMP process is performed, a higher polishing rate is obtained on the −c plane than on the + c plane. For this reason, it can be said that the easily polished surface in the GaN layer is a -c surface. However, when the CMP process is performed on the −c surface of the GaN layer, it is difficult to reliably stop the CMP process at a predetermined position because of the high polishing rate. Therefore, it has been difficult to obtain a GaN layer having a predetermined thickness.

  The present invention has been made in view of such problems, and an object thereof is to provide a method for manufacturing a semiconductor device for efficiently manufacturing a semiconductor device including a nitride semiconductor layer having a high-precision thickness. There is.

  The method for manufacturing a semiconductor device of the present invention includes a step of forming a GaN layer having a + c plane as a main surface on a substrate, and a step of selectively digging a partial region of the GaN layer in the + c plane to form a groove. And a step of forming a metal layer so as to fill the groove, and after separating the substrate and the GaN layer, the −c surface of the GaN layer is polished over the entire surface until the metal layer is exposed, and the thickness direction And a step of removing a part of the above. Here, the crystal structure of the GaN layer which is a group III-V compound semiconductor is a hexagonal wurtzite structure or a zinc blend structure, and when cleaved in a plane perpendicular to the c-axis, the surface on the + c-axis side (+ c-plane) Is a crystal plane in which gallium (Ga) atoms are arranged, and a plane on the −c axis side (−c plane) is a crystal plane in which nitrogen (N) atoms are arranged.

  In the method for manufacturing a semiconductor device of the present invention, after forming a metal layer so as to fill the groove in the + c plane of the GaN layer, the −c plane of the GaN layer is polished over the entire surface, and a part of the thickness direction is polished. It was made to remove. As a result, the polishing rate is greatly reduced when the metal layer filled in the bottom of the groove is exposed, so that it is easy to stop the polishing process without proceeding excessively. Alternatively, the polishing process may be performed while detecting a change in electrical resistance, and the polishing process may be stopped when a sudden change in electrical resistance occurs when the metal layer is exposed. In any case, a GaN layer having a thickness corresponding to the depth of the groove remains.

  According to the method for manufacturing a semiconductor device of the present invention, after forming the metal layer so as to fill the groove in the + c plane of the GaN layer, the polishing of the −c plane opposite to the + c plane in the GaN layer is advanced. Therefore, polishing can be stopped immediately when the metal layer is exposed. As a result, a GaN layer having a highly accurate thickness can be easily and efficiently produced.

It is sectional drawing of the light emitting diode as one embodiment of this invention. It is sectional drawing showing 1 process in the manufacturing method of the light emitting diode shown in FIG. FIG. 3 is a cross-sectional view illustrating a process following FIG. 2. FIG. 4 is a cross-sectional view illustrating a process following FIG. 3. FIG. 5 is a cross-sectional view illustrating a process following FIG. 4. FIG. 6 is a cross-sectional view illustrating a process following FIG. 5. FIG. 8 is a cross-sectional view illustrating a process following FIG. 7. FIG. 8 is a cross-sectional view illustrating a process following FIG. 7. It is a characteristic view showing the time-dependent change of the GaN layer at the time of grinding in the example of the present invention.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

[Configuration of light-emitting diode]
FIG. 1 shows a cross-sectional structure of a light emitting diode (LED) as an embodiment of the present invention. Note that FIG. 1 is a schematic representation and is different from actual dimensions and shapes.

  This light emitting diode includes a semiconductor layer 20 including a nitride III-V compound semiconductor, a p-side electrode 30, and an n-side electrode 35. The semiconductor layer 20 is a stacked body formed by stacking a GaN layer 22, an n-type contact layer 23, an n-type cladding layer 24, an active layer 25, a p-type cladding layer 26, and a p-type contact layer 27 in this order. The p-side electrode 30 is provided on the surface of the p-type contact layer 27, and the n-side electrode 35 is provided on the surface of the GaN layer 22. Part of the p-side electrode 30 is connected to the conductive connection layer 33. The connection layer 33 serves as a path for supplying current from the external power source to the p-side electrode 30. The connection layer 33 is bonded to the support substrate 50 via an adhesive layer 41 (not shown here). This light emitting diode is a semiconductor light emitting element of a type (so-called bottom emission type) in which light from the active layer 25 is emitted through an n type semiconductor layer composed of an n type contact layer 23 and an n type cladding layer 24. It is.

  The nitride III-V compound semiconductor referred to here is a gallium nitride compound containing gallium (Ga) and nitrogen (N). For example, GaN, AlGaN (aluminum nitride / gallium), Alternatively, AlGaInN (aluminum nitride, gallium, indium) and the like can be given. These may be n-type impurities composed of group IV and group VI elements such as Si (silicon), Ge (germanium), O (oxygen), Se (selenium), or Mg (magnesium), Zn (zinc as required) ), C (carbon) and other p-type impurities composed of group II and group IV elements.

  The GaN layer 22 is made of, for example, undoped GaN having a thickness of 0.5 μm, and is formed by growing on the c-plane of sapphire using a lateral crystal growth technique such as an ELO (Epitaxial Lateral Overgrowth) technique. Is. The n-type contact layer 23 is made of, for example, n-type GaN having a thickness of 4.0 μm, and the n-type cladding layer 24 is made of, for example, n-type AlGaN having a thickness of 1.0 μm.

The active layer 25 includes, for example, an undoped In x Ga 1-x N well layer (0 <x <1) having a thickness of 3.5 nm and an undoped In y Ga 1-y N barrier layer having a thickness of 7.0 nm ( A multiple quantum well structure is formed by stacking three sets of 0 <y <1). This active layer 25 has a light emitting region 25A in which photons are generated by recombination of injected electrons and holes in the central region in the in-plane direction. The p-type cladding layer 26 is made of, for example, p-type AlGaN having a thickness of 0.5 μm. The p-type contact layer 27 is made of, for example, p-type GaN having a thickness of 0.1 μm, and has a higher p-type impurity concentration than the p-type cladding layer 26.

  A light reflection layer 31 is provided on a part of the upper surface of the p-type contact layer 27. The light reflecting layer 31 is completely covered with a protective layer 32 which is a plating film formed by an electroless plating method. The protective layer 32 is made of, for example, one of nickel (Ni), copper (Cu), palladium (Pd), gold (Au), and tin (Sn), or an alloy containing two or more of these elements. .

  In addition, between the p-type contact layer 27 and the light reflection layer 31, for example, transition metals such as palladium (Pd), nickel (Ni), platinum (Pt), and rhodium (Rh), or transition metals thereof are used. A metal layer made of a material to which silver (Ag) is added may be inserted. By providing this metal layer, effects such as improving the mechanical adhesion between the p-type contact layer 27 and the light reflecting layer 31 and improving the electrical contact can be expected.

  The light reflecting layer 31 is made of a material having metallic properties, such as silver (Ag) or an alloy thereof, and has a thickness of, for example, 30 nm or more and 200 nm or less. The silver alloy is configured by adding at least one substance of platinum (Pt), palladium (Pd), gold (Au), copper (Cu), indium (In), and gallium (Ga) to silver. Is mentioned. More specifically, the light reflecting layer 31 is a so-called APC alloy containing 98% silver, 1% palladium, and 1% copper.

  Pure silver and silver alloys have extremely high reflectivity. As a result, the light reflecting layer 31 exhibits a function of reflecting the light emitted from the light emitting region 25 </ b> A of the active layer 25 toward the GaN layer 22 toward the side opposite to the GaN layer 22 that is the emission window. . The light reflecting layer 31 constitutes the p-side electrode 30 together with the metal layer 32 </ b> A (described later) and the protective layer 32, and is electrically connected to the connection layer 33. Therefore, the light reflection layer 31 is also required to have high electrical contact with the p-type contact layer 27.

  A metal layer 32 </ b> A is provided on the upper surface of the light reflecting layer 31. This metal layer 32A functions as a plating base layer (plating seed layer) when the protective layer 32 is formed by electroless plating. The constituent material of the metal layer 32A is, for example, nickel or a nickel alloy.

  A metal layer 38 is formed so as to cover the semiconductor layer 20 and the p-side electrode 30. However, an insulating layer 37 is provided between the metal layer 38 and the end face of the semiconductor layer 20, and the metal layer 38 is in contact with only the protective layer 32 of the p-side electrode 30.

[Method for manufacturing light-emitting diode]
Next, an example of a method for manufacturing a light emitting diode having such a configuration will be described in detail with reference to FIGS. 2 to 8 each show a cross-sectional configuration of the light emitting diode in the manufacturing process. Here, a case where a plurality of light emitting diodes are collectively formed will be described as an example.

First, as shown in FIG. 2A, for example, sapphire whose principal surface is the c-plane (plane orientation {0001}) is prepared as the substrate 10, and then the buffer layer 11 is interposed on the c-plane. A semiconductor film 20A made of a nitride III-V group compound semiconductor such as GaN is formed over the entire surface by, for example, MOCVD (Metal Organic Chemical Vapor Deposition). The buffer layer 11 is also formed by low-temperature growth on the c-plane of sapphire by MOCVD, and is made of undoped GaN having a thickness of 30 nm, for example. At this time, for example, trimethylaluminum (TMA), trimethylgallium (TMG), trimethylindium (TMIn), and ammonia (NH 3 ) are used as the raw material for the GaN-based compound semiconductor, and the donor impurity raw material is, for example, silane. (SiH 4 ) is used as the acceptor impurity raw material, for example, bis = methylcyclopentadienyl magnesium ((CH 3 C 5 H 4 ) 2 Mg) or bis = cyclopentadienyl magnesium ((C 5 H 5 ). 2 Mg) is used.

  Specifically, first, the surface (c-plane) of the substrate 10 is cleaned by, for example, thermal cleaning. Subsequently, after the buffer layer 11 is grown at a low temperature, for example, at a temperature of about 500 ° C., for example, by MOCVD, on the cleaned substrate 10, GaN is grown at a growth temperature of, for example, 1000 ° C., for example, by a lateral crystal growth technique such as ELO. Layer 22 is grown.

  Next, the n-type contact layer 23, the n-type cladding layer 24, the active layer 25, the p-type cladding layer 26, and the p-type contact layer 27 are sequentially grown on the GaN layer 22 by, for example, MOCVD. Here, the growth temperature of the n-type contact layer 23, the n-type cladding layer 24, the p-type cladding layer 26, and the p-type contact layer 27, which are layers not containing indium (In), is about 1000 ° C., for example, and indium (In). The growth temperature of the active layer 25, which is a layer that includes, for example, is 700 ° C. or higher and 800 ° C. or lower. After crystal growth of the semiconductor layer 20 in this manner, the acceptor impurity in the p-type cladding layer 26 and the p-type contact layer 27 is activated by heating for several tens of minutes at a temperature of, for example, 600 ° C. or more and 700 ° C. or less. Let

  Next, a resist pattern 40 having a predetermined shape is formed on the p-type contact layer 27. After that, as shown in FIG. 2B, the exposed portion of the semiconductor film 20A is formed by the RIE (Reactive Ion Etching) method using, for example, a chlorine-based gas using the resist pattern 40 as a mask. By digging up to reach the buffer layer 11, a plurality of semiconductor layers 20 separated by the grooves 29 are formed.

  Next, as shown in FIG. 3A, after removing the resist pattern 40, the light reflecting layer 31 and the metal layer 32A are sequentially laminated on the p-type contact layer 27 by, for example, sputtering.

  After forming the metal layer 32A, as shown in FIG. 3B, the protective layer 32 is completely covered by the electroless plating method using the metal layer 32A as a plating base layer. Form. Thereby, the p-side electrode 30 is obtained. At this time, at least the upper surface of the p-type contact layer 27 (the surface opposite to the p-type cladding layer 26), the end surface of the light reflecting layer 31, and the surface of the metal layer 32A are immersed in the plating bath. By doing so, plating growth occurs not only on the surface of the metal layer 32A but also on the surface of the p-type contact layer 27 in the peripheral region of the metal layer 32A. That is, here, plating growth occurs with at least one of the metal layer 32A, the light reflection layer 31 and the p-type contact layer 27 as a base point. As a result, a dense and strong protective layer 32 covering the periphery of the light reflecting layer 31 and the metal layer 32A is formed. Here, by changing at least one of the thickness of the metal layer 32A and the composition of the constituent material, the surface potential of the metal layer 32A and the light reflecting layer 31, and the p-type cladding layer that changes depending on the surface potential thereof. It is desirable to adjust the potential of 26. This is because the electrochemical reactivity in the plating bath can be controlled and the formation region (spreading) of the protective layer 32 that is a plating film can be adjusted. In particular, the potential of the p-type cladding layer 26 converges to the natural potential in the plating bath as the distance from the metal layer 32A increases according to the magnitude of the internal resistance of the p-type cladding layer 26 itself. By controlling the gradient of this potential, the formation region (spread) of the protective layer 32 can be adjusted. 3A and 3B show an example in which the metal layer 32A is provided so as to cover the entire upper surface of the light reflecting layer 31, but only a part of the upper surface of the light reflecting layer 31 is covered. The metal layer 32A may be formed. Since the reactivity of the electrochemical reaction can be controlled also by changing the surface area of the metal layer 32A in this way, the protective layer 32 having a desired planar shape and cross-sectional shape can be obtained.

  After that, the insulating layer 37 is selectively formed so as to cover all exposed portions of the semiconductor layer 20 and the buffer layer 11 and expose at least a part of the p-side electrode 30. Here, the insulating film is formed by applying a resist so as to cover the entire surface. After that, heat treatment (baking) is performed as necessary, and the insulating film 37 is selectively removed by using a photolithography technique so that a part of the upper surface of the protective layer 32 is exposed. obtain.

  Next, as shown in FIG. 4A, a metal layer 38 made of, for example, copper (Cu) is formed so as to cover the whole. As the metal layer 38, titanium (Ti), aluminum (Al), nickel (Ni), gold (Au), chromium (Cr), etc. can be used in addition to copper.

  Further, an insulating film 39A is formed by applying a resist or the like so as to cover the whole. At this time, it is preferable to form the insulating film 39A with a sufficient thickness so that the trench 29 separating the adjacent semiconductor layers 20 is completely filled and the upper surface thereof is flat. After that, after performing heat treatment (baking) as necessary, the insulating film 39A is exposed so that a part of the upper surface of the protective layer 32 is exposed using a photolithography technique as shown in FIG. Is selectively removed to form an insulating layer 39.

  Subsequently, a connection layer 33 connected to the p-side electrode 30 is formed as shown in FIG. 5 by patterning after forming a plating film made of copper (Cu) or the like by, for example, electroplating. After that, an adhesive layer 41 is formed so as to cover the connection layer 33 and fill the periphery thereof, and a support substrate 50 made of sapphire or the like is bonded to the connection layer 33 through the adhesive layer 41.

  Thereafter, an excimer laser, for example, is irradiated from the back side of the substrate 10 over the entire surface. As a result, laser ablation occurs, and the interface between the substrate 10 and the buffer layer 11 is peeled off to separate them. Laser ablation is a phenomenon in which the substrate 10 and the buffer layer 11 are peeled off when a part of the buffer layer 11 irradiated with the laser is locally heated and sublimated. At this time, a damaged layer is formed on the surface of the peeled buffer layer 11.

  For this reason, as shown in FIG. 6, the damaged layer is surely removed by polishing the −c surface of the buffer layer 11 by a chemical mechanical polishing (CMP) method. When CMP is proceeded in the laminating direction as it is, the entire buffer layer 11 is removed, and the insulating layer 37 located at the bottom of the semiconductor layer 20 and the bottom of the groove 29 appears on the polished surface.

  When CMP is further advanced, the insulating layer 37 filling the bottom surface of the groove 29 is removed, and the polished surface reaches the metal layer 38 as shown in FIG. When the metal layer 38 is exposed in this way, the polishing rate is significantly reduced as compared to before the metal layer 38 is exposed. Therefore, the polishing can be stopped accurately at a predetermined position by detecting the change.

Specifically, the CMP method includes polishing particles such as SiO 2 (colloidal silica), CeO 2 , Al 2 O 3 , MnO 2 , an electrolyte such as potassium hydroxide (KOH), an oxidizing agent such as hydrogen peroxide, A dispersion obtained by dispersing in water containing an inorganic acid such as nitric acid, hydrofluoric acid or buffered hydrofluoric acid, an organic acid such as carboxylic acid, an inorganic or organic alkali agent, an organic dispersant or a surfactant. Polishing is performed using a polishing liquid (CMP slurry). Usually, polishing is performed using a polishing pad made of polyurethane or the like. According to such a CMP method, unlike normal polishing, the chemical action and the mechanical action cooperate to cut the surface without forming a work-affected layer on the work surface. In addition, the abrasive particles used in the CMP method cause the chemical reaction to proceed by locally raising the temperature of the contact interface with the polishing surface, or the reaction product is adsorbed on the surface of the abrasive particles to advance the polishing. Can be. In normal polishing, a fine microcrack layer is formed by the mechanical action of the abrasive particles, and a damaged portion may be generated. On the other hand, if the CMP method is used, polishing can be performed without generating a minute microcrack layer. Accordingly, when forming an electrode or the like in a later process, it is advantageous to suppress an increase in contact resistance on the polished surface.

  Further, a titanium (Ti) layer, a platinum (Pt) layer, and a gold (Au) layer are sequentially stacked by an evaporation method or the like so as to cover the surface opposite to the p-side electrode 30 in the semiconductor layer 20 exposed by the CMP process. After that, the n-side electrode 35 is formed by patterning so as to have a predetermined shape (see FIG. 8).

  Finally, the light emitting diode of the present embodiment is manufactured through a predetermined process such as dividing the semiconductor layer 20.

  In the light emitting diode manufactured in this manner, when current is supplied to the p-side electrode 30 and the n-side electrode 35, the current is injected into the light emitting region 25A of the active layer 25, thereby recombining electrons and holes. Light emission due to. Of the emitted light generated in the light emitting region 25A, the light L1 that goes directly to the GaN layer 22 that is an emission window passes through the substrate 10 and is emitted to the outside, and the lights L2 and L3 that go to the opposite side of the GaN layer 22 are light. After being reflected toward the GaN layer 22 by the reflective layer 31, it passes through the semiconductor layer 20 and is emitted to the outside (see FIG. 1).

  At this time, since the lights L2 and L3 are reflected by the light reflecting layer 31 including silver (Ag) having an extremely large reflectance, the light reflecting layer 31 does not include silver (Ag). Reflectivity and light extraction efficiency are increased.

[Operation and effect of the present embodiment]
As described above, in the present embodiment, after a plurality of semiconductor layers 20 made of GaN or the like separated by the grooves 29 are formed on the buffer layer 11, the bottom surfaces of the grooves 29 are covered and the semiconductor layers 20 are formed. A metal layer 38 was formed in contact with the + c plane. After that, CMP was performed from the −c plane side of the semiconductor layer 20 to remove all of the buffer layer 11 and part of the semiconductor layer 20 in the thickness direction. As a result, the polishing rate is greatly reduced when the metal layer 38 formed at the bottom of the groove 29 is exposed to the polishing surface, so that it is easy to stop at a predetermined position without excessive CMP.

  This phenomenon is considered as follows. First, GaN constituting the semiconductor layer 20 has a crystal field due to internal polarization or the like. Therefore, in the stage before the metal layer 38 is exposed to the polished surface, the surface of the semiconductor layer 20 on the side in contact with the p-side electrode 30 (+ c surface), and the p-side electrode 30 and the metal layer 38 that are electrically connected thereto are compared. It will have a noble potential. On the other hand, the surface of the semiconductor layer 20 opposite to the p-side electrode 30 (the surface to be polished, that is, the −c surface) has a relatively base potential. In this situation, there is a difference in the surface potential between the + c plane and the −c plane, so that the corrosion on the −c plane with the polishing liquid used for CMP tends to proceed. However, when CMP progresses and the metal layer 38 is exposed to the polishing surface, the polishing surface and the metal layer 38 become equipotential due to contact between the polishing pad of the CMP processing apparatus and the metal layer 38. That is, the surface potentials of the + c plane and the −c plane are equal, and corrosion on the −c plane due to the polishing liquid is less likely to occur. As a result, it is considered that the polishing rate is significantly reduced.

  Further, in the present embodiment, the polishing process is performed while detecting a change in electric resistance, and the polishing process is surely stopped when a sudden change in the electric resistance occurs when the metal layer 38 is exposed to the polishing surface. You can also. In either case, the semiconductor layer 20 having a thickness corresponding to the depth of the groove 29 remains. That is, after forming the metal layer 38 so as to fill the groove 29 formed by digging down the + c plane of the semiconductor film 20A, the polishing of the −c plane in the semiconductor layer 20 is advanced, so that the metal layer 38 is exposed. Polishing can be stopped immediately at the time. As a result, the semiconductor layer 20 having a highly accurate thickness can be easily and efficiently manufactured. As a result, a highly reliable light-emitting diode that exhibits desired performance can be realized.

  In this embodiment, when forming the trench 29, a part of the semiconductor film 20A is dug until reaching the buffer layer 11. However, the part of the semiconductor film 20A is left partly in the thickness direction. You may do it. Also in this case, if the metal layer 38 is formed so as to cover the bottom surface of the groove 29 and be in contact with the + c surface of the semiconductor film 20A, the metal layer 38 is polished from the + c surface side of the semiconductor film 20A. When it is exposed to the surface, it can be stopped accurately. At the same time, the semiconductor film 20 </ b> A is separated into a plurality of semiconductor layers 20.

  Examples of the present invention will be described in detail.

(Example)
As an example, the light emitting diode of FIG. 1 was manufactured according to the description of the above embodiment. Here, first, sapphire having a c-plane as a main surface is prepared as the substrate 10, and then the buffer layer 11 made of undoped GaN having a thickness of 30 nm is grown on the c-plane by MOCVD at 500 ° C. Formed. After that, undoped GaN was grown on the buffer layer 11 at 1000 ° C. by the ELO technique to form a GaN layer 22 having a thickness of 0.5 μm. Further, the n-type contact layer 23, the n-type cladding layer 24, the active layer 25, the p-type cladding layer 26, and the p-type contact layer 27 are sequentially grown on the GaN layer 22 by MOCVD, and the semiconductor film 20A is formed. Obtained. Here, the growth temperature of the n-type contact layer 23, the n-type cladding layer 24, the p-type cladding layer 26, and the p-type contact layer 27 is about 1000 ° C., and the growth temperature of the active layer 25 is 720 ° C. for green. The blue color was 780 ° C. The n-type contact layer 23 was made of n-type GaN having a thickness of 4.0 μm, and the n-type cladding layer 24 was made of n-type AlGaN having a thickness of 1.0 μm. The active layer 25 includes an undoped In x Ga 1-x N well layer (0 <x <1) having a thickness of 3.5 nm and an undoped In y Ga 1-y N barrier layer (0 <x) having a thickness of 7.0 nm. A multi-quantum well structure is formed by stacking three sets of y <1). The p-type cladding layer 26 is made of p-type AlGaN having a thickness of 0.5 μm, and the p-type contact layer 27 has a higher p-type impurity concentration than the p-type cladding layer 26 having a thickness of 0.1 μm. It was composed of p-type GaN.

  Next, after forming the p-side electrode 30 at a predetermined position, the convex portion 28 and the groove 29 were formed by digging the semiconductor film 20A selectively until reaching the GaN layer 22 by using the RIE method. After that, a metal layer 38 was formed using copper so as to cover the whole. Here, the depth of the groove 29 was 2.1 μm. That is, the target value of the thickness of the semiconductor layer 20 was 2.1 μm.

  Subsequently, after peeling the substrate 10 from the buffer layer 11, the buffer layer 11 and the −c surface of the GaN layer were polished over the entire surface. At that time, the relationship between the polishing time (elapsed time) and the change in film thickness was investigated. The result is shown in FIG. In FIG. 9, the horizontal axis represents the polishing time (minutes), and the vertical axis represents the film thickness of the remaining semiconductor layer 20 (semiconductor film 20A). Note that a polishing liquid containing potassium hydroxide (KOH) was used, and the polishing rate was 0.07 μm / min. It was.

(Comparative example)
Instead of the metal layer 38, the convex portion 28 and the groove 29 are covered with a resin (“VPA100” manufactured by Nippon Steel Chemical Co., Ltd.) containing bisphenolfluorene epoxy acrylate acid adduct and propylene glycol monomethyl ether acetate (PGMEA) as main components. A light emitting diode as a comparative example was manufactured in the same manner except for the above.

  As shown in FIG. 9, in the example (curve indicated by □), the polishing rate decreases as the thickness of the semiconductor layer 20 approaches the target value of 2.1 μm, and when the thickness reaches 2.1 μm ( At the time when the metal layer 38 filling the groove 29 was exposed, polishing hardly proceeded. On the other hand, in the comparative example (curve indicated by ●), the polishing rate slightly decreases when the thickness of the semiconductor layer 20 reaches the target value of 2.1 μm (when the resin filling the groove 29 is exposed). However, polishing continued to proceed.

  Thus, according to this example, it was confirmed that a semiconductor layer (GaN layer) having a desired thickness can be easily manufactured.

  Although the present invention has been described with reference to the embodiment, the present invention is not limited to the aspect described in the above-described embodiment, and various modifications can be made. For example, in the above embodiment, the light emitting diode is exemplified as the semiconductor element. However, the semiconductor element of the present invention is a concept including other devices such as a transistor having a GaN layer.

  DESCRIPTION OF SYMBOLS 10 ... Substrate, 11 ... Buffer layer, 20A ... Semiconductor film, 20 ... Semiconductor layer, 22 ... GaN layer, 23 ... n-type contact layer, 24 ... n-type cladding layer, 25 ... Active layer, 25A ... Light emitting region, 26 ... p-type cladding layer, 27... p-type contact layer, 28... convex, 29 .. groove, 30 .. p-side electrode, 31 .. light reflecting layer, 32 A. metal layer, 32. n-side electrode, 36... n-side bump portion, 37 .. insulating layer, 38 .. metal layer, 39 .. insulating layer, 40 .. resist pattern, 41 .. adhesive layer, 50 .. support substrate, L1, L2, L3.

Claims (6)

  1. Forming a gallium nitride (GaN) layer having a + c plane as a main surface on a substrate;
    Selectively digging a partial region in the + c plane of the GaN layer to form a groove;
    Forming a metal layer to fill the groove;
    A step of separating the substrate and the GaN layer, polishing the entire −c surface of the GaN layer until the metal layer is exposed, and removing a part in the thickness direction thereof. Manufacturing method.
  2.   The method for manufacturing a semiconductor device according to claim 1, wherein polishing of the −c surface of the GaN layer is stopped when the metal layer is exposed.
  3. A sapphire substrate having a + c plane as a main surface is used as the substrate,
    The method for manufacturing a semiconductor device according to claim 1, wherein the GaN layer is formed by epitaxial growth on a + c plane of the sapphire substrate.
  4.   The method for manufacturing a semiconductor device according to claim 1, wherein the −c surface of the GaN layer is polished by a chemical mechanical polishing (CMP) method using a polishing liquid containing potassium hydroxide (KOH).
  5.   2. The method of manufacturing a semiconductor device according to claim 1, wherein the substrate and the GaN layer are separated by a laser ablation method.
  6.   The method of manufacturing a semiconductor element according to claim 1, wherein the metal layer is formed using copper (Cu).
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JP2015122452A (en) * 2013-12-25 2015-07-02 サンケン電気株式会社 Light-emitting device
WO2015146069A1 (en) * 2014-03-28 2015-10-01 パナソニックIpマネジメント株式会社 Light emitting diode element

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EP3242791A4 (en) * 2015-01-05 2018-10-31 e-Vision Smart Optics Inc. Methods and systems for mold releases

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TWI243488B (en) 2003-02-26 2005-11-11 Osram Opto Semiconductors Gmbh Electrical contact-area for optoelectronic semiconductor-chip and its production method
JP4729896B2 (en) 2004-09-17 2011-07-20 ソニー株式会社 Semiconductor thin film surface treatment method
JP2007081113A (en) * 2005-09-14 2007-03-29 Sony Corp Method for manufacturing semiconductor device
JP2007081312A (en) * 2005-09-16 2007-03-29 Showa Denko Kk Method of manufacturing nitride-based semiconductor light-emitting element
US20080150085A1 (en) * 2006-12-22 2008-06-26 Armin Dadgar Gruppe-iii-nitrid-halbleiterbauelement mit hoch p-leitfahiger schicht
WO2009146583A1 (en) * 2008-06-02 2009-12-10 Hong Kong Applied Science and Technology Research Institute Co. Ltd Semiconductor wafer, semiconductor device and methods for manufacturing semiconductor wafer and device

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JP2015122452A (en) * 2013-12-25 2015-07-02 サンケン電気株式会社 Light-emitting device
WO2015146069A1 (en) * 2014-03-28 2015-10-01 パナソニックIpマネジメント株式会社 Light emitting diode element

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