JP2011199357A - Power amplifying device and method of controlling the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a technique for suppressing deterioration in power efficiency in a group of amplifiers connected in parallel while suppressing occurrence of nonlinear distortion in a power amplifying device including a plurality of amplifiers connected in parallel.SOLUTION: The power amplifying device has the plurality of amplifiers connected in parallel. The amount of bias to apply to an amplifying element of each amplifier is adjusted individually so that the amount of operating current flowing in the amplifying element of each amplifier becomes the same, and a measurement value of the nonlinear distortion included in an output signal of the power amplifying device is within a predetermined range.

Description

  The present invention relates to a power amplifying apparatus including a plurality of amplifiers connected in parallel and a control method thereof.

  As a technique for extracting a large amount of power from a power amplification device, a configuration in which a plurality of field effect transistors (FETs) are connected in parallel is widely known. Thus, when connecting multiple FETs in parallel, if the output level of each FET is the same, the combined loss when combining the output power is small, but if the output level of each FET is different, the combined loss increases. The power efficiency of the power amplifying device is deteriorated. Therefore, when FETs are connected in parallel, it is important to keep the output level of each FET the same. However, since FETs have large individual differences and variations in gain, variations in the output level of each FET also occur. .

  For example, in a power amplifying device, in order to achieve high power, several tens of FETs may be connected in parallel, but as the number of FETs connected in parallel increases, the difference in the output level of each FET increases. The possibility is higher and the power efficiency tends to deteriorate.

  Also, if the variation in the output level of each FET is large, for example, when the power amplifying device is operating so as to have a rated output as a whole, the output level of some FETs becomes too large and nonlinear distortion occurs. There is also.

  As a technique for solving this problem, it is conceivable to adjust the bias voltage applied to each FET so that the operating currents flowing through the FETs are the same, thereby making the output levels of the FETs the same. A circuit for adjusting the bias voltage so that the amount of current flowing in each FET connected in parallel is the same is disclosed in Patent Document 1, for example.

  FIG. 6 shows a circuit diagram of a parallel-connected FET circuit disclosed in Patent Document 1. In FIG.

As shown in FIG. 6, operational amplifiers (OP _{2 to} OP _n ) for controlling the gate-source voltage are individually connected to the FETs (FET _{2 to} FET _n ) connected in parallel. The operational amplifiers (OP _{2 to} OP _n ) operate so that the potential differences (Vf _{2 to} Vf _n ) generated at both ends of the resistors (Rf _{2 to} Rf _n ) connected to the source side of the FETs are the same. As a result, the amount of current (i _{1 to} i _n ) flowing through each FET becomes equal.

Japanese Utility Model Sho 62-129615

  In general, an amplifier using an amplifying element such as an FET or a bipolar transistor is classified into A class, AB class, B class, and the like depending on the amount of bias applied to the amplifying element.

  Among these, in the class AB amplifier and the class B amplifier, when the bias amount applied to the amplifying element is increased, a large operating current flows through the amplifying element, so that the power consumption increases and the power efficiency decreases. On the other hand, if the bias amount applied to the amplifying element is too small, nonlinear distortion due to crossover distortion occurs.

  Accordingly, even if the amount of current flowing through each amplifier is the same by applying the technique described in Patent Document 1 to a power amplifying device in which a class AB amplifier or a class B amplifier operates in parallel, the applied bias amount is too large. There is a problem that nonlinear distortion occurs when the power efficiency is lowered and the bias amount is too small.

  In addition, even when the amount of current flowing through each amplifier is made the same by applying the technique described in Patent Document 1 to a power amplifying device in which class A amplifiers operate in parallel, the amount of bias to be applied is not an appropriate amount. There is a problem that the linear region of the amplification characteristic becomes narrow and the linearity of the output signal (proportionality with respect to the input signal) decreases.

  An object of the present invention is to provide a technique for suppressing a decrease in power efficiency in an amplifier group connected in parallel while suppressing occurrence of nonlinear distortion in a power amplifying apparatus including the amplifier group connected in parallel. That is.

In order to achieve the above object, a power amplification device of the present invention is a power amplification device that amplifies an input signal to a desired power,
An amplifier group in which a plurality of amplifiers are connected in parallel;
Distributing means for distributing an input signal to supply the plurality of amplifiers;
Combining means for combining the output signals of the plurality of amplifiers;
Bias applying means for individually biasing the amplifying element of each amplifier;
Current detection means for measuring the amount of current flowing through the amplification element of each amplifier;
Distortion detection means for measuring nonlinear distortion included in the signal synthesized by the synthesis means;
While obtaining information indicating the amount of current flowing through the amplification element of each amplifier from the current detection means, obtaining a measurement value of the nonlinear distortion from the distortion detection means, the current amount of the amplification element of each amplifier becomes the same, Control means for adjusting the amount of bias applied by the bias applying means to the amplifying element of each amplifier so that the measured value of the nonlinear distortion falls within a predetermined range;
Have

In order to achieve the above object, a control method of the present invention is a control method of a power amplifying apparatus including a plurality of amplifiers connected in parallel,
Measure the amount of current flowing through the amplifier element of each amplifier,
Measure nonlinear distortion included in the output signal of the power amplifier,
The amount of bias applied to the amplifying element of each amplifier is individually adjusted so that the amount of current of the amplifying element of each amplifier becomes the same and the measured value of the nonlinear distortion falls within a predetermined range.

  ADVANTAGE OF THE INVENTION According to this invention, in a power amplification apparatus provided with the amplifier group connected in parallel, the fall of the power efficiency in the amplifier group connected in parallel can be suppressed, suppressing generation | occurrence | production of nonlinear distortion.

It is a figure which shows the structure of the power amplification apparatus of 1st Embodiment. It is a flowchart which shows the process sequence when the power amplification apparatus 1 shown in FIG. 1 makes the output level of each amplifier the same. 2 is a flowchart showing a processing procedure when the power amplifying apparatus 1 shown in FIG. 1 adjusts a bias voltage applied to each FET based on an IM value of an output signal. It is a flowchart which shows the process sequence when the power amplification apparatus 1 shown in FIG. 1 adjusts a drain voltage based on IM value of an output signal. It is a figure which shows the structure of the power amplification apparatus of 2nd Embodiment. 1 is a circuit diagram of a parallel-connected FET circuit disclosed in Patent Document 1. FIG.

  Next, the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a diagram illustrating a configuration of the power amplifying device according to the first embodiment.

  As illustrated in FIG. 1, the power amplifying apparatus 1 according to the present embodiment includes an amplification processing unit 10, a distortion compensator 30, and a directional coupler 33. Note that the power amplifying apparatus 1 is used at an output level with high linearity with a sufficient margin (backoff) from the saturated output value in order to improve the distortion characteristics.

  The amplification processing unit 10 has a function of amplifying an input signal to a desired power by connecting a plurality of amplifiers in parallel, and includes a variable attenuator 11, a drive amplifier 12, an input detector 13, and an amplifier parallel configuration stage 14. , An output detector 18, a CPU (Central Processing Unit) 19, a bias application unit 20, a current detector 21, and a voltage supply unit 22.

  The variable attenuator 11 is a known attenuator that attenuates an externally input signal to an appropriate level.

  The drive amplifier 12 amplifies the signal output from the variable attenuator 11 to an appropriate level and supplies the amplified signal to the amplifier parallel configuration stage 14.

The amplifier parallel configuration stage 14 includes a distributor 15, a first amplifier 16 ₁ to an nth amplifier 16 _n, and a combiner 17. Note that each amplifier of the present embodiment is a class AB amplifier or a class B amplifier composed of FETs.

In the amplifier parallel configuration stage 14, the distributor 15 distributes the signal output from the drive amplifier 12 and supplies the signal to the first amplifier 16 ₁ to the nth amplifier 16 _n, and each signal distributed by the distributor 15 is supplied. The first amplifier 16 ₁ to the n-th amplifier 16 _n amplify, and the synthesizer 17 synthesizes the signals amplified by the amplifiers and outputs them to the outside.

  The input detector 13 detects the level of the signal input to the amplifier parallel configuration stage 14 and notifies input level information indicating the level of the input signal in response to an acquisition request from the CPU 19.

  On the other hand, the output detector 18 detects the level of the signal output from the amplifier parallel configuration stage 14 (that is, the output signal of the power amplification device 1), and obtains output level information indicating the level of the output signal from the CPU 19. Notify according to.

The bias applying unit 20 is a device that individually biases the amplifying elements of the first amplifier 16 ₁ to the n-th amplifier 16 _n , and the bias applying unit 20 of the present embodiment has a bias voltage Vg applied to the FET of each amplifier. supplying ₁ through Vg _n, it changes the magnitude of the bias voltage Vg ₁ through Vg _n in response to a bias control signal from the CPU 19. For example, the bias applying unit 20 is realized by a D / A (digital / analog) converter that converts a control signal from the CPU 19 into an analog signal.

The voltage supply unit 22 is a power supply device that supplies a power supply voltage to the output terminals of the amplification elements of the first amplifier 16 ₁ to the n-th amplifier 16 _n via the current detector 21, and the voltage supply according to the present embodiment. The unit 22 supplies the drain voltage Vd to the drain terminal of the FET of each amplifier, and changes the magnitude of the drain voltage Vd according to the voltage control signal from the CPU 19.

The current detector 21 is a detector that measures the amount of current flowing through each of the amplifier elements of the first amplifier 16 ₁ to the n-th amplifier 16 _n , and the current detector 21 of the present embodiment is connected to the FET of each amplifier. drain current (hereinafter, referred to as the operating current) flowing current amount (hereinafter referred to as the operating current amount) was measured Id ₁ ~Id _n, according the current amount information indicating the measured operating current amount acquisition request from CPU19 To notify.

  The directional coupler 33 takes out the output signal of the amplification processing unit 10 and supplies it to the distortion compensator 30.

  The distortion compensator 30 has a function of correcting an original signal input from the outside and outputting it to the amplification processing unit 10, and includes a correction unit 31 and a distortion detection unit 32. The correction unit 31 and the distortion detection unit 32 are realized by, for example, an LSI (Large Scale Integration) composed of a logic circuit or the like, or a CPU or DSP (Digital Signal Processor) that operates according to a program.

  The distortion detection unit 32 is a detector that measures nonlinear distortion included in the output signal of the amplification processing unit 10 supplied from the directional coupler 33, and the distortion detection unit 32 of the present embodiment is the amplification processing unit 10. The IM (inter-modulation distortion) value indicating the intermodulation distortion included in the output signal is measured, IM value information indicating the measured IM value is notified to the correction unit 31, and the CPU 19 responds to an acquisition request from the CPU 19. Also notify. Intermodulation distortion is distortion due to a new frequency component that occurs between two adjacent frequency components, and occurs when the output signal has nonlinearity (not completely proportional to the input signal). Moreover, since the measuring method of IM value is described in Unexamined-Japanese-Patent No. 2005-244430, detailed description is abbreviate | omitted here.

  The correction unit 31 uses the output signal of the amplification processing unit 10 supplied from the directional coupler 33 so that the IM value measured by the distortion detection unit 32 becomes the best value, and the original input from the outside. The signal is corrected and output to the amplification processing unit 10.

  The CPU 19 obtains input level information, output level information, current amount information of each amplifier, and IM value information from the input detector 13, the output detector 18, the current detector 21, and the distortion detector 32, respectively. The control device adjusts the attenuation amount of the variable attenuator 11, the bias voltage supplied from the bias applying unit 20 to the FET of each amplifier, and the drain voltage supplied from the voltage supply unit 22 to the FET of each amplifier.

  Below, the outline | summary of operation | movement of the power amplification apparatus 1 of this embodiment is demonstrated.

First, in the power amplifying apparatus 1, in order to suppress a reduction in power efficiency of the amplifier parallel configuration stage 14, it is necessary to make the output level of each amplifier the same and reduce the synthesis loss in the combiner 17. Since the first amplifier 16 ₁ to the n-th amplifier 16 _n of the present embodiment are class AB amplifiers or class B amplifiers composed of FETs, bias voltages Vg ₁ to be applied to the FETs of the amplifiers by changing the vg _n, by adjusting the operating current of Id ₁ ~Id _n flowing through respective FET output level of each amplifier can be made identical.

  In addition, the bias voltage applied to each FET is set so that the amount of drain current (hereinafter referred to as idle current) flowing through each FET when no signal is input to the power amplifying device 1 is the same for all FETs. Although it is possible to adjust, since FETs have large individual differences and variations in gain, even when each FET is adjusted to have the same idle current, each power amplifying apparatus 1 is set to a rated output. The drain current (operating current) flowing through the FETs is not always the same.

Therefore, in this embodiment, CPU 19 is in a state where the output level of the power amplifier 1 is adjusted attenuation of the variable attenuator 11 so that the rated output, the operating current amount Id ₁ ~Id _n currents flowing through the respective FET obtained from the detector 21, so that each operating current amount is the same, with a bias control signal, adjusts the bias voltage Vg ₁ through Vg _n that the bias applying unit 20 is applied to each FET.

Incidentally, by changing the bias voltage Vg ₁ through Vg _n to be applied to each FET, the gain of each FET is varied, also varied gain of the power amplifier 1. Therefore, since the output level of the power amplifying apparatus 1 deviates from the rated output, the CPU 19 obtains output level information from the output detector 18 and attenuates the variable attenuator 11 so that the output level of the power amplifying apparatus 1 becomes the rated output. Readjust the amount.

  In addition, since the power efficiency is the ratio of the output power to the power consumption, it is important to reduce the power consumption of each FET in order to suppress the reduction in the power efficiency of the amplifier parallel configuration stage 14. In the class AB amplifier and the class B amplifier, when the bias voltage applied to the FET is reduced, the amount of operating current flowing through the FET is reduced, so that power consumption can be reduced. Since most of the power consumption of the power amplifying apparatus 1 is consumed by the FETs of the amplifiers in the amplifier parallel configuration stage 14, the power consumption of the entire power amplifying apparatus 1 is also reduced by reducing the power consumption of each FET. Can be reduced.

Therefore, CPU 19 adjusts the bias voltage Vg ₁ through Vg _n so as to reduce the operating current of Id ₁ ~Id _n flowing through respective FET.

On the other hand, in the class AB amplifier and the class B amplifier, if the bias voltage applied to the FET is excessively reduced, nonlinear distortion due to crossover distortion occurs. Therefore, the allowable range of IM value to ensure the linearity of the output signal determined in advance for, CPU 19 adjusts the bias voltage Vg ₁ through Vg _n as IM value falls within the allowable range.

  Further, when the back-off amount of the power amplifying device 1 is sufficiently large, the power consumption of each FET may be reduced by reducing the drain voltage supplied to the FET of each amplifier in the amplifier parallel configuration stage 14. On the other hand, when the drain voltage is reduced, the saturation output value of each FET becomes small and the back-off amount becomes small. Therefore, if the drain voltage is reduced too much, the linearity of the output signal is lowered. Therefore, the CPU 19 uses the voltage control signal to reduce the drain voltage Vd supplied to each FET under the condition that the IM value falls within the allowable range determined to ensure the linearity of the output signal. The supply unit 22 is controlled.

  Even when the drain voltage Vd is changed, the CPU 19 acquires the output level information from the output detector 18 and adjusts the attenuation amount of the variable attenuator 11 so that the output level of the power amplifier 1 becomes the rated output.

  Next, a processing procedure when the power amplifying apparatus 1 shown in FIG. 1 makes the output levels of the amplifiers the same will be described with reference to the flowchart shown in FIG.

As shown in FIG. 2, the CPU 19 of the power amplifying device 1 first has an idle current flowing through each FET of the first amplifier 16 ₁ to the n-th amplifier 16 _{n in} a state where no signal is input to the power amplifying device 1. so that the amount of the same across all FET, using a bias control signal, adjusts the bias voltage Vg ₁ through Vg _n that the bias applying unit 20 is applied to the FET (step S1).

  When adjustment is made so that the amount of idle current flowing through all FETs is the same, the CPU 19 obtains input level information from the input detector 13 and determines whether or not a signal is input to the amplifier parallel configuration stage 14. The system waits until a signal is input to the amplifier parallel configuration stage 14. When a signal is input to the amplifier parallel configuration stage 14, the CPU 19 acquires output level information from the output detector 18 to determine the output level of the power amplifying apparatus 1, and the power amplifying apparatus 1 becomes a rated output. In this manner, the attenuation amount of the variable attenuator 11 is controlled (step S2).

When the power amplifying apparatus 1 is set to the rated output, the CPU 19 uses the current detector 21 to obtain information on the amount of operating current flowing through the FETs of the first amplifier 16 ₁ to the n-th amplifier 16 _n at the rated output of the power amplifying apparatus 1. Get from. Then, CPU 19 is such that the amount of current operating current amount is set in advance for each FET, adjusts the bias voltage Vg ₁ through Vg _n with bias control signals (step S3). The bias voltage to be applied is increased for FETs whose operating current amount is less than a preset current amount, and the bias voltage to be applied is reduced for FETs having an operating current amount greater than a preset current amount. As a result, the CPU 19 adjusts the operation current amounts of the FETs to be the same, and makes the output levels of the amplifiers the same.

  On the other hand, when the bias voltage applied to each FET is changed, the gain of each FET varies, and the output level of the power amplifying apparatus 1 deviates from the rated output. Therefore, the CPU 19 acquires output level information from the output detector 18 and readjusts the attenuation amount of the variable attenuator 11 so that the output level of the power amplifying apparatus 1 becomes the rated output. Thereafter, the CPU 19 acquires input level information from the input detector 13 and acquires output level information from the output detector 18. Then, the CPU 19 calculates the gain of the amplifier parallel configuration stage 14 from the input level information and the output level information, and determines whether or not the calculated gain is in a predetermined range (step S4).

If not in the range where the gain of the amplifier parallel configuration stage 14 is predetermined, CPU 19 again adjusts the bias voltage Vg ₁ through Vg _n with bias control signals (step S5). For example, if the gain of the amplifier parallel configuration stage 14 is large, CPU 19 by reducing the bias voltage Vg ₁ through Vg _n, decreases the output level by reducing the operating current of each FET. On the other hand, if the gain of the amplifier parallel configuration stage 14 is small, CPU 19, by increasing the bias voltage Vg ₁ through Vg _n, to increase the output level by increasing the operating current of each FET. Also in this case, similarly to the processing in step S3, CPU 19, the operation current of each FET to adjust the bias voltage Vg ₁ through Vg _n to be the same.

When readjusting the bias voltage Vg ₁ through Vg _n, CPU 19 again, the operation proceeds to Step S4, the output level of the amplifier unit 10 adjusts the attenuation of the variable attenuator 11 so that the rated output, It is determined whether or not the gain of the amplifier parallel configuration stage 14 is within a predetermined range.

  On the other hand, when the gain of the amplifier parallel configuration stage 14 enters a predetermined range, the CPU 19 ends the bias voltage adjustment processing.

  Next, the processing procedure when the power amplifying apparatus 1 shown in FIG. 1 adjusts the bias voltage applied to each FET based on the IM value of the output signal will be described with reference to the flowchart shown in FIG.

  In the flowchart shown in FIG. 3, it is assumed that an allowable range (minimum value to maximum value) of the IM value is set in advance in the power amplification device 1 so as to ensure the linearity of the output signal. Further, it is assumed that the power amplifying apparatus 1 is adjusted so that the output level of each amplifier at the rated output is the same by the process shown in FIG. 2 before the process shown in FIG. 3 is started.

  The distortion compensator 30 is always supplied with the output signal of the amplification processing unit 10 taken out by the directional coupler 33. Then, the distortion detection unit 32 measures the IM value of the output signal of the amplification processing unit 10 and notifies the correction unit 31 of the measured IM value. On the other hand, the correction unit 31 is input from the outside using the output signal of the amplification processing unit 10 supplied from the directional coupler 33 so that the IM value measured by the distortion detection unit 32 becomes the best value. The original signal is corrected and output to the amplification processing unit 10.

  As shown in FIG. 3, the CPU 19 first acquires the IM value information of the output signal of the amplification processing unit 10 from the distortion detection unit 32 (step S11), and the IM value of the output signal of the amplification processing unit 10 falls within an allowable range. It is determined whether or not it is within the range (step S12).

  When the IM value is within the allowable range, the CPU 19 ends the bias voltage adjustment process.

On the other hand, if the IM value is not within the allowable range, CPU 19, as IM value falls within the allowable range, to adjust the bias voltage Vg ₁ through Vg _n with a bias control signal (Step S13). When the IM value is better than the allowable range (intermodulation distortion of the output signal is small), the CPU 19 has a sufficient distortion characteristic. Therefore, the CPU 19 reduces the bias voltage applied to each FET as a whole. The power efficiency of the amplifier parallel configuration stage 14 is increased. On the other hand, when the IM value is worse than the allowable range (the intermodulation distortion of the output signal is large), the CPU 19 increases the bias voltage applied to each FET as a whole to improve the linearity of the output power, Good characteristics. At this time, CPU 19, the process and the operating current of the FET similar step S3 in FIG. 2 to adjust the bias voltage Vg ₁ through Vg _n to be the same.

  When the bias voltage applied to each FET is changed, the gain of each FET varies, and the output level of the power amplifying apparatus 1 deviates from the rated output. Therefore, the CPU 19 acquires output level information from the output detector 18, and readjusts the attenuation amount of the variable attenuator 11 so that the output level of the amplification processing unit 10 becomes the rated output (step S14).

  When the attenuation amount of the variable attenuator 11 is readjusted, the CPU 19 proceeds to step S11 again, acquires the IM value information of the output signal of the amplification processing unit 10 from the distortion detection unit 32, and outputs the output signal of the amplification processing unit 10 It is determined whether or not the IM value is within an allowable range (step S12).

  Next, a processing procedure when the power amplifying apparatus 1 shown in FIG. 1 adjusts the drain voltage based on the IM value of the output signal will be described with reference to the flowchart shown in FIG.

  In the flowchart shown in FIG. 4, it is assumed that the allowable range of the IM value of the output signal is set in advance in the power amplification device 1. Further, before the processing shown in FIG. 4 is started, the power amplifying apparatus 1 adjusts the bias voltage applied to each FET based on the IM value of the output signal by the processing shown in FIG. It is assumed that the IM value is within an allowable range.

  Similarly to the processing shown in FIG. 3, the distortion compensator 30 of the power amplifying apparatus 1 always receives the output signal of the amplification processing unit 10 taken out by the directional coupler 33. Then, the distortion detection unit 32 measures the IM value of the output signal of the amplification processing unit 10 and notifies the correction unit 31 of the measured IM value. On the other hand, the correction unit 31 is input from the outside using the output signal of the amplification processing unit 10 supplied from the directional coupler 33 so that the IM value measured by the distortion detection unit 32 becomes the best value. The original signal is corrected and output to the amplification processing unit 10.

  As shown in FIG. 4, the CPU 19 first controls the voltage supply unit 22 using the voltage control signal so as to reduce the drain voltage Vd supplied to each FET (step S21).

  When the drain voltage Vd supplied to each FET is changed, the CPU 19 obtains output level information from the output detector 18 and readjusts the attenuation amount of the variable attenuator 11 so that the output level of the power amplifying apparatus 1 becomes the rated output. (Step S22).

  When the attenuation amount of the variable attenuator 11 is readjusted, the CPU 19 acquires IM value information of the output signal of the amplification processing unit 10 from the distortion detection unit 32 (step S23), and the IM value of the output signal of the amplification processing unit 10 is allowed. It is determined whether or not it is within the range (step S24).

  When the IM value is within the allowable range, the CPU 19 proceeds to step S21 again to control the voltage supply unit 22 using the voltage control signal so as to further reduce the drain voltage Vd supplied to each FET. To do.

  On the other hand, if the IM value is not within the allowable range, the CPU 19 returns the drain voltage Vd supplied to each FET to the voltage value set immediately before (step S25), and ends the drain voltage adjustment processing.

  In the present embodiment, an example in which each amplifier is configured by an FET is shown. However, the present invention is not limited to this. For example, each amplifier may be configured by a bipolar transistor. In this case, the current detector 21 may measure the amount of collector current flowing through the bipolar transistor of each amplifier and notify the CPU 19 of information indicating the amount of collector current. The bias applying unit 20 may apply a bias current individually to each bipolar transistor and change the amount of bias current to be supplied to each bipolar transistor in accordance with a bias control signal from the CPU 19. The voltage supply unit 22 may supply the collector voltage to the collector terminal of each bipolar transistor and change the collector voltage according to the voltage control signal from the CPU 19.

  Further, in this embodiment, an example in which each amplifier is a class AB amplifier or a class B amplifier is shown, but the present invention is not limited to this, and for example, each amplifier may be a class A amplifier. In this case as well, the power amplifying apparatus 1 may adjust the bias voltage applied to each FET so that the operation current amount of each FET is the same and the IM value falls within a predetermined range. The drain voltage may be reduced under the condition that the IM value falls within a predetermined range.

  In the present embodiment, the power amplifying apparatus 1 measures the intermodulation distortion of the output signal, and supplies the bias voltage applied to each FET and each FET so that the intermodulation distortion falls within a predetermined range. Although an example of adjusting the drain voltage is shown, the present invention is not limited to this. The information referred to for adjusting the bias voltage and the drain voltage may be any information indicating nonlinear distortion. For example, the power amplifying apparatus 1 measures the harmonic distortion of the output signal, and the harmonic distortion is measured. The bias voltage applied to each FET may be adjusted so that it falls within a predetermined range.

  In the present embodiment, the example in which the bias voltage applied to each FET is adjusted in a state where the power amplifying apparatus 1 is set to the rated output has been described, but the present invention is not limited to this. In order to make the output level of each amplifier the same during the operation of the power amplifying device 1, it is desirable to adjust the bias voltage while making the output level of the power amplifying device 1 as large as possible. It is not necessary to make 1 the rated output. For example, an output level for adjusting the bias voltage may be determined in advance, and the bias voltage may be adjusted in a state where the output level of the power amplifying apparatus 1 is set to the determined level.

  Further, for example, the power amplifying apparatus 1 always measures the amount of operating current flowing through each FET and the IM value of the output signal so that the amount of operating current of each FET becomes the same, and the IM value falls within a predetermined range. In addition, the bias voltage applied to each FET may be adjusted. In this case, the power amplifying apparatus 1 may adjust the bias voltage without changing the output level by adjusting the attenuation amount of the variable attenuator 11.

  Moreover, in this embodiment, although the example which reduces the drain voltage supplied to each FET in the state which made the power amplification apparatus 1 into the rated output was shown, this invention is not limited to this. For example, an output level for adjusting the drain voltage may be determined in advance, and the drain voltage may be adjusted in a state where the output level of the power amplifying apparatus 1 is set to the determined level. In this case, the power amplifying apparatus 1 can ensure the linearity of the output signal when operating at an output level equal to or lower than the predetermined level.

  As described above, according to the present embodiment, the power amplifying apparatus includes a plurality of amplifiers connected in parallel, the amount of operating current flowing through the amplifying elements of each amplifier is the same, and measurement of nonlinear distortion of the output signal The amount of bias applied to the amplification element of each amplifier is adjusted so that the value falls within a predetermined range.

  As a result, the power amplifying apparatus reduces the bias amount and suppresses the power consumption of each amplifier when the nonlinear distortion is sufficiently small (good) while keeping the output level of each amplifier the same, and the nonlinear distortion is large. In the case of (bad), the bias amount is increased to improve the distortion characteristics of the output signal. Therefore, in a power amplifying apparatus including a plurality of amplifiers connected in parallel, it is possible to suppress a decrease in power efficiency in the amplifier group connected in parallel while suppressing the occurrence of nonlinear distortion.

  In addition, the power amplifying apparatus according to the present embodiment adjusts the bias amount applied to the amplifying element of each amplifier in a state where the output level of the apparatus is set to a predetermined level. As a result, the power amplifying apparatus can suppress variations in the output level of each amplifier during operation without always performing adjustment processing of the bias amount applied to the amplification element of each amplifier. While suppressing an increase in processing load, a decrease in power efficiency in the amplifier group connected in parallel can be suppressed.

  In addition, the power amplifying apparatus according to the present embodiment has the output level of the self-apparatus set to a predetermined output level, and the measured value of the nonlinear distortion of the output signal falls within a predetermined range. The voltage supplied to the output terminal of the amplifying element is reduced. As a result, the power amplifying device does not always perform the adjustment process of the voltage supplied to each amplifying element, and ensures the linearity of the output signal when operating at the determined output level. The supplied voltage can be reduced. Therefore, when the power amplifying device operates at a predetermined output level, it suppresses an increase in processing load due to adjustment processing of the voltage supplied to each amplifying element, while ensuring linearity of the output signal and each amplifier. An increase in power consumption can be suppressed.

(Second Embodiment)
FIG. 5 is a diagram illustrating a configuration of the power amplification device according to the second embodiment.

As shown in FIG. 5, the power amplifying apparatus 1 according to this embodiment includes an amplifier group in which a _first amplifier 16 ₁ to an nth amplifier 16 _n are connected in parallel, and an input signal distributed to the first amplifier 16. ₁ to the nth amplifier 16 _n , the divider 15 for synthesizing the output signals of the first amplifier 16 ₁ to the nth amplifier 16 _n , and the first amplifier 16 ₁ to the nth amplifier A bias applying unit 20 that individually biases the amplifier elements of the amplifier 16 _n and a current detector 21 are current detectors that measure the amount of operating current flowing through the amplifier elements of the first amplifier 16 ₁ to the n-th amplifier 16 _n . 21, a distortion detector 32 that measures nonlinear distortion included in the signal synthesized by the synthesizer 17, and a CPU 19.

  Then, the CPU 19 acquires information indicating the amount of operating current flowing through the amplifier element of each amplifier from the current detector 21, acquires a measurement value of nonlinear distortion from the distortion detector 32, and operates the operating current of the amplifier element of each amplifier. The bias application unit 20 adjusts the amount of bias applied to the amplification element of each amplifier so that the amount is the same and the measured value of the nonlinear distortion falls within a predetermined range.

  As described above, also in the second embodiment, a power amplifying apparatus including a plurality of amplifiers connected in parallel can suppress a decrease in power efficiency in a group of amplifiers connected in parallel while suppressing the occurrence of nonlinear distortion. .

DESCRIPTION OF SYMBOLS 1 Power amplifier 10 Amplification process part 11 Variable attenuator 12 Drive amplifier 13 Input detector 14 Amplifier parallel structure stage 15 Divider 16 ₁ 1st amplifier 16 ₂ 2nd amplifier 16 ₃ 3rd amplifier 16 _n nth amplifier 17 Synthesizer 18 Output detector 19 CPU
20 Bias application unit 21 Current detector 22 Voltage supply unit 30 Strain compensator 31 Correction unit 32 Strain detection unit 33 Directional coupler 111 FET ₁
112 Power control unit 113 Rf ₁
114 i ₁
115 Vf ₁
121 FET ₂
122 OP ₂
123 Rf ₂
124 i ₂
125 Vf ₂
131 FET _n
132 OP _n
133 Rf _n
134 i _n
135 Vf _n
144 I

Claims (6)

A power amplification device that amplifies an input signal to a desired power,
An amplifier group in which a plurality of amplifiers are connected in parallel;
Distributing means for distributing an input signal to supply the plurality of amplifiers;
Combining means for combining the output signals of the plurality of amplifiers;
Bias applying means for individually biasing the amplifying element of each amplifier;
Current detection means for measuring the amount of current flowing through the amplification element of each amplifier;
Distortion detection means for measuring nonlinear distortion included in the signal synthesized by the synthesis means;
While obtaining information indicating the amount of current flowing through the amplification element of each amplifier from the current detection means, obtaining a measurement value of the nonlinear distortion from the distortion detection means, the current amount of the amplification element of each amplifier becomes the same, Control means for adjusting the amount of bias applied by the bias applying means to the amplifying element of each amplifier so that the measured value of the nonlinear distortion falls within a predetermined range;
A power amplifying apparatus. The power amplifying device according to claim 1,
The control means adjusts the bias amount in a state where the level of the output signal of the power amplifying apparatus is set to a predetermined level. In the power amplification device according to claim 2,
Voltage supply means for supplying a voltage to the output terminals of the amplifying elements of the plurality of amplifiers;
The control means is a voltage supplied by the voltage supply means under the condition that the measured value of the nonlinear distortion falls within the predetermined range in a state where the level of the output signal of the power amplification device is set to a predetermined level. A power amplifying apparatus that controls the voltage supply means so as to reduce the noise. A method for controlling a power amplifying apparatus comprising a plurality of amplifiers connected in parallel,
Measure the amount of current flowing through the amplifier element of each amplifier,
Measure nonlinear distortion included in the output signal of the power amplifier,
A control method for individually adjusting the amount of bias applied to the amplifying element of each amplifier so that the current amount of the amplifying element of each amplifier is the same and the measured value of the nonlinear distortion is within a predetermined range. The control method according to claim 4, wherein
A control method comprising adjusting the bias amount in a state where the level of the output signal of the power amplifying apparatus is set to a predetermined level. The control method according to claim 5, wherein
Supplying to the output terminals of the amplifier elements of the plurality of amplifiers under the condition that the measured value of the nonlinear distortion falls within the predetermined range in a state where the level of the output signal of the power amplification device is set to a predetermined level. The control method characterized by reducing the voltage to perform.

Images