JP2011191754A - 表示装置及び電子機器 - Google Patents
表示装置及び電子機器 Download PDFInfo
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- JP2011191754A JP2011191754A JP2011031880A JP2011031880A JP2011191754A JP 2011191754 A JP2011191754 A JP 2011191754A JP 2011031880 A JP2011031880 A JP 2011031880A JP 2011031880 A JP2011031880 A JP 2011031880A JP 2011191754 A JP2011191754 A JP 2011191754A
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- Prior art keywords
- transistor
- wiring
- gate
- electrically connected
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Links
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Images
Classifications
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1225—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
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Abstract
【解決手段】酸化物半導体によりチャネル領域が形成されるトランジスタをプルダウントランジスタとして適用する。当該酸化物半導体は、2.0eV以上、好ましくは2.5eV以上、より好ましくは3.0eV以上のバンドギャップを有する。そのため、トランジスタにおけるホットキャリア劣化を抑制することができる。その結果、当該プルダウントランジスタを有する半導体装置の回路規模を縮小することができる。また、プルアップトランジスタのゲートを、当該トランジスタのスイッチングによって浮遊状態とする。なお、当該酸化物半導体を高純度化することで、トランジスタのオフ電流を1aA/μm(1×10−18A/μm)以下とすることが可能である。その結果、半導体装置の駆動能力の向上が図れる。
【選択図】図1
Description
本実施の形態では、本発明の一態様である表示装置に係わる回路について説明する。
トランジスタ103は、配線113とノード11との間の導通状態を制御するスイッチとしての機能を有する。トランジスタ104は、配線114とノード11との間の導通状態を制御するスイッチとしての機能を有する。また、トランジスタ104は、入力端子が配線114と接続され、出力端子がノード11と接続されたダイオードとしての機能を有する。トランジスタ105は、配線113とノード11との間の導通状態を制御するスイッチとしての機能を有する。トランジスタ201は、配線116とノード12との間の導通状態を制御するスイッチとしての機能を有する。また、トランジスタ201は、第2の端子とゲートとの容量結合により、ノード21の電位を上昇させるタイミングを制御する機能を有する。トランジスタ202は、配線113とノード12との間の導通状態を制御するスイッチとしての機能を有する。トランジスタ203は、配線116とのノード12との間の導通状態を制御するスイッチとしての機能を有する。また、トランジスタ203は、入力端子が配線116と接続され、出力端子がノード21と接続されたダイオードとしての機能を有する。トランジスタ204は、配線113とノード21との間の導通状態を制御するスイッチとしての機能を有する。
本実施の形態では、本発明の一態様である表示装置に係わるシフトレジスタ回路について説明する。本実施の形態のシフトレジスタ回路は、実施の形態1で説明される回路を含むことができる。また、本実施の形態のシフトレジスタ回路は、ゲートドライバ回路及び/又はソースドライバ回路等の表示装置の駆動回路に用いることができる。
本実施の形態では、実施の形態1又は2で説明される回路を構成するトランジスタの一例について説明する。具体的には、チャネル領域が酸化物半導体によって形成されるトランジスタの構造及び作製工程の一例について説明する。
本実施の形態では、本発明の一態様に係わる表示装置の例について説明する。
本実施の形態においては、電子機器の例について説明する。
12 ノード
21 ノード
101 トランジスタ
102 トランジスタ
103 トランジスタ
104 トランジスタ
105 トランジスタ
111 配線
112 配線
113 配線
114 配線
115 配線
116 配線
117 配線
118 配線
121 トランジスタ
122 トランジスタ
123 トランジスタ
124 トランジスタ
125 トランジスタ
126 容量素子
200 回路
201 トランジスタ
202 トランジスタ
203 トランジスタ
204 トランジスタ
301 回路
311 配線
312 配線
313 配線
314 配線
315 配線
400 基板
402 ゲート絶縁層
403 保護絶縁層
410 トランジスタ
411 ゲート電極層
415a ソース電極層
415b ドレイン電極層
416 酸化物絶縁層
430 酸化物半導体膜
431 酸化物半導体層
5000 筐体
5001 表示部
5002 第2表示部
5003 スピーカ
5004 LEDランプ
5005 操作キー
5006 接続端子
5007 センサ
5008 マイクロフォン
5009 スイッチ
5010 赤外線ポート
5011 記録媒体読込部
5012 支持部
5013 イヤホン
5015 シャッターボタン
5016 受像部
5017 充電器
5018 支持台
5019 外部接続ポート
5020 ポインティングデバイス
5021 リーダ/ライタ
5022 筐体
5023 表示部
5024 リモコン装置
5025 スピーカ
5026 表示パネル
5027 ユニットバス
5028 表示パネル
5029 車体
5030 天井
5031 表示パネル
5032 ヒンジ部
5360 タイミングコントローラ
5361 回路
5362 回路
5362a 回路
5362b 回路
5363_1 回路
5363_2 回路
5364 画素部
5367 画素
5371 ソース信号線
5372 ゲート信号線
5380 基板
5381 端子
Claims (6)
- 複数のゲート信号線と、複数のソース信号線と、前記ゲート信号線と前記ソース信号線との交差領域に各々配置される画素と、前記複数のゲート信号線と電気的に接続されるゲートドライバ回路とを有し、
前記ゲートドライバ回路は、第1のトランジスタと、第2のトランジスタと、インバータ回路とを有し、
前記第1のトランジスタの第1の端子は、第1の配線と電気的に接続され、前記第1のトランジスタの第2の端子は、第2の配線と電気的に接続され、
前記第2のトランジスタの第1の端子は、第3の配線と電気的に接続され、前記第2のトランジスタの第2の端子は、前記第2の配線と電気的に接続され、
前記インバータ回路の入力端子は、前記第1のトランジスタのゲートと電気的に接続され、前記インバータ回路の出力端子は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタ及び前記第2のトランジスタは、酸化物半導体によりチャネル領域が形成され、
前記第1のトランジスタ及び前記第2のトランジスタのオフ電流が1aA/μm以下である表示装置。 - 複数のゲート信号線と、複数のソース信号線と、前記ゲート信号線と前記ソース信号線との交差領域に各々配置される画素と、前記複数のゲート信号線と電気的に接続されるゲートドライバ回路とを有し、
前記ゲートドライバ回路は、第1のトランジスタと、第2のトランジスタと、インバータ回路とを有し、
前記第1のトランジスタの第1の端子は、第1の配線と電気的に接続され、前記第1のトランジスタの第2の端子は、第2の配線と電気的に接続され、
前記第2のトランジスタの第1の端子は、第3の配線と電気的に接続され、前記第2のトランジスタの第2の端子は、前記第1のトランジスタのゲートと電気的に接続され、
前記インバータ回路の入力端子は、前記第1のトランジスタのゲートと電気的に接続され、前記インバータ回路の出力端子は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタ及び前記第2のトランジスタは、酸化物半導体によりチャネル領域が形成され、
前記第1のトランジスタ及び前記第2のトランジスタのオフ電流が1aA/μm以下である表示装置。 - 複数のゲート信号線と、複数のソース信号線と、前記ゲート信号線と前記ソース信号線との交差領域に各々配置される画素と、前記複数のゲート信号線と電気的に接続されるゲートドライバ回路とを有し、
前記ゲートドライバ回路は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、インバータ回路とを有し、
前記第1のトランジスタの第1の端子は、第1の配線と電気的に接続され、前記第1のトランジスタの第2の端子は、第2の配線と電気的に接続され、
前記第2のトランジスタの第1の端子は、第3の配線と電気的に接続され、前記第2のトランジスタの第2の端子は、前記第2の配線と電気的に接続され、
前記第3のトランジスタの第1の端子は、第4の配線と電気的に接続され、前記第3のトランジスタの第2の端子は、前記第1のトランジスタのゲートと電気的に接続され、前記第3のトランジスタのゲートは、前記第4の配線と電気的に接続され、
前記インバータ回路の入力端子は、前記第1のトランジスタのゲートと電気的に接続され、前記インバータ回路の出力端子は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタ乃至前記第3のトランジスタは、酸化物半導体によりチャネル領域が形成され、
前記第1のトランジスタ乃至前記第3のトランジスタのオフ電流が1aA/μm以下である表示装置。 - 複数のゲート信号線と、複数のソース信号線と、前記ゲート信号線と前記ソース信号線との交差領域に各々配置される画素と、前記複数のゲート信号線と電気的に接続されるゲートドライバ回路とを有し、
前記ゲートドライバ回路は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、インバータ回路とを有し、
前記第1のトランジスタの第1の端子は、第1の配線と電気的に接続され、前記第1のトランジスタの第2の端子は、第2の配線と電気的に接続され、
前記第2のトランジスタの第1の端子は、第3の配線と電気的に接続され、前記第2のトランジスタの第2の端子は、前記第2の配線と電気的に接続され、
前記第3のトランジスタの第1の端子は、前記第3の配線と電気的に接続され、前記第3のトランジスタの第2の端子は、前記第1のトランジスタのゲートと電気的に接続され、前記第3のトランジスタのゲートは、第4の配線と電気的に接続され、
前記インバータ回路の入力端子は、前記第1のトランジスタのゲートと電気的に接続され、前記インバータ回路の出力端子は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタ乃至前記第3のトランジスタは、酸化物半導体によりチャネル領域が形成され、
前記第1のトランジスタ乃至前記第3のトランジスタのオフ電流が1aA/μm以下である表示装置。 - 複数のゲート信号線と、複数のソース信号線と、前記ゲート信号線と前記ソース信号線との交差領域に各々配置される画素と、前記複数のゲート信号線と電気的に接続されるゲートドライバ回路とを有し、
前記ゲートドライバ回路は、第1のトランジスタと、第2のトランジスタと、第3のトランジスタと、第4のトランジスタと、インバータ回路とを有し、
前記第1のトランジスタの第1の端子は、第1の配線と電気的に接続され、前記第1のトランジスタの第2の端子は、第2の配線と電気的に接続され、
前記第2のトランジスタの第1の端子は、第3の配線と電気的に接続され、前記第2のトランジスタの第2の端子は、前記第2の配線と電気的に接続され、
前記第3のトランジスタの第1の端子は、第4の配線と電気的に接続され、前記第3のトランジスタの第2の端子は、前記第1のトランジスタのゲートと電気的に接続され、前記第3のトランジスタのゲートは、前記第4の配線と電気的に接続され、
前記第4のトランジスタの第1の端子は、前記第3の配線と電気的に接続され、前記第4のトランジスタの第2の端子は、前記第1のトランジスタのゲートと電気的に接続され、前記第4のトランジスタのゲートは、第5の配線と電気的に接続され、
前記インバータ回路の入力端子は、前記第1のトランジスタのゲートと電気的に接続され、前記インバータ回路の出力端子は、前記第2のトランジスタのゲートと電気的に接続され、
前記第1のトランジスタ乃至前記第4のトランジスタは、酸化物半導体によりチャネル領域が形成され、
前記第1のトランジスタ乃至前記第4のトランジスタのオフ電流が1aA/μm以下である表示装置。 - 請求項1乃至請求項5のいずれか一項に記載の表示装置と、前記表示装置の画像を操作する操作スイッチとを具備する電子機器。
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