JP2011181830A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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JP2011181830A
JP2011181830A JP2010046832A JP2010046832A JP2011181830A JP 2011181830 A JP2011181830 A JP 2011181830A JP 2010046832 A JP2010046832 A JP 2010046832A JP 2010046832 A JP2010046832 A JP 2010046832A JP 2011181830 A JP2011181830 A JP 2011181830A
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wiring
semiconductor device
insulating substrate
semiconductor
metal layer
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Yuji Negishi
祐司 根岸
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Casio Computer Co Ltd
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Casio Computer Co Ltd
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    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
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    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
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    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
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    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/19—Manufacturing methods of high density interconnect preforms
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    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
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    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92142—Sequential connecting processes the first connecting process involving a layer connector
    • H01L2224/92144—Sequential connecting processes the first connecting process involving a layer connector the second connecting process involving a build-up interconnect
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    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
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    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
    • H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip

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Abstract

<P>PROBLEM TO BE SOLVED: To stabilize an electric connection between a semiconductor construction, called a CSP, and wiring of a printed wiring board in a semiconductor device provided with the semiconductor construction on the printed wiring board. <P>SOLUTION: One end of a base metal layer 26, formed by electroless plating etc., of fourth wiring 24 of the printed wiring board 21 is connected to a land 13a of second wiring 13 provided on a lower surface of a sealing film 12 including a columnar electrode (projection electrode) 11 of the semiconductor construction 1 through electric conduction holes 33 and 35 of a film substrate (insulating substrate) 22. In this case, the connection is made by the electroless plating etc., so that the electric connection is stabilized. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

この発明は半導体装置およびその製造方法に関する。   The present invention relates to a semiconductor device and a manufacturing method thereof.

従来の半導体装置には、半導体チップをプリント配線板上に実装したものがある（例えば、特許文献１参照）。この場合、プリント配線板は、フィルム基板の上面に上層配線が設けられ、フィルム基板の下面に下層配線が設けられ、下層配線がフィルム基板に設けられた導通用孔を介して上層配線に接続されたものからなっている。そして、半導体チップは、その下面に設けられた突起電極をプリント配線板の上層配線に接続された状態で、プリント配線板上に実装されている。プリント配線板の下層配線の下面には半田ボールが設けられている。   Some conventional semiconductor devices include a semiconductor chip mounted on a printed wiring board (see, for example, Patent Document 1). In this case, the printed wiring board is provided with an upper layer wiring on the upper surface of the film substrate, a lower layer wiring is provided on the lower surface of the film substrate, and the lower layer wiring is connected to the upper layer wiring through a conduction hole provided in the film substrate. It consists of things. The semiconductor chip is mounted on the printed wiring board with the protruding electrodes provided on the lower surface thereof connected to the upper layer wiring of the printed wiring board. Solder balls are provided on the lower surface of the lower layer wiring of the printed wiring board.

特開２００３−１３３４８３号公報JP 2003-133383 A

ところで、上記従来の半導体装置では、半導体チップをプリント配線板上にマウントして実装しているので（特許文献１の第２１段落参照）、半導体チップの下面に設けられた突起電極とプリント配線板の上層配線との接続が単なる面接触となり、その間の電気的接続が不安定となってしまうという問題がある。   By the way, in the conventional semiconductor device, since the semiconductor chip is mounted and mounted on the printed wiring board (see the 21st paragraph of Patent Document 1), the protruding electrode and the printed wiring board provided on the lower surface of the semiconductor chip. There is a problem that the connection with the upper layer wiring is merely a surface contact, and the electrical connection therebetween becomes unstable.

そこで、この発明は、プリント配線板上に実装された半導体チップ等からなる半導体構成体とプリント配線板の配線との間の電気的接続を安定化することができる半導体装置およびその製造方法を提供することを目的とする。   Accordingly, the present invention provides a semiconductor device capable of stabilizing electrical connection between a semiconductor structure made of a semiconductor chip or the like mounted on a printed wiring board and the wiring of the printed wiring board, and a method for manufacturing the same. The purpose is to do.

請求項１に記載の発明に係る半導体装置は、半導体基板と、接続パッドと、該接続パッドに接続された第１の配線と、該第１の配線と電気的に接続された第２の配線と、を有する半導体構成体と、前記第２の配線を覆う接着層と、前記半導体構成体および前記接着層の周側面を覆い、且つ前記半導体構成体の下面を覆う外部封止膜と、を備えていることを特徴とするものである。
請求項２に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体および前記外部封止膜の上面に設けられた絶縁性基板と、該絶縁性基板および前記接着層に設けられた導通用孔を介して前記第２の配線に接続された第４の配線と、を備え、前記第４の配線は、前記絶縁性基板の一面に設けられた、金属層、下地金属層および上部金属層からなる３層構造であり、前記下地金属層が前記導通用孔を介して前記半導体構成体の第２の配線のランドに接続されていることを特徴とするものである。
請求項３に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体および前記外部封止膜の上面に設けられた絶縁性基板と、該絶縁性基板および前記接着層に設けられた導通用孔を介して前記第２の配線に接続された第４の配線と、を備え、前記第４の配線は、前記絶縁性基板の一面に設けられた下地金属層および上部金属層からなる２層構造であり、前記下地金属層が前記導通用孔を介して前記半導体構成体の第２の配線のランドに接続されていることを特徴とするものである。
請求項４に記載の発明に係る半導体装置は、請求項２または３に記載の発明において、前記絶縁性基板の他面に第３の配線が設けられていることを特徴とするものである。
請求項５に記載の発明に係る半導体装置は、請求項４に記載の発明において、前記導通用孔は前記第３の配線を貫通して設けられ、前記第４の配線は前記導通用孔を介して前記第３の配線にも接続されていることを特徴とするものである。
請求項６に記載の発明に係る半導体装置は、請求項４に記載の発明において、前記第３の配線と前記第４の配線とは、前記導通用孔が設けられた領域以外の領域における前記絶縁性基板に設けられたスルーホール導通部を介して接続されていることを特徴とするものである。
請求項７に記載の発明に係る半導体装置は、請求項４に記載の発明において、前記絶縁性基板の前記第３の配線が設けられた面に、薄膜誘導素子が設けられていることを特徴とするものである。
請求項８に記載の発明に係る半導体装置は、請求項１に記載の発明において、前記半導体構成体は、前記第１の配線に接続された突起電極および該突起電極の周囲に設けられた封止膜を有し、前記第２の配線は前記突起電極を含む前記封止膜の外部に設けられていることを特徴とするものである。
請求項９に記載の発明に係る半導体装置は、請求項２乃至４、６、７に記載の発明において、前記絶縁性基板は、ガラス布基材エポキシ系樹脂、ガラス布基材ポリイミド系樹脂のいずれかからなることを特徴とするものである。
請求項１０に記載の発明に係る半導体装置の製造方法は、半導体基板と、接続パッドと、該接続パッドに接続された第１の配線と、該第１の配線と電気的に接続された第２の配線と、を有する半導体構成体を形成する工程と、前記第２の配線を覆う接着層を形成する工程と、前記半導体構成体および前記接着層の周側面を覆い、且つ前記半導体構成体の下面を覆う外部封止膜を形成する工程と、を有することを特徴とするものである。
請求項１１に記載の発明に係る半導体装置の製造方法は、半導体基板と第２の配線とを有する半導体構成体と、絶縁性基板と、を準備する工程と、前記絶縁性基板と、前記半導体構成体と、を接着層を介して接着する工程と、前記第２の配線のランドに対応する部分における前記絶縁性基板および前記接着層に、導通用孔を形成する工程と、前記導通用孔内を含む前記絶縁性基板の一面に下地金属層を形成する工程と、前記下地金属層上に上部金属層を形成する工程と、を有することを特徴とするものである。
請求項１２に記載の発明に係る半導体装置の製造方法は、請求項１１に記載の発明において、準備された前記絶縁性基板の一面には予め金属層が設けられていることを特徴とするものである。
請求項１３に記載の発明に係る半導体装置の製造方法は、請求項１１に記載の発明において、前記絶縁性基板の他面に第３の配線が予め形成されていることを特徴とするものである。
請求項１４に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記導通用孔を形成する工程は、前記第３の配線に導通用孔を形成する工程を含むことを特徴とするものである。
請求項１５に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記第３の配線と前記第４の配線とは、前記導通用孔が形成される領域以外の領域における前記絶縁性基板に設けられたスルーホール導通部を介して接続されていることを特徴とするものである。
請求項１６に記載の発明に係る半導体装置の製造方法は、請求項１３に記載の発明において、前記絶縁性基板の前記第３の配線が設けられた面に、薄膜誘導素子が形成されていることを特徴とするものである。
請求項１７に記載の発明に係る半導体装置の製造方法は、請求項１０または１１に記載の発明において、前記半導体構成体は、前記配線に接続された突起電極および該突起電極の周囲に設けられた封止膜を有し、前記第２の配線は前記突起電極を含む前記封止膜の外部に設けられていることを特徴とするものである。
請求項１８に記載の発明に係る半導体装置の製造方法は、請求項１１乃至１３、１５、１６に記載の発明において、前記絶縁性基板は、ガラス布基材エポキシ系樹脂、ガラス布基材ポリイミド系樹脂のいずれかからなることを特徴とするものである。 According to a first aspect of the present invention, a semiconductor device includes a semiconductor substrate, a connection pad, a first wiring connected to the connection pad, and a second wiring electrically connected to the first wiring. And an external sealing film that covers a peripheral side surface of the semiconductor structure and the adhesive layer, and covers a lower surface of the semiconductor structure. It is characterized by having.
According to a second aspect of the present invention, there is provided a semiconductor device according to the first aspect of the present invention, wherein the semiconductor substrate and the external sealing film are provided on an insulating substrate, the insulating substrate, and the adhesion. A fourth wiring connected to the second wiring through a conduction hole provided in the layer, and the fourth wiring is a metal layer provided on one surface of the insulating substrate, A three-layer structure comprising a base metal layer and an upper metal layer, wherein the base metal layer is connected to a land of a second wiring of the semiconductor structure through the conduction hole. is there.
According to a third aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the semiconductor substrate and the insulating substrate provided on the top surfaces of the external sealing film, the insulating substrate, and the adhesion are provided. And a fourth wiring connected to the second wiring via a conduction hole provided in the layer, the fourth wiring including a base metal layer provided on one surface of the insulating substrate and It has a two-layer structure composed of an upper metal layer, and the base metal layer is connected to the land of the second wiring of the semiconductor structure through the hole for conduction.
A semiconductor device according to a fourth aspect of the present invention is the semiconductor device according to the second or third aspect, wherein a third wiring is provided on the other surface of the insulating substrate.
According to a fifth aspect of the present invention, in the semiconductor device according to the fourth aspect, the conduction hole is provided through the third wiring, and the fourth wiring is provided with the conduction hole. Further, it is also connected to the third wiring.
The semiconductor device according to a sixth aspect of the present invention is the semiconductor device according to the fourth aspect, wherein the third wiring and the fourth wiring are in the region other than the region where the hole for conduction is provided. It is connected through a through-hole conducting portion provided on the insulating substrate.
A semiconductor device according to a seventh aspect of the present invention is the semiconductor device according to the fourth aspect, wherein a thin film induction element is provided on a surface of the insulating substrate on which the third wiring is provided. It is what.
According to an eighth aspect of the present invention, there is provided the semiconductor device according to the first aspect, wherein the semiconductor structure includes a protruding electrode connected to the first wiring and a seal provided around the protruding electrode. It has a stop film, and the second wiring is provided outside the sealing film including the protruding electrode.
A semiconductor device according to a ninth aspect of the present invention is the semiconductor device according to the second to fourth, sixth, or seventh aspect, wherein the insulating substrate is made of a glass cloth base epoxy resin or a glass cloth base polyimide resin. It consists of either.
According to a tenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device, comprising: a semiconductor substrate; a connection pad; a first wiring connected to the connection pad; and a first wiring electrically connected to the first wiring. A step of forming a semiconductor structure having two wirings; a step of forming an adhesive layer that covers the second wiring; and a peripheral surface of the semiconductor structure and the adhesive layer; and the semiconductor structure Forming an external sealing film covering the lower surface of the substrate.
A method of manufacturing a semiconductor device according to an eleventh aspect includes a step of preparing a semiconductor structure having a semiconductor substrate and a second wiring, and an insulating substrate, the insulating substrate, and the semiconductor A step of bonding the structure through an adhesive layer, a step of forming a conductive hole in the insulating substrate and the adhesive layer in a portion corresponding to the land of the second wiring, and the conductive hole The method includes a step of forming a base metal layer on one surface of the insulating substrate including the inside, and a step of forming an upper metal layer on the base metal layer.
According to a twelfth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the eleventh aspect, wherein a metal layer is provided in advance on one surface of the prepared insulating substrate. It is.
According to a thirteenth aspect of the present invention, there is provided a method for manufacturing a semiconductor device according to the eleventh aspect, wherein a third wiring is formed in advance on the other surface of the insulating substrate. is there.
According to a fourteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect, the step of forming the conduction hole includes a step of forming a conduction hole in the third wiring. It is characterized by this.
According to a fifteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect of the present invention, the third wiring and the fourth wiring are other than the region where the hole for conduction is formed. It is connected through a through-hole conducting part provided in the insulating substrate in the region.
According to a sixteenth aspect of the present invention, in the semiconductor device manufacturing method according to the thirteenth aspect of the present invention, a thin film induction element is formed on the surface of the insulating substrate on which the third wiring is provided. It is characterized by this.
According to a seventeenth aspect of the present invention, there is provided a semiconductor device manufacturing method according to the tenth or eleventh aspect, wherein the semiconductor structure is provided around a protruding electrode connected to the wiring and the protruding electrode. The second wiring is provided outside the sealing film including the protruding electrodes.
The method of manufacturing a semiconductor device according to claim 18 is the method according to claim 11, wherein the insulating substrate is made of glass cloth base epoxy resin, glass cloth base polyimide. It is characterized by being made of any one of resin.

この発明によれば、絶縁性基板および接着層に設けられた導通用孔を介して半導体構成体の第２の配線のランドに接続される第４の配線の少なくとも一部をメッキにより形成することにより、絶縁性基板上に実装された半導体構成体と絶縁性基板の第４の配線との間の電気的接続を安定化することができる。また、半導体構成体の封止膜および接着層の周側面は外部封止膜によって覆われているので、これらの周側面が保護され、従って、熱や衝撃があった場合でも、半導体構成体の封止膜と接着層との界面にクラックが発生することはない。   According to this invention, at least a part of the fourth wiring connected to the land of the second wiring of the semiconductor structure is formed by plating through the insulating substrate and the conduction hole provided in the adhesive layer. Thereby, the electrical connection between the semiconductor structure mounted on the insulating substrate and the fourth wiring of the insulating substrate can be stabilized. Further, since the sealing film of the semiconductor structure and the peripheral side surface of the adhesive layer are covered with the external sealing film, these peripheral side surfaces are protected, and therefore, even when there is heat or impact, the semiconductor structure Cracks do not occur at the interface between the sealing film and the adhesive layer.

この発明の第１実施形態としての半導体装置の平面図。1 is a plan view of a semiconductor device as a first embodiment of the present invention. 図１のII−II線にほぼ沿う部分の断面図。Sectional drawing of the part which follows the II-II line of FIG. 図１および図２に示す半導体装置の製造方法の一例において、当初準備したものの断面図。Sectional drawing of what was initially prepared in an example of the manufacturing method of the semiconductor device shown in FIG.1 and FIG.2. 図３に示すフィルム基板の一部の平面図。The top view of a part of film substrate shown in FIG. 図３に続く工程の断面図。Sectional drawing of the process following FIG. 図５に続く工程の断面図。Sectional drawing of the process following FIG. 図６に続く工程の断面図。Sectional drawing of the process following FIG. 図７に続く工程の断面図。Sectional drawing of the process following FIG. 図８に続く工程の断面図。FIG. 9 is a cross-sectional view of the process following FIG. 8. 図９に続く工程の断面図。Sectional drawing of the process following FIG. 図１０に続く工程の断面図。Sectional drawing of the process following FIG. この発明の第２実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 2nd Embodiment of this invention. この発明の第３実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 3rd Embodiment of this invention. 図１３に示す半導体装置の薄膜誘導素子の部分の平面図。FIG. 14 is a plan view of a thin film induction element portion of the semiconductor device shown in FIG. 13. この発明の第４実施形態としての半導体装置の断面図。Sectional drawing of the semiconductor device as 4th Embodiment of this invention.

（第１実施形態）
図１はこの発明の第１実施形態としての半導体装置の平面図を示し、図２は図１のII−II線にほぼ沿う部分の断面図を示す。この半導体装置では、半導体構成体１がプリント配線板２１上の中央部に実装されている。まず、半導体構成体１について説明する。半導体構成体１は、一般的にはＣＳＰ(chip size package)と呼ばれるものであり、平面方形状のシリコン基板（半導体基板）２を備えている。 (First embodiment)
FIG. 1 is a plan view of a semiconductor device as a first embodiment of the present invention, and FIG. 2 is a cross-sectional view of a portion substantially along the line II-II in FIG. In this semiconductor device, the semiconductor structure 1 is mounted on the central portion on the printed wiring board 21. First, the semiconductor structure 1 will be described. The semiconductor structure 1 is generally called a CSP (chip size package), and includes a planar rectangular silicon substrate (semiconductor substrate) 2.

シリコン基板２の下面には、図示していないが、所定の機能の集積回路を構成する素子、例えば、トランジスタ、ダイオード、抵抗、コンデンサ等の素子が形成されている。シリコン基板１の下面周辺部には、上記集積回路の各素子に接続されたアルミニウム系金属等からなる複数の接続パッド３が設けられている。   Although not shown, elements constituting an integrated circuit having a predetermined function, such as transistors, diodes, resistors, and capacitors, are formed on the lower surface of the silicon substrate 2. A plurality of connection pads 3 made of an aluminum-based metal or the like connected to each element of the integrated circuit are provided on the lower surface periphery of the silicon substrate 1.

シリコン基板２の周辺部および接続パッド３の中央部を除くシリコン基板２の下面には酸化シリコン、窒化シリコン等からなるパッシベーション膜４が設けられ、接続パッド３の中央部はパッシベーション膜４に設けられた開口部５を介して露出されている。パッシベーション膜４の下面にはポリイミド系樹脂等からなる保護膜６が設けられている。パッシベーション膜４の開口部５に対応する部分における保護膜６には開口部７が設けられている。   A passivation film 4 made of silicon oxide, silicon nitride or the like is provided on the lower surface of the silicon substrate 2 excluding the peripheral portion of the silicon substrate 2 and the central portion of the connection pad 3, and the central portion of the connection pad 3 is provided on the passivation film 4. It is exposed through the opening 5. A protective film 6 made of polyimide resin or the like is provided on the lower surface of the passivation film 4. An opening 7 is provided in the protective film 6 in a portion corresponding to the opening 5 of the passivation film 4.

保護膜６の下面には複数の第１の配線８が設けられている。第１の配線８は、保護膜６の下面に設けられた銅からなる下地金属層９と、下地金属層９の下面に設けられた銅からなる上部金属層１０との２層構造となっている。第１の配線８の一端部は、パッシベーション膜４および保護膜６の開口部５、７を介して接続パッド３に接続されている。   A plurality of first wirings 8 are provided on the lower surface of the protective film 6. The first wiring 8 has a two-layer structure of a base metal layer 9 made of copper provided on the lower surface of the protective film 6 and an upper metal layer 10 made of copper provided on the lower surface of the base metal layer 9. Yes. One end of the first wiring 8 is connected to the connection pad 3 through the openings 5 and 7 of the passivation film 4 and the protective film 6.

ここで、図１に示すように、第１の配線８は、接続パッド３に接続された端部８ａと、後述する柱状電極（突起電極）１１の台座となる平面円形状のランド８ｂと、その間の引き回し線部８ｃとからなっている。そして、第１の配線８のランド８ｂは保護膜６の下面にマトリクス状に配置されている。   Here, as shown in FIG. 1, the first wiring 8 includes an end portion 8 a connected to the connection pad 3, a planar circular land 8 b that serves as a pedestal of a columnar electrode (projection electrode) 11 described later, It is composed of a lead wire portion 8c between them. The lands 8 b of the first wiring 8 are arranged in a matrix on the lower surface of the protective film 6.

第１の配線８のランド８ｂ下面には銅からなる平面円形状の柱状電極１１が設けられている。シリコン基板２の周辺部下面、第１の配線８を含む保護膜６の下面において柱状電極１１の周囲にはシリカフィラーを含むエポキシ系樹脂からなる封止膜１２が設けられている。ここで、柱状電極１１は、その下面が封止膜１２の下面と面一乃至封止膜１２より数μｍ凹むように設けられている。 A planar circular columnar electrode 11 made of copper is provided on the lower surface of the land 8 b of the first wiring 8. A sealing film 12 made of an epoxy resin containing silica filler is provided around the columnar electrode 11 on the lower surface of the peripheral portion of the silicon substrate 2 and the lower surface of the protective film 6 including the first wiring 8. Here, the columnar electrode 11 is provided such that its lower surface is flush with the lower surface of the sealing film 12 or is recessed by several μm from the sealing film 12.

柱状電極１１を含む封止膜１２の下面には複数の第２の配線１３が設けられている。第２の配線１３は、柱状電極１１を含む封止膜１２の下面に設けられた銅からなる下地金属層１４と、下地金属層１４の下面に設けられた銅からなる上部金属層１５との２層構造となっている。第２の配線１３の一端部は柱状電極１１に接続されている。第２の配線１３の他端部は、封止膜１２の下面周辺部に配置され、ランド１３ａとなっている。この場合、第２の配線１３のランド１３ａは、接続パッド３と同数であり、平面的に見て接続パッド３と同じ位置に配置されているが、これに限定されるものではない。 A plurality of second wirings 13 are provided on the lower surface of the sealing film 12 including the columnar electrode 11. The second wiring 13 includes a base metal layer 14 made of copper provided on the lower surface of the sealing film 12 including the columnar electrode 11 and an upper metal layer 15 made of copper provided on the lower surface of the base metal layer 14. It has a two-layer structure. One end of the second wiring 13 is connected to the columnar electrode 11. The other end portion of the second wiring 13 is disposed in the periphery of the lower surface of the sealing film 12 and serves as a land 13a. In this case, the number of the lands 13a of the second wiring 13 is the same as the number of the connection pads 3 and is arranged at the same position as the connection pads 3 in plan view, but the present invention is not limited to this.

次に、プリント配線板２１について説明する。プリント配線板２１は、ガラス布にエポキシやポリイミド等の樹脂を含浸させた、ガラス布基材エポキシ系樹脂、ガラス布基材ポリイミド系樹脂等からなるプリプレグ（樹脂含浸基材）である平面方形状のフィルム基板（絶縁性基板）２２を備えている。フィルム基板２２の平面サイズは半導体構成体１の平面サイズよりもある程度大きくなっている。フィルム基板２２の上面には銅箔からなる複数の第３の配線２３が設けられている。 Next, the printed wiring board 21 will be described. The printed wiring board 21 is a planar rectangular shape that is a prepreg (resin-impregnated base material) made of glass cloth base epoxy resin, glass cloth base polyimide resin, or the like obtained by impregnating glass cloth with a resin such as epoxy or polyimide. The film substrate (insulating substrate) 22 is provided. The planar size of the film substrate 22 is somewhat larger than the planar size of the semiconductor structure 1. A plurality of third wirings 23 made of copper foil are provided on the upper surface of the film substrate 22.

フィルム基板２２の下面には複数の第４の配線２４が設けられている。第４の配線２４は、フィルム基板２２の下面に設けられた銅箔からなる金属層２５と、金属層２５の下面に設けられた銅からなる下地金属層２６と、下地金属層２６の下面に設けられた銅からなる上部金属層２７との３層構造となっている。このうち、金属層２５および下地金属層２６の詳細については後で説明する。   A plurality of fourth wirings 24 are provided on the lower surface of the film substrate 22. The fourth wiring 24 includes a metal layer 25 made of copper foil provided on the lower surface of the film substrate 22, a base metal layer 26 made of copper provided on the lower surface of the metal layer 25, and a lower surface of the base metal layer 26. It has a three-layer structure with an upper metal layer 27 made of copper. Among these, details of the metal layer 25 and the base metal layer 26 will be described later.

第４の配線２４を含むフィルム基板２２の下面にはソルダーレジスト等からなるオーバーコート膜２８が設けられている。第４の配線２４のランドに対応する部分におけるオーバーコート膜２８には開口部２９が設けられている。開口部２９内およびその下方には半田ボール３０が第４の配線２４のランドに接続されて設けられている。   An overcoat film 28 made of a solder resist or the like is provided on the lower surface of the film substrate 22 including the fourth wiring 24. An opening 29 is provided in the overcoat film 28 in a portion corresponding to the land of the fourth wiring 24. Solder balls 30 are provided in the opening 29 and below the opening 29 so as to be connected to the land of the fourth wiring 24.

次に、半導体構成体１のプリント配線板２１上への実装構造について説明する。半導体構成体１は、プリント配線板２１上の中央部に接着層３１を介して実装されている。この状態では、第１に、図２の右側に示すように、プリント配線板２１の一部の第４の配線２４の下地金属層２６の一端部は、金属層２５に設けられた開口部３２並びにフィルム基板２２および接着層３１に設けられた導通用孔３３を介して半導体構成体１の一部の第２の配線１３のランド１３ａに接続されている。   Next, a mounting structure of the semiconductor structure 1 on the printed wiring board 21 will be described. The semiconductor structure 1 is mounted on the central portion on the printed wiring board 21 via an adhesive layer 31. In this state, first, as shown on the right side of FIG. 2, one end portion of the base metal layer 26 of the fourth wiring 24 that is a part of the printed wiring board 21 has an opening 32 provided in the metal layer 25. In addition, the semiconductor substrate 1 is connected to a land 13 a of the second wiring 13 through a conduction hole 33 provided in the film substrate 22 and the adhesive layer 31.

第２に、図２の左側に示すように、プリント配線板２１の残りの第４の配線２４の下地金属層２６の一端部は、金属層２５に設けられた開口部３４並びにフィルム基板２２、第３の配線２３および接着層３１に設けられた導通用孔３５を介して当該第３の配線２３および半導体構成体１の残りの第２の配線１３のランド１３ａに接続されている。ここで、金属層２５の開口部３２、３４の平面サイズは導通用孔３３、３５の平面サイズよりもやや大きくなっている。   Second, as shown on the left side of FIG. 2, one end portion of the base metal layer 26 of the remaining fourth wiring 24 of the printed wiring board 21 includes an opening 34 provided in the metal layer 25, a film substrate 22, The third wiring 23 and the land 13 a of the remaining second wiring 13 of the semiconductor structure 1 are connected to each other through the conduction hole 35 provided in the third wiring 23 and the adhesive layer 31. Here, the planar size of the openings 32 and 34 of the metal layer 25 is slightly larger than the planar size of the conduction holes 33 and 35.

そして、半導体構成体１の周囲におけるプリント配線板２１のフィルム基板２２の上面および半導体構成体１のシリコン基板１の上面にはシリカフィラーを含むエポキシ系樹脂からなる外部封止膜３６が設けられている。この状態では、半導体構成体１のシリコン基板２および封止膜１２並びに接着層３１の周側面は外部封止膜３６によって覆われている。   An outer sealing film 36 made of epoxy resin containing silica filler is provided on the upper surface of the film substrate 22 of the printed wiring board 21 and the upper surface of the silicon substrate 1 of the semiconductor structure 1 around the semiconductor structure 1. Yes. In this state, the peripheral surfaces of the silicon substrate 2, the sealing film 12, and the adhesive layer 31 of the semiconductor structure 1 are covered with the external sealing film 36.

次に、この半導体装置の製造方法の一例について説明する。まず、図３に示すように、半導体構成体１の第２の配線１３を含む封止膜１２の下面に接着層３１が設けられたものを複数個準備し、また１枚のプリント配線板２１を準備する。この場合、プリント配線板２１は、フィルム基板２２の上面に銅箔からなる第３の配線２３が形成され、フィルム基板２２の下面に銅箔からなる金属層２５が形成されたものからなっている。   Next, an example of a method for manufacturing this semiconductor device will be described. First, as shown in FIG. 3, a plurality of substrates having an adhesive layer 31 provided on the lower surface of the sealing film 12 including the second wiring 13 of the semiconductor structure 1 are prepared, and one printed wiring board 21 is prepared. Prepare. In this case, the printed wiring board 21 is configured such that the third wiring 23 made of copper foil is formed on the upper surface of the film substrate 22 and the metal layer 25 made of copper foil is formed on the lower surface of the film substrate 22. .

また、この時点では、フィルム基板２２および第３の配線２３には、図２に示す導通用孔３３、３５は形成されていない。また、金属層２５には、図２に示す導通用孔３３、３５を形成する領域に対応する部分に開口部３２、３４が形成されているだけであり、パターン化されていない。   Further, at this time, the conduction holes 33 and 35 shown in FIG. 2 are not formed in the film substrate 22 and the third wiring 23. Further, the metal layer 25 has openings 32 and 34 only in portions corresponding to regions where the conduction holes 33 and 35 shown in FIG. 2 are formed, and is not patterned.

また、図４に示すように、フィルム基板２２は長尺なものからなり、その幅方向両側には搬送用のスプロケットホール４１が形成されている。なお、図４において、一点鎖線で示す方形状の領域は半導体構成体１を実装する領域である。したがって、図４に示す場合、半導体構成体１はフィルム基板２２の幅方向に３個実装されることになる。また、図４において符号４２で示す二点鎖線および図３において符号４２で示す領域は切断ラインである。   Further, as shown in FIG. 4, the film substrate 22 is long, and sprocket holes 41 for conveyance are formed on both sides in the width direction. In FIG. 4, a rectangular region indicated by a one-dot chain line is a region where the semiconductor structure 1 is mounted. Therefore, in the case shown in FIG. 4, three semiconductor structures 1 are mounted in the width direction of the film substrate 22. Moreover, the dashed-two dotted line shown with the code | symbol 42 in FIG. 4 and the area | region shown with the code | symbol 42 in FIG. 3 are cutting lines.

ここで、半導体構成体１の製造方法の一例について簡単に説明する。まず、ウエハ状態のシリコン基板（半導体ウエハ）２下に接続パッド３、パッシベーション膜４、保護膜６、第１の配線８、柱状電極１１および封止膜１２が形成されたものを準備する。次に、柱状電極１１を含む封止膜１２の下面に、無電解メッキにより、銅からなる下地金属層を、電解メッキにより、銅からなる上部金属層を形成し、次いでこれらをフォトリソグラフィ法によりパターニングすることにより、下地金属層１４および上部金属層１５からなる２層構造の第２の配線１３を形成する。   Here, an example of a method for manufacturing the semiconductor structure 1 will be briefly described. First, a wafer in which a connection pad 3, a passivation film 4, a protective film 6, a first wiring 8, a columnar electrode 11, and a sealing film 12 are formed under a silicon substrate (semiconductor wafer) 2 in a wafer state is prepared. Next, a base metal layer made of copper is formed on the lower surface of the sealing film 12 including the columnar electrode 11 by electroless plating, and an upper metal layer made of copper is formed by electrolytic plating, and these are then formed by photolithography. By patterning, a second wiring 13 having a two-layer structure including the base metal layer 14 and the upper metal layer 15 is formed.

次に、第２の配線１３を含む封止膜１２の下面に、非導電性フィルムであるＮＣＦ（Non conductive
Film）等からなるフィルム状の接着層３１を貼り付ける。次に、ダイシングを行うと、図３に示すように、下面に接着層３１を有する半導体構成体１が複数個得られる。なお、フィルム状の接着層３１を貼り付ける前に、ダイシングを行い、個片化された半導体構成体１の下面に個片化されたフィルム状の接着層３１を貼り付けるようにしてもよい。 Next, NCF (Non conductive) which is a non-conductive film is formed on the lower surface of the sealing film 12 including the second wiring 13.
A film-like adhesive layer 31 made of film or the like is attached. Next, when dicing is performed, as shown in FIG. 3, a plurality of semiconductor structures 1 having an adhesive layer 31 on the lower surface are obtained. Note that, before the film-like adhesive layer 31 is attached, dicing may be performed so that the individual film-like adhesive layer 31 is attached to the lower surface of the individual semiconductor structure 1.

さて、図３に示すものを準備したら、次に、図５に示すように、ボンディングを行うことにより、第３の配線２３を含むフィルム基板２２の上面の半導体構成体実装領域に半導体構成体１の第２の配線１３を含む封止膜１２の下面を接着層３１を介して接着する。ここで、半導体構成体１の下面に接着層３１を貼り付けずに、第３の配線２３を含むフィルム基板２２の上面の半導体構成体実装領域に個片化されたフィルム状の接着層３１を貼り付けるようにしてもよい。また、フィルム状の接着層３１を用いずに、第３の配線２３を含むフィルム基板２２の上面の半導体構成体実装領域に、非導電性ペーストであるＮＣＰ（Non Conductive Paste）等からなる液状の接着剤をスクリーン印刷法等により塗布して、接着層３１を形成するようにしてもよい。   3 is prepared, next, as shown in FIG. 5, by bonding, the semiconductor structure 1 is formed in the semiconductor structure mounting region on the upper surface of the film substrate 22 including the third wiring 23. The lower surface of the sealing film 12 including the second wiring 13 is bonded through an adhesive layer 31. Here, without attaching the adhesive layer 31 to the lower surface of the semiconductor structure 1, the film-like adhesive layer 31 separated into the semiconductor structure mounting region on the upper surface of the film substrate 22 including the third wiring 23 is provided. You may make it stick. Further, without using the film-like adhesive layer 31, a liquid component made of NCP (Non Conductive Paste) or the like, which is a non-conductive paste, is formed on the semiconductor structure mounting region on the upper surface of the film substrate 22 including the third wiring 23. The adhesive layer 31 may be formed by applying an adhesive by a screen printing method or the like.

次に、図６に示すように、半導体構成体１および接着層３１の周囲におけるフィルム基板２２の上面および半導体構成体１のシリコン基板２の上面に、印刷法やモールド法等により、シリカフィラーを含むエポキシ系樹脂からなる外部封止膜３６を形成する。この状態では、半導体構成体１のシリコン基板２および封止膜１２並びに接着層３１の周側面は外部封止膜３６によって覆われている。   Next, as shown in FIG. 6, silica filler is applied to the upper surface of the film substrate 22 and the upper surface of the silicon substrate 2 of the semiconductor structure 1 around the semiconductor structure 1 and the adhesive layer 31 by a printing method, a molding method, or the like. An external sealing film 36 made of an epoxy resin is formed. In this state, the peripheral surfaces of the silicon substrate 2, the sealing film 12, and the adhesive layer 31 of the semiconductor structure 1 are covered with the external sealing film 36.

次に、図７に示すように、金属層２５の開口部３２の中央部にレーザビームを照射するレーザ加工を行うことにより、金属層２５の開口部３２の中央部に対応する部分におけるフィルム基板２２および接着層３１に、半導体構成体１の一部の第２の配線１３のランド１３ａに達する深さの導通用孔３３を形成する。また、金属層２５の開口部３４の中央部にレーザビームを照射するレーザ加工を行うことにより、金属層２５の開口部３４の中央部に対応する部分におけるフィルム基板２２、第３の配線２３および接着層３１に、半導体構成体１の残りの第２の配線１３のランド１３ａに達する深さの導通用孔３５を形成する。   Next, as shown in FIG. 7, the film substrate in a portion corresponding to the central portion of the opening portion 32 of the metal layer 25 is performed by performing laser processing to irradiate the central portion of the opening portion 32 of the metal layer 25 with a laser beam. 22 and the adhesive layer 31 are formed with conduction holes 33 having a depth reaching the lands 13a of the second wiring 13 of a part of the semiconductor structure 1. In addition, by performing laser processing to irradiate the central portion of the opening 34 of the metal layer 25 with a laser beam, the film substrate 22, the third wiring 23, and the portion in the portion corresponding to the central portion of the opening 34 of the metal layer 25 A conduction hole 35 having a depth reaching the land 13 a of the remaining second wiring 13 of the semiconductor structure 1 is formed in the adhesive layer 31.

ここで、この場合のレーザ加工について説明する。第２の配線１３の厚さは、そのランド１３ａがレーザビームの照射を受けても貫通孔が形成されないようにするため、比較的厚い厚さとなっている。第３の配線２３の厚さは、第３の配線２３にレーザ加工により導通用孔３３を形成することができるようにするため、第２の配線１３の厚さよりもある程度薄い厚さとなっている。   Here, laser processing in this case will be described. The thickness of the second wiring 13 is relatively thick so that the through hole is not formed even when the land 13a is irradiated with the laser beam. The thickness of the third wiring 23 is somewhat smaller than the thickness of the second wiring 13 so that the conduction hole 33 can be formed in the third wiring 23 by laser processing. .

レーザとして例えばＣＯ２レーザを用いる場合には、第２の配線１３の厚さが１５μｍ以上であると、そのランド１３ａに貫通孔が形成されないようにすることができるので、第２の配線１３の厚さは１５〜２０μｍが好ましい。一方、第３の配線２３の厚さが１０μｍ以下であると、第３の配線２３に導通用孔３５を形成することができるので、第３の配線２３の厚さは３〜１０μｍが好ましい。 For example, when a CO 2 laser is used as the laser, if the thickness of the second wiring 13 is 15 μm or more, it is possible to prevent a through hole from being formed in the land 13a. The thickness is preferably 15 to 20 μm. On the other hand, if the thickness of the third wiring 23 is 10 μm or less, the conduction hole 35 can be formed in the third wiring 23, and therefore the thickness of the third wiring 23 is preferably 3 to 10 μm.

ところで、金属層２５は開口部３２、３４が形成されていないベタ状のものとしてもよい。このようにした場合には、ベタ状の金属層２５にもレーザ加工により導通用孔を形成することになるので、この金属層２５の厚さも比較的薄く、例えば３〜１０μｍとした方が好ましい。ただし、上述の如く、金属層２５には開口部３２、３４を予め形成しておく方がより一層好ましい。   By the way, the metal layer 25 is good also as a solid thing in which the opening parts 32 and 34 are not formed. In such a case, since the conductive hole is also formed in the solid metal layer 25 by laser processing, the thickness of the metal layer 25 is relatively thin, for example, preferably 3 to 10 μm. . However, as described above, it is more preferable to form the openings 32 and 34 in the metal layer 25 in advance.

次に、図８に示すように、金属層２５の開口部３２、３４内および導通用孔３３、３５内を含む金属層２５の下面に下地金属層２６を形成する。この場合、下地金属層２６は、無電解メッキにより形成された銅層のみであってもよく、またスパッタにより形成された銅層のみであってもよく、さらにスパッタにより形成されたチタン等の薄膜層上にスパッタにより銅層を形成したものであってもよい。   Next, as shown in FIG. 8, the base metal layer 26 is formed on the lower surface of the metal layer 25 including the openings 32 and 34 of the metal layer 25 and the conduction holes 33 and 35. In this case, the base metal layer 26 may be only a copper layer formed by electroless plating, or may be only a copper layer formed by sputtering, and a thin film such as titanium formed by sputtering. A copper layer may be formed on the layer by sputtering.

次に、下地金属層２６をメッキ電流路とした銅の電解メッキを行なうことにより、下地金属層２６の下面に上部金属層２７を形成する。次に、上部金属層２７、下地金属層２６および金属層２５に対してフォトリソグラフィ法によるパターニングを行うと、図９に示すように、フィルム基板２２の下面に、金属層２５、下地金属層２６および上部金属層２７からなる３層構造の第４の配線２４が形成される。   Next, the upper metal layer 27 is formed on the lower surface of the base metal layer 26 by performing electrolytic plating of copper using the base metal layer 26 as a plating current path. Next, when the upper metal layer 27, the base metal layer 26 and the metal layer 25 are patterned by photolithography, the metal layer 25 and the base metal layer 26 are formed on the lower surface of the film substrate 22 as shown in FIG. Then, a fourth wiring 24 having a three-layer structure composed of the upper metal layer 27 is formed.

この状態では、一部の第４の配線２４の下地金属層２６の一端部は、金属層２５に形成された開口部３２並びにフィルム基板２２および接着層３１に形成された導通用孔３３を介して半導体構成体１の一部の第２の配線１３のランド１３ａに接続されている。また、残りの第４の配線２４の下地金属層２６の一端部は、金属層２５に形成された開口部３４並びにフィルム基板２２、第３の配線２３および接着層３１に形成された導通用孔３５を介して当該第３の配線２３および半導体構成体１の残りの第２の配線１３のランド１３ａに接続されている。   In this state, one end portion of the base metal layer 26 of a part of the fourth wiring 24 passes through the opening 32 formed in the metal layer 25 and the conduction hole 33 formed in the film substrate 22 and the adhesive layer 31. The semiconductor structure 1 is connected to a part of the land 13 a of the second wiring 13. In addition, one end portion of the base metal layer 26 of the remaining fourth wiring 24 is connected to the opening 34 formed in the metal layer 25 and the conduction hole formed in the film substrate 22, the third wiring 23, and the adhesive layer 31. 35 is connected to the land 13 a of the third wiring 23 and the remaining second wiring 13 of the semiconductor structure 1.

次に、図１０に示すように、第４の配線２４を含むフィルム基板２２の下面に、スクリーン印刷法により、ソルダーレジスト等からなるオーバーコート膜２８を形成する。次に、第４の配線２４のランドに対応する部分におけるオーバーコート膜２８に、レーザビームを照射するレーザ加工により、開口部２９を形成する。次に、オーバーコート膜２８の開口部２９内およびその下方に半田ボール３０を第４の配線２４のランドに接続させて形成する。次に、図１１に示すように、外部封止膜３６、フィルム基板２２およびオーバーコート膜２８を切断ライン４２に沿って切断すると、図１および図２に示す半導体装置が複数個得られる。   Next, as shown in FIG. 10, an overcoat film 28 made of a solder resist or the like is formed on the lower surface of the film substrate 22 including the fourth wiring 24 by a screen printing method. Next, an opening 29 is formed in the overcoat film 28 in a portion corresponding to the land of the fourth wiring 24 by laser processing that irradiates a laser beam. Next, a solder ball 30 is formed in the opening 29 of the overcoat film 28 and below the opening 29 so as to be connected to the land of the fourth wiring 24. Next, as shown in FIG. 11, when the external sealing film 36, the film substrate 22 and the overcoat film 28 are cut along the cutting line 42, a plurality of semiconductor devices shown in FIGS. 1 and 2 are obtained.

このようにして得られた半導体装置では、半導体構成体１の柱状電極１１を含む封止膜１２の下面に設けられた第２の配線１３のランド１３ａに、プリント配線板２１の第４の配線２４の無電解メッキ等により形成された下地金属層２６の一端部をフィルム基板２２の導通用孔３３、３５を介して接続しているので、上記従来の場合のマウントによる単なる面接触による電気的接続と比較して、電気的接続を安定化することができる。   In the semiconductor device thus obtained, the fourth wiring of the printed wiring board 21 is formed on the land 13 a of the second wiring 13 provided on the lower surface of the sealing film 12 including the columnar electrode 11 of the semiconductor structure 1. Since one end portion of the base metal layer 26 formed by electroless plating 24 is connected through the conduction holes 33 and 35 of the film substrate 22, it is electrically connected by simple surface contact by the mount in the conventional case. Compared with the connection, the electrical connection can be stabilized.

なお、上記実施形態では、プリント配線板２１の第３の配線２３と第４の配線２４との接続を導通用孔３５内に形成された下地金属層２５を介して行っているが、これに限定されるものではない。例えば、プリント配線板２１は、導通用孔３３、３５を形成する領域以外の領域において、第３の配線２３と第４の配線２４とがフィルム基板２２に形成されたスルーホール導通部を介して接続されたものであってもよい。   In the above embodiment, the third wiring 23 and the fourth wiring 24 of the printed wiring board 21 are connected via the base metal layer 25 formed in the conduction hole 35. It is not limited. For example, the printed wiring board 21 has a third wiring 23 and a fourth wiring 24 in a region other than a region where the conduction holes 33 and 35 are formed via a through-hole conduction part formed on the film substrate 22. It may be connected.

また、上記実施形態では、プリント配線板２１の第４の配線２４を金属層２５、下地金属層２６および上部金属層２７の３層構造としているが、これに限定されるものではない。例えば、プリント配線板２１の第４の配線２４を下地金属層２６および上部金属層２７の２層構造としてもよい。すなわち、図３に示すような状態では、フィルム基板２２の下面に金属層２５が形成されていなくてもよい。ただし、この場合も、下地金属層２６は導通用孔３３、３５を介して半導体構成体１の第２の配線１３のランド１３ａに接続される。   Moreover, in the said embodiment, although the 4th wiring 24 of the printed wiring board 21 is made into the three-layer structure of the metal layer 25, the base metal layer 26, and the upper metal layer 27, it is not limited to this. For example, the fourth wiring 24 of the printed wiring board 21 may have a two-layer structure of the base metal layer 26 and the upper metal layer 27. That is, in the state shown in FIG. 3, the metal layer 25 may not be formed on the lower surface of the film substrate 22. However, also in this case, the base metal layer 26 is connected to the land 13 a of the second wiring 13 of the semiconductor structure 1 through the conduction holes 33 and 35.

更に、上記実施形態では、第２の配線１３および第４の配線２４を形成するとき、下地金属層１４、２６の下面全体に上部金属層１５、２７を形成しているが、これに限定されるものではない。例えば、下地金属層１４、２６の下面に開口部を有するレジスト膜を形成し、レジスト膜の開口部内における下地金属層１４、２６の下面に電解メッキにより上部金属層１５、２７を形成し、レジスト膜を剥離した後、上部金属層１５、２７をマスクとして下地金属層１４、２６（金属層２５を含む）をエッチングするようにしてもよい。   Furthermore, in the above embodiment, when the second wiring 13 and the fourth wiring 24 are formed, the upper metal layers 15 and 27 are formed on the entire lower surface of the base metal layers 14 and 26. However, the present invention is not limited to this. It is not something. For example, a resist film having openings on the lower surfaces of the base metal layers 14 and 26 is formed, and upper metal layers 15 and 27 are formed on the lower surfaces of the base metal layers 14 and 26 in the openings of the resist film by electrolytic plating. After the film is peeled off, the base metal layers 14 and 26 (including the metal layer 25) may be etched using the upper metal layers 15 and 27 as a mask.

（第２実施形態）
図１２はこの発明の第２実施形態としての半導体装置の断面図を示す。この半導体装置において、図２に示す半導体装置と異なる点は、図２に示す半導体装置では、半田ボール３０を半導体構成体１下にのみ配置したのに対し、半田ボール３０を半導体構成体１下の周囲にも配置した点である。この半導体構成体の製造方法は、上記第１実施形態の場合と同様であるので、その説明は省略する。 (Second Embodiment)
FIG. 12 is a sectional view of a semiconductor device as a second embodiment of the present invention. The semiconductor device shown in FIG. 2 is different from the semiconductor device shown in FIG. 2 in that the solder ball 30 is disposed only under the semiconductor structure 1 whereas the solder ball 30 is disposed under the semiconductor structure 1. It is also a point placed around the. Since the manufacturing method of this semiconductor structure is the same as that of the said 1st Embodiment, the description is abbreviate | omitted.

（第３実施形態）
図１３はこの発明の第３実施形態としての半導体装置の断面図を示し、図１４はその薄膜誘導素子５１の部分の平面図を示す。この場合、図１３は図１４のXIII−XIII線に沿う部分に相当する断面図である。この半導体装置において、図２に示す半導体装置と大きく異なる点は、プリント配線板２１のフィルム基板２２の上面に薄膜誘導素子５１を設けた点である。 (Third embodiment)
FIG. 13 shows a cross-sectional view of a semiconductor device as a third embodiment of the present invention, and FIG. 14 shows a plan view of a portion of the thin film induction element 51. In this case, FIG. 13 is a cross-sectional view corresponding to a portion along line XIII-XIII in FIG. This semiconductor device is greatly different from the semiconductor device shown in FIG. 2 in that a thin film induction element 51 is provided on the upper surface of the film substrate 22 of the printed wiring board 21.

すなわち、フィルム基板２２の上面には渦巻き形状の薄膜誘導素子５１が設けられている。薄膜誘導素子５１は、フィルム基板２２の上面に設けられた渦巻き形状の第１の銅層５１ａと、第１の銅層５１ａの平面円形状の内端部上面に設けられた第２の銅層５１ｂとからなっている。なお、薄膜誘導素子５１の渦巻き形状は、図１４に示す如く、角渦巻き形状であってもよく、また図示していないが、円渦巻き形状であってもよい。   That is, a spiral thin film inductive element 51 is provided on the upper surface of the film substrate 22. The thin film inductive element 51 includes a spiral first copper layer 51a provided on the upper surface of the film substrate 22, and a second copper layer provided on the upper surface of the planar circular inner end of the first copper layer 51a. 51b. Note that the spiral shape of the thin film inductive element 51 may be a square spiral shape as shown in FIG. 14 or may be a circular spiral shape although not shown.

薄膜誘導素子５１の外端部は所定の第３の配線２３の一端部に接続されている。薄膜誘導素子５１の内端部は所定の第４の配線２４の一端部に接続されている。この場合、所定の第４の配線２４の下地金属層２６の一端部は、金属層２５に設けられた開口部５２並びにフィルム基板２２および第１の銅層５１ａに設けられた導通用孔５３を介して薄膜誘導素子５１の内端部に接続されている。   The outer end portion of the thin film induction element 51 is connected to one end portion of a predetermined third wiring 23. The inner end portion of the thin film induction element 51 is connected to one end portion of a predetermined fourth wiring 24. In this case, one end portion of the base metal layer 26 of the predetermined fourth wiring 24 has an opening 52 provided in the metal layer 25 and a conduction hole 53 provided in the film substrate 22 and the first copper layer 51a. To the inner end of the thin film induction element 51.

次に、この半導体装置の薄膜誘導素子５１の部分の製造方法について説明する。まず、フィルム基板２２の上面にベタ状に形成された比較的薄い銅箔の上面の所定の箇所に、当該銅箔をメッキ電流路とした銅の電解メッキを行うことにより、比較的厚い平面円形状の第２の銅層５１ｂを形成する。次に、ベタ状の当該銅箔をフォトリソグラフィ法によりパターニングすることにより、第３の配線２３および渦巻き形状の第１の銅層５１ａを形成する。ここで、比較的厚い平面円形状の第２の銅層５１ｂは、レーザビームの照射によるレーザ加工により導通用孔３４、３５、５３を形成するとき、薄膜誘導素子５１の内端部に貫通孔が形成されないようにするためのものである。   Next, a method for manufacturing the thin film induction element 51 of this semiconductor device will be described. First, a relatively thick planar circle is formed by performing copper electroplating using a copper foil as a plating current path on a predetermined portion of the upper surface of a relatively thin copper foil formed in a solid shape on the upper surface of the film substrate 22. A second copper layer 51b having a shape is formed. Next, the solid copper foil is patterned by a photolithography method to form the third wiring 23 and the spiral first copper layer 51a. Here, the relatively thick planar circular second copper layer 51b has a through-hole formed in the inner end portion of the thin-film induction element 51 when the conduction holes 34, 35, 53 are formed by laser processing by laser beam irradiation. This is to prevent the formation of.

（第４実施形態）
図１５はこの発明の第４実施形態としての半導体装置の断面図を示す。この半導体装置において、図２に示す半導体装置と異なる点は、半導体構成体１において、柱状電極１１を省略した点である。この場合、第１の配線８のランドに対応する部分における封止膜１２には、第２の配線１３の一端部を第１の配線８のランドに接続するための開口部１２ａが形成されている。また、封止膜１２はソルダーレジストによって形成するようにしてもよい。なお、この半導体構成体の製造方法は、上記第１実施形態の場合と同様であるので、その説明は省略する。 (Fourth embodiment)
FIG. 15 is a sectional view of a semiconductor device as a fourth embodiment of the present invention. This semiconductor device is different from the semiconductor device shown in FIG. 2 in that the columnar electrode 11 is omitted from the semiconductor structure 1. In this case, an opening 12 a for connecting one end of the second wiring 13 to the land of the first wiring 8 is formed in the sealing film 12 in a portion corresponding to the land of the first wiring 8. Yes. Further, the sealing film 12 may be formed of a solder resist. The method for manufacturing the semiconductor structure is the same as that in the first embodiment, and a description thereof will be omitted.

１ 半導体構成体
２ シリコン基板（半導体基板）
３ 接続パッド
４ パッシベーション膜
６ 保護膜
８ 第１の配線
１１ 柱状電極（突起電極）
１２ 封止膜
１３ 第２の配線
２１ プリント配線板
２２ フィルム基板（絶縁性基板）
２３ 第３の配線
２４ 第４の配線
２８ オーバーコート膜
３０ 半田ボール
３１ 接着層
３２、３３ 開口部
３４、３５ 導通用孔
３６ 外部封止膜 DESCRIPTION OF SYMBOLS 1 Semiconductor structure 2 Silicon substrate (semiconductor substrate)
DESCRIPTION OF SYMBOLS 3 Connection pad 4 Passivation film 6 Protective film 8 1st wiring 11 Columnar electrode (projection electrode)
12 Sealing film 13 Second wiring 21 Printed wiring board 22 Film substrate (insulating substrate)
23 Third wiring 24 Fourth wiring 28 Overcoat film 30 Solder ball 31 Adhesive layer 32, 33 Opening 34, 35 Conductive hole 36 External sealing film

Claims (18)

半導体基板と、接続パッドと、該接続パッドに接続された第１の配線と、該第１の配線と電気的に接続された第２の配線と、を有する半導体構成体と、
前記第２の配線を覆う接着層と、
前記半導体構成体および前記接着層の周側面を覆い、且つ前記半導体構成体の下面を覆う外部封止膜と、
を備えていることを特徴とする半導体装置。 A semiconductor structure having a semiconductor substrate, a connection pad, a first wiring connected to the connection pad, and a second wiring electrically connected to the first wiring;
An adhesive layer covering the second wiring;
An external sealing film that covers peripheral surfaces of the semiconductor structure and the adhesive layer, and covers a lower surface of the semiconductor structure;
A semiconductor device comprising: 請求項１に記載の発明において、前記半導体構成体および前記外部封止膜の上面に設けられた絶縁性基板と、該絶縁性基板および前記接着層に設けられた導通用孔を介して前記第２の配線に接続された第４の配線と、を備え、
前記第４の配線は、前記絶縁性基板の一面に設けられた、金属層、下地金属層および上部金属層からなる３層構造であり、前記下地金属層が前記導通用孔を介して前記半導体構成体の第２の配線のランドに接続されていることを特徴とする半導体装置。 The invention according to claim 1, wherein the semiconductor substrate and the outer sealing film are provided with an insulating substrate, and the insulating substrate and the adhesive layer are provided with a conduction hole. A fourth wiring connected to the second wiring,
The fourth wiring has a three-layer structure including a metal layer, a base metal layer, and an upper metal layer provided on one surface of the insulating substrate, and the base metal layer is connected to the semiconductor via the conduction hole. A semiconductor device, wherein the semiconductor device is connected to a land of a second wiring of the structure. 請求項１に記載の発明において、前記半導体構成体および前記外部封止膜の上面に設けられた絶縁性基板と、該絶縁性基板および前記接着層に設けられた導通用孔を介して前記第２の配線に接続された第４の配線と、を備え、
前記第４の配線は、前記絶縁性基板の一面に設けられた下地金属層および上部金属層からなる２層構造であり、前記下地金属層が前記導通用孔を介して前記半導体構成体の第２の配線のランドに接続されていることを特徴とする半導体装置。 The invention according to claim 1, wherein the semiconductor substrate and the outer sealing film are provided with an insulating substrate, and the insulating substrate and the adhesive layer are provided with a conduction hole. A fourth wiring connected to the second wiring,
The fourth wiring has a two-layer structure including a base metal layer and an upper metal layer provided on one surface of the insulating substrate, and the base metal layer is connected to the semiconductor structure through the conduction hole. A semiconductor device connected to a land of two wirings. 請求項２または３に記載の発明において、前記絶縁性基板の他面に第３の配線が設けられていることを特徴とする半導体装置。   4. The semiconductor device according to claim 2, wherein a third wiring is provided on the other surface of the insulating substrate. 請求項４に記載の発明において、前記導通用孔は前記第３の配線を貫通して設けられ、前記第４の配線は前記導通用孔を介して前記第３の配線にも接続されていることを特徴とする半導体装置。   In the invention according to claim 4, the conduction hole is provided through the third wiring, and the fourth wiring is also connected to the third wiring through the conduction hole. A semiconductor device. 請求項４に記載の発明において、前記第３の配線と前記第４の配線とは、前記導通用孔が設けられた領域以外の領域における前記絶縁性基板に設けられたスルーホール導通部を介して接続されていることを特徴とする半導体装置。   In the invention according to claim 4, the third wiring and the fourth wiring are connected through a through-hole conduction portion provided in the insulating substrate in a region other than the region in which the conduction hole is provided. A semiconductor device characterized by being connected. 請求項４に記載の発明において、前記絶縁性基板の前記第３の配線が設けられた面に、薄膜誘導素子が設けられていることを特徴とする半導体装置。   5. The semiconductor device according to claim 4, wherein a thin film induction element is provided on a surface of the insulating substrate on which the third wiring is provided. 請求項１に記載の発明において、前記半導体構成体は、前記第１の配線に接続された突起電極および該突起電極の周囲に設けられた封止膜を有し、前記第２の配線は前記突起電極を含む前記封止膜の外部に設けられていることを特徴とする半導体装置。   2. The semiconductor device according to claim 1, wherein the semiconductor structure includes a protruding electrode connected to the first wiring and a sealing film provided around the protruding electrode, and the second wiring A semiconductor device, wherein the semiconductor device is provided outside the sealing film including a protruding electrode. 請求項２乃至４、６、７に記載の発明において、前記絶縁性基板は、ガラス布基材エポキシ系樹脂、ガラス布基材ポリイミド系樹脂のいずれかからなることを特徴とする半導体装置。   8. The semiconductor device according to claim 2, wherein the insulating substrate is made of a glass cloth base epoxy resin or a glass cloth base polyimide resin. 半導体基板と、接続パッドと、該接続パッドに接続された第１の配線と、該第１の配線と電気的に接続された第２の配線と、を有する半導体構成体を形成する工程と、
前記第２の配線を覆う接着層を形成する工程と、
前記半導体構成体および前記接着層の周側面を覆い、且つ前記半導体構成体の下面を覆う外部封止膜を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 Forming a semiconductor structure having a semiconductor substrate, a connection pad, a first wiring connected to the connection pad, and a second wiring electrically connected to the first wiring;
Forming an adhesive layer covering the second wiring;
Forming an external sealing film that covers peripheral surfaces of the semiconductor structure and the adhesive layer and covers a lower surface of the semiconductor structure;
A method for manufacturing a semiconductor device, comprising: 半導体基板と第２の配線とを有する半導体構成体と、絶縁性基板と、を準備する工程と、
前記絶縁性基板と、前記半導体構成体と、を接着層を介して接着する工程と、
前記第２の配線のランドに対応する部分における前記絶縁性基板および前記接着層に、導通用孔を形成する工程と、
前記導通用孔内を含む前記絶縁性基板の一面に下地金属層を形成する工程と、
前記下地金属層上に上部金属層を形成する工程と、
を有することを特徴とする半導体装置の製造方法。 Preparing a semiconductor structure having a semiconductor substrate and a second wiring, and an insulating substrate;
Adhering the insulating substrate and the semiconductor structure via an adhesive layer;
Forming a conduction hole in the insulating substrate and the adhesive layer in a portion corresponding to the land of the second wiring;
Forming a base metal layer on one surface of the insulating substrate including the inside of the conduction hole;
Forming an upper metal layer on the base metal layer;
A method for manufacturing a semiconductor device, comprising: 請求項１１に記載の発明において、準備された前記絶縁性基板の一面には予め金属層が設けられていることを特徴とする半導体装置の製造方法。 12. The method of manufacturing a semiconductor device according to claim 11, wherein a metal layer is provided in advance on one surface of the prepared insulating substrate. 請求項１１に記載の発明において、前記絶縁性基板の他面に第３の配線が予め形成されていることを特徴とする半導体装置の製造方法。   12. The method of manufacturing a semiconductor device according to claim 11, wherein a third wiring is formed in advance on the other surface of the insulating substrate. 請求項１３に記載の発明において、前記導通用孔を形成する工程は、前記第３の配線に導通用孔を形成する工程を含むことを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, wherein the step of forming the conduction hole includes a step of forming a conduction hole in the third wiring. 請求項１３に記載の発明において、前記第３の配線と前記第４の配線とは、前記導通用孔が形成される領域以外の領域における前記絶縁性基板に設けられたスルーホール導通部を介して接続されていることを特徴とする半導体装置の製造方法。   In the invention according to claim 13, the third wiring and the fourth wiring are connected through a through-hole conducting portion provided in the insulating substrate in a region other than a region where the conducting hole is formed. A method of manufacturing a semiconductor device, wherein 請求項１３に記載の発明において、前記絶縁性基板の前記第３の配線が設けられた面に、薄膜誘導素子が形成されていることを特徴とする半導体装置の製造方法。   14. The method of manufacturing a semiconductor device according to claim 13, wherein a thin film induction element is formed on a surface of the insulating substrate on which the third wiring is provided. 請求項１０または１１に記載の発明において、前記半導体構成体は、前記配線に接続された突起電極および該突起電極の周囲に設けられた封止膜を有し、前記第２の配線は前記突起電極を含む前記封止膜の外部に設けられていることを特徴とする半導体装置の製造方法。   The invention according to claim 10 or 11, wherein the semiconductor structure includes a protruding electrode connected to the wiring and a sealing film provided around the protruding electrode, and the second wiring is the protruding A method for manufacturing a semiconductor device, wherein the method is provided outside the sealing film including an electrode. 請求項１１乃至１３、１５、１６に記載の発明において、前記絶縁性基板は、ガラス布基材エポキシ系樹脂、ガラス布基材ポリイミド系樹脂のいずれかからなることを特徴とする半導体装置の製造方法。   17. The semiconductor device according to claim 11, wherein the insulating substrate is made of either a glass cloth base epoxy resin or a glass cloth base polyimide resin. Method.
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Citations (3)

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JP2008021789A (en) * 2006-07-12 2008-01-31 Matsushita Electric Ind Co Ltd Semiconductor device and radio apparatus using the same
JP2009043857A (en) * 2007-08-08 2009-02-26 Casio Comput Co Ltd Semiconductor device and manufacturing method thereof
JP2009182200A (en) * 2008-01-31 2009-08-13 Casio Comput Co Ltd Semiconductor device and method of manufacturing the same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008021789A (en) * 2006-07-12 2008-01-31 Matsushita Electric Ind Co Ltd Semiconductor device and radio apparatus using the same
JP2009043857A (en) * 2007-08-08 2009-02-26 Casio Comput Co Ltd Semiconductor device and manufacturing method thereof
JP2009182200A (en) * 2008-01-31 2009-08-13 Casio Comput Co Ltd Semiconductor device and method of manufacturing the same

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