JP2011180766A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device capable of reducing power consumption as compared to a conventional device, and capable of avoiding an increase of a processing load of an external control device. <P>SOLUTION: The semiconductor device includes: a plurality of function circuits; and a bus management circuit managing the use of an internal bus by each function circuit. The bus management circuit has a function to decide the communication state of each function circuit based on data communication information notified from each function circuit and to transfer it to a power saving mode according to a decision result thereof. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

 The present invention relates to a semiconductor device.

  As is well known, an ASIC (Application Specific Integrated Circuit) is a semiconductor device (semiconductor integrated circuit) including a plurality of modules designed for a specific application. The ASIC includes a Hub circuit that arbitrates the right to use the internal bus shared by each module, decodes data input / output via the internal bus, and the like.

 This Hub circuit is a function to notify an external CPU of such an event by an interrupt or the like when there is no access from all modules connected to itself, and shift to a power saving mode (sleep state) under the control of the CPU. have. As a technique for reducing power consumption when the shared bus is not used, a technique described in Patent Document 1 below is known.

JP 2002-49580 A

  As described above, in order to shift the Hub circuit in the ASIC to the power saving mode, mode transition control by software processing of the CPU (for example, supply of a clock signal to the Hub circuit is stopped) is necessary. Therefore, the Hub circuit cannot shift to the power saving mode without waiting for the software processing of the CPU and cannot obtain a sufficient power saving effect (that is, there is room for improvement from the viewpoint of low power consumption). was there). Further, since the CPU performs mode transition control as interrupt processing, the CPU processing load is increased.

  Further, conventionally, when access from one module to the Hub circuit is lost, access from all modules is lost even though there is a time zone in which only the processing part in the Hub circuit related to that module can be stopped. Since the mode is shifted to the power saving mode only in the case of a failure, sufficient power saving control effect cannot be obtained.

    The present invention has been made in view of the above-described circumstances, and provides a semiconductor device capable of reducing power consumption as compared with the prior art and avoiding an increase in processing load of an external control device. The purpose is to do.

In order to achieve the above object, a semiconductor device according to the present invention is a semiconductor device including a plurality of functional circuits and a bus management circuit that manages the use of an internal bus by each functional circuit, and the bus management circuit includes: The communication state of each functional circuit is determined based on the data communication information notified from each functional circuit, and the mode is shifted to the power saving mode according to the determination result.
According to the semiconductor device having such characteristics, the bus management circuit (Hub circuit) itself determines the communication state of each functional circuit (module) and shifts to the power saving mode according to the determination result. Therefore, it is possible to immediately shift to the power saving mode without waiting for the software processing of the external control device, and it is possible to achieve lower power consumption than the conventional one. In addition, since it is not necessary for the external control device to perform mode transition control as interrupt processing, an increase in processing load on the external control device can be avoided.

In the semiconductor device according to the present invention, the bus management circuit includes a reception processing circuit that performs one-to-one communication corresponding to each functional circuit, and each reception processing circuit notifies from the functional circuit corresponding to itself. The communication state of the functional circuit corresponding to itself is determined based on the data communication information to be transferred, and the mode is shifted to the power saving mode according to the determination result.
As a result, according to the communication state of each functional circuit, the reception processing circuit corresponding to each functional circuit can be individually shifted to the power saving mode. Compared with the case of shifting to the power saving mode, lower power consumption can be achieved.

 According to the present invention, it is possible to provide a semiconductor device that can reduce power consumption as compared with the prior art and can avoid an increase in processing load of an external control device.

1 is a functional block diagram of an ASIC (semiconductor device) 10 in the present embodiment.

 An embodiment of the present invention will be described below with reference to the drawings. In the following, an ASIC controlled by a CPU that is an external control device will be described as an example of the semiconductor device according to the present invention.

 FIG. 1 is a functional block diagram of the ASIC 10 in the present embodiment. As shown in FIG. 1, the ASIC 10 in this embodiment is a semiconductor device (semiconductor integrated circuit) that is communicably connected to the CPU 20 via a CPU bus 30, and includes an internal bus 11, an I / F circuit 12, 1 module 13, second module 14, third module 15, hub circuit 16, and memory controller 17.

 The internal bus 11 is a shared bus shared by the modules 13 to 15. The I / F circuit 12 is a communication interface that performs transmission and reception of signals between the internal bus 11 and the CPU bus 30 (in other words, realizes bidirectional communication between the external device including the CPU 20 and the ASIC 10). Each of the modules 13 to 15 is a functional circuit having a different function, and is connected to the hub circuit 16 so as to be communicable.

 Specifically, the first module 13 performs bidirectional communication with the first reception processing circuit 16a in the Hub circuit 16, and notifies the first reception processing circuit 16a of the data communication information f1. The second module 14 performs bidirectional communication with the second reception processing circuit 16b in the Hub circuit 16, and notifies the second reception processing circuit 16b of the data communication information f2. In addition, the third module 15 performs bidirectional communication with the third reception processing circuit 16c in the Hub circuit 16, and notifies the third reception processing circuit 16c of the data communication information f3.

 The Hub circuit 16 is a bus management circuit that manages the use of the internal bus 11 by each of the modules 13 to 15, and is connected to the I / F circuit 12 and the memory controller 17 via the internal bus 11 so as to communicate with each other. Specifically, the hub circuit 16 performs bus arbitration processing for assigning the right to use the internal bus 11 in response to a bus use request notified from each of the modules 13 to 15 and data input / output via the internal bus 11. Decoding processing (destination control) and the like.

  The Hub circuit 16 includes reception processing circuits (a first reception processing circuit 16a, a second reception processing circuit 16b, and a third reception processing circuit 16c) provided on a one-to-one basis corresponding to the modules 13 to 15. I have. The first reception processing circuit 16a performs two-way communication with the first module 13, determines the communication state of the first module 13 based on the data communication information f1 notified from the first module 13, and the determination result Depending on the situation, it shifts itself to the power saving mode. The second reception processing circuit 16b performs bidirectional communication with the second module 14, determines the communication state of the second module 14 based on the data communication information f2 notified from the second module 14, and the determination result Depending on the situation, it shifts itself to the power saving mode. The third reception processing circuit 16c performs bidirectional communication with the third module 15, and determines the communication state of the third module 15 based on the data communication information f3 notified from the third module 15, It shifts to the power saving mode according to the determination result.

  The memory controller 17 is connected to the I / F circuit 12 and the Hub circuit 16 via the internal bus 11 and controls memory read / write for data read / write to the external memory 40 in response to requests from the modules 13 to 15. Circuit.

  Next, the power saving mode transition operation of the hub circuit 16 in the ASIC 10 configured as described above will be specifically described. For example, paying attention to the first reception processing circuit 16a of the Hub circuit 16, the first reception processing circuit 16a determines the communication state of the first module 13 based on the data communication information f1 notified from the first module 13, According to the determination result, the apparatus shifts to the power saving mode.

  In the present embodiment, as the data communication information f1 to be notified from the first module 13 to the first reception processing circuit 16a, the number of data transfers (for example, Read / Write for the external memory 40, the address on the external memory 40, the data size, Is assumed to be used using the number of tables required for processing to be performed from now on.

  When receiving the notification of the number of data transfers as the data communication information f1 from the first module 13, the first reception processing circuit 16a counts the actual number of data transfers of the first module 13 based on the notification information. The first reception processing circuit 16a determines that the communication state of the first module 13 has transitioned to the communication end state when the notified data transfer count matches the actual data transfer count, and the power saving mode Migrate to The same applies to the other second reception processing circuits 16b and 16c. The hub circuit 16 shifts the overall operation state to the power saving mode when all of the reception processing circuits 16a to 16c shift to the power saving mode.

  As described above, according to the present embodiment, the Hub circuit 16 itself determines the communication state of each of the modules 13 to 15 and shifts to the power saving mode according to the determination result. Therefore, it is possible to immediately shift to the power saving mode without waiting for the software processing, and lower power consumption can be achieved compared to the conventional case. Further, since the CPU 20 does not need to perform mode transition control as interrupt processing, an increase in processing load on the CPU 20 can be avoided.

  In addition, according to the respective communication states of the modules 13 to 15, the reception processing circuits 16a to 16c corresponding to the modules 13 to 15 can be individually shifted to the power saving mode. Compared with the case of shifting to the power saving mode when there is no access, the power consumption can be further reduced.

  In addition, in the said embodiment, although the case where each reception processing circuit 16a-16c was individually transferred to a power saving mode was illustrated, not only this but the communication state of all the modules 13-15 changed to the communication end state. In this case, the entire Hub circuit 16 may be shifted to the power saving mode. Moreover, although the case where the number of data transfers was used as data communication information was illustrated in the said embodiment, it is not restricted to this, For example, the communication state of each module 13-15, such as a data size and data transfer time, changes to a communication end state Any information that can be used to determine whether the data has been received can be used as data communication information.

<Application example>
As a system to which the semiconductor device (ASIC 10) according to the present invention can be applied, for example, an image forming apparatus such as a printer, a copier, or a multifunction peripheral can be cited. Specifically, the first module 13 has a function of storing the image data of the original read by the scanner in the external memory 40, and the second module 14 reads the image data from the external memory 40 and compresses or enlarges it. The image processing after the image processing is performed, and the image data after the image processing is stored in the external memory 40 again. Further, the third module 15 reads the image data after the image processing from the external memory 40 and performs laser exposure. A system with a function of transmitting to a device can be considered.

 DESCRIPTION OF SYMBOLS 10 ... ASIC (semiconductor device), 11 ... Internal bus, 12 ... I / F circuit, 13 ... 1st module (functional circuit), 14 ... 2nd module (functional circuit), 15 ... 3rd module (functional circuit), 16 ... Hub circuit (bus management circuit), 17 ... Memory controller, 20 ... CPU, 30 ... CPU bus, 40 External memory

Claims (2)

A semiconductor device comprising a plurality of functional circuits and a bus management circuit that manages the use of an internal bus by each functional circuit,
The bus management circuit determines a communication state of each functional circuit based on data communication information notified from each functional circuit, and shifts to a power saving mode according to the determination result. The bus management circuit includes a reception processing circuit that performs one-to-one communication corresponding to each functional circuit,
Each reception processing circuit determines the communication state of the functional circuit corresponding to itself based on the data communication information notified from the functional circuit corresponding to itself, and shifts to the power saving mode according to the determination result. The semiconductor device according to claim 1.

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