JP2011164975A - Information processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To automatically and properly increase the number of ways according to an application to improve utilization efficiency and hit rate of a cache. <P>SOLUTION: The information processor includes a cache unit installed between a processing unit that processes data and a memory that stores data, and including a plurality of data arrays where data in the memory is copied and an information array that holds information on the order of the time elapsed from the last use of ways in the data arrays. Each of the data arrays has one or more ways. At least one of them is different in the number of entries. For each sub-memory area, one entry is assigned in the plurality of data arrays. The number of ways is dynamically changed to the proper one by entry according to an application to be executed. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to an information processing apparatus having a cache unit.

  In the processor system, a cache is used to increase the access speed from the processor to the memory related to reading of data stored in the memory (main memory). As a mapping method between a cache entry and a memory address related to correspondence between data in a cache and data in a memory, a direct mapping method, a set associative method, and a full associative method are well known.

  As for the cache hit rate, the performance improves in the order of the direct mapping method, the set associative method, and the full associative method. On the other hand, the ease of mounting becomes lower in the order of the direct mapping method, the set associative method, and the full associative method, and the full associative method is actually difficult to implement. Therefore, it is common to use a set associative method of about 4 ways.

FIG. 11 is a diagram showing the configuration of a 4-way set associative cache.
In FIG. 11, 110 is a tag array, 111 is a data array, 112 (112-0 to 112-3) is a comparator, 113 is a selection circuit, and 114 is an LRU (Least Recently Used) array. The data array 111 stores a copy of data in the memory (main memory) in blocks in units of cache line size. The tag array 110 stores a tag (a part of a memory address) for data stored in each block of the data array 111. As shown in the figure, out of all bits of the address, a predetermined number of bits corresponding to the number of entries (the number of blocks in the vertical direction in the data array) positioned higher than the offset portion with the lower bits corresponding to the cache line size as an offset Is the index of the cache. The remaining bits that are higher than the index part are cache tags. The LRU array 114 holds LRU information indicating the order of the way in the tag array 110 and the data array 111 (the order of the elapsed time since the last use).

  When accessing an address in the memory space, when an address indicating an access destination is input, the tag array 110 is referred to based on the index portion in the address, and a tag is identified from the block corresponding to the index in each way. Read out. The read tag and the bit pattern of the tag portion in the address are compared for each way by the comparator 112, and the comparison result is output to the selection circuit 113.

  When the read tag matches the bit pattern of the tag portion in the address, a cache hit occurs. At this time, data is read from the block of the data array 111 corresponding to the index, and the data read from the block corresponding to the way with the matching tag is read by the selection circuit 113 according to the comparison result in the comparator 112. Selected and output as output data.

  On the other hand, in any way, if the read tag does not match the bit pattern of the tag portion in the address, a cache miss occurs. In the case of a cache miss, by accessing the memory, data is read from the storage area of the memory corresponding to the address indicating the access destination and output as output data. Further, data read from the memory is supplied and registered as input data in the cache. The tag at the address is registered in the block of the tag array 110 corresponding to the index in the address, and the data read from the memory is registered in the block of the data array 111 corresponding to the index. At this time, based on the LRU information held in the LRU array 114, the tag and data are replaced in the block of the tag array 110 and the data array 111 corresponding to the index that has the longest time since the last use. (Rewritten).

  In addition, a cache system has been proposed in which a cache system can be changed by specifying a combination of the number of ways and a block size in a register (see Patent Document 1). In this way, the cache utilization efficiency and hit rate are improved by changing the cache configuration to the optimum number of ways and block size for the application. In addition, a cache has been proposed in which a circuit for observing the hit rate of the cache is provided, and the number of ways to be operated can be controlled by turning on / off the power supply to the data array in units of ways based on an appropriate threshold. (See Patent Document 2).

JP 2000-20396 A Japanese Patent Laid-Open No. 9-50401

  As a cache, a set associative cache of about 4 ways is generally used from the viewpoint of hit rate and hardware amount. However, depending on the application to be executed, about 2 ways may be sufficient, and if it is not about 8 ways, the cache data may be frequently replaced. In addition to the number of ways in the entire data array, the usage frequency may be uneven for each entry number.

  According to the techniques described in Patent Document 1 and Patent Document 2 described above, the number of cache ways can be changed. However, the method in which the user previously determines the number of ways according to the application and uses the fixed number manually by the user as in Patent Document 1 has a problem in view of ease of use. . Further, since the number of ways is uniquely changed for all entry numbers, improvement in cache utilization efficiency cannot be expected if there is a difference in the frequency of use for each entry number. Also, in Patent Document 2, since the number of ways is uniquely changed for all entry numbers, improvement in cache utilization efficiency cannot be expected if there is a bias in use frequency for each entry number.

  According to one aspect of the present invention, an information processing apparatus is provided that includes a processing unit that performs processing on data, and a cache unit that is provided between a storage unit that stores data and the processing unit. The cache unit includes a plurality of data arrays to which data in the storage unit is copied, and an information array that holds information indicating the order of way ages in the plurality of data arrays. Each of the plurality of data arrays has a number of ways of 1 or more, and at least one of the plurality of data arrays has a different number of entries, and each of the plurality of data arrays has 1 for each of the storage areas of the divided storage units. One entry is assigned.

  According to the present invention, the number of ways can be dynamically increased / decreased in entry units according to the application to be executed and automatically changed to the optimum number of ways, and the cache utilization efficiency and the hit rate can be improved.

It is a figure which shows the structural example of the information processing apparatus in embodiment of this invention. It is a figure which shows the structural example of the cache part in this embodiment. It is a figure for demonstrating a response | compatibility with the memory address and cache entry in this embodiment. It is a flowchart which shows an example of the access operation | movement in this embodiment. It is a flowchart which shows a LRU reference operation process. It is a figure for demonstrating the change of the number of ways of the cache in this embodiment. It is a figure which shows the example of the LRU information in this embodiment. It is a figure which shows the example of the encoding system of LRU information in this embodiment. It is a figure for demonstrating the specific operation example in this embodiment. It is a figure for demonstrating the specific operation example in this embodiment. It is a figure which shows an example of the cache of a set associative system.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram illustrating a configuration example of an information processing apparatus according to an embodiment of the present invention.
In FIG. 1, 1 is an information processing apparatus, and 4 is a memory (main memory). The information processing apparatus 1 reads (loads) data from the memory 4 to perform processing, and writes (stores) data obtained as a processing result in the memory. The memory 4 stores data related to processing in the information processing apparatus 1.

  The information processing apparatus 1 includes a processing unit 2 that performs processing according to a command, and a cache unit 3 to which data in the memory 4 is copied. In FIG. 1, a CPU core is shown as an example of the processing unit 2, but the present invention is not limited to this, and may be an accelerator, for example.

  When the processing unit 2 of the information processing apparatus 1 accesses a certain address in the memory space and loads data, the cache unit 3 is first referred to and the desired data (the data in the storage area specified by the address) is stored. It is determined whether or not a copy exists in the cache unit 3. As a result, when a copy of desired data exists in the cache unit 3 (cache hit), a copy of the desired data is read from the cache unit 3 and supplied to the processing unit 2.

  On the other hand, when a copy of the desired data does not exist in the cache unit 3 (cache miss), the memory 4 is accessed and the desired data is read. Then, the desired data read from the memory 4 is supplied to the processing unit 2 and is replaced (replaced) with the data in the cache unit 3 (for example, the data having the longest time elapsed since the last use). And registered in the cache unit 3.

FIG. 2 is a diagram showing a configuration example of the cache unit 3 shown in FIG.
In FIG. 2, 10 is a first array (main array), 20 is a second array (subarray), and 30 is an LRU (Least Recently Used) array. The first array (main array) 10 corresponds to, for example, a 2-way set associative cache having 2 ways, and the second array (sub-array) 20 has, for example, 4 ways having 4 ways. This corresponds to a set associative cache.

  The first array (main array) 10 and the second array (subarray) 20 have different numbers of entries (number of vertical blocks in the array), and the number of entries in the first array (main array) 10. Is larger than the number of entries in the second array (subarray) 20. For example, the number of entries in the first array (main array) 10 is preferably about four times the number of entries in the second array (subarray) 20.

  The main array 10 includes a main tag array 12, a main data array 14, a comparator 16 (16-0, 16-1), and a selection circuit 18. The main data array 14 stores a copy of data in the memory 4 in blocks in units of cache line size. The main tag array 12 stores a tag (part of a memory address) for data stored in each block of the main data array 14.

  The comparator 16 compares the tag read from the main tag array 12 with the bit pattern of the tag portion in the address for each way based on the input address indicating the access destination, and the comparison result is sent to the selection circuit 18. Output. The selection circuit 18 selects the data read from the main data array 14 based on the input address according to the comparison result in the comparator 16 and outputs it as output data. Specifically, the selection circuit 18 selects the way in which the tag read from the main tag array 12 and the bit pattern of the tag portion in the address match among the data read from the main data array 14 based on the address. Select and output the data. Note that the selection circuit 18 does not output data when the tag read in any way does not match the bit pattern of the tag portion in the address.

  The subarray 20 includes a subtag array 22, a subdata array 24, comparators 26 (26-0 to 26-3), and a selection circuit 28. The sub data array 24 stores a copy of data in the memory 4 in blocks in units of cache line size. The sub tag array 22 stores a tag (part of a memory address) for data stored in each block of the sub data array 24.

  The comparator 26 compares the tag read from the sub tag array 22 with the bit pattern of the tag portion in the address for each way based on the input address, and outputs the comparison result to the selection circuit 28. Similar to the selection circuit 18, the selection circuit 28 selects the data read from the sub data array 24 based on the input address according to the comparison result in the comparator 26 and outputs it as output data.

  The LRU array 30 holds LRU information indicating the order of the way in the main array 10 and the sub-array 20 (order of elapsed time since the last use) in each entry unit. In addition, the cache unit 3 includes a cache control unit (not shown) that controls each functional unit in the cache unit 3. The cache control unit, for example, updates LRU information, or controls access to the memory 4 at the time of a cache miss or replacement of each data array.

  In the cache unit 3 according to the present embodiment, among all the bits of the address, a lower number bit corresponding to the cache line size is used as an offset, and a predetermined number of bits positioned higher than the offset unit and corresponding to the number of entries are the cache index. Become. The remaining bits that are higher than the index part are cache tags. Here, the main array 10 and the sub-array 20 have different numbers of entries. Therefore, the cache tag and index in the main array 10 and the cache tag and index in the subarray 20 are different for an arbitrary address.

  For example, the address is 32 bits with the least significant bit as the first bit and the most significant bit as the 32nd bit, the cache line size is 32 bytes, the number of entries in the main array 10 is 128, the subarray 20 The number of entries is 32. At this time, for the main array 10, 5 bits from the 1st bit to the 5th bit in the address are offset, 7 bits from the 6th bit to 12th bit are an index, and 20 bits from the 13th bit to the 32nd bit are It becomes a tag. For the subarray 20, 5 bits from the 1st bit to the 5th bit in the address are offset, 5 bits from the 6th bit to the 10th bit are indexes, and 22 bits from the 11th bit to the 32nd bit are tags. Become.

  FIG. 3 is a diagram for explaining a correspondence between a memory address and a cache entry in the information processing apparatus according to the present embodiment. In FIG. 3, reference numeral 100 denotes a memory (main memory), 101 denotes a main array (main data array) of the cache unit, and 102 denotes a sub array (sub data array) of the cache unit. In the example shown in FIG. 3, the main array 10 is an array having 8 entries and 2 ways, and the sub-array 102 is an array having 2 entries and 4 ways. The cache line size is 32 bytes.

  Data is copied from the memory 100 to the main array 101 and the sub-array 102 of the cache unit in units of cache line size. The memory space is divided by the cache line size, and the divided storage areas (spaces) are sequentially assigned to the entries.

  When the space from address A to address (A + 20) is represented as “A” in hexadecimal notation, in the example shown in FIG. 3, for example, “0x0000”, “0x0100”, “0x0200”,. It is assigned to one entry (0th entry) of the array 101. Similarly, for example, “0x0000”, “0x0040”, “0x0080”, “0x00c0”, “0x0100”,... In the memory 100 are assigned to one entry (0th entry) of the subarray 102.

  As described above, in this embodiment, one storage area divided by the cache line size in the memory space is allocated to one entry in the main array 101 and the subarray 102, respectively. For example, in the example shown in FIG. 3, “0x0000” in the memory 100 is assigned to the 0th entry of the main array 101 and to the 0th entry of the subarray 102.

  However, in this embodiment, when copying the data in the memory 100, it is registered in one block of the assigned entry of the main array 101 or the assigned entry of the subarray 102. Therefore, a copy of data at a certain address in the memory 100 does not exist in both the main array 101 and the subarray 102 at the same time. Data is copied from the memory 100 to the main array 101 and the sub-array 102 based on LRU information held in the LRU array. By replacing each block of the assigned entry in each of the main array 101 and the sub-array 102 with a block having the longest time elapsed since the last use (hereinafter also referred to as the oldest block), the memory 100 is replaced. The data is copied.

  FIG. 4 is a flowchart showing an example of the operation in the present embodiment. FIG. 4 shows the operation of the cache unit 3 when the processing unit (CPU core) 2 loads data at a certain address in the memory space, and is based on the control of the cache unit 3 by a cache control unit (not shown). Executed.

  In step S11, when the processing unit (CPU core) 2 accesses the memory 4, an address indicating the access destination is sent from the processing unit 2, and in step S12, the main address in the cache unit 3 is used using the address. Array 10 and subarray 20 are referenced simultaneously.

  In step S12, the main tag array 12 is referred to based on the index portion in the address corresponding to the number of entries in the main array 10, and the sub tag array 22 based on the index portion in the address corresponding to the number of entries in the subarray 20. Is referenced. Then, the tag is read from the block corresponding to the index in each way of the main tag array 12 and the sub tag array 22, and the read tag and the bit pattern of the tag portion in the address are compared for each way by the comparators 16, 26. Compared by.

  As a result of the comparison, if the read tag and the bit pattern of the tag portion in the address match in any of the ways of the main tag array 12 and the sub tag array 22, it is determined that the cache hit (step Y of S13), the process proceeds to step S14. On the other hand, as a result of the comparison, if the read tag and the bit pattern of the tag portion in the address do not match in any way of the main tag array 12 and the sub tag array 22, it is determined that there is a cache miss. (N of step S13), it progresses to step S15.

  In step S14, the data read from the block corresponding to the index corresponding to the index in the main data array 14 or the sub data array 24 and the way corresponding to the read tag and the bit pattern of the tag portion in the address. Is output from the selection circuits 18 and 28 as output data. In addition, the update of the LRU information held in the LRU array 30 is performed so that the block from which the output data is read out is the block that has not been used for the longest time (hereinafter also referred to as the latest block). To finish the operation.

  On the other hand, in step S15, the LRU reference operation process shown in FIG. 5 is performed. In the LRU reference operation processing, a block that refers to the LRU information held in the LRU array 30 and discards a copy of already registered data and a corresponding tag from the blocks of the main array 10 and the subarray 20 (Oldest block) is determined.

FIG. 5 is a flowchart showing the flow of the LRU reference operation process in step S15 shown in FIG.
In step S 21, LRU information corresponding to the address indicating the access destination is read from the LRU array 30. In other words, from the LRU information held in the LRU array 30, LRU information including information on the order of way ages in the entries of the main array 10 and the sub-array 20 to which the access destination addresses are assigned is read.

  In step S22, the oldest block is determined across the main array and the sub-array by referring to the LRU information read in step S21, and set as a replacement target block in which a copy of the data read from the memory 4 is replaced.

  Returning to FIG. 4, in step S <b> 16, access to the memory 4 is executed, and data is read from the storage area of the memory 4 corresponding to the address indicating the access destination and supplied to the processing unit 2. Further, a copy of the data read from the memory 4 and a tag corresponding to the copy are registered (replaced) in the oldest block determined in the LRU reference operation process in step S15. Then, the LRU information held in the LRU array 30 is updated so that the oldest block in which the data copy and the tag are replaced is the latest block, and the operation ends.

  According to the present embodiment, the main array 10 and the subarray 20 having different numbers of entries are provided, and one area obtained by dividing the memory space by the cache line size is assigned to one entry in each of the main array 10 and the subarray 20. .

  For example, as shown in FIG. 6A, for the address to which the 0th entry consisting of blocks mw00 and mw10 in the main array (way number 2) is assigned, blocks sw00, sw10, sw20 in the subarray (way number 4), The 0th entry consisting of sw30 is assigned. For the address to which the second entry consisting of the blocks mw02 and mw12 of the main array is assigned, the 0th entry of the subarray is assigned. The 0th entry of the subarray is also assigned to each of the address to which the fourth entry consisting of the blocks mw04 and mw14 of the main array is assigned and the address to which the sixth entry consisting of the blocks mw06 and mw16 of the main array is assigned. .

  That is, the 0th entry of the subarray is shared by the 4 entries of the 0th entry, the 2nd entry, the 4th entry, and the 6th entry in the main array. With this configuration, it is possible to realize a mechanism in which four entries in the main array share one entry in the subarray, and each block (way) of the subarray entry is dynamically assigned to the main array entry. be able to. Thus, the number of ways can be dynamically increased or decreased individually for each entry, instead of increasing or decreasing the number of ways uniformly for all entries.

  For example, if the number of ways in the main array is m and the number of ways in the sub-array is n, the number of ways in each entry in the main array can be dynamically changed to a minimum of m and a maximum of (m + n). It is. In the example shown in FIG. 6, as shown in FIG. 6B, the number of ways of each entry is dynamically changed to a minimum of 2 ways by the main array and a maximum of 6 ways by the main array and the subarray. be able to. Therefore, during application execution, the hardware can automatically determine and dynamically increase or decrease the number of ways for each entry according to the application, and automatically change to the optimal number of ways. And the hit rate can be improved.

  According to the present embodiment, due to the increase in the number of ways due to the provision of sub-arrays, even in the case of the conventional method using only the main array, the number of cases of cache hits increases even in the case of a cache miss. Can be improved. Also, comparing this embodiment with the same data array size (when the total number of blocks in the data array is the same) and the conventional method, comparing the number of entries with the conventional configuration according to the subarray in this embodiment, The number of comparators can be reduced.

  Further, when this embodiment is compared with the conventional method with the same data array size (when the total number of blocks in the data array is the same), the subarray blocks can be dynamically allocated to the required entries. Cache utilization efficiency and hit rate can be improved. For example, the cache unit in the present embodiment in which the main array as illustrated has 8 entries and 2 ways and the subarray has 2 entries and 4 ways is compared with the conventional cache unit of 8 entries and 3 ways. At this time, conventionally, when an entry corresponding to the same index is accessed three or more times corresponding to the way size, a cache miss occurs. However, in this embodiment, a cache miss may not occur even if accessed up to six times. The hit rate can be improved.

  In the above-described embodiment, all blocks (way) of sub-array entries are dynamically allocated to main array entries. However, a certain block (way) is fixed to an entry in the main array. May be assigned.

Next, the LRU information held in the LRU array 30 will be described.
When a cache miss occurs, the cache unit 3 performs data copying, tag eviction, and replacement based on the LRU information. In this embodiment, since a plurality of entries in the main array share one entry in the sub-array, the main array is divided for each number of entries in the sub-array, and the total way is considered to be arranged side by side. Let LRU information be a number.

  For example, as shown in FIG. 7A, if the main array has 8 entries and 2 ways, and the subarray has 2 entries and 4 ways, the LRU information is entered as shown in FIG. 7B. Shows the order of the way old when is considered to be placed. That is, LRU information including a set of the 0th entry, the 2nd entry, the 4th entry, the 6th entry, and the 0th entry of the subarray in the main array is held in the LRU array. Similarly, LRU information including a first entry in the main array, a third entry, a fifth entry, a seventh entry, and a first entry in the subarray is held in the LRU array.

  Here, if the way oldness is simply encoded as the LRU information, the number of bits of the LRU information becomes enormous. In order to avoid this, for example, the LRU information may be divided and held in each array (in the main array and in each subarray) and between the arrays (in the main array and the subarray). The amount can be reduced. For example, in the example shown in FIG. 7, as shown in FIG. 7C, the LRU information in each array is encoded by a binary relationship, and the LRU information between arrays is encoded by an order relationship. The per LRU information is composed of 46 bits. In this case, the LRU information between the arrays only needs to be identified in the oldest order not in units of blocks but in units of entries.

  Here, the binary relationship encoding is a method in which the new / old relationship between two blocks (ways) is held in one bit as shown in FIG. In the example shown in FIG. 8A, each bit in order from the upper side is the new / old relationship of the 0th block to the first block, the new / old relationship of the 0th block to the second block, and the old and new of the 0th block to the third block. The relationship shows a new / old relationship of the first block to the second block, a new / old relationship of the first block to the third block, and a new / old relationship of the second block to the third block. For example, the bit indicating the old / new relationship (i and j are integers) of the i-th block with respect to the j-th block is set to “0” when the i-th block is newer than the j-th block, and when the i-th block is older than the j-th block. The value is “1”. Accordingly, when the second block (oldest), the first block, the 0th block, and the third block (latest) are in order, the LRU information is “001011”.

  Further, the encoding based on the order relationship is a method of holding the block numbers as the LRU information in the oldest order as shown in FIG. When the second block (oldest), first block, zeroth block, and third block (latest) are in order, the LRU information is “10010011” as shown in FIG.

  Therefore, the LRU information in the example shown in FIG. 7C indicates that the blocks are older in the order of mw01, mw13, mw11, mw15, sw21, sw11, mw03, mw07, mw17, sw01, mw05, sw31. Yes. mwXY indicates a block of way X and entry Y in the main array, and swXY indicates a block of way X and entry Y in the sub-array. In the above description, the case where the complete new / old relationship is held as the LRU information is described as an example. However, the old / old relationship may be held by breaking to some extent.

  Next, a specific operation example of how each way is dynamically allocated in the main array and sub-array of the cache unit 3 in this embodiment will be described with reference to FIGS. In the following, a case where the program sequence shown in FIG. 9A is executed is shown as an example. Further, for simplicity, the cache configuration will be described assuming that the cache line size is 16 bytes, the main array has 8 entries and 2 ways, and the subarray has 2 entries and 4 ways as shown in FIG. 9B. .

  In the program sequence shown in FIG. 9A, “LD @ (add), R1” indicates a process of reading data at address add and writing it to register R1. In the following, the way wayX and entry 0xY block in the main array are indicated as mwXY, and the way wayX and entry 0xY block in the subarray are indicated as swXY. For example, the block of entry 0x3 of way way1 in the main array is indicated as mw13, and the block of entry 0x1 of way way2 in the sub array is indicated as sw21. Also, the initial values of LRU information (ascending order from old to new, and so on) with the entries 0x1, 0x3, 0x5, 0x7 in the main array and the entry 0x1 in the subarray as one set are mw01, mw11, mw03, mw13, mw05 , Mw15, mw07, mw17, sw01, sw11, sw21, and sw31.

  FIG. 10A shows a state when processing up to the instruction “LD @ (0x51018), R1”. Data of address 0x1101_ is copied to the block mw01. ('_' (Underscore) indicates data divided by the cache line size including the word data of the address accessed by the instruction.) Also, the data at addresses 0x2101_ and 0x1207_ are copied to the blocks mw11 and mw07, respectively. Data of addresses 0x1a01_, 0x1301_, and 0x5101_ are respectively copied to the blocks sw01, sw11, and sw21. At this time, the LRU information is mw03, mw13, mw05, mw15, mw17, sw31, mw01, mw11, mw07, sw01, sw11, and sw21.

  Next, the instruction “LD @ (0x11018), R1” is executed, but a copy of the data at the address 0x1101_ exists in the block mw01 of the main array, which results in a cache hit. Therefore, there is no data change for the main array and the sub-array, and the LRU information is updated. The LRU information is updated as mw03, mw13, mw05, mw15, mw17, sw31, mw11, mw07, sw01, sw11, sw21, mw01.

  Subsequently, the instructions “LD @ (0xab078), R1” and “LD @ (0x22070), R1” are executed. FIG. 10B shows a state after the processing of the instruction “LD @ (0x22070), R1” is completed. The difference from the state shown in FIG. 10A is that data at address 0xab07_ is copied to block mw17 and data at address 0x2207_ is copied to block sw31. The LRU information is updated with the execution of the instruction. At this time, the LRU information is mw03, mw13, mw05, mw15, mw11, mw07, sw01, sw11, sw21, mw01, mw17, and sw31.

  Next, the instruction “LD @ (0xab070), R1” is executed, but a copy of the data at the address 0xab07_ exists in the block mw17 of the main array, so that a cache hit occurs. Therefore, there is no data change for the main array and the sub-array, and the LRU information is updated. The LRU information is updated as mw03, mw13, mw05, mw15, mw11, mw07, sw01, sw11, sw21, mw01, sw31, mw17.

  Next, the instruction “LD @ (0xcb070), R1” is executed. At this time, a copy of the data at the address 0xcb07_ does not exist in the main array and the subarray, resulting in a cache miss. As a result, the data at the address 0xcb07_ is read from the memory and replaced with the oldest block. However, the replaceable blocks are main array blocks corresponding to the accessed address (0xcb07_), that is, blocks mw07 and mw17, and subarray blocks sw01, sw11, sw21, and sw31. Therefore, based on the LRU information, the data at address 0xcb07_ is copied to the oldest block mw07. Also, the LRU information is updated, and the LRU information becomes mw03, mw13, mw05, mw15, mw11, sw01, sw11, sw21, mw01, sw31, mw17, and mw07.

  Next, the instruction “LD @ (0x2b070), R1” is executed. In this case as well, a cache miss occurs, and the data at address 0x2b07_ is read from the memory and replaced with the oldest block. The replaceable blocks are main array blocks corresponding to the accessed address (0x2b07_), that is, blocks mw07 and mw17, and subarray blocks sw01, sw11, sw21, and sw31. Therefore, based on the LRU information, the data at the address 0x2b07_ is copied to the oldest block sw01, and the data is as shown in FIG. Also, the LRU information is updated, and the LRU information becomes mw03, mw13, mw05, mw15, mw11, sw11, sw21, mw01, sw31, mw17, mw07, sw01.

  Although the case where the cache unit has two arrays of the main array and the sub-array has been described as an example, the present invention is not limited to this, and the cache unit may have three or more arrays. It suffices to have a plurality of data arrays and at least one of the data arrays has a different number of entries (that is, the number of data array entries is two or more). A plurality of arrays are simultaneously referred to based on the index portion having the number of bits corresponding to the number of entries in the address indicating the access destination, and two or more pieces of data can be copied at a certain time in the memory space. Avoid being in the array at the same time. The number of entries in the data array having the maximum number of entries is preferably an integer multiple of the number of entries in the other data array. Moreover, although the number of ways is 2 and 4 as an example, the number of ways is not limited to this, and the number of ways is arbitrary. Note that the number of ways may be 1, that is, the direct mapping method.

  The above-described embodiments are merely examples of implementation in carrying out the present invention, and the technical scope of the present invention should not be construed as being limited thereto. That is, the present invention can be implemented in various forms without departing from the technical idea or the main features thereof.

DESCRIPTION OF SYMBOLS 1 Information processing apparatus 2 Processing part 3 Cache part 4 Memory 10 1st array (main array)
20 Second array (subarray)
30 LRU array 12, 22 Tag array 14, 24 Data array 16, 26 Comparator 18, 28 Selection circuit

Claims (5)

A processing unit for processing the data;
A cache unit provided between the storage unit storing the data and the processing unit;
The cache unit is
A plurality of data arrays to which data of the storage unit is copied;
An information array holding first information indicating the order of the way in the plurality of data arrays,
Each of the plurality of data arrays has a number of ways of 1 or more, and at least one of the plurality of data arrays has a different number of entries,
An information processing apparatus, wherein one entry is allocated in each of the plurality of data arrays to a storage area of the storage unit divided into a predetermined size.   2. The information processing according to claim 1, wherein the plurality of data arrays are simultaneously referred to based on an index portion in the address corresponding to each data array based on an address indicating an access destination from the processing unit. apparatus.   3. The information processing apparatus according to claim 1, wherein when the data in the storage unit is copied to the data array, the information processing apparatus copies the data to any one of the plurality of data arrays.   The first information is stored in the information array by dividing into information indicating the order of way ages in the data array for each data array and information indicating the order of way ages between the data arrays. The information processing apparatus according to claim 1, wherein the information processing apparatus is an information processing apparatus.   5. The information processing according to claim 1, wherein the number of entries in the data array having the maximum number of entries is an integer multiple of the number of entries in the data array other than the data array. apparatus.

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