JP2011134960A - Semiconductor device, method for manufacturing the same, wiring base material for connecting semiconductor element, wiring board for mounting semiconductor device, and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which is thinned as a first characteristic and has excellent high connection reliability as a second characteristic. <P>SOLUTION: There is provided the semiconductor device including a conductive metal layer pattern having a semiconductor element electrically connected thereto and a conductive metal layer pattern for wiring via a die-bonding material on the lower part of the semiconductor element, wherein the patterns are sealed with a sealing resin. In the semiconductor device, the conductive metal layer patterns are partly exposed to protrude in the thickness direction. The amount of protrusion of the conductive metal layer is a thickness of 1 μm or more in the thickness direction and 1/2 or less of the thickness of the metal layer, and a portion with the maximum width of a cross sectional shape is buried in the sealing material or the die-bonding material. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a semiconductor device, a manufacturing method thereof, a wiring substrate for connecting a semiconductor element, a wiring board mounted with a semiconductor device, and a manufacturing method thereof.

Conventionally, as a CSP semiconductor device, a semiconductor device manufacturing method using a conventional wiring board manufacturing process has been proposed (see Patent Document 1). Patent Document 1 generally describes the following (in particular, see FIGS. 33 and 37). First, a polyimide film with a single-sided adhesive is prepared. A through hole is made at a position where a solder ball is mounted on the polyimide film, and then a copper foil is thermocompression bonded to one side of the polyimide film with an adhesive. Next, a photosensitive resist film is bonded to the copper foil surface, and exposed and developed by a conventional method to form an etching resist pattern. Next, after etching the copper foil, the dry film is peeled off to form a substrate having a predetermined wiring pattern. Next, nickel plating and gold plating are applied to the formed wiring pattern by plating. Next, a semiconductor element having an aluminum wiring electrode pad, usually on one side, is bonded to the central portion with a die bond film, and then the aluminum wiring electrode pad and the wiring pad of the substrate are connected with a gold bonding wire. These are then sealed with a sealing material, and finally, separated into individual CSPs by dicing, and solder balls are mounted at predetermined positions.
However, in the case of Patent Document 1, since one side of a single-sided polyimide film wiring board on which a pattern is formed by photolithography is resin-sealed as it is, the cross-sectional shape of the wiring pattern becomes a shape with a tail, and the wiring shape corresponds to the sealing resin. Since the anchor effect is low and the adhesion between the polyimide film and the sealing resin is low, there is a problem that the adhesion strength between the polyimide film wiring board and the sealing resin is low. Further, since the conductor on which the solder ball is mounted does not protrude from the surface of the semiconductor device, there is a limit to the reliability with respect to the shearing force of the external connection portion. Furthermore, since the wiring is formed after the copper foil is thermocompression-bonded to one side of the polyimide film, there is a problem that warping occurs if the rigidity of the support substrate is low. Above all, there is a problem in that it is necessary to form a wiring pattern for each product, which is very expensive.
A conventional method for manufacturing a semiconductor device using a manufacturing process of a wiring board has limitations in high connection reliability, thinning, and productivity (cost reduction) of a CSP semiconductor device.

JP 2007-329503 A

  The present invention firstly provides a semiconductor device excellent in thinning. Second, a semiconductor device excellent in high connection reliability is provided. In addition, the present invention provides a wiring board including such a semiconductor device and a wiring substrate for connecting a semiconductor element for producing such a semiconductor device. Moreover, this invention provides the manufacturing method excellent in productivity of such a semiconductor device and a wiring board.

The present invention relates to the following.
1. A semiconductor device including a conductive metal layer pattern to which a semiconductor element is electrically connected and a conductive metal layer pattern for wiring under a semiconductor element via a die bonding material, and these are sealed with a sealing material The semiconductor device, wherein the conductive metal layer pattern is partially exposed in the thickness direction.
2. The connecting member of the semiconductor element and the conductive metal layer pattern is a bonding wire for wire bonding connection between a predetermined position of the semiconductor element and the conductive metal layer pattern, and the semiconductor element, the conductive metal layer pattern and the bonding wire are Item 2. The semiconductor device according to Item 1, which is sealed with a sealing material.
3. Item 2. The semiconductor device according to Item 1, wherein the semiconductor element and the conductive metal layer pattern connecting member and the die bond material are anisotropic conductive adhesives, and these are sealed with a sealing material.
4). Item 4. The semiconductor device according to any one of Items 1 to 3, wherein the protruding amount of the conductive metal layer is 1 μm or more in the thickness direction and a thickness of ½ or less of the metal layer thickness.
5. Item 5. The semiconductor device according to any one of Items 1 to 4, wherein a portion of the conductive metal layer having a maximum width in a cross-sectional shape is buried in a sealing material or a die bond material.
6). Item 6. The semiconductor device according to any one of Items 1 to 5, wherein a solder ball is bonded to a conductive metal layer portion to be electrically bonded to the wiring board.
7). On the substrate for peeling, the conductive metal layer pattern to be connected to the semiconductor element and the conductive metal layer pattern for wiring on which the semiconductor element is to be mounted via the die-bonding material, and these conductive metal layer patterns are A wiring substrate for connecting a semiconductor element, which is partially embedded in the thickness direction.
8). Item 8. The wiring substrate for connecting a semiconductor element according to Item 7, wherein the amount of the conductive metal layer embedded in the substrate for peeling is 1 μm or more in the thickness direction and 1/2 or less the thickness of the metal layer.
9. Item 9. The wiring substrate for connecting a semiconductor element according to any one of Items 7 and 8, wherein the conductive metal layer has a cross-sectional shape having a maximum width exposed from the substrate for peeling.
10. The process of joining a semiconductor element via a die-bonding material on the conductive metal layer pattern for wiring on which the semiconductor element of the wiring base material for semiconductor element connection in any one of claim | item 7 -9 is mounted, Bonded semiconductor A step of connecting an element and the conductive metal layer pattern for connecting the semiconductor element, a step of integrally sealing the semiconductor element and the conductive metal layer pattern bonded on the peelable substrate with a sealing material, and sealing A method for manufacturing a semiconductor device, comprising a step of peeling a peeling substrate from a semiconductor element mounting substrate on which a semiconductor element is mounted, which is sealed with a stopper.
11. While joining a semiconductor element on the conductive metal layer pattern for wiring by which the semiconductor element of the wiring base material for semiconductor element connection in any one of claim | item 7 -9 should be mounted using anisotropic conductive adhesive A step of connecting a semiconductor element having a bump at a position to be electrically connected and a conductive metal layer pattern for connecting a semiconductor element;
A semiconductor element bonded and connected on the peelable substrate and a step of integrally sealing the conductive metal layer pattern with a sealing material, and a semiconductor element mounted with the semiconductor element sealed with the sealing material A method for manufacturing a semiconductor device, comprising a step of peeling a peeling substrate from a mounting substrate.
12 Item 12. The semiconductor device according to any one of Items 10 or 11, further comprising a step of performing connection plating on a connection portion of the conductive metal layer pattern before the step of bonding the semiconductor element and the conductive metal layer pattern for connecting the semiconductor element. Manufacturing method.
13. Item 13. The method for producing a semiconductor device according to any one of Items 10 to 12, further comprising a step of bonding a solder ball to a conductive metal layer portion to be electrically bonded to the wiring board.
14 Item 7. A semiconductor device mounting wiring board, wherein the semiconductor device according to any one of Items 1 to 6 is soldered to a predetermined position of the wiring board with a metal layer portion protruding from the semiconductor device.
15. Soldering is performed so that the protruding metal layer of the semiconductor device according to any one of Items 1 to 5 is covered with solder through the solder at the predetermined position of the wiring board on which the solder is attached at a predetermined position on the wiring. A method for manufacturing a semiconductor device mounting wiring board.
16. A method of manufacturing a wiring board having a semiconductor device mounted thereon, wherein the semiconductor device according to item 6 is soldered to a predetermined position of wiring on the wiring board with solder balls of the semiconductor device.

  According to the wiring substrate for connecting a semiconductor element according to the present invention, since a peelable substrate is used, it is easy to manufacture a semiconductor device including a semiconductor element and a conductive metal layer pattern for connecting a semiconductor element or mounting a semiconductor element. In addition, the semiconductor device can be thinned. Furthermore, by using this wiring substrate for mounting a semiconductor element, a part of the conductive metal layer pattern can be easily protruded from the semiconductor device in the thickness direction, so that the connection reliability of external connection is excellent. A semiconductor device can be easily obtained. In addition, the number of manufacturing steps of the semiconductor device can be reduced, and productivity can be improved. As a result, it is easy to manufacture a wiring board on which such a semiconductor device is mounted.

The partial perspective view which shows an example of the electroconductive base material for plating of this invention. AA sectional drawing of FIG. The partial cross section figure of the electroconductive base material for plating which has a recessed part. The partial cross section figure which shows an example of the process which shows the manufacturing method of the electroconductive base material for plating. The partial cross section figure which shows the preparation example of the wiring base material for a semiconductor element connection. Sectional drawing which shows the state which formed the metal layer by plating in the formation part (recessed part) for plating of the electroconductive base material for plating. The partial cross section figure which shows an example of the plated wiring base material for semiconductor element connection. The partial cross section figure which shows the first half of the manufacturing process of a semiconductor device. The partial cross section figure which shows the middle half of the manufacturing process of a semiconductor device. The partial cross section figure which shows the latter half of the manufacturing process of a semiconductor device. The partial cross section figure which shows the process of mounting a semiconductor device on a motherboard by soldering and producing a semiconductor device mounting wiring board.

The wiring substrate for connecting a semiconductor element according to the present invention has a conductive metal layer pattern for wiring on which a semiconductor device is to be mounted via a conductive metal layer pattern for connecting a semiconductor element and a die bonding material on a peelable substrate. The wiring substrate for connecting a semiconductor element temporarily mounts a semiconductor element.
Examples of the substrate material of the peelable substrate in the present invention include a plate made of glass, plastic, etc., a plastic film, a plastic sheet, a metal sheet and the like. As the glass, glass such as soda glass, non-alkali glass, and tempered glass can be used.
Plastics include polystyrene resin, acrylic resin, polymethyl methacrylate resin, polycarbonate resin, polyvinyl chloride resin, polyvinylidene chloride resin, polyethylene resin, polypropylene resin, polyamide resin, polyamideimide resin, polyetherimide resin, polyetheretherketone Resin, polyarylate resin, polyacetal resin, polybutylene terephthalate resin, polyethylene terephthalate resin, thermoplastic polyester resin such as polyethylene naphthalate, cellulose acetate resin, fluororesin, polysulfone resin, polyethersulfone resin, polymethylpentene resin, polyurethane resin And thermoplastic resins such as diallyl phthalate resin and thermosetting resins. Among plastics, polystyrene resin, acrylic resin, polymethyl methacrylate resin, polycarbonate resin, and polyvinyl chloride resin, which are excellent in transparency, are preferably used. Examples of the metal include metals such as copper, aluminum, stainless steel, nickel, iron, and titanium, and alloys thereof (42 alloy, etc.).

  The substrate material of the peelable substrate in the present invention is preferably a plastic film. Examples of the plastic film include polyesters such as polyethylene terephthalate (PET) and polyethylene naphthalate (PEN), polyolefins such as polyethylene, polypropylene, polystyrene and EVA, vinyl resins such as polyvinyl chloride and polyvinylidene chloride, polysulfone, A film made of plastic such as polyethersulfone, polycarbonate, polyamide, polyimide, and acrylic resin is preferable, and a film having a total visible light transmittance of 70% or more is preferable. These can be used as a single layer, but may be used as a multilayer film in which two or more layers are combined. Among the plastic films, a polyethylene naphthalate film or a polycarbonate film is particularly preferable from the viewpoints of transparency, heat resistance, ease of handling, and cost.

  The thickness of the base material is not particularly limited, but is preferably 10 μm or more and 1 mm or less, and more preferably 20 μm or more and 0.5 mm or less. If the base material is too thick, curling is likely to occur on the base material, and in the case of a roll product, curling tends to occur. On the other hand, when the substrate material is too thin, the handleability in the transport process is deteriorated when the roll-to-roll method is used. When it is necessary to convey in the form of a single wafer, the base material is required to have a certain degree of rigidity. Therefore, the thickness of the base material is preferably 200 μm or more.

In addition, the peelable substrate has sufficient adhesion in the semiconductor device manufacturing process with respect to the conductive metal layer pattern formed thereon and the sealing material provided in contact with the peelable substrate. When peeling, it is easy to peel off. In particular, for example, the curing process of the sealing material is usually 6 hours at a high temperature of 175 ° C., and it is necessary to peel off the substrate after receiving a thermal history. For that purpose, the peelable substrate needs to have an appropriate adhesion strength of the peelable substrate to the conductive metal layer pattern formed thereon and the sealing material provided in contact with the peelable substrate. . In the present invention, the adhesiveness of the peelable substrate (or adhesive) is such that the adhesion strength of the conductive metal layer pattern to the peelable substrate (or adhesive) is 90 ° peel strength at 25 ° C., 0.05 It is preferably ˜5 kN / m, more preferably 0.1 to 3 kN / m.
In the present invention, the 90-degree peel strength at 25 ° C. is measured in accordance with the JIS Z 0237 90-degree peeling method. Specifically, at 25 ° C., 270 to 330 mm per minute, preferably every minute. The 90-degree peel strength when the peelable substrate (or adhesive) is peeled off at a speed of 300 mm is measured. For example, a 90-degree peel tester (manufactured by Tester Sangyo) can be used.
In addition, the adhesion strength of the conductive metal layer pattern after sealing to the sealing material must be lower than the adhesion strength of the conductive metal layer pattern to the peelable substrate (or adhesive).

Although the said peelable base material needs to have moderate adhesiveness and peelability, in other words, it needs to have moderate adhesiveness. For that purpose, the base material itself of the peelable substrate may have the necessary adhesiveness, but it is preferable to laminate a suitable pressure-sensitive adhesive layer on the base material to form a peelable base material. . In this case, it is preferable that the pressure-sensitive adhesive layer is peeled off together with the base material.
In the pressure-sensitive adhesive layer, the peeling force is determined by the 90-degree peel strength at 25 ° C. described above.

  It is preferable that the base material has sufficiently high adhesion to the pressure-sensitive adhesive. If the adhesiveness is low, only the base material may be peeled while leaving the pressure-sensitive adhesive layer when the peelable base material is to be peeled off during the manufacturing process of the semiconductor device described later.

The base material preferably has a shrinkage rate of 1% or less after receiving a heat history in the sealing step in order to reduce warpage after the conductive metal layer pattern is applied, and 0.1% More preferably, it is as follows. Further, the linear thermal expansion coefficient at 20 to 200 ° C. is preferably 3.0 × 10 ⁻⁵ / ° C. or less, more preferably 2.5 × 10 ⁻⁵ / ° C. or less. It is more preferable that it is 0.0 × 10 ⁻⁵ / ° C. or less, and it is best that it is equal to or approximately equal to the linear expansion coefficient of the conductive metal.

In addition, it is easy to bring the linear expansion coefficient of the base material to a metal layer selected from metals as the base material, and it is easy to reduce the warpage of the semiconductor element mounting base material according to the present invention.
Moreover, when using curable resin hardened | cured by irradiation of an active energy ray as an adhesive layer, the base material has a preferable thing which permeate | transmits these active energy rays.

As the material having adhesiveness, a resin having a glass transition temperature of 80 ° C. or lower is preferable, a resin having a temperature of 20 ° C. or lower is more preferable, and a resin having a temperature of 0 ° C. or lower is most preferable. However, in the case of a thermoplastic resin, one having a low glass transition temperature may be used, but in view of stability after solidification, one having a glass transition temperature of 50 ° C. or higher is preferable, and one that melts by heating at the time of adhesion is preferable.
Moreover, as a material used for an adhesive layer, a thermoplastic resin, a thermosetting resin, resin hardened | cured by irradiation of an active energy ray, etc. can be used. The thermoplastic resin, thermosetting resin, and resin cured by irradiation with active energy rays preferably have a weight average molecular weight of 500 or more. If the molecular weight is less than 500, the cohesive strength of the resin is too low, and the adhesion to the metal may be reduced.

  Typical examples of the thermoplastic resin include the following. For example, natural rubber, polyisoprene, poly-1,2-butadiene, polyisobutene, polybutene, poly-2-heptyl-1,3-butadiene, poly-2-t-butyl-1,3-butadiene, poly-1,3 -Dienes such as butadiene), polyethers such as polyoxyethylene, polyoxypropylene, polyvinyl ethyl ether, polyvinyl hexyl ether and polyvinyl butyl ether, polyesters such as polyvinyl acetate and polyvinyl propionate, polyurethane, ethyl cellulose , Polyvinyl chloride, polyacrylonitrile, polymethacrylonitrile, polysulfone, polysulfide, phenoxy resin, polyethyl acrylate, polybutyl acrylate, poly-2-ethylhexyl acrylate, poly-t-butyl Acrylate, poly-3-ethoxypropyl acrylate), polyoxycarbonyl tetramethacrylate, polymethyl acrylate, polyisopropyl methacrylate, polydodecyl methacrylate, polytetradecyl methacrylate, poly-n-propyl methacrylate, poly-3,3,5-trimethyl Poly (meth) acrylic acid esters such as cyclohexyl methacrylate, polyethyl methacrylate, poly-2-nitro-2-methylpropyl methacrylate, poly-1,1-diethylpropyl methacrylate, and polymethyl methacrylate can be used. The monomers constituting these polymers may be used as a copolymer obtained by copolymerization of two or more, if necessary, or may be used by blending two or more of the above polymers or copolymers. .

Examples of the resin curable with active energy rays include materials in which an acrylic resin, an epoxy resin, a polyester resin, a urethane resin, or the like is used as a base polymer and a radically polymerizable or cationically polymerizable functional group is added to each. As the radical polymerizable functional group, there are carbon-carbon double bonds such as an acrylic group (acryloyl group), a methacryl group (methacryloyl group), a vinyl group, and an allyl group, and a highly reactive acrylic group (acryloyl group) is preferable. Used for. As the cationically polymerizable functional group, an epoxy group (glycidyl ether group, glycidylamine group) is representative, and a highly reactive alicyclic epoxy group is preferably used. Specific materials include acrylic urethane, epoxy (meth) acrylate, epoxy-modified polybutadiene, epoxy-modified polyester, polybutadiene (meth) acrylate, and acrylic-modified polyester. As the active energy rays, ultraviolet rays, electron beams and the like are used.
When the active energy ray is ultraviolet, photosensitizers or photoinitiators added at the time of ultraviolet curing include known materials such as benzophenone, anthraquinone, benzoin, sulfonium salt, diazonium salt, onium salt, and halonium salt. Can be used. In addition to the above materials, a general-purpose thermoplastic resin may be blended.

  As thermosetting resins, natural rubber, isoprene rubber, chloroprene rubber, polyisobutylene, butyl rubber, halogenated butyl, acrylonitrile-butadiene rubber, styrene-butadiene rubber, polyisobutene, carboxy rubber, neoprene, polybutadiene and the like as crosslinking agents Sulfur, aniline formaldehyde resin, urea formaldehyde resin, phenol formaldehyde resin, ligrin resin, xylene formaldehyde resin, xylene formaldehyde resin, melamine formaldehyde resin, epoxy resin, urea resin, aniline resin, melamine resin, phenol resin, formalin resin, metal oxide Products, metal chlorides, oximes, alkylphenol resins and the like. In addition, for these purposes, additives such as general-purpose vulcanization accelerators can be used for the purpose of increasing the crosslinking reaction rate.

  As a thermosetting resin, those using a curing agent include a resin having a functional group such as a carboxyl group, a hydroxyl group, an epoxy group, an amino group, an unsaturated hydrocarbon group, an epoxy group, a hydroxyl group, an amino group, an amide group, Some are used in combination with a curing agent having a functional group such as a carboxyl group or a thiol group, or a curing agent such as a metal chloride, isocyanate, acid anhydride, metal oxide, or peroxide. In addition, for the purpose of increasing the curing reaction rate, additives such as general-purpose catalysts can be used. Specific examples include curable acrylic resin compositions, unsaturated polyester resin compositions, diallyl phthalate resins, epoxy resin compositions, polyurethane resin compositions, and the like.

Furthermore, as a thermosetting resin or a resin curable with an active energy ray, an adduct of acrylic acid or methacrylic acid can be exemplified as a preferable one.
As an adduct of acrylic acid or methacrylic acid, epoxy acrylate (n = 1.48 to 1.60), urethane acrylate (n = 1.5 to 1.6), polyether acrylate (n = 1.48 to 1) .49), polyester acrylate (n = 1.48 to 1.54), and the like can also be used. In particular, urethane acrylate, epoxy acrylate, and polyether acrylate are excellent from the viewpoint of adhesiveness. Examples of epoxy acrylate include 1,6-hexanediol diglycidyl ether, neopentyl glycol diglycidyl ether, allyl alcohol diglycidyl ether, and resorcinol. (Meth) acrylic such as diglycidyl ether, diglycidyl adipate, diglycidyl phthalate, polyethylene glycol diglycidyl ether, trimethylolpropane triglycidyl ether, glycerin triglycidyl ether, pentaerythritol tetraglycidyl ether, sorbitol tetraglycidyl ether An acid adduct is mentioned. A polymer having a hydroxyl group in the molecule, such as epoxy acrylate, is effective in improving adhesion. These copolymer resins can be used in combination of two or more as required.

  In the present invention, those having adhesiveness or those exhibiting adhesiveness (hereinafter referred to as “adhesive”) are optionally cross-linking agent, curing agent, diluent, plasticizer, oxidation You may mix | blend additives, such as an inhibitor, a filler, a coloring agent, a ultraviolet absorber, and a tackifier.

  In forming the pressure-sensitive adhesive layer on the base material, it is easy and preferable to apply the pressure-sensitive adhesive to the base material. The method for applying the pressure-sensitive adhesive is not particularly limited, and examples thereof include die coating, roll coating, reverse roll coating, gravure coating, bar coating, and comma coating.

  The thickness of the pressure-sensitive adhesive layer is preferably 0.5 to 100 μm, more preferably 3 μm or more, and further preferably 5 μm or more in order to have sufficient adhesion in the process of manufacturing a semiconductor device. Moreover, since adhesiveness will become high when the thickness of an adhesive layer is thick, especially peeling after a heat history becomes difficult, it is more preferable that it is 30 micrometers or less, and it is further more preferable that it is 20 micrometers or less.

  When the said adhesive is using curable resin, it is preferable that the glass transition temperature of the adhesive after hardening is 50-300 degreeC, in order to improve heat resistance, it is 100-300 degreeC. It is more preferable, and it is especially preferable that it is 150-250 degreeC. If the glass transition temperature is too low, the pressure-sensitive adhesive layer is softened by heat in the wire bonding process, and wire bonding failure is likely to occur, or the pressure-sensitive adhesive layer is softened by heat in the sealing process and laminated thereon. There is a possibility that defects due to heat, such as a tendency for the plating resist to easily enter between the metal layers, may occur. Moreover, when the glass transition temperature is too high, the 90-degree peel strength at 25 ° C. with the metal layer pattern tends to decrease. The glass transition temperature is measured with a thermomechanical analyzer (for example, TMA-120, manufactured by Seiko Denshi Kogyo Co., Ltd.) in a tensile mode with a heating rate of 10 ° C./min and a load of 10 g. .

Moreover, the linear thermal expansion coefficient in 20-200 degreeC of the said adhesive layer (when using curable resin, the adhesive layer after hardening) may be 3.0 * 10 < ^-5 > / degrees C or less. Preferably, it is 2.5 × 10 ⁻⁵ / ° C. or less, and more preferably 2.0 × 10 ⁻⁵ / ° C. or less. It is best to be equal to or approximately equal to the coefficient of linear expansion of the conductive metal.

  The metal layer pattern is preferably made of a conductive metal such as copper, gold, silver, aluminum, tungsten, nickel, iron, or chromium. Although the material of a metal layer pattern is not specifically limited, It is preferable that it is copper so that a metal layer pattern can be formed easily. The conductive metal layer pattern is designed to be applied to a semiconductor device or a manufacturing process thereof.

  The conductor thickness of the metal layer pattern is not particularly limited, but is preferably 5 to 100 μm, more preferably 10 to 50 μm, and particularly preferably 15 to 30 μm. If the conductor thickness of the metal layer pattern is too thick, it takes time to form the metal layer pattern, and the material cost also increases. If it is too thin, the wiring strength decreases.

A method for producing a wiring substrate for connecting semiconductor elements according to the present invention will be described.
In a preferred method for manufacturing a wiring substrate for connecting a semiconductor element according to the present invention, a metal layer corresponding to a conductive metal layer pattern required in a semiconductor device or its manufacturing process is formed on a conductive substrate for plating by plating, This metal layer is produced by transferring to a transfer substrate. The transfer substrate is the above-described peelable substrate.

First, the conductive substrate for plating will be described.
A preferred conductive substrate for plating used in the present invention is a conductive substrate having a plating forming portion corresponding to the conductive metal layer pattern, and an insulating layer is formed on the surface of the conductive substrate. And the recessed part (plating formation part) opened in order to form plating in the insulating layer is formed. The conductive material is exposed on the bottom surface of the recess. The concave portion preferably has a shape that is wide toward the opening direction.

  In the present invention, the conductive material used for the conductive substrate has sufficient conductivity for depositing metal on the exposed surface by electrolytic plating, and is particularly preferably a metal. In addition, the base material has low adhesion to the metal layer formed on it so that the metal layer formed by electrolytic plating on the surface can be transferred to the transfer base material, and can be easily peeled off. It is preferable that As such a conductive base material, stainless steel, chrome-plated cast iron, chrome-plated steel, titanium, titanium-lined material, nickel and the like are particularly preferable.

  Examples of the shape of the conductive substrate include a sheet shape, a plate shape, a roll shape, and a hoop shape. In the case of a roll, a sheet or plate attached to a rotating body (roll) may be used. In the case of a hoop shape, a configuration in which rolls are installed at two to several locations inside the hoop and a hoop-shaped conductive base material is passed through the roll can be considered. Since it is possible to continuously produce a metal foil in both a roll shape and a hoop shape, the production efficiency is higher than that in a sheet shape or a plate shape, which is preferable. When the conductive substrate is used by being wound around a roll, a conductive roll is preferably used so that the roll and the conductive substrate are easily conducted.

  The thickness of the insulating layer corresponds to the depth of the recess. Since the depth of the recess is related to the thickness of the plating to be deposited, it is appropriately determined according to the purpose. The thickness of the insulating layer is preferably in the range of 0.10 μm to 100 μm, more preferably in the range of 0.1 μm to 20 μm, and particularly preferably in the range of 0.5 μm to 10 μm. . If the insulating layer is too thin, pinholes are likely to be generated in the insulating layer, so that when the plating is performed, the metal is likely to be deposited on the portion where the insulating layer is applied. The thickness of the insulating layer is particularly preferably 1 to 5 μm.

The insulating layer can be formed of a carbon thin film similar to diamond, a so-called diamond-like carbon (hereinafter referred to as DLC) thin film having an insulating property. The DLC thin film is particularly preferable because it is excellent in durability and chemical resistance.
Furthermore, the insulating layer can be formed of an inorganic material such as an inorganic compound such as Al ₂ O ₃ or SiO ₂ .

  The shape of the recess or the insulating layer is appropriately determined according to the purpose, but corresponds to the conductive metal layer pattern for a semiconductor device or the conductive metal layer pattern required in the manufacturing process thereof.

An example of the conductive substrate for plating according to the present invention will be described with reference to the drawings.
FIG. 1 is a partial perspective view showing an example of a conductive substrate for plating according to the present invention. FIG. 2 is a cross-sectional view taken along the line AA in FIG. FIG. 2A shows a case where the side surface of the recess is planar, while FIG. 2B shows a case where the side surface of the recess has gentle irregularities. In the conductive base material 1 for plating, an insulating layer 3 is laminated on a conductive base material 2, and a recess 4 is formed in the insulating layer 3. The conductive base material 2 is exposed at the bottom of the recess 4. The bottom of the recess 4 may be a conductor layer that is electrically connected to the conductive substrate.
In this example, a certain pattern composed of the insulating layer 3 and the recess 4 is repeated in the cross-sectional direction of FIG. 2, but the number of repetitions is appropriately determined. In addition, in the direction perpendicular to the cross-sectional direction, the insulating layer 3 or the concave portion 4 extends so as to have a predetermined length, and as shown in the front of FIG. 1, it joins the concave portion in the cross-sectional direction of FIG. It ’s good. The concave portion is not limited to the groove shape (the planar shape is linear, rectangular or other shapes), and the planar shape may be a square such as a square, a circle, or a hole having another shape. It is determined appropriately according to the purpose.
A conductive or insulating intermediate layer (not shown) may be laminated between the conductive substrate 2 and the insulating layer 3 for the purpose of improving the adhesiveness of the insulating layer 3 or the like. Or the side surface of the recessed part 4 has spread as a whole toward the opening direction.

The said recessed part is demonstrated. FIG. 3 is a partial cross-sectional view of a conductive substrate for plating having a recess. An insulating layer 3 is laminated on the conductive substrate 2, and a recess 4 is formed in the insulating layer 3. Although it is preferable that the side surface of the concave portion is open toward the opening direction, it is not always necessary that the side surface of the concave portion is constantly spread with the gradient α as shown in FIG. If there is no problem in peeling off the metal layer formed by plating, the side surface may have a part that closes toward the opening direction, but it is better not to have such a part, and the side surface is open. It is preferable that it is not closed toward the direction and spreads as a whole. In particular, it is preferable that one side surface of the concave portion together with the opposite surface thereof has no portion that is perpendicular to the bottom surface and continues in the height direction by 1 μm or more. If it is such a conductive substrate for plating, after plating using it, when peeling the deposited metal layer from the conductive substrate for plating, friction between the metal layer and the insulating layer or The resistance can be reduced, and the peeling becomes easier.
The width, diameter, etc. of the recess (d at the opening and d ′ at the bottom) are determined according to the purpose.

によってαを決定する。
αは、角度で３０度以上９０度未満が好ましく、３０度以上８０度以下がより好ましく、３０度以上６０度以下が特に好ましい。この角度が小さいと作製が困難となる傾向があり、大きいと凹部にめっきにより形成し得た金属層（金属層パターン）を剥離する際、又は、転写用基材に転写する際の抵抗が大きくなる傾向がある。 The side surface of the recess is not necessarily a flat surface. In this case, as shown in FIG. 2 (b), the gradient α is such that the height h of the concave portion (in this drawing, the thickness of the insulating layer) and the width s of the side surface of the concave portion (the concave portion in the horizontal direction). Width direction of the side)

Determines α.
α is preferably 30 ° or more and less than 90 °, more preferably 30 ° or more and 80 ° or less, and particularly preferably 30 ° or more and 60 ° or less. If this angle is small, the production tends to be difficult. If the angle is large, the resistance when peeling the metal layer (metal layer pattern) formed by plating in the recess or transferring to the transfer substrate is large. Tend to be.

  In addition, the thickness of the insulating layer is the same as described above. In order to correspond to this, the depth of the recess 4 in the conductive substrate for plating of the present invention is preferably 0.1 to 100 μm. 0.1 to 20 μm is more preferable, 0.5 to 10 μm is further preferable, and 1 to 5 μm is particularly preferable.

As a preferred method for producing the conductive substrate for plating in the present invention, an insulating layer is formed on the surface of the conductive substrate so that a specific conductive metal layer pattern is drawn by the recesses exposing the conductive substrate. Forming.
This step is a step (A) of forming a removable convex pattern (corresponding to the above conductive metal layer pattern) on the surface of the conductive substrate,
(B) including a step of forming an insulating layer on the surface of the conductive substrate on which a removable convex pattern is formed, and (C) a step of removing the convex pattern to which the insulating layer is attached. .

For the step (A) of forming a removable convex pattern on the surface of the conductive substrate, a method of forming a resist pattern using a photolithographic method can be used.
This method (Method a)
(A-1) a step of forming a photosensitive resist layer on the conductive substrate;
(A-2) including a step of exposing the photosensitive resist layer through a mask corresponding to the conductive metal layer pattern, and (a-3) a step of developing the exposed photosensitive resist layer.

Further, in this method (method b), the step (A) of forming a removable convex pattern on the surface of the conductive substrate is as follows:
(B-1) a step of forming a photosensitive resist layer on the conductive substrate;
(B-2) a step of irradiating the photosensitive resist layer with a laser beam without masking a portion corresponding to the conductive metal layer pattern; and (b-3) a step of developing the photosensitive resist layer after the laser beam irradiation. including.

  As the photosensitive resist, a well-known negative resist (a portion irradiated with light is cured) can be used. At this time, a negative mask (light passes through a portion corresponding to the concave portion) is also used as the mask. Further, a positive resist can be used as the photosensitive resist. Corresponding to these methods, the light irradiation part in the method a and method b is appropriately determined.

  As a specific method, by laminating a dry film resist (photosensitive resin layer) on a conductive substrate, and wearing a mask to expose it, the part that remains as a convex pattern can be cured and the unnecessary part can be developed. It can be formed by developing and removing unnecessary portions. In addition, the convex pattern is a state in which the portion that remains as the convex pattern is cured by applying a liquid resist to the conductive substrate and then drying or temporarily curing the solvent, and then exposing the mask with a mask. Alternatively, the unnecessary portion can be developed, and the unnecessary portion can be developed and removed. The liquid resist can be applied by spraying, dispenser, dipping, roll, spin coating or the like.

In the above, after laminating a dry film resist or applying a liquid resist, it is also possible to employ a method of directly exposing without using a mask with a laser beam or the like instead of exposing through a mask. If the patterning can be performed by irradiating the photocurable resin with active energy rays with or without a mask, the mode is not limited.
When the size of the conductive substrate is large, a method using a dry film resist is preferable from the viewpoint of productivity. When the conductive substrate is a plating drum, the dry film resist is laminated or a liquid resist is applied. Then, a method of directly exposing with a laser beam or the like without using a mask is preferable.

  In the above, it can carry out also by the method of using a thermosetting resin instead of a photosensitive resist, and removing the unnecessary part of a thermosetting resin by irradiation of a laser beam.

  Although a resist pattern (convex pattern) can be formed by using a printing method, in this case, various methods can be used as a resist pattern printing method. For example, screen printing, letterpress printing, letterpress offset printing, letterpress reversal offset printing, intaglio printing, letterpress printing, ink jet printing, flexographic printing, and the like can be used. As the resist, a photocurable or thermosetting resin can be used. After printing, the resist is cured by light irradiation or heat.

An example of the manufacturing method of the electroconductive base material for plating in this invention is demonstrated using drawing.
FIG. 4 is a sectional view showing an example of a process showing a method for producing a conductive substrate for plating.

  A photosensitive resist layer (photosensitive resin layer) 5 is formed on the conductive substrate 2 (FIG. 4A). The photosensitive resist layer 5 is patterned by applying a photolithographic method to the photosensitive resist layer (photosensitive resin layer) 5 of the laminate (FIG. 4B). Patterning is performed by placing a photomask on which a pattern is formed on the photosensitive resist layer 5, exposing it, developing it, removing unnecessary portions of the photosensitive resist layer 5, and leaving protrusions 6. Done. The shape of the protruding portion 6 and the convex pattern formed therefrom are considered to correspond to the concave portion 4 on the conductive substrate 2 and the pattern.

At this time, in the cross-sectional shape of the protrusion 6, the side surface is perpendicular to the conductive substrate 2, or the protrusion 6 is in contact with the end where the protrusion 6 is in contact with the conductive substrate 2. It is preferable that at least a part of the upper side of the side cover the end. In terms of the width of the protruding portion 6, the maximum width d ₁ of the protruding portion 6 is preferably equal to or larger than the width d ₀ where the protruding portion 6 is in contact with the conductive substrate 2. This is because the recess width of the insulating layer 3 having good adhesion is determined by d ₁ . Here, in the cross-sectional shape of the protrusion 6, the maximum width d ₁ of the protrusion 6 is equal to or larger than the width d in contact with the protrusion 6 and the conductive substrate 2. A resist having a characteristic of over-developing or having an undercut shape may be used. d ₁ is preferably is realized at the top of the convex portion.
The shape of the protrusion 6 forming the pattern of the removable convex portion is associated with the shape of the concave portion. The width of the protrusion is d ₁ , which corresponds to the width d ′ of the bottom of the recess, and the height is 1.2 to 10 of the thickness of the insulating layer to be formed on the conductive substrate. Double is preferred.

(B) The process of forming an insulating layer on the surface of the conductive substrate on which the removable convex pattern is formed will be described.
An insulating layer 3 is formed on the surface of the conductive substrate 2 having a convex pattern composed of the protrusions 6 (FIG. 4C).

  As a method for forming a DLC thin film as an insulating layer, a vacuum deposition method, a sputtering method, an ion plating method, an arc discharge method, a physical vapor deposition method such as an ionization deposition method, a chemical vapor deposition method such as a plasma CVD method, etc. However, the plasma CVD method using a high frequency or pulse discharge in which the film forming temperature can be controlled from room temperature is particularly preferable.

  In order to form the DLC thin film by a plasma CVD method, a hydrocarbon-based gas is preferably used as a carbon source as a raw material. For example, alkane gases such as methane, ethane, propane, butane, pentane, hexane, alkene gases such as ethylene, propylene, butene, pentene, alkadiene gases such as pentadiene, butadiene, acetylene, methylacetylene, etc. Alkyne gases, aromatic hydrocarbon gases such as benzene, toluene, xylene, indene, naphthalene and phenanthrene, cycloalkane gases such as cyclopropane and cyclohexane, cycloalkene gases such as cyclopentene and cyclohexene, methanol And alcohol gases such as ethanol, ketone gases such as acetone and methyl ethyl ketone, and aldehyde gases such as methanal and ethanal. The said gas may be used independently and may use 2 or more types together. Further, a mixture of the above-mentioned carbon source and hydrogen gas as a raw material gas containing carbon and hydrogen as elements, and the above-mentioned carbon source and a compound gas consisting only of carbon and oxygen such as carbon monoxide gas and carbon dioxide gas. A mixture of a compound gas composed of only carbon and oxygen, such as a mixture, carbon monoxide gas, carbon dioxide gas, and hydrogen gas; a compound gas composed of only carbon and oxygen, such as carbon monoxide gas, carbon dioxide gas; Examples thereof include a mixture with oxygen gas or water vapor. Further, these source gases may contain a rare gas. The rare gas is a gas composed of an element belonging to Group 0 of the periodic table, and examples thereof include helium, argon, neon, and xenon. These rare gases may be used alone or in combination of two or more.

The insulating layer may be formed entirely by the above-described insulating DLC thin film, but it improves the adhesion of the DLC thin film to a conductive substrate such as a metal plate, thereby improving the durability of the insulating layer. In order to further improve, it is preferable to insert an intermediate layer composed of one or more components selected from Ti, Cr, W, Si, nitrides or carbides thereof, or the like, between the two.
The Si or SiC thin film has excellent adhesion to, for example, a metal such as stainless steel, and also forms SiC at the interface with the insulating DLC thin film laminated thereon to improve the adhesion of the DLC thin film. Has the effect of improving.
The intermediate layer can be formed by the dry coating method as described above.
The thickness of the intermediate layer is preferably 1 μm or less, and more preferably 0.5 μm or less in consideration of productivity. A coating of 1 μm or more is not suitable because the coating time becomes long and the internal stress of the coating film increases.
The intermediate layer is preferably formed before the insulating layer 3 is formed, but may be formed on the surface of the conductive substrate 2 before the convex pattern 6 is formed. Thereafter, a convex pattern is formed on the surface by the procedure as described above. In this case, if an intermediate layer is used that is sufficiently conductive to allow electroplating, the bottom of the recess may remain the intermediate layer, but if the intermediate layer does not have sufficient conductivity, dry The intermediate layer at the bottom of the recess is removed by a method such as etching to expose the conductive substrate 2.

Even when the insulating layer is formed of an inorganic material such as an inorganic compound such as Al ₂ O ₃ or SiO ₂ , a physical vapor deposition method such as a sputtering method or an ion plating method or a chemical vapor deposition method such as plasma CVD may be used. Can be used. For example, in the case of forming by sputtering, an oxide or nitride such as SiO ₂ or Si ₃ N ₄ can be formed by introducing Si or Al as a target and introducing oxygen, nitrogen or the like as a reactive gas. it can. In the case of using the ion plating method, Si or Al can be used as a raw material, and an electron beam can be irradiated to evaporate to form a film on the substrate. At that time, an oxide, nitride, or carbide film can be formed by introducing a reactive gas such as oxygen, nitrogen, or acetylene.
In the case of forming a film by the CVD method, the film can be formed by using a chemical gas such as a metal chloride, a metal hydride, an organometallic compound, etc. as a raw material. The CVD of silicon oxide can be performed by, for example, plasma CVD using TEOS or ozone. The CVD of silicon nitride can be performed by plasma CVD using ammonia and silane, for example.

Next, the step (C) of removing the convex pattern to which the insulating layer is attached will be described. In a state where the insulating layer 3 is attached (see FIG. 4C), the convex pattern including the protrusions 6 is removed (see FIG. D (d)).
A commercially available resist stripping solution, inorganic, organic alkali, organic solvent, or the like can be used to remove the resist to which the insulating layer is attached. In addition, if there is a dedicated stripping solution corresponding to the resist used to form the pattern, it can be used.
As a peeling method, for example, it is possible to remove the resist after it has been swelled, broken or dissolved by immersion in a chemical solution. In order to sufficiently impregnate the resist with the solution, techniques such as ultrasonic waves, heating, and stirring may be used in combination. In addition, the liquid can be applied with a shower, a jet or the like in order to promote peeling, and can be rubbed with a soft cloth or cotton swab.
In addition, when the heat resistance of the insulating layer is sufficiently high, a method of baking at a high temperature to carbonize the resist and removing it, or irradiating with a laser to burn off can be used.
As the stripping solution, for example, a 3% NaOH solution is used, and showering or dipping can be applied as the stripping method.

The insulating layer formed on the conductive substrate 2 and the insulating layer formed on the side surface of the protruding portion 6 are made to have different properties or characteristics. That is, the hardness of the former is greater than the latter. This is the case when the DLC film is formed by plasma CVD. In general, when an insulating film is formed, when the moving speed of the insulating material is different by, for example, an angle of 90 degrees, the properties or characteristics of the film formed as described above are different.
The distance from the side surface of the convex pattern (as a plane perpendicular to the base material) between the insulating layer formed on the conductive substrate and the insulating layer formed on the side surface of the convex pattern is the convex pattern. It is preferable that it does not become small toward the standing position, but becomes large as a whole.
The side surface of the convex pattern (as a surface perpendicular to the conductive substrate) is the surface if the side surface of the convex pattern is perpendicular to the substrate, but the side surface of the convex pattern is the base. In the case of covering the material side, the side surface of the convex pattern is a vertical surface raised vertically from a point ending with the conductive base material.
When the protrusion 6 is removed, the insulating layer is separated at this boundary, and as a result, the side surface of the recess has an inclination angle α. The inclination angle α is preferably 30 degrees or more and less than 90 degrees, more preferably 30 degrees or more and 80 degrees or less, further preferably 30 degrees or more and 60 degrees or less, and particularly preferably 40 degrees or more and 60 degrees or less, and the DLC film is plasma-treated. In the case of manufacturing by CVD, it becomes easy to control to about 40 to 60 degrees. That is, the concave portion 4 is formed so as to become wider toward the opening direction. As a method of controlling the inclination angle α, a method of adjusting the height of the protrusion 6 is preferable. As the height of the protrusion 6 increases, the inclination angle α can be controlled more greatly.

  In the formation of the insulating layer, the conductive base material does not become a shadow of the resist, and therefore the insulating layer on the conductive base material has uniform properties. On the other hand, the insulating layer is formed on the side surface of the convex pattern because the side surface of the convex pattern has an angle with respect to the film thickness direction on the conductive substrate. As for the film, an insulating layer having the same characteristics (for example, the same hardness) as the insulating layer on the conductive substrate cannot be obtained. In such a heterogeneous insulating layer contact surface, a boundary surface of the insulating layer is formed as the insulating layer grows, and the boundary surface is a growth surface of the insulating layer, and is smooth. For this reason, when the convex pattern consisting of the protrusions is removed, the insulating layer (particularly the DLC film) is easily separated at this boundary. Furthermore, the inclination angle α that becomes the boundary surface, that is, the side surface of the concave portion is that the growth of the insulating layer is delayed on the side surface of the protruding portion with respect to the film thickness direction on the conductive substrate. , Controlled as described above.

In the present invention, the hardness of the insulating layer formed on the conductive substrate is preferably 10 to 40 GPa. The insulating layer having a hardness of less than 10 GPa is soft, and when the conductive substrate is used as a plating plate, durability in repeated use is reduced. When the hardness is 40 GPa or more, it becomes impossible to follow the deformation of the base material when the conductive base material is processed such as bending, and the insulating layer is likely to be cracked or cracked. The hardness of the insulating layer formed on the conductive substrate is more preferably 12 to 30 GPa.
On the other hand, the hardness of the insulating layer formed on the side surface of the convex portion is preferably 1 to 15 GPa. The insulating layer formed on the side surface of the convex portion must be formed so as to be at least lower than the hardness of the insulating layer formed on the conductive substrate. By doing so, a boundary surface is formed between the two, and a wide concave portion is formed after a process of peeling the convex pattern composed of the protruding portion to which the insulating layer adheres later. The hardness of the insulating layer formed on the side surface of the protrusion is more preferably 1 to 10 GPa.

The hardness of the insulating layer can be measured using a nanoindentation method. In the nanoindentation method, a regular triangular pyramid (Berkovic type) indenter with a diamond tip is pressed into the surface of a thin film or material, and the hardness is obtained from the load applied to the indenter and the projected area under the indenter. As a measurement by the nanoindentation method, a device called a nanoindenter is commercially available. The hardness of the film formed on the conductive substrate can be measured by pressing an indenter from the conductive substrate as it is. In addition, in order to measure the hardness of the film formed on the side surface of the convex part, a part of the conductive substrate is cut out and cast with resin, and the indenter is pushed into the insulating layer formed on the side surface of the convex part from the cross section. Can be measured. Normally, in the nanoindentation method, the hardness is measured by applying a minute load of 1 to 100 mN to the indenter. In the present invention, the value measured by applying a load of 3 mN for 10 seconds is described as the hardness value.
Thus, the electroconductive base material 1 for plating can be produced.

In the present invention, the wiring substrate for semiconductor element connection is
(B) a step of depositing a metal by plating on the plating forming portion of the conductive base material for plating, and (b) a step of transferring the metal deposited on the plating forming portion of the conductive base material to the transfer base material. It is manufactured by the method containing.

A well-known method can be employ | adopted for the plating method in this invention. As the plating method, an electrolytic plating method, an electroless plating method, or other plating methods can be applied.
The electrolytic plating will be further described. For example, in the case of electrolytic copper plating, a copper sulfate bath, a copper borofluoride bath, a copper pyrophosphate bath, a copper cyanide bath, or the like can be used as an electrolytic bath for plating. At this time, it is known that the dispersion of electrodeposition stress can be further reduced by adding a stress relieving agent (also having an effect as a brightener) due to organic matter or the like to the plating bath. For electrolytic nickel plating, a Watt bath, a sulfamic acid bath, or the like can be used. In order to adjust the flexibility of the nickel foil in these baths, additives such as saccharin, paratoluenesulfonamide, sodium benzenesulfonate, sodium naphthalene trisulfonate, and commercial additions that are preparations as necessary An agent may be added. Furthermore, in the case of electrolytic gold plating, alloy plating using potassium gold cyanide, pure gold plating using an ammonium citrate bath or a potassium citrate bath, or the like is used. In the case of alloy plating, a gold-copper, gold-silver, gold-cobalt binary alloy or a gold-copper-silver ternary alloy is used. Similarly, other known methods can be used for other metals. As the electroplating method, for example, “Practical plating for field engineers” (edited by the Japan Plating Association, published by Sakai Shoten in 1986), pages 87 to 504 can be referred to.

Next, the electroless plating will be further described. Typical examples of the electroless plating method include copper plating, nickel plating, tin plating, gold plating, silver plating, cobalt plating, iron plating, and the like. In the process of electroless plating used industrially, a reducing agent is added to a plating solution, and electrons generated by the oxidation reaction are used for metal precipitation reaction. , Reducing agent, pH adjusting agent, pH buffering material, stabilizer and the like. In the case of electroless copper plating, copper sulfate is preferably used as the metal salt, formalin as the reducing agent, and Rossel salt or ethylenediaminetetraacetic acid (EDTA) as the complexing agent. Moreover, although pH is mainly adjusted with sodium hydroxide, potassium hydroxide, lithium hydroxide, etc. can be used, carbonate and phosphate are used as a buffer, and monovalent as a stabilizer. Cyanide, thiourea, bipyridyl, O-phenanthroline, neocuproine, etc. that complex preferentially with copper are used. In the case of electroless nickel plating, nickel sulfate is preferably used as the metal salt, and sodium hypophosphite, hydrazine, a borohydride compound, or the like is preferably used as the reducing agent. When sodium hypophosphite is used, phosphorus is contained in the plating film, and the corrosion resistance and wear resistance are excellent. Moreover, as a buffering agent, a monocarboxylic acid or its alkali metal salt is often used. As the complexing agent, one that forms a stable soluble complex with nickel ions in the plating solution is used, and acetic acid, lactic acid, tartaric acid, malic acid, citric acid, glycine, alanine, EDTA, etc. are used. In this case, sulfur compounds and lead ions are added. For the electroless plating method, refer to pages 505 to 545 of the above-mentioned “Practical Plating for On-Site Engineers” (edited by the Japan Plating Association, published by Sakai Shoten in 1986).
Furthermore, in order to obtain the reducing action of the reducing agent, it may be necessary to activate the catalyst on the metal surface. When the substrate is a metal such as iron, steel, nickel, etc., these metals have catalytic activity, so they are deposited just by immersing them in the electroless plating solution, but copper, silver or their alloys, and stainless steel In this case, in order to impart catalyst activation, a method is used in which the object to be plated is immersed in an acidic hydrochloric acid solution of palladium chloride and palladium is deposited on the surface by ion substitution.

The electroless plating that can be used in the present invention is, for example, immersed in an electroless copper plating solution at a temperature of about 60 to 90 ° C. after a palladium catalyst is attached to the concave portion of the conductive base material for plating, if necessary. This is a method of performing copper plating.
In electroless plating, the substrate is not necessarily conductive. However, when anodizing the substrate, the substrate needs to be conductive.
In particular, when the material of the conductive base material is Ni, electroless plating includes a method in which the recesses are anodized and then immersed in an electroless copper plating solution to deposit copper.

  As a metal that appears or precipitates by plating, conductive metals such as silver, copper, gold, aluminum, tungsten, nickel, iron, and chromium are used, but the volume resistivity (specific resistance) at 20 ° C. is used. It is desirable to include at least one kind of metal of 20 μΩ · cm or less. This is because when the structure obtained according to the present invention is used as an electromagnetic wave shielding sheet, the metal constituting it is grounded as an electromagnetic wave as a current, and the higher the conductivity, the better the electromagnetic wave shielding property. Such metals include silver (1.62 μΩ · cm), copper (1.72 μΩ · cm), gold (2.4 μΩ · cm), aluminum (2.75 μΩ · cm), tungsten (5.5 μΩ · cm). ), Nickel (7.24 μΩ · cm), iron (9.0 μΩ · cm), chromium (17 μΩ · cm, all values at 20 ° C.), etc., but are not particularly limited thereto. If possible, the volume resistivity is more preferably 10 μΩ · cm, and further preferably 5 μΩ · cm. In view of the price of metal and availability, copper is most preferably used. These metals may be used alone, or may be an alloy with another metal or a metal oxide for imparting functionality. However, it is preferable from the viewpoint of conductivity that a metal having a volume resistivity of 20 μΩ · cm is contained in the largest amount as a component.

  The thickness (plating thickness) of the metal layer formed by plating on the plating forming portion of the conductive substrate is appropriately determined according to the purpose. In order to show sufficient heat dissipation, the plating thickness is preferably 5 μm or more, and reduces the possibility that pinholes are formed in the conductor layer (for example, the electromagnetic shielding properties are reduced at this time). Therefore, it is more preferable that the thickness is 10 μm or more. If the plating thickness is too large, the formed metal layer also spreads in the width direction. This is also adjusted appropriately according to the purpose.

The thickness of the metal foil formed by plating is reduced from the viewpoint that the metal layer to be deposited can be more shaped by making the recess deeper relative to the thickness of the deposited metal layer. The height of the insulating layer is preferably 2 times or less, particularly preferably 1.5 times or less, and further preferably 1.2 times or less, but is not limited thereto.
The degree of plating can be such that the deposited metal layer is present in the recess. Even in such a case, since the concave shape is wide in the opening direction, and further, the surface of the side surface of the concave formed by the insulating layer can be smoothed, so that the anchor effect when peeling the metal layer pattern is reduced. it can. Moreover, it becomes possible to make high the ratio of the height with respect to the width | variety of the metal layer to deposit, and to improve the transmittance | permeability more.

An example of manufacturing a wiring substrate for connecting a semiconductor element using the above conductive substrate for plating will be described below.
FIG. 5 is a cross-sectional view showing an example of manufacturing a wiring substrate for connecting a semiconductor element.
Through the above-described plating step, plating is performed in the plating forming portion (recessed portion) 4 of the conductive base material 1 for plating having the insulating layer 3 on the conductive base material 2 described above to form the metal layer 7 (FIG. 5 (e)). Next, a transfer substrate (peelable substrate) 8 prepared separately, which is a substrate material 9 and a pressure-sensitive adhesive layer 10 laminated thereon. Preparation for pressure-bonding the transfer base material 8 with the pressure-sensitive adhesive layer 10 facing the conductive base material 1 for plating on which the metal layer pattern 8 is formed is performed (FIG. 5F).
Next, the transfer substrate 8 is pressure-bonded to the conductive substrate 1 for plating on which the metal layer 7 is formed with the pressure-sensitive adhesive layer 10 facing (FIG. 5G). At this time, the pressure-sensitive adhesive layer 10 may contact the insulating layer 3.
Next, when the transfer substrate 8 is peeled off, the metal layer 7 adheres to the pressure-sensitive adhesive layer 10 and is peeled off from the plating forming portion 4 of the plating conductive substrate 1 and transferred to the transfer substrate. As a result, a substrate 11 for mounting a semiconductor that can be said to be a substrate with a conductor layer pattern is obtained (FIG. 5H).
When the pressure-sensitive adhesive is a curable resin, it is cured at the same time as the above-mentioned pressure bonding, before or after peeling after the pressure bonding, but may be partially or completely cured at the same time as the above pressure bonding or before peeling after pressure bonding. This is preferable. For partial curing and complete curing, it goes without saying that the resin or thermosetting resin that is cured by irradiation with active energy rays is irradiated with active energy rays or heated to an extent corresponding to the degree of curing, respectively. .
In the semiconductor mounting substrate thus obtained, the metal layer is partially embedded in the releasable substrate (preferably an adhesive layer) in the thickness direction. The embedding amount in the thickness direction is preferably 1 μm or more, more preferably 3 μm or more, and particularly preferably 5 μm or more. Further, the upper limit of the burying amount is preferably 1 μm smaller than the thickness of the metal layer, more preferably 2/3 of the thickness of the metal layer, and particularly preferably 1/2 of the thickness of the metal layer. If the embedded amount is too small or too large, the protruding portion of the metal layer of the semiconductor device obtained by using the semiconductor mounting substrate is likely to be inappropriate, and the resistance to shearing force is reduced.

  In the above, when the adhesive is an active energy ray-curable resin, the active energy ray is irradiated to the semiconductor mounting substrate obtained by transferring the metal layer to the transfer substrate, It is preferable to cure the pressure-sensitive adhesive layer of the irradiated part. At the time of transfer, the pressure-sensitive adhesive has adhesiveness in an uncured or partially cured state, and therefore the metal layer can be easily transferred even at room temperature, for example. After the transfer, the workability of the subsequent steps can be improved by reducing or eliminating the tackiness by irradiating the active energy rays to sufficiently cure the resin surface. Furthermore, the active energy rays may be irradiated from either side of the semiconductor mounting substrate, but it is preferable to irradiate from the surface where the metal layer exists. When irradiated from the opposite side of the surface on which the metal layer exists (use a material that transmits active energy rays as the base material), the resin under the metal layer is also cured, but at that time, the resin is cured. If the adhesion between the metal layer and the resin is reduced due to shrinkage and a gap is formed, when a liquid solder resist is applied as described later, the resist enters the gap and the lower surface of the metal layer is covered with the resist. As a result, the occurrence of a defect that insulates the connection portion to the wiring board is considered, and the plating solution penetrates into the gap at the time of gold plating or silver plating, thereby forming extra plating and increasing the cost. There is also a problem. On the other hand, when the active energy ray is irradiated from the surface where the metal layer exists, the resin under the metal layer is not irradiated with the active energy ray, and since the curing does not proceed, the adhesiveness remains. There is little influence of curing shrinkage, and there is no risk of defects and defects as described above.

FIG. 6 is a cross-sectional view showing a state in which a metal layer is formed by plating on the plating formation portion (recess) of the conductive base material for plating. FIG. 6A is a plan view of the plating formation portion (recess). FIG. 6B shows a state in which the metal layer is formed in the plating forming portion (concave portion).
When plating on a conductive substrate for plating, the plating grows isotropically, so that the deposition of plating that started from the exposed portion of the conductive substrate overflows from the recess and covers the insulating layer as it progresses. It protrudes and deposits (FIG. 6A). From the viewpoint of sticking to the transfer substrate, it is preferable to deposit the plating so as to protrude. However, at this time, the plating may be deposited so as to be within the recess 4 (FIG. 6B). Even in this case, by sufficiently pressing the transfer substrate, the metal layer is transferred to the pressure-sensitive adhesive layer, and the metal layer 7 is peeled off from the conductive substrate 1 for plating. A material can be produced. In this case, since the metal layer protrudes above the pressure-sensitive adhesive layer, the metal layer is further pressed in the thickness direction of the metal layer by pressing the metal layer with a roll or a press device without or via a protective film. It is preferable to bury the part in the pressure-sensitive adhesive layer.
Note that. In FIG. 6A, the metal layer 7 has a bulging surface, but this is likely to occur when the width of the recess is small. If the width of the recess is sufficiently large, the central portion of the plating surface is flat. become.

As shown in the sectional view of FIG. 7, the wiring substrate 11 for connecting a semiconductor element as shown in FIG. 5 (h) has a nickel plating 12 and a gold plating 13 sequentially on the surface of the conductor layer (plated copper, etc.). It is prepared so that it can be easily subjected to wire bonding performed later. The gold plating may be palladium plating or silver plating. At the time of this plating, a resist film may be formed on a portion that is not desired to be plated, if necessary.
The plating may be electroless plating or electrolytic plating. In the case of electrolytic plating, it is preferable to form a metal layer on each metal layer 7 in a shape in which lead wires are coupled.

Next, a method for manufacturing a semiconductor device using the wiring substrate for connecting a semiconductor element according to the present invention will be described.
FIG. 8 is a partial cross-sectional view showing the first half of the manufacturing process of the semiconductor device. FIG. 9 is a partial cross-sectional view showing the middle half of the manufacturing process of the semiconductor device. FIG. 10 is a partial cross-sectional view showing the second half of the manufacturing process of the semiconductor device.
First, the wiring substrate 11 for connecting a semiconductor element is prepared (FIG. 8 (h ′)). This is, for example, as shown in FIG. In FIG. 8 (h ′), the metal layer 7 is partially embedded in the pressure-sensitive adhesive layer 10 on the base material 9 in the thickness direction. In FIG. 8 (h ′) (and so on), the metal layer schematically shows a rectangular cross-sectional shape.
On the metal layer 7 of the wiring board 11 for semiconductor connection, nickel plating and gold plating 14 (in FIG. 8 (i), these platings are indicated by a single reference numeral 14. The same applies hereinafter. These platings are at least wire bonding pads. Is performed at a predetermined position of the semiconductor element connecting portion such as a portion) to obtain a semiconductor element connecting wiring substrate 15 immediately before the semiconductor element is mounted (see FIG. 8I). In some cases, a resist film is formed on the surface where the metal layer is exposed by a photolithographic method using a liquid resist at a place where precipitation of nickel plating and gold plating is prevented.

FIG. 9 is a partially omitted cross-sectional view showing the middle half of the manufacturing process of the semiconductor device.
In FIG. 9 (j), in the peelable substrate 8 (consisting of the substrate material 9 and the pressure-sensitive adhesive layer 10), the metal layer is connected to the semiconductor element via the metal layer 71 connected to the semiconductor element and the die bond material 16. 17 includes a metal layer 72 and a metal layer 73 bonded to each other. In FIG. 9, the metal layer 71 and the semiconductor element 17 are each wire-bonded by a bonding wire 18 at a wire bonding portion to form a semiconductor element laminate 19. The metal layer 72 is a part for soldering to a wiring board (motherboard) or the like, and the metal layer 73 is a wiring connecting the corresponding metal layer 71 and the metal layer 72. That is, each metal layer 71 is connected to a corresponding soldered portion (metal layer) by an appropriate wiring (metal layer). The die bond material 16 is also in contact with the pressure-sensitive adhesive layer 10. The metal layer 72 and its surroundings are not covered with a die bond material.
The planar sizes of the metal layer 71, the metal layer 72, and the metal layer 73 will be described. The metal layer 71 is preferably a square having a side of 20 to 1000 μm or a width corresponding thereto, and the metal layer 72 is preferably a circle having a diameter of 100 to 1000 μm or a width corresponding to this, The metal 73 is preferably linear with a width of 10 to 120 μm. If the metal layer 71 and the metal layer 72 are too large, the area becomes unnecessary for connection, and if it is too small, the connection tends to be poor. The metal layer 72 should just be what makes the metal layer 71 and the metal layer 72 fully conduct | electrically_connected.
Examples of the die bond material include an epoxy resin, a polyimide resin, a silicone resin, a polyurethane resin, and a liquid crystal resin, and these may further contain a filler such as alumina. The die bond material used here is insulative.
Examples of the semiconductor element include a semiconductor element such as a memory semiconductor element, a power semiconductor element, a CPU, an LED semiconductor element, and a chip capacitor. For example, a gold wire is used as the bonding wire.
In the semiconductor element laminate 19, the metal layer, the semiconductor element, the bonding wire, and the like are sealed with a sealing material 20 to obtain a sealed semiconductor element laminate 21 (FIG. 9K).

FIG. 10 is a partially omitted cross-sectional view showing the second half of the semiconductor device manufacturing process.
The peelable base material 8 (consisting of the base material 9 and the pressure-sensitive adhesive layer 10) is peeled from the sealed semiconductor element laminate 21 to obtain the semiconductor device 22 before dicing (FIG. 1L).
In the semiconductor device 22 before dicing, a metal layer partially protrudes in the cross-sectional direction and is exposed.
This protrusion amount is preferably 1 μm or more, more preferably 3 μm or more, and particularly preferably 5 μm or more in the thickness direction. Further, the upper limit of the protruding amount is preferably 1 μm smaller than the thickness of the metal layer, more preferably 2/3 of the thickness of the metal layer, and particularly preferably 1/2 of the thickness of the metal layer. If the protruding amount is too small or too large, the resistance to shearing force is lowered.

Next, a solder resist 23 is applied to the exposed surface of the metal layer of the semiconductor device 22 before dicing. The solder resist 23 has an opening so as to expose the metal layer 72 that is a soldering portion (solder ball mounting pad), and the other portions are entirely covered.
Next, the peelable substrate is peeled off and then diced to an appropriate size. Dicing is preferably performed in a state where the sealing material is sufficiently cured.
Further, the tin plating 24 is applied to the exposed surface of the metal layer 72. Tin plating can be easily performed by applying electroless plating or barrel plating.
Further, the solder balls 25 are bonded to the metal layer 72 on which the tin plating 24 has been applied to form the semiconductor device 26 (FIG. 10 (m)). In order to bond the solder balls, it is preferable to first apply a solder paste to the tin plating 24 (not shown) and then bond the solder balls. Here, the bonding of the solder balls is not essential. Soldering can be performed using solder on the wiring board by applying a solder paste to a predetermined position of the wiring on the wiring board on which the semiconductor device described later is mounted.
Note that. When electrolytic plating is performed on the metal layer, lead wires are attached to the metal layer 71 in advance. For this reason, it is preferable to form a recess corresponding to the lead wire on the electroconductive substrate for plating. Therefore, when there is a lead wire, the lead wire on the side surface of the semiconductor device is cut after the peelable substrate is peeled off so as not to be exposed on the side surface of the semiconductor device. The cutting time is particularly preferably immediately after peeling of the peelable substrate and before dicing, and is preferably performed in a state where the sealing material is sufficiently cured.

The semiconductor device 26 obtained as described above is mounted on a semiconductor device mounting wiring board (including a mother board and a multilayer wiring board), and used for end use (or further downstream products).
FIG. 11 is a cross-sectional view showing a process of manufacturing a semiconductor device mounting wiring board by mounting the semiconductor device obtained above on a wiring board for mounting a semiconductor device by soldering.
FIG. 11 (p) shows a state immediately before the semiconductor device 26 is mounted on the mother board 29. The wiring board 29 for mounting a semiconductor device shows a part thereof, but a conductor wiring 27 is applied to a board body (portion excluding the wiring layer on the surface) 26.
Next, the solder balls 25 of the semiconductor device 26 are reflowed on the conductor wirings 27 of the semiconductor device mounting wiring board 29 to be joined to form the semiconductor device mounting wiring board 30.
In addition, it is not necessarily the coupling | bonding by a solder ball, You may couple | bond by applying a solder paste to the predetermined position on a wiring board, and reflowing.

  In the above, the metal layer 71 and the semiconductor element 17 are wire-bonded. However, these connections can be made not by wire bonding but also by using an anisotropic conductive adhesive that also serves as a die bonding material. In this case, the metal layer 71 is also disposed below the semiconductor element 17, and bumps are formed at the connection portions of the semiconductor element 17. Bumps are not formed on the metal layer 73. Therefore, even if an anisotropic conductive adhesive is used as a die bond material, it does not conduct. Further, the metal layer 72 and its surroundings are not covered with the die bond material as described above.

In addition, as described above, a rotating body (roll) can be used as the conductive base material for plating used in the present invention. The rotating body (roll) is preferably made of metal. Furthermore, it is preferable to use a drum electrode or the like used in the drum-type electrolytic deposition method as the rotating body. As described above, the material that forms the surface of the drum electrode may be a material with relatively low plating adhesion, such as stainless steel, chrome-plated cast iron, chrome-plated steel, titanium, or titanium-lined material. preferable. By using a rotating body as the conductive base material, it is possible to obtain a base material with a conductor layer pattern as a roll, and in this case, productivity is greatly increased.
Using a rotating body, while continuously peeling the pattern formed by electroplating, rotating the drum electrode when using the drum electrode as the conductive substrate and the process of obtaining the substrate with the conductor layer pattern as a scroll In addition, a method and an apparatus described in International Publication WO2008 / 081904 can be used as an apparatus for continuously depositing metal by electroplating and continuously peeling the deposited metal.

Furthermore, as described above, the hoop-like conductive substrate for plating can be used as the conductive substrate for plating used in the present invention. This will be described in detail. The hoop-shaped conductive substrate for plating can be produced by forming an insulating layer and a recess on the surface of the strip-shaped conductive substrate and then joining the end portions together. As described above, the material forming the surface of the conductive substrate is made of a material with relatively low plating adhesion, such as stainless steel, chrome-plated cast iron, chrome-plated steel, titanium, or titanium-lined material. It is preferable. When a hoop-like conductive base material is used, the process of blackening treatment, rust prevention treatment, transfer, etc. can be processed in one continuous process, so the productivity of the base material with a conductive pattern is high. Moreover, the base material with an electroconductive pattern can be produced continuously, and it can be set as a product as a scroll. The thickness of the hoop-like conductive substrate may be determined as appropriate, but is preferably 100 to 1000 μm.
Using a hoop-like conductive base material, a conductor layer pattern formed by electroplating was continuously peeled off, and a structure was obtained as a scroll, and a hoop-like conductive base material was used as the conductive base material. In some cases, a method and an apparatus described in International Publication WO2008 / 081904 can be used as an apparatus for continuously peeling a conductor layer pattern while depositing it by electroplating.

  Moreover, the wiring substrate for connecting a semiconductor element according to the present invention is not limited to a method using a continuous plating method using a rotating roll or a hoop as described above, and can be manufactured as a single wafer. When performed in a single wafer, it is easy to handle when preparing a conductive substrate for plating, and even when the same insulating layer is peeled off after repeated use of the same conductive substrate for plating, it is drum-shaped. In the case of a hoop-shaped substrate, it is difficult to extract or replace only a specific portion. However, if it is a sheet, it is possible to extract or replace only the conductive substrate for plating in which a defect has occurred. In this way, by making a single wafer, it is easy to handle when a problem occurs in the conductive substrate for plating. The thickness of the sheet-like conductive base material may be determined as appropriate, but the thickness is preferably 20 μm or more in consideration of giving sufficient strength not depending on the stirring of the liquid in the plating tank. If it is too thick, the weight increases and it is difficult to handle, so a thickness of 10 cm or less is preferable.

(Pattern specification 1)
As a test pattern, a CSP wiring pattern (opaque) was formed using a negative film. There is a frame-like (opaque) portion with a small width on the outer periphery, which is connected by a wiring pattern and a lead wire pattern (opaque). As a wiring pattern for CSP, a portion corresponding to the metal layer 71 in FIG. 9 is a rectangle of 50 μm × 100 μm, a portion corresponding to the metal layer 72 is a circle having a diameter of 400 μm, and a portion corresponding to the metal layer 73 is a linear shape having a width of 10 μm. It was.

(Formation of convex pattern)
A resist film (Photech RY3315, manufactured by Hitachi Chemical Co., Ltd.) was bonded to both sides of a 150 mm square stainless steel plate (SUS316L, # 400 polished finish, thickness 500 μm, manufactured by Nisshin Steel Co., Ltd.) (FIG. 4A ) But not the same). The bonding conditions were a roll temperature of 105 ° C., a pressure of 0.5 MPa, and a line speed of 1 m / min. Subsequently, the negative film of the pattern specification 1 was left still on the single side | surface of a stainless plate (conductive base material). Using an ultraviolet irradiation device, ultraviolet rays were irradiated at 250 mJ / cm ² from above the stainless steel plate on which the negative film was placed under a vacuum of 600 mmHg or less. Further, by developing with a 1% aqueous sodium carbonate solution, a protrusion resist film (protrusion; height 10 μm) was obtained. The surface opposite to the surface on which the pattern is formed is not developed because it is exposed to the entire surface, and a resist film is formed on the entire surface (corresponding to FIG. 4B but not the same).

(Formation of insulating layer)
A DLC film was formed using a PBII / D apparatus (Type III, manufactured by Kurita Seisakusho Co., Ltd.). A stainless steel substrate with a resist film attached thereto was placed in the chamber, the inside of the chamber was evacuated, and the substrate surface was cleaned with argon gas. Next, hexamethyldisiloxane was introduced into the chamber, and an intermediate layer was formed to a thickness of 0.1 μm. Next, toluene, methane, and acetylene gas were introduced, and a DLC layer was formed on the intermediate layer so as to have a film thickness of 2 to 3 μm (corresponding to FIG. 4C, but not the same).

(Concavity formation; removal of convex pattern with insulating layer attached)
The stainless steel substrate with the insulating layer attached was immersed in an aqueous sodium hydroxide solution (10%, 50 ° C.) and left for 8 hours with occasional rocking. The resist film forming the convex pattern and the DLC film adhering thereto have been peeled off. Since there was a portion that was difficult to peel off, the entire surface was peeled off by lightly rubbing with a cloth to obtain a conductive substrate for plating (corresponding to FIG. 4 (d) but not the same).
The shape of the recess was wider toward the opening direction, and the inclination angle of the side surface of the recess was the same as the angle of the boundary surface. The depth of the recess was 2 to 3 μm. Moreover, the recessed part of the CSP wiring pattern corresponding to a negative film was formed.

(Copper plating)
Furthermore, an adhesive film (Hitalex K-3940B, manufactured by Hitachi Chemical Co., Ltd.) was attached to the surface (back surface) where the pattern of the conductive substrate for plating obtained above was not formed.
Electrolytic bath for electrolytic copper plating (copper sulfate (pentahydrate) 250 g / L, sulfuric acid 70 g / L, cube light AR), with the electroconductive substrate for plating with the adhesive film attached as the cathode and phosphorous copper as the anode (Added by Ebara Eugene Corporation, additive) 4 ml / L aqueous solution, 30 ° C.) The current density is 10 A / dm ² , and the thickness of the metal layer deposited in the concave portion of the conductive substrate for plating is Plating was performed until the thickness was approximately 10 μm. Plating was formed so as to overflow in and out of the concave portion of the conductive base material for plating (corresponding to FIG. 5 (e) but not the same).

(Preparation of transfer substrate)
(Composition composition 1)
2-ethylhexyl methacrylate 70 parts by weight Butyl acrylate 15 parts by weight 2-hydroxyethyl methacrylate 10 parts by weight Acrylic acid 5 parts by weight Azobisisobutyronitrile 0.1 part by weight Toluene 60 parts by weight and ethyl acetate 60 parts by weight

Into a 500 cm3 three-necked flask equipped with a thermometer, a cooling pipe, and a nitrogen introduction pipe, the above-mentioned composition 1 is charged, heated to 60 ° C. with gentle stirring, to initiate polymerization, and then bubbled with nitrogen The mixture was stirred at 60 ° C. for 8 hours under reflux to obtain an acrylic resin having a hydroxyl group in the side chain. Thereafter, 5 parts by weight of Karenz MOI (2-isocyanatoethyl methacrylate; manufactured by Showa Denko KK) is added and reacted at 50 ° C. with gentle stirring, and a reactive polymer having a photopolymerizable functional group in the side chain. Solution 1 was obtained.
The obtained reactive polymer 1 had a methacryloyl group in the side chain, and the weight average molecular weight in terms of polystyrene measured by gel permeation chromatography was 800,000.
2-methyl-1 [4-methylthio] phenyl] -2-morpholinopropan-1-one (trade name Irgacure 907, Ciba Geigy (as a photopolymerization initiator) was added to 100 parts by weight (solid content) of the solution 1 of the reactive polymer. 1 part by weight, 3 parts by weight of an isocyanate-based crosslinking agent (trade name Coronate L-38ET, manufactured by Nippon Polyurethane Co., Ltd.) and 50 parts by weight of toluene were added to obtain Resin Composition 1.
The obtained resin composition 1 is deposited on the surface of a polyethylene naphthalate film (Q65FA, manufactured by Teijin DuPont Films Co., Ltd.) which is a 120 mm square substrate material with a thickness of 250 μm, and the film thickness after drying at 100 ° C. is 20 μm. Then, an adhesive layer having ultraviolet curability was formed on the base material to prepare a transparent transfer base material. The drying condition was 100 ° C. for 10 minutes.

(Metal layer pattern transfer)
The transfer substrate was preheated at 100 ° C. for 5 minutes, and was then bonded to the surface of the pressure-sensitive adhesive layer and the copper-plated surface of the conductive substrate for plating using a roll laminator (FIG. 5). (F) Corresponds to (g) but not the same). Lamination conditions were a roll temperature of 150 ° C., a pressure of 0.5 MPa, and a line speed of 0.1 m / min.
Subsequently, when the base material bonded to the electroconductive substrate for plating was peeled off, the metal layer pattern made of copper deposited on the electroconductive substrate for plating was transferred to the adhesive layer, and the wiring base for semiconductor element connection A material (a substrate with a conductor layer pattern) was produced (corresponding to FIG. 5 (h) but not the same). Since the pattern was transferred after the metal layer pattern was formed, warpage of the substrate could be reduced.
A part of the obtained wiring substrate for connecting a semiconductor element was cut out, and the cross section was observed on a scanning electron micrograph (magnification 2000 times). A metal layer pattern corresponding to the CSP wiring pattern was formed. Each line was buried 4 μm in the thickness direction in the adhesive.

(Fabrication of semiconductor devices)
Thereafter, the outer peripheral frame-shaped portion was used as an electrode, and nickel plating 5 μm and gold plating (purity 99.99%) 0.3 μm were sequentially applied to the copper surface of the CSP wiring pattern by electroplating (FIGS. 7 and 8). Corresponding to (i) but not identical).
Next, the semiconductor elements were mounted with a die bond film and then connected by wire bonding (corresponding to FIG. 9 (j)). Next, the epoxy sealing material was sealed under the transfer mold method at 175 ° C. for 2 minutes (corresponding to FIG. 9 (k)).
Wire bonding is performed using a wire bonding apparatus 4524AD (Kulicke & Soffa, Ltd.) with a capillary of model 40472-0010-320 (Kullike & Soffa, Ltd.). )] Was used, and the type GMH type 25 μm (manufactured by Tanaka Kikinzoku Kogyo Co., Ltd.) was used as the wire. The connection conditions were such that the temperature was 130 ° C., the ultrasonic output was 0.2 W, and the ultrasonic output time was 45 ms.

Thereafter, the transfer substrate (peelable substrate) was peeled off. At this time, the pressure-sensitive adhesive was adhered to the polyethylene naphthalate, and the pressure-sensitive adhesive could be easily peeled off without remaining in the metal layer pattern and the sealant.
Next, in order to cut the lead wire for electrolytic nickel plating and electrolytic gold plating, a groove is cut in the thickness direction of the wiring substrate for semiconductor element connection by a dicing device from the surface opposite to the semiconductor element mounting surface to be a semiconductor device. The line was cut (corresponding to the semiconductor device 22 before dicing in FIG. 10L).
A liquid resist (PSR-4000, manufactured by Taiyo Ink Co., Ltd.) is applied on the solder ball mounting surface side of the semiconductor device (120 mm square) before dicing after cutting the lead wire, except for pads on which solder balls are mounted by screen printing. The part was printed on one side. When dried at 100 ° C. for 5 minutes, the resist film thickness was 20 μm. Further, it was cured by heating at 160 ° C. for 1 hour.

Next, the wafer was cut into a predetermined size (7 mm × 7 mm × 200 μm) with a dicing device to obtain a CSP semiconductor device.
Thereafter, the exposed solder ball mounting pad was surface treated, and then the solder ball was mounted. The solder adhered so as to cover the solder ball mounting pad protruding from the semiconductor device (corresponding to FIG. 10 (m)).

  In the CSP semiconductor device obtained in this way, the cross-sectional shape of the CSP wiring pattern has an anchor effect on the sealing material, so that the wiring pattern does not fall off, and the solder mounting pad is exposed from the CSP semiconductor device. Therefore, the CSP semiconductor device can be made thin because the solder connection reliability is high and the resin base material does not remain. In addition, since the photolithographic method for each product is not required for pattern formation, the process is short and basically the production. Good cost and low cost.

(Drop test)
The semiconductor device obtained above was mounted on a wiring board, and the following experiment confirmed that the adhesion strength between the semiconductor device and the wiring board was improved.
(Test Example 1)
In accordance with the manufacturing method of the wiring substrate for connecting semiconductor elements in Example 1, four cylindrical copper foils with a plating thickness of 30 μm and a diameter of 0.25 mm and a spacing of 0.50 mm (pattern pitch of 0.75 mm), and a width of 4 The base material with a conductor layer pattern which has a metal layer pattern arranged in total 16 pieces was obtained. A dam was formed and sealed with a sealing material in the same manner as in Example 1 around the metal layer pattern of the substrate with the conductor layer pattern. Thereafter, unnecessary portions such as dams were cut off, and the transfer base material was peeled off to produce a dummy semiconductor device. The external dimensions of the dummy semiconductor device were 5 mm in length, 5 mm in width, and 0.2 mm in thickness, and the protrusion in the thickness direction of the metal layer pattern was 10 μm.
On the other hand, a copper-clad laminate (MCL-E-679, plate thickness 1.0 mm, copper foil thickness 18 μm, manufactured by Hitachi Chemical Co., Ltd.) was etched, and φ0.27 mm cylindrical copper foils were spaced 0.48 μm ( A laminated board having copper foil patterns arranged in a total of 16 pieces in a pattern of 4 in the vertical direction and 4 in the horizontal direction at a pattern pitch of 0.75 mm was cut out to produce a dummy wiring board having an external dimension of 5 mm in length and 5 mm in width. Electrolytic solder plating with a thickness of 20 μm was applied on the cylindrical copper foil of the dummy wiring board to produce a dummy semiconductor mounting wiring board. The dummy semiconductor device mounting wiring board was soldered and fixed to the dummy semiconductor mounting wiring board by solder reflow at 245 ° C. for 10 seconds to obtain a dummy semiconductor device mounting wiring board. At this time, the reflowed solder adhered so as to cover the protruding metal layer pattern of the dummy semiconductor device. In this way, ten dummy semiconductor device-mounted wiring boards were produced and used as drop test specimens.
In the drop test, the test piece was observed on the concrete from a height of 1.8 m. In each test, each of the six faces was repeatedly dropped so that each of them faced down, and the number of the dummy semiconductor device and the dummy wiring board dropped out during that period (the number of failures) was examined. As a result, there were no failures among the dummy semiconductor device mounting wiring boards.
(Comparative Test Example 1)
The test was performed in the same manner as in Test Example 1 except that the protruding metal layer pattern of the dummy semiconductor device obtained in the same manner as in the above Test Example was shaved by polishing so as not to protrude. As a result, the number of rejected products was 3.

  A CSP semiconductor device was produced in the same manner as in Example 1 except that in the production of the semiconductor device, instead of gold plating of 0.3 μm, silver plating of 1 μm was performed.

1: Conductive substrate for plating 2: Conductive substrate 3: Insulating layer 4: Recessed portion 5: Photosensitive resist layer (photosensitive resin layer)
6: Protrusion 7, 71, 72, 73: Metal layer 8: Peelable substrate 9: Substrate material 10: Adhesive layer 11: Wiring substrate for connecting semiconductor elements 12: Nickel plating 13: Gold plating 14: Plating 16: Die bonding material 17: Semiconductor element 18: Bonding wire 20: Sealing material 21: Sealing resin 22: Semiconductor device before dicing having a releasable substrate 23: Solder resist 24: Tin plating 25: Solder ball 26: Semiconductor device

Claims (16)

  A semiconductor device including a conductive metal layer pattern to which a semiconductor element is electrically connected and a conductive metal layer pattern for wiring under a semiconductor element via a die bonding material, and these are sealed with a sealing material The semiconductor device, wherein the conductive metal layer pattern is partially exposed in the thickness direction.   The connecting member of the semiconductor element and the conductive metal layer pattern is a bonding wire for wire bonding connection between a predetermined position of the semiconductor element and the conductive metal layer pattern, and the semiconductor element, the conductive metal layer pattern and the bonding wire are The semiconductor device according to claim 1, which is sealed with a sealing material.   The semiconductor device according to claim 1, wherein the connection member and the die bond material of the semiconductor element and the conductive metal layer pattern are anisotropic conductive adhesives, and these are sealed with a sealing material.   The semiconductor device according to claim 1, wherein the protruding amount of the conductive metal layer is 1 μm or more in the thickness direction and is a thickness of ½ or less of the metal layer thickness.   The semiconductor device according to any one of claims 1 to 4, wherein a portion of the conductive metal layer having a maximum width in a cross-sectional shape is buried in a sealing material or a die bond material.   6. The semiconductor device according to claim 1, wherein a solder ball is bonded to a conductive metal layer portion to be electrically bonded to the wiring board.   On the substrate for peeling, the conductive metal layer pattern to be connected to the semiconductor element and the conductive metal layer pattern for wiring on which the semiconductor element is to be mounted via the die-bonding material, and these conductive metal layer patterns are A wiring substrate for connecting a semiconductor element, which is partially embedded in the thickness direction.   8. The wiring substrate for connecting a semiconductor element according to claim 7, wherein the conductive metal layer is embedded in the peeling substrate in a thickness direction of 1 [mu] m or more and 1/2 or less of the metal layer thickness.   The wiring base material for a semiconductor element connection according to claim 7, wherein a portion of the conductive metal layer having a maximum width in the cross-sectional shape is exposed from the base material for peeling. A step of bonding the semiconductor element via a die bond material on the conductive metal layer pattern for wiring on which the semiconductor element of the wiring substrate for connecting a semiconductor element according to claim 7 is to be mounted;
Connecting the bonded semiconductor element and the conductive metal layer pattern for connecting the semiconductor element,
A step of integrally sealing the semiconductor element bonded on the peelable substrate and the conductive metal layer pattern with a sealing material, and for mounting a semiconductor element on which the semiconductor element is mounted by sealing with the sealing material A method for producing a semiconductor device, comprising a step of peeling a peeling substrate from a substrate. The semiconductor element is bonded onto the conductive metal layer pattern for wiring on which the semiconductor element of the wiring substrate for connecting a semiconductor element according to any one of claims 7 to 9 is to be mounted using an anisotropic conductive adhesive. Connecting a semiconductor element having a bump at a position to be electrically connected with the conductive metal layer pattern for connecting the semiconductor element,
A semiconductor element bonded and connected on the peelable substrate and a step of integrally sealing the conductive metal layer pattern with a sealing material, and a semiconductor element mounted with the semiconductor element sealed with the sealing material A method for manufacturing a semiconductor device, comprising a step of peeling a peeling substrate from a mounting substrate.   The semiconductor according to claim 10, further comprising a step of performing connection plating on a connection portion of the conductive metal layer pattern before the step of bonding the semiconductor element and the conductive metal layer pattern for connecting the semiconductor element. Device manufacturing method.   Furthermore, the manufacturing method of the semiconductor device in any one of Claims 10-12 including the process of couple | bonding a solder ball to the electroconductive metal layer part which should be electrically joined with a wiring board.   A semiconductor device mounting wiring board, wherein the semiconductor device according to claim 1 is soldered to a predetermined position of the wiring board with a metal layer portion protruding from the semiconductor device.   Soldering so that the protruding metal layer of the semiconductor device according to any one of claims 1 to 5 is covered with solder through the solder at the predetermined position of the wiring board having solder attached to the predetermined position on the wiring. A method of manufacturing a wiring board having a semiconductor device mounted thereon.   A method of manufacturing a wiring board having a semiconductor device mounted thereon, wherein the semiconductor device according to claim 6 is soldered to a predetermined position of wiring on the wiring board by a solder ball of the semiconductor device.

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