JP2011128663A - Data processing apparatus - Google Patents

Data processing apparatus Download PDF

Info

Publication number
JP2011128663A
JP2011128663A JP2009283525A JP2009283525A JP2011128663A JP 2011128663 A JP2011128663 A JP 2011128663A JP 2009283525 A JP2009283525 A JP 2009283525A JP 2009283525 A JP2009283525 A JP 2009283525A JP 2011128663 A JP2011128663 A JP 2011128663A
Authority
JP
Japan
Prior art keywords
data
bus
bit
processor
address
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009283525A
Other languages
Japanese (ja)
Inventor
Takeshi Hongo
Yasunori Okazaki
保憲 岡崎
健 本郷
Original Assignee
Yokogawa Electric Corp
横河電機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Yokogawa Electric Corp, 横河電機株式会社 filed Critical Yokogawa Electric Corp
Priority to JP2009283525A priority Critical patent/JP2011128663A/en
Publication of JP2011128663A publication Critical patent/JP2011128663A/en
Application status is Pending legal-status Critical

Links

Images

Abstract

[PROBLEMS] To reduce the load on a processor and prevent the third party from decrypting data in a non-volatile memory and preventing intentional tampering / rewriting to ensure security from a malicious third party. A simple data processing device.
In a data processing apparatus for securely writing and reading data between a processor and a non-volatile memory, data or address designation input from the processor or the non-volatile memory via a bus composed of a plurality of signal lines Bus conversion means for converting or restoring the bit arrangement of each bit data of the signal and outputting the converted data to the nonvolatile memory or the processor is provided.
[Selection] Figure 1

Description

  The present invention relates to a data processing apparatus that securely writes and reads data between a processor and a non-volatile memory, and in particular, reduces the load on the processor, decodes data in the non-volatile memory by a third party, and intentional tampering. Regarding prevention of rewriting.

  2. Description of the Related Art Conventionally, a data processing apparatus represented by a computer in which a non-volatile memory is mounted has a processor such as a CPU (Central Processing Unit) and a non-volatile memory connected to each other via an address bus and a data bus. Data is read (read) and written (write).

  However, since the non-volatile memory exists even if the power is turned off, the data inside the memory does not volatilize, so a third party can unintentionally remove the non-volatile memory from the data processing device and decrypt the data, There was a problem that there was a risk of rewriting it intentionally.

  In order to prevent such problems, in recent years, a data processing apparatus that securely writes and reads data between the processor and the nonvolatile memory by encrypting the data with the processor and storing it in the nonvolatile memory has been studied. Has been.

  As a prior art document related to such a conventional data processing apparatus, there is the following Patent Document 1.

JP 2001-154920 A

However, in the conventional data processing apparatus, every time the processor performs read (read) / write (write) access to the non-volatile memory via the bus, data encryption or decryption processing of the encrypted data occurs. There was a problem that a great load was generated on the processor.
The present invention solves the above-mentioned problems, and its purpose is to reduce the load on the processor and prevent the third party from decoding the data in the non-volatile memory and preventing intentional tampering / rewriting. Another object is to realize a data processing apparatus capable of ensuring security from a malicious third party.

In order to achieve such a problem, the invention according to claim 1 of the present invention is:
In a data processing apparatus for securely writing and reading data between a processor and a non-volatile memory,
A bus that converts or restores the bit arrangement of each bit data of data or addressing signal input from the processor or the nonvolatile memory via a bus composed of a plurality of signal lines, and outputs the converted bit array to the nonvolatile memory or the processor A data processing apparatus comprising a conversion means.

The invention according to claim 2 is the data processing apparatus according to claim 1,
The bus conversion means
Each bit data of data or addressing signal input from the processor or the non-volatile memory via a bus composed of a plurality of signal lines is output to the non-volatile memory or the processor by changing the arrangement of the signal lines of the bus. Bus conversion means is provided.

The invention according to claim 3 is the data processing apparatus according to claim 1 or 2,
The bus conversion means
A plurality of selectors for inputting all bit data via the bus and outputting one bit data of all the bit data;
Comprising selector control means for designating 1-bit data output from each selector;
The plurality of selectors;
At least several bits of data inputted from the bus are provided.

The invention according to claim 4 is the data processing apparatus according to any one of claims 1 to 3,
The bus conversion means
Each bit data input from the processor via a first data bus composed of a plurality of signal lines is output to the nonvolatile memory by changing the arrangement of the signal lines of the data bus, or
Data bus conversion means for outputting each bit data input from the nonvolatile memory via a second data bus comprising a plurality of signal lines to the processor by changing the arrangement of the signal lines of the data bus. And

The invention according to claim 5 is the data processing device according to any one of claims 1 to 3,
The bus conversion means
Each bit data of an address designation signal input via a first address bus comprising a plurality of signal lines from the processor is output to the nonvolatile memory by changing the arrangement of the signal lines of the address bus, or
Address bus conversion means for outputting each bit data of an address designation signal input from the nonvolatile memory via a second address bus composed of a plurality of signal lines to the processor by changing the arrangement of the signal lines of the address bus It is characterized by being.

The invention according to claim 6 is the data processing device according to claim 4 or 5, wherein
The data bus conversion means and the address bus conversion means are provided.

  As described above, according to the present invention, the bit arrangement of each bit data of the data input from the processor or the nonvolatile memory via the bus composed of a plurality of signal lines is converted and restored, and output to the nonvolatile memory or the processor. By providing the bus conversion means, it is possible to reduce the load on the processor when writing data more securely than before.

  In addition, the data processing apparatus of the present invention is also malicious because a third party can illegally remove the non-volatile memory to prevent the data in the non-volatile memory from being decoded and prevented from intentional tampering / rewriting. Security from a third party can be secured.

  According to the present invention, the bit array of each bit data of the data or the addressing signal input from the processor or the nonvolatile memory via the bus composed of a plurality of signal lines is converted, and the nonvolatile memory or the processor By providing data bus conversion means and address bus conversion means for output, the address bus and the data bus are converted via the address bus conversion means and the data bus conversion means, respectively. In addition, the storage destination address of the nonvolatile memory can be changed, which is effective in improving the difficulty of data interpretation.

  Further, according to the present invention, the bus conversion means receives all bit data via the bus, and outputs a plurality of selectors that output one bit data out of all the bit data and the one bit data output from each selector. It has a selector control means to specify, and since it can be realized with a simple combination circuit of hardware by providing a plurality of selectors with at least several bits of data input from the bus, it can be realized at low cost. This is also effective in that the load on the host processor is not increased because unnecessary conversion time does not occur due to data bus conversion.

It is a block diagram which shows one Example of the data processor which concerns on this invention. It is explanatory drawing before and after the bit arrangement | sequence conversion of the data by the data bus conversion means of the data processor which concerns on this invention, in other words before and after conversion of the signal line which outputs the bit data in a data bus (data bus conversion). It is a block diagram which shows the other Example of the data processor which concerns on this invention. It is a block diagram which shows one Example of the data bus conversion means of the data processor which concerns on this invention.

The main feature of the data processing apparatus of the present invention is that a bit array of each bit data of data or addressing signal input from a processor or a nonvolatile memory via a bus composed of a plurality of signal lines is converted, and the nonvolatile memory Alternatively, a bus conversion means for outputting to the processor is provided.
Hereinafter, a data processing apparatus and a manufacturing method thereof according to the present invention will be described with reference to the drawings.

<Example 1>
FIG. 1 is a block diagram showing an embodiment of a data processing apparatus according to the present invention. Hereinafter, a case where the bus is a 4-bit bus will be described as an example to simplify the description. Note that the bus of the data processing apparatus of the present invention is not limited to a 4-bit bus, and may be any bit bus as long as it is 2 bits or more.

  In addition, the data processing apparatus of the present invention may be any apparatus as long as it includes a processor such as a computer, a general-purpose server, and other electronic devices and a nonvolatile memory, and securely reads and writes data.

(Description of main configuration)
In FIG. 1, the data processing apparatus is mainly a CPU that can control each function of the data processing apparatus, and is a host processor that is an example of a processor that writes data to or reads data from storage means such as a memory. 1 and an example of bus conversion means for converting and restoring the bit arrangement of each bit data of data input from the host processor 1 via the first data bus 100 and outputting via the second data bus 200 The data bus conversion means 2 and data input from the data bus conversion means 2 via the second data bus 200 are written, and a nonvolatile memory 3 such as a flash memory for storing the data is configured.

The data bus conversion means 2 can be realized by a simple combination circuit using a pattern wiring on a printed circuit board or a small-scale gate array.
(Description of each component and its arrangement)

  The host processor 1 and the non-volatile memory 3 are connected to each other via an address bus 300, and input / output of an address designating signal for designating an address of a desired non-volatile memory 3 desired to be read access (read) / write access (write). The

The host processor 1 outputs a write request signal for requesting data writing to the nonvolatile memory 3 via a data write signal line (not shown).
When making a write request, the host processor 1 outputs to the nonvolatile memory 3 an address designation signal that designates an address of a desired nonvolatile memory 3 that is desired to be write-accessed (written) via the address bus 300.
Further, the host processor 1 outputs data to be written (written) to the nonvolatile memory 3 to the data bus 100 and writes the data to the nonvolatile memory 3.

On the other hand, the host processor 1 also outputs a read request signal for requesting the nonvolatile memory 3 to read data via a memory read signal line (not shown).
At this time, the host processor 1 outputs an address designation signal for designating an address of a desired nonvolatile memory 3 to be read-accessed (read) via the address bus 300 to the nonvolatile memory 3 and reads data from the nonvolatile memory 3. To do.

When the read request signal is input via the read signal line, the nonvolatile memory 3 stores the data stored in the memory address specified by the address specifying signal input via the address bus 300 as the second address. The data is output to the data bus 200.
Further, when a read request signal is input via the read signal line, the nonvolatile memory 3 stores the data stored in the memory address specified by the address specifying signal input via the address bus 300 as the second data. To the data bus 200.

When data (write data) is input from the host processor 1 via the first data bus 100, the data bus conversion means 2 converts the bit arrangement of each bit data of the input data to obtain the second data The data is output to the nonvolatile memory 3 via the data bus 200.
Further, when data (read data) is input from the nonvolatile memory 3 via the second data bus 200, the data bus conversion means 2 converts the bit arrangement of each bit data of the input data, and 1 to the host processor 1 via the data bus 100.

  In other words, the data bus is connected to the host processor 1 and the nonvolatile memory 3 via the data bus conversion means 2.

FIG. 2 is an explanatory view before and after bit array conversion of data by the data bus conversion means of the data processing apparatus according to the present invention, in other words, before and after conversion of a signal line for outputting bit data on the data bus (data bus conversion). .
In FIG. 2, the upper bit arrangement is a bit arrangement in the host processor 1, and the lower bit arrangement is a bit arrangement stored in the nonvolatile memory 3.

In FIG. 2, a to d indicate 1-bit data, and D0 to D3 indicate signal lines of the data bus on the host processor 1 side. D0 to d3 indicate signal lines of the data bus on the nonvolatile memory 3 side.
For example, as shown in FIG. 2, the bit array of data before conversion in the host processor 1 is (D0: a, D1: b, D2: c, D3: d).

  Data before conversion in the host processor 1 is subjected to bit array conversion (data bus conversion) of data by the data bus conversion means 2 of the data processing apparatus of the present invention, and stored in the nonvolatile memory 3, for example. Is a bit array after conversion (d0: b, d1: d, d2: a, d3: c) as shown in FIG.

(Description of operation)
With such a configuration, the data processing apparatus of the present invention performs the following A: write operation and B: read operation.

A: Write Operation The host processor 1 outputs a write request signal for requesting data write to the nonvolatile memory 3 via a data write signal line (not shown).
At this time, the host processor 1 outputs an address designation signal for designating an address of a desired non-volatile memory 3 to be write-accessed (written) to the non-volatile memory 3 via the address bus 300.
The host processor 1 outputs data to be written (written) to the nonvolatile memory 3 to the first data bus 100.

  When data (write data) is input from the host processor 1 via the first data bus 100, the data bus conversion means 2 converts the bit arrangement of each bit data of the input data to obtain the second data The data is output to the nonvolatile memory 3 via the data bus 200.

  For example, the data bus conversion means 2 converts the bit array “D0: a, D1: b, D2: c, D3: d” of the data before conversion in the host processor 1 as described with reference to FIG. (Convert the data bus), and output the converted bit array “d0: b, d1: d, d2: a, d3: c” to the nonvolatile memory 3 via the second data bus 200.

  For this reason, the data from the host processor undergoes bit array conversion (data bus conversion) of the data by the data bus conversion means 2, so that the data bit array in the nonvolatile memory is the data bit array in the host processor. Unlike the state, the third party cannot interpret the data.

  When the write request signal is input via the write signal line and the write data is input via the second data bus 200, the nonvolatile memory 3 is designated by the address designation signal input via the address bus 300. Write to the specified memory address.

Thus, in the data processing apparatus of the present invention, the data to be written is stored in the nonvolatile memory 3 because the data array is changed by the data bus conversion means 2 and output to the nonvolatile memory 3. The bit arrangement of the data is different from the bit arrangement of the data in the host processor, and the data is stored in the memory in a state in which the data cannot be interpreted by a third party.
In this state, the data processing apparatus of the present invention can prevent the third party from illegally removing the non-volatile memory to decrypt the data in the non-volatile memory, and prevent intentional tampering / rewriting, Security from malicious third parties can be secured.

  In addition, the data processing apparatus of the present invention includes bus conversion means for converting the bit arrangement of each bit data of the data input from the processor via the bus composed of a plurality of signal lines and outputting it to the nonvolatile memory. Thus, the load on the processor can be reduced when data is securely read between the processor and the nonvolatile memory.

B: Read Operation The host processor 1 outputs a read request signal for requesting data read from the nonvolatile memory 3 via a memory read signal line (not shown).
At this time, the host processor 1 outputs an address designation signal for designating an address of a desired nonvolatile memory 3 to be read-accessed (read) to the nonvolatile memory 3 via the address bus 300.

  When the read request signal is input via the read signal line, the nonvolatile memory 3 stores the data stored in the memory address specified by the address specifying signal input via the address bus 300 as the second address. The data is output to the data bus 200.

  When data (read data) is input from the nonvolatile memory 3 via the second data bus 200, the data bus conversion means 2 converts (restores) the bit arrangement of each bit data of the input data. And output to the host processor 1 via the first data bus 100.

  Specifically, the data bus conversion means 2 uses the bit array “d0: b, d1: d, d2: a, d3: c” of the data in the nonvolatile memory 3 as described with reference to FIG. Conversion (converting the array of signal lines on the data bus) and converting the converted bit array “D0: a, D1: b, D2: c, D3: d” via the first data bus 100 to the host processor 1 Output to.

  Therefore, the data to be read is stored in the non-volatile memory 3 in a state in which the data cannot be interpreted by a third party as described in “A: Write operation”. The bit array of the read data output from the non-volatile memory 3 by the means 2 becomes the same state as the initial bit array of the data in the host processor, and returns to a state where the data can be decoded.

  The data after bit array conversion output from the data bus conversion means 2 is input to the host processor 1 via the first data bus 100.

  That is, the data output from the nonvolatile memory 3 is input to the host processor 1 in a state where the bit array is converted (data bus conversion) by the data bus conversion means 2 and the bit array is restored.

  For this reason, the data processing apparatus of the present invention changes the arrangement of the signal lines to be output (data to be output) for each bit data input from the nonvolatile memory via the second data bus including a plurality of signal lines. Data bus conversion means for outputting the data to the processor via the first data bus 100), so that a third party cannot interpret the data in the nonvolatile memory 3. The processor load can be reduced when the stored data is ready to be decrypted (in other words, the data is securely read between the processor and the non-volatile memory).

  As a result, the data processing apparatus of the present invention converts and restores the bit arrangement of each bit data of the data input from the processor or the nonvolatile memory via the bus composed of a plurality of signal lines, to the nonvolatile memory or the processor. By providing the bus conversion means for outputting, it is possible to reduce the load on the processor when writing data more securely than before.

  In addition, the data processing apparatus of the present invention is also malicious because a third party can illegally remove the non-volatile memory to prevent the data in the non-volatile memory from being decoded and prevented from intentional tampering / rewriting. Security from a third party can be secured.

<Example 2>
The data processing apparatus according to the present invention is an example of a bus conversion unit in which the host processor and the nonvolatile memory convert not only the data bus conversion unit but also the address bus (converts the bit data array of the address designation signal). It may be connected via some address bus conversion means.

(Description of main configuration)
FIG. 3 is a block diagram showing another embodiment of the data processing apparatus according to the present invention. The same reference numerals are given to the parts common to FIG.

  In FIG. 3, the data processing apparatus of the present invention mainly includes a bit array of each bit data of an address designation signal input from the host processor 1 via the host processor 1, the data bus conversion means 2, and the address bus 300. The address bus converting means 4 which is an example of the bus converting means for converting / restoring and outputting the data via the second address bus 400, and the data inputted via the second data bus 200 via the address bus 400 And a non-volatile memory 3 such as a flash memory written at an address designated by an address designation signal inputted.

  In other words, the data bus is connected to the host processor 1 and the nonvolatile memory 3 via the data bus conversion means 2, and the address bus is connected to the host processor 1 and the nonvolatile memory 3 via the address bus conversion means 4. Is done.

When an address designation signal is input from the host processor 1 via the first address bus 300, the address bus conversion means 4 converts the bit arrangement of each bit data of the input address designation signal to generate the second The data is output to the nonvolatile memory 3 via the address bus 400.
Further, when data (read data) is input from the nonvolatile memory 3 via the second data bus 200, the data bus conversion means 2 converts the bit arrangement of each bit data of the input data, and 1 to the host processor 1 via the data bus 100.
The address bus conversion means 4 can be realized by a simple combination circuit using a pattern wiring on a printed board or a small-scale gate array.

(Description of operation)
With such a configuration, the data processing apparatus of the present invention performs the following C: write operation and D: read operation.

C: Write Operation The host processor 1 outputs a write request signal for requesting data write to the nonvolatile memory 3 via a data write signal line (not shown).
At this time, the host processor 1 outputs an address designation signal for designating an address of a desired nonvolatile memory 3 to be write-accessed (written) to the address bus conversion means 4 via the first address bus 300.
The host processor 1 outputs data to be written (written) to the nonvolatile memory 3 to the first data bus 100.

  When data (write data) is input from the host processor 1 via the first data bus 100, the data bus conversion means 2 converts the bit arrangement of each bit data of the input data to obtain the second data The data is output to the nonvolatile memory 3 via the data bus 200.

  On the other hand, when an address designation signal is input from the host processor 1 via the first address bus 300, the address bus conversion means 4 converts the bit arrangement of each bit data of the input address designation signal to obtain the second Output to the nonvolatile memory 3 via the address bus 200.

  For example, as described with reference to FIG. 2 above, the address bus conversion unit 4 has a bit array “D0: a, D1: b, D2: c, D3: d” of the address designation signal before conversion in the host processor 1. Is converted (data bus signal line array is converted), and the converted bit array “d0: b, d1: d, d2: a, d3: c” is nonvolatile via the second address bus 400. Output to the memory 3.

  The nonvolatile memory 3 receives a write request signal via the write signal line, receives write data via the second data bus 200, and converts the address bus via the second address bus 400. When the address designation signal is input, the data after bit array (data bus) conversion is written to the memory address designated by the address designation signal after bit array (address bus) conversion.

Therefore, in the data processing apparatus of the present invention, the address designation signal from the host processor undergoes bit array conversion (address bus conversion) of the data by the address conversion means 4, and the data from the host processor is the data bus. Since the bit array conversion (data bus conversion) of the data is performed by the conversion means 2, the memory address of the data in the nonvolatile memory is the state of the memory address of the original data specified by the host processor (address specification signal). Since the bit arrangement of the data is different from that in the host processor, the data is stored in the memory in a state in which the third party cannot interpret the data.
In this state, the data processing apparatus of the present invention can prevent the third party from illegally removing the non-volatile memory to decrypt the data in the non-volatile memory, and prevent intentional tampering / rewriting, Security from malicious third parties can be secured.

  In addition, the data processing apparatus of the present invention includes bus conversion means for converting the bit arrangement of each bit data of the data input from the processor via the bus composed of a plurality of signal lines and outputting it to the nonvolatile memory. Thus, the load on the processor can be reduced when data is securely read between the processor and the nonvolatile memory.

D: Read Operation The host processor 1 outputs a read request signal for requesting data read from the nonvolatile memory 3 via a memory read signal line (not shown).
At this time, the host processor 1 outputs an address designation signal for designating an address of a desired nonvolatile memory 3 to be read-accessed (read) via the first address bus 300 to the address conversion means 4.

  When an address designation signal is input from the host processor 1 via the first address bus 300, the address bus conversion means 4 converts the bit arrangement of each bit data of the input address designation signal to generate the second The data is output to the nonvolatile memory 3 via the address bus 400.

  When a read request signal is input via the read signal line, the nonvolatile memory 3 receives the address designation after conversion of the bit arrangement (address bus) input from the address bus conversion unit 4 via the first address bus 300. Data stored in the memory address designated by the signal is output to the second data bus 400.

  For this reason, the data to be read cannot be interpreted by a third party as described in the description of “C: write operation” (the memory address of the data in the non-volatile memory is specified by the host processor). Is stored in the nonvolatile memory 3 in a state different from the memory address state (bit arrangement state of the address designation signal) of the original data, but is output from the nonvolatile memory 3 by the address bus conversion means 4. The memory address of the data specified by the address specification signal of the read data becomes the same as the bit array of the memory address specified by the address specification signal output from the original host processor, and the data can be decoded again.

  Further, when data (read data) is input from the nonvolatile memory 3 via the second data bus 200, the data bus conversion means 2 converts the bit arrangement of each bit data of the input data, The data is output to the host processor 1 via the first data bus 100.

  Specifically, the data bus conversion means 2 uses the bit array “d0: b, d1: d, d2: a, d3: c” of the data in the nonvolatile memory 3 as described with reference to FIG. The data is converted (data bus is converted), and the converted bit array “D0: a, D1: b, D2: c, D3: d” is output to the host processor 1 via the first data bus 100.

  The data after bit array conversion is input to the host processor 1 via the first data bus 100.

  That is, the data output from the nonvolatile memory 3 is input to the host processor 1 in a state where the bit array is converted (data bus conversion) by the data bus conversion means 2 and the bit array is restored.

As a result, the data processing device of the present invention converts the bit array of each bit data of the data or the addressing signal input from the processor or the nonvolatile memory via the bus composed of a plurality of signal lines, and the nonvolatile memory or By providing the data bus conversion means and the address bus conversion means for outputting to the processor, the address bus and the data bus are converted via the address bus conversion means and the data bus conversion means, respectively. Not only the array change but also the storage destination address of the nonvolatile memory can be changed, which is effective in improving the difficulty of data interpretation.
This makes it more difficult for a third party to illicitly remove the non-volatile memory and decrypt the data, or to intentionally rewrite the data, thus ensuring security from a malicious third party. It is valid.
In addition, since both address bus conversion means and data bus conversion means can be realized by a simple combination circuit of hardware, there is no unnecessary conversion time for bus conversion and the load on the host processor is not increased. But it is effective. It is also effective in that it can be realized at low cost.

The data processing apparatus according to the present embodiment is described as including a data bus conversion unit and an address bus conversion unit. However, the present invention is not limited to this, and the data processing apparatus is only an address bus conversion unit. It may be provided.
Even in this case, the data processing apparatus of the present invention reduces the load on the processor and prevents the third party from decoding the data in the non-volatile memory and preventing intentional tampering / rewriting. It is possible to secure security from malicious third parties.

<Example 3>
The data processing apparatus according to the present invention may be capable of changing / controlling the bus conversion rule (data bit array conversion rule) of the data bus conversion means or the address bus conversion means.

(Description of main configuration)
FIG. 4 is a block diagram showing an embodiment of the data bus conversion means of the data processing apparatus according to the present invention. In FIG. 4, the configuration in the case where the data bus is a 4-bit bus will be described as an example. However, the configuration is not particularly limited to this. Any configuration is possible as long as it has several bits of data input from the data bus. The configuration of the address bus conversion unit 4 is the same as that of the data bus conversion unit 3.

  In FIG. 4, the data bus conversion means 3 is a plurality of selectors that mainly receive all bit data from the host processor 1 via the first data bus 100 and output 1 bit data out of these all bit data. 31A to 31D, diodes 32A to 32D, which are examples of directional elements, and all bit data are input from the nonvolatile memory 3 via the second data bus 200, and 1 bit data of these all bit data is received. A plurality of selectors 33A to 33D to be output, diodes 34A to 34D as examples of directional elements, and a selector control module 35 as an example of selector control means for designating 1-bit data output from each selector.

  The plurality of selectors 31A to 31D and the diodes 32A to 32D of the data bus conversion means 3 constitute a write data conversion unit 300, and the plurality of selectors 33A to 33D and the diodes 34A to 34D constitute a read data conversion unit 310.

(Description of each component and its arrangement)
The selectors 31A to 31D select arbitrary 1-bit data among the 1-bit data inputted from the data lines D0 to D3 of the data bus on the host processor 1, respectively, and the signal lines of the data bus on the nonvolatile memory 3 side, respectively. Output to d0 to d3.
The selectors 33A to 33D select arbitrary 1-bit data among the 1-bit data input from the signal lines d0 to d3 of the data bus on the non-volatile memory 3 side, and the signal lines of the data bus on the host processor 1 side respectively. Output to D0 to D3.

  The diodes 32 </ b> A to 32 </ b> D have a function of flowing current only in a certain direction, and output output signals from the selectors 31 </ b> A to 31 </ b> D to the second data bus 200.

  The diodes 34 </ b> A to 34 </ b> D have a function of flowing current only in a certain direction, and output output signals from the selectors 33 </ b> A to 33 </ b> D to the first data bus 100.

In the write data conversion unit 300, the first data bus 100 is connected to the input terminals of the plurality of selectors 31A to 31D, and all bit data is sent from the host processor 1 to the selectors 31A to 31D via the first data bus 100. Each is entered.
The output terminals of the selectors 31A to 31D are connected to the input terminals of the diodes 32A to 32D, respectively, and the output terminals of the diodes 32A to 32D are connected to the second data bus 200.

In the read data conversion unit 300, the second data bus 200 is connected to the input terminals of the plurality of selectors 33A to 33D, and all bit data is sent from the host processor 1 to the selectors 33A to 33D via the second data bus 200. Each is entered.
The output terminals of the plurality of selectors 33A to 33D are connected to the input terminals of the diodes 34A to 34D, respectively, and the output terminals of the diodes 34A to 34D are connected to the first data bus 100.

  The output terminals of the selector control module 35 are connected to the control terminals of the selectors 31A to 31D and the selectors 33A to 33D through control lines, respectively, and the selector control module 35 is based on a “bus conversion switching signal” input from the outside. The generated select signals are input to the selectors 31A to 31D and the selectors 33A to 33D, respectively.

  Here, the bus conversion switching signal is a signal for switching the bus conversion rule of the bus conversion means (in other words, the bit arrangement conversion rule of the data (or addressing signal)). For example, the data bus conversion performed by the bus conversion means As shown in FIG. 2, a predetermined conversion rule for (bit array conversion) is as follows (D0: a, D1: b, D2: c, D3: d) → after conversion (d0: b, d1: d, d2). : A, d3: c) before conversion (D0: a, D1: b, D2: c, D3: d) → after conversion (d0: c, d1: d, d2: a, d3: b) ).

The select signal is generated by the selector control module 35 based on the “bus conversion switching signal”, and is a signal for selecting the outputs of the selectors 31A to 31D and the selectors 33A to 33D.
For example, the selector control module 35 determines that the input bus conversion switching signal changes the data conversion rule from before conversion (D0: a, D1: b, D2: c, D3: d) to after conversion (d0: c, d1: d, d2: a, d3: b), a “select signal” for outputting the bit data input to the signal line D2 of the data bus on the host processor 1 side to the selector 31A. Output.

(Description of operation)
With such a configuration, the data bus conversion means 3 of the data processing apparatus according to the present invention performs data bus conversion (data conversion from the host processor 1) as follows.

First, the user inputs a bus switching signal to the selector control module 35 via input means (not shown).
The selector control module 35 outputs select signals to the selectors 31A to 31D and the selectors 33A to 33D, respectively.
The selectors 31A to 31D and the selectors 33A to 33D set bit data to be output based on the select signal received from the select control module 35.

In this state, when the selectors 31A to 31D receive data from the host processor 1 via the first data bus 100, the individual bits on the bus set based on the select signal received from the select control module 35 are displayed. Is output exclusively.
Also, when the selectors 33A to 33D receive data from the nonvolatile memory 3 via the second data bus 200, the individual bits on the bus set based on the select signal received from the select control module 35 are exclusively obtained. Output.

  As a result, in the data processing apparatus of the present invention, the bus conversion means receives all bit data via the bus, a plurality of selectors that output one bit data out of all the bit data, and each selector outputs 1 Since selector control means for designating bit data is provided, and a plurality of selectors are provided with at least the number of bits of data input from the bus, it can be realized by a simple combination circuit of hardware, so that the cost is low. This is also effective in that it does not increase the load on the host processor because no unnecessary conversion time is generated by data bus conversion.

  Note that the bus conversion means of the data processing apparatus of the present invention may be realized by a reconfigurable gate array (FPGA (Field Programmable Gate Array) or the like). It is possible to implement it more effectively against unauthorized decryption of data by third parties and intentional rewriting of data.

(Additional item 1)
The bus conversion means includes
Data bus conversion means for converting a bit array of write data output from the processor and outputting the converted data to the nonvolatile memory and converting a bit array of read data output from the nonvolatile memory and outputting the converted data to the processor The data processing apparatus according to claim 1, wherein the data processing apparatus is provided.
(Appendix 2)
The bus conversion means includes
The bit array of each bit data of the address specification signal of the write data output from the processor is converted and output to the nonvolatile memory, and each bit data of the address specification signal of the read data output from the nonvolatile memory 3. The data processing apparatus according to claim 1, wherein the data processing apparatus is an address bus conversion unit that converts a bit arrangement and outputs the converted bit array to the processor.

DESCRIPTION OF SYMBOLS 1 Host processor 2 Non-volatile memory 3 Data bus conversion means 31A-31D, 33A-33D Selector 35 Selector control module 4 Address bus conversion means

Claims (6)

  1. In a data processing apparatus for securely writing and reading data between a processor and a non-volatile memory,
    A bus that converts or restores the bit arrangement of each bit data of data or addressing signal input from the processor or the nonvolatile memory via a bus composed of a plurality of signal lines, and outputs the converted bit array to the nonvolatile memory or the processor A data processing apparatus comprising conversion means.
  2. The bus conversion means includes
    Each bit data of data or addressing signal input from the processor or the non-volatile memory via a bus composed of a plurality of signal lines is output to the non-volatile memory or the processor by changing the arrangement of the signal lines of the bus. The data processing apparatus according to claim 1, further comprising a bus conversion unit.
  3. The bus conversion means includes
    A plurality of selectors for inputting all bit data via the bus and outputting one bit data of all the bit data;
    Comprising selector control means for designating 1-bit data output from each selector;
    The plurality of selectors;
    3. The data processing apparatus according to claim 1, further comprising at least several bits of data input from the bus.
  4. The bus conversion means includes
    Each bit data input from the processor via a first data bus composed of a plurality of signal lines is output to the nonvolatile memory by changing the arrangement of the signal lines of the data bus, or
    Data bus conversion means for outputting each bit data input from the nonvolatile memory via a second data bus comprising a plurality of signal lines to the processor by changing the arrangement of the signal lines of the data bus. The data processing apparatus according to claim 1, wherein the data processing apparatus is characterized in that:
  5. The bus conversion means includes
    Each bit data of an address designation signal input from the processor via a first address bus composed of a plurality of signal lines is output to the nonvolatile memory by changing the arrangement of the signal lines of the address bus, or
    Address bus conversion means for outputting each bit data of an address designation signal input from the nonvolatile memory via a second address bus composed of a plurality of signal lines to the processor by changing the arrangement of the signal lines of the address bus The data processing apparatus according to claim 1, wherein the data processing apparatus is a data processing apparatus.
  6.   6. The data processing apparatus according to claim 4, further comprising: the data bus conversion unit and the address bus conversion unit.
JP2009283525A 2009-12-15 2009-12-15 Data processing apparatus Pending JP2011128663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009283525A JP2011128663A (en) 2009-12-15 2009-12-15 Data processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009283525A JP2011128663A (en) 2009-12-15 2009-12-15 Data processing apparatus

Publications (1)

Publication Number Publication Date
JP2011128663A true JP2011128663A (en) 2011-06-30

Family

ID=44291241

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009283525A Pending JP2011128663A (en) 2009-12-15 2009-12-15 Data processing apparatus

Country Status (1)

Country Link
JP (1) JP2011128663A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015097072A (en) * 2013-10-11 2015-05-21 富士電機株式会社 Embedded system
US9569371B2 (en) 2014-06-13 2017-02-14 Samsung Electronics Co., Ltd. Memory device, memory system, and operating method of memory system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015097072A (en) * 2013-10-11 2015-05-21 富士電機株式会社 Embedded system
US9569371B2 (en) 2014-06-13 2017-02-14 Samsung Electronics Co., Ltd. Memory device, memory system, and operating method of memory system

Similar Documents

Publication Publication Date Title
CN1129916C (en) Programmable access protection in flash memory device
US6944083B2 (en) Method for detecting and preventing tampering with one-time programmable digital devices
DE60001927T2 (en) Method and device for protecting configuration data property for programmable logical devices
US6356637B1 (en) Field programmable gate arrays
JP4299679B2 (en) Control function that restricts data access in the integrated system using the requesting master ID and data address
EP1815681B1 (en) Digital audio/video data processing unit and method for controlling access to said data
US7185208B2 (en) Data processing
Kean Secure configuration of field programmable gate arrays
US8074082B2 (en) Anti-tamper module
EP2294529B1 (en) Electronic device and method of software or firmware updating of an electronic device
US20080022396A1 (en) Memory data protection device and IC card LSI
US4797928A (en) Encryption printed circuit board
US5131091A (en) Memory card including copy protection
US20070150752A1 (en) Secure system-on-chip
US10235540B2 (en) Apparatus and method for generating identification key
US20140164793A1 (en) Cryptographic information association to memory regions
JP6239259B2 (en) System on chip, operation method thereof, and system in package including the same
EP0114522A2 (en) ROM protection device
US6651170B1 (en) Integrated circuit and smart card comprising such a circuit
JP4606339B2 (en) Method and apparatus for performing secure processor processing migration
KR20100039647A (en) Data storage device and data storage system having the same
US8175276B2 (en) Encryption apparatus with diverse key retention schemes
EP1234239B1 (en) Microprocessor arrangement having an encoding function
US6691921B2 (en) Information processing device
JP2004519111A (en) Field programmable gate array with program encryption