JP2011124273A - Wiring structure manufacturing method, and wiring structure - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring structure manufacturing method, along with a wiring structure, wherein the wiring structure can be formed in a simple process and wiring extraction with a high degree of freedom is allowed in a simple configuration. <P>SOLUTION: The wiring structure manufacturing method includes a two-dimensional electronic gas layer forming process of forming a lamination by laminating different kinds of materials via an interface where charge accumulation occurs to form a two-dimensional electronic gas layer on the interface of the lamination, and a selective heating process of selectively heating the two-dimensional electronic gas layer to selectively form a nonconductive region on the two-dimensional electronic gas layer and forming a given wiring structure consisting of the nonconductive region and a nonheated conductive region. <P>COPYRIGHT: (C)2011,JPO&amp;INPIT

Description

  The present invention relates to a method for manufacturing a wiring structure and a wiring structure, and more particularly to a method for manufacturing a wiring structure using a two-dimensional electron gas layer and a wiring structure.

  Conventionally, by stacking a first compound semiconductor layer and a second compound semiconductor layer having a composition different from that of the first compound semiconductor layer on a conductive substrate, a two-dimensional electron gas layer is formed at the junction interface between the two. Then, oxygen ions are implanted into unnecessary portions of the first compound semiconductor layer and the second compound semiconductor layer to extinguish the properties of the semiconductor, insulating unnecessary two-dimensional electron gas, and necessary two-dimensional Impedance in which an electron gas layer is left in a linear shape, electrodes are further provided on the second compound semiconductor layers at both ends of the linear two-dimensional electron gas layer, and an ohmic diffusion layer is formed under the electrode to reach the two-dimensional electron gas layer A track is known (see, for example, Patent Document 1).

Japanese Patent Laid-Open No. 7-326737

  However, in the configuration described in Patent Document 1 described above, it is difficult to perform miniaturization processing by reducing the width of the insulating portion at a low cost. There was a problem that the degree of freedom was limited.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a wiring structure manufacturing method and a wiring structure which can form a wiring structure with a simple process and can take out wiring with a high degree of freedom with a simple structure.

In order to achieve the above object, a method for manufacturing a wiring structure according to a first aspect of the present invention is to form a laminate by stacking different materials that generate charge accumulation at a junction interface, and to form a two-dimensional electron at the junction interface of the laminate. A two-dimensional electron gas layer forming step of forming a gas layer;
A selective heating step of selectively heating the two-dimensional electron gas layer to selectively form a non-conductive region in the two-dimensional electron gas layer and forming a predetermined wiring structure with the non-heated conductive region It is characterized by including these.

  As a result, it is possible to manufacture a wiring structure that saves space by a simple process of forming a two-dimensional electron gas layer and then performing selective heating.

A second invention is a method of manufacturing a wiring structure according to the first invention.
In the selective heating step, a mask forming step of forming a heat-insulating mask on the surface of the stacked body above the position where the conductive region is formed;
And a heating step of performing heat treatment by supplying heat from above the mask.

  Thereby, the selective heating process can be easily performed by forming the mask, and the process can be simplified.

A third invention is a method of manufacturing a wiring structure according to the second invention,
The selective heating step further includes a light element injection step of injecting a light element into the surface of the stacked body between the mask formation step and the heating step, and generating a crystal defect in a region where the mask does not exist. It is characterized by including.

  Thereby, formation of the nonelectroconductive area | region of the two-dimensional electron gas layer in a selective heating process can be accelerated | stimulated.

4th invention is the manufacturing method of the wiring structure which concerns on any one of 1st-3rd invention,
The method further includes a protective film forming step of forming a protective film on the surface of the stacked body above the conductive region after the selective heating step.

  Accordingly, even when a material that easily generates / accumulates a charge on the surface is used for the upper layer of the stacked body, leakage between wirings can be prevented.

  A fifth invention is characterized in that the method for manufacturing a wiring structure according to any one of the first to third inventions is repeated to form a multilayer wiring including a plurality of conductive regions.

  As a result, a space-saving multi-layered wiring can be easily formed by repeating simple steps.

A wiring structure according to a sixth aspect of the present invention is a laminated portion made of a different material having a two-dimensional electron gas layer having conductivity at a bonding interface;
It includes a portion in contact with the two-dimensional electron gas layer and a take-out electrode having a portion existing outside the stacked portion.

  Thereby, the extraction electrode can be provided with a simple configuration with few restrictions, and space saving and the degree of freedom of the wiring configuration can be improved.

According to a seventh invention, in the wiring structure according to the sixth invention,
The laminated portion is configured by partially laminating a second material layer on the first material layer,
The extraction electrode is a metal thin film formed on the first material layer.

  Thereby, the extraction electrode can be provided with a simple structure using a metal thin film, and the wiring structure can be configured without providing a space for the extraction electrode separately.

An eighth invention is the wiring structure according to the sixth or seventh invention,
A portion of the extraction electrode existing outside the stacked portion is exposed.

  Thereby, electric power can be directly supplied to the exposed part from the outside, and electric power can be supplied with little loss.

According to a ninth invention, in the wiring structure according to the seventh invention,
On the upper layer of the extraction electrode, a non-conductive region is formed,
In the non-conductive region, a contact hole that is electrically connected to the extraction electrode is formed.

  As a result, as in a general semiconductor device, the wiring of the wiring structure can be electrically connected to the external electrode or wiring using a contact hole.

A tenth invention is the wiring structure according to the seventh or ninth invention,
The stacked portion has a multilayer structure in which the first material layers and the second material layers are alternately stacked.

  As a result, it is possible to configure a multilayer wiring structure without providing a space for the extraction electrode, preventing the situation where the structure is complicated and the degree of freedom is restricted due to the multilayering, and the structure is simple and has a high degree of freedom. A wiring structure can be realized.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing process of wiring structure can be simplified and the freedom degree of wiring can be improved.

It is the figure which showed the example of the wiring structure manufactured by the manufacturing method of the wiring structure which concerns on a present Example. FIG. 1A is a diagram illustrating an example of a wiring structure including a non-conductive region 50. FIG. 1B is a diagram illustrating an example of a wiring structure in which the stacking relationship of the stacking materials is reversed from that in FIG. It is the figure which showed the example of the multilayer wiring structure manufactured with the manufacturing method of the wiring structure which concerns on a present Example. FIG. 2A is a diagram illustrating an example of a wiring structure using a multilayer interface. FIG. 2B is a diagram showing an example of a wiring structure using multilayer interfaces arranged in parallel in the vertical direction. It is the figure which showed the example of the wiring structure which does not contain the nonelectroconductive area | region 50 manufactured by the manufacturing method of the wiring structure which concerns on a present Example. FIG. 3A is a cross-sectional view showing an example of a wiring structure without the protective film 60. FIG. 3B is a cross-sectional view showing an example of a wiring structure having a protective film 60. It is the figure which showed an example of the two-dimensional electron gas layer formation process of the manufacturing method of the wiring structure which concerns on Example 1. FIG. 6 is a diagram showing an example of a mask forming process of the method for manufacturing a wiring structure according to Example 1. FIG. 6 is a diagram illustrating an example of a light element implantation step in the method for manufacturing a wiring structure according to Example 1. FIG. 6 is a diagram showing an example of a heating process of the method for manufacturing a wiring structure according to Example 1. FIG. 6 is a diagram illustrating an example of a mask removing process of the manufacturing method of the wiring structure according to Example 1. FIG. 6 is a diagram showing an example of a protective film forming step of the method for manufacturing a wiring structure according to Example 1. FIG. It is the figure which showed the example of a two-dimensional electron gas layer formation process for manufacturing a multilayer wiring structure. It is the figure which showed an example of the two-dimensional electron gas layer formation process of the manufacturing method of the wiring structure which concerns on Example 2. FIG. 6 is a diagram illustrating an example of a mask forming process of a manufacturing method of a wiring structure according to Example 2. FIG. 6 is a diagram illustrating an example of an etching process of a manufacturing method of a wiring structure according to Example 2. FIG. 6 is a diagram illustrating an example of a mask removing process of a manufacturing method of a wiring structure according to Example 2. FIG. 6 is a diagram illustrating an example of a protective film forming step of a method for manufacturing a wiring structure according to Example 2. FIG. 6 is a diagram illustrating an example of an ion implantation step of a method for manufacturing a wiring structure according to Example 3. FIG. It is the figure which showed an example of the mask removal process of the manufacturing method of the wiring structure which concerns on Example 3, and a diffusion process. It is the figure which showed an example of the 1st material layer lamination process of the manufacturing method of the wiring structure which concerns on Example 3. FIG. It is the figure which showed an example of the two-dimensional electron gas layer formation process of the manufacturing method of the wiring structure which concerns on Example 3. FIG. 6 is a diagram showing an example of an etching process of a method for manufacturing a wiring structure according to Example 3. FIG. FIG. 10 is a diagram illustrating an example of a mask removal process of a method for manufacturing a wiring structure according to Example 3. It is the figure which showed an example of the wiring structure which concerns on Example 4 of this invention. FIG. 8A is a cross-sectional view of the wiring structure according to the fourth embodiment. FIG. 8B is a perspective view of the wiring structure according to the fourth embodiment. FIG. 10 is a diagram illustrating an example of a cross-sectional configuration of a wiring structure according to a fifth embodiment. FIG. 10 is a diagram illustrating an example of a cross-sectional configuration of a wiring structure according to Example 6; 10 is a diagram showing an example of a cross-sectional configuration of a wiring structure according to Example 7. FIG.

  DESCRIPTION OF EMBODIMENTS Hereinafter, embodiments for carrying out the present invention will be described with reference to the drawings.

  FIG. 1 is a diagram illustrating an example of a wiring structure manufactured by a method for manufacturing a wiring structure according to an embodiment of the present invention. FIG. 1A is a diagram showing an example of a wiring structure including a non-conductive region 50. FIG. 1B is a wiring structure in which the stacking relationship of the stacking material is reversed from that in FIG. It is the figure which showed an example.

  In FIG. 1A, the wiring structure manufactured by the wiring structure manufacturing method according to the present embodiment includes a first material layer 10, a second material layer 20, a two-dimensional electron gas layer 40, Conductive region 50. A second material layer 20 is laminated on the first material layer 10 to form a laminated portion 30. The stacked portion 30 is formed in a convex shape. The two-dimensional electron gas layer 40 is formed at the bonding interface between the first material layer 10 and the second material layer 20. Further, the non-conductive region 50 fills a region other than the stacked portion 30 so as to cover the convex stacked portion 30 from the periphery.

  The first material layer 10 and the second material layer 20 are composed of a combination of different materials that cause charge accumulation at the junction interface between the first material layer 10 and the second material layer 20, for example, a semiconductor and an insulator. Or it is comprised from dissimilar semiconductors. Here, charge accumulation at the junction interface means a state in which electrons are two-dimensionally distributed and filled with electrons at the junction interface. The two-dimensional electron gas layer 40 formed at the bonding interface between the first material layer 10 and the second material layer 20 is filled with such electrons. The electrons in the two-dimensional electron gas layer 40 move along the bonding interface, and are rare electrons having momentum only in the two-dimensional plane. Therefore, the two-dimensional electron gas layer 40 constitutes a two-dimensional conductive region.

  The first material layer 10 and the second material layer 20 may be made of various different materials that form a two-dimensional electron gas layer at the stack interface when stacked. For example, InAs and AlSb, InAlAs and InGaAs Various combinations of GaAs and AlGaAs, GaN and AlGaN, etc. are conceivable. Further, a wiring structure in which a combination of different kinds of materials is used for the same semiconductor device may be used. For example, a two-dimensional wiring formed of AlSb and InAs and a two-dimensional wiring formed of GaAs and AlGaAs are the same semiconductor. It may be formed in the device. In the example of FIG. 1A, the left convex wiring structure and the right convex wiring structure may be a combination of different materials. In FIG. 1A, it is assumed that the first material layer 10 is made of AlSb, the second material layer 20 is made of InAs, and semiconductor materials having different compositions are used.

  The non-conductive region 50 is a region of an insulator that does not have conductivity. In the manufacturing method of the wiring structure according to the present embodiment, the wiring structure is constituted by the region of the two-dimensional electron gas layer 40 having conductivity and the non-conductive region 50 having no conductivity.

  In FIG. 1B, AlSb used for the first material layer 10 in FIG. 1 is used for the second material layer 21, and InAs used for the second material layer 20 in FIG. The example which comprises the laminated part 31 using the material layer 11 of this is shown. A conductive two-dimensional electron gas layer 41 is formed at the bonding interface between the first material layer 11 and the second material layer 21, and is filled so as to cover the non-conductive region 51. Even in this case, a wiring structure similar to that shown in FIG.

  Thus, as long as the 1st material layer 10 and the 2nd material layer 20 are the combination of the dissimilar materials which form the two-dimensional electron gas layers 40 and 41 in a joining interface, any may be made into the upper layer side. For example, when the surface of the stacked unit 30 is exposed, the second material layer 20 may be configured as a material that is less likely to be oxidized.

  FIG. 2 is a diagram illustrating an example of a multilayer wiring structure manufactured by the wiring structure manufacturing method according to the present embodiment. FIG. 2A is a diagram showing an example of a wiring structure using a multilayer interface, and FIG. 2B shows an example of a wiring structure using a multilayer interface arranged in parallel vertically. FIG. Components similar to those in FIG. 1 are denoted by the same reference numerals and description thereof is omitted.

  In FIG. 2A, a stacked portion 30 formed by stacking a first material layer 10 and a second material layer 20 has a two-dimensional electron gas layer 40 at the stack interface, and its periphery is non- The point filled with the conductive region 50 is the same as in FIG. In FIG. 2A, the first material layer 12 is further stacked on the upper layer of the stacked portion 30 and the non-conductive region 50, and the stacked portion 32 is configured with the second material layer 22. This is different from FIG. The upper layer stack portion 32 is configured as a stacked body of different materials of the first material layer 12 and the second material layer 22, and 2 at the bonding interface between the first material layer 12 and the second material layer 22. The two-dimensional electron gas layer 42 is formed, and the periphery thereof is filled and covered with the non-conductive region 52 in the same manner as the lower layered portion 30. As described above, the stacked portions 30 and 32 may be formed as a multilayer structure to constitute a multilayer wiring structure.

  2A, the two-dimensional electron gas layer 40 of the stacked unit 30 and the two-dimensional electron gas layer 42 of the stacked unit 32 are configured independently, and the two-dimensional electron gas layer 40, 42 shows an example in which each layer is used as a different wiring. Thus, the two-dimensional electron gas layers 40 and 42 of each layer can be independently configured.

  In FIG. 2A, both of the first material layers 10 and 12 are made of AlSb, and both of the second material layers 20 and 22 are made of InAs, and different materials of the same combination are used. The stacked portions 30 and 32 may be configured, or the stacked portions 30 and 32 may be configured with different combinations of different materials.

  Unlike FIG. 2A, FIG. 2B is a diagram showing an example of a cross-sectional configuration of a multi-layer wiring using multi-layer interfaces arranged in parallel in the vertical direction. 2B is the same as FIG. 2A in that the first material layer 10 and the second material layer 20 are stacked to form a two-dimensional electron gas layer 40. However, in FIG. 2B, only one third material layer 13 is stacked over the second material layer 20, and 2 between the second material layer 20 and the third material layer 13. A two-dimensional electron gas layer 43 is formed and the periphery of the two-dimensional electron gas layers 40 and 43 is filled with a common non-conductive region 53, which is different from the multilayer wiring structure of FIG. The two-dimensional electron gas layers 40 and 43 are formed in parallel vertically. In such a wiring structure, the two-dimensional electron gas regions 40 and 43 can be used as a two-dimensional wiring in which a plurality of two-dimensional electron gas regions 40 and 43 are arranged in parallel vertically.

  Note that the third material layer 13 may be made of the same material (for example, AlSb) as the first material layer 10 or different from both the first material layer 10 and the second material layer 20. A material may be used.

  Further, in FIGS. 2A and 2B, the multilayer wiring structure has been described by taking two layers as an example. However, a multilayer structure may be formed by further stacking layers to cover the number of layers.

  FIG. 3 is a diagram showing an example of a wiring structure that does not include the non-conductive region 50 manufactured by the manufacturing method of the wiring structure according to the present embodiment. 3A is a cross-sectional view showing an example of a wiring structure not covered with the protective film 60, and FIG. 3B is a cross-sectional view showing an example of a wiring structure covered with the protective film 60. FIG.

  In FIG. 3A, the second material layer 24 is partially stacked on the first material layer 14 to form a stacked portion 34. A two-dimensional electron gas layer 44 is formed at the bonding interface between the first material layer 14 and the second material layer 24. The difference from FIG. 1A is that the nonconductive region 50 that covers the stacked portion 34 from the periphery is not formed, and the nonconductive region 50 does not exist. As described above, the wiring structure may be formed by removing the two-dimensional electron gas layer 44 in a region where the two-dimensional electron gas layer 44 constituting the wiring is not necessary. For example, a wiring structure having a configuration as shown in FIG. 3A can be formed by removing the stacked portion 34 by etching in a region where the two-dimensional electron gas layer 44 is unnecessary.

  FIG. 3B shows a wiring structure having a structure in which the surface of the wiring structure of FIG. In the configuration shown in FIG. 3A, the surface of the second material layer 24, the side surface of the two-dimensional electron gas layer 44, which is a conductive region, and the surface of the first material layer 14 are exposed to air. Therefore, in the configuration shown in FIG. 3B, the exposed portion is covered with the protective film 60 in order to prevent oxidation and adhesion of foreign matter. As described above, the surface of the wiring structure may be covered with the protective film 60.

  Note that the two-dimensional electron gas layers 40 to 44 constituting the conductive region (wiring portion) described with reference to FIGS. 1 to 3 can be composed of 10 [nm] or less. In the formation of a wiring structure by ion implantation and thermal diffusion used in a semiconductor process, the ion implantation portion expands laterally and in the depth direction by thermal diffusion and requires a depth of several tens to several hundreds [nm]. On the other hand, the conductive region can be formed very thin, and the wiring structure can be saved.

  4A to 4F are diagrams illustrating a series of steps of the method for manufacturing a wiring structure according to the first embodiment of the present invention. In the method for manufacturing a wiring structure according to the first embodiment, as an example, a method for manufacturing a wiring structure using InAlAs and InGaAs will be described. As long as these are combinations of different materials that accumulate charges at the interface, various combinations can be applied. For example, a combination of AlSb and InAs, GaAs and AlGaAs, GaN and AlGaN, or the like may be used. In the manufacturing method of the wiring structure according to the present embodiment, a specific material will be described as an example for easy understanding.

  FIG. 4A is a diagram illustrating an example of a two-dimensional electron gas layer forming step of the method for manufacturing a wiring structure according to the first embodiment. FIG. 4A shows a state in which an n-doped InAlAs layer 2, an undoped InAlAs layer 15, and an InGaAs layer 25 are formed on the InP substrate 1. The undoped InAlAs layer 15 corresponds to the first material layer, and the InGaAs layer 25 corresponds to the second material layer. Further, the undoped InAlAs layer 15 and the InGaAs layer 25 constitute a stacked body 35. In addition, a two-dimensional electron gas layer 45 that is a conductive region having an interface charge is formed at the junction interface between the undoped InAlAs layer 15 that is the first material layer and the InGaAs layer 25 that is the second material layer. ing.

  In the two-dimensional electron gas layer forming step of the manufacturing method of the wiring structure according to the first embodiment, the n-doped InAlAs layer 2, the undoped InAlAs layer 15, and the like on the InP substrate 1 by molecular beam epitaxy (MBE). By forming the InGaAs layer 25, a two-dimensional electron gas layer 45 is formed at the junction interface between the undoped InAlAs layer 15 and the InGaAs layer 25. The layer thickness may be, for example, 3 [nm] for the n-doped InAlAs layer 2, 15 [nm] for the undoped InAlAs layer 15 and 10 [nm] for the InGaAs layer 25.

  Thus, in the two-dimensional electron gas layer forming step, the two-dimensional electron gas layer 45 is formed on the entire bonding interface of the stacked body 35 by laminating the first material layer and the second material layer of different materials. Form.

  FIG. 4B is a diagram illustrating an example of a mask forming process of the method for manufacturing the wiring structure according to the first embodiment. In the mask formation step, a mask 70 is formed on the surface of the stacked body 35, that is, on the surface of the second stacked body, such as InGaAs 25, according to the wiring shape, and the mask 70 is patterned. In addition, the mask 70 is comprised using a heat insulating material, for example, is comprised with heat insulating materials, such as a polyimide. Further, the mask 70 is formed so as to cover a portion to be left as a wiring. For example, the mask 70 may be formed with a thickness of about 200 nm and a width of about 200 nm.

  FIG. 4C is a diagram illustrating an example of a light element implantation step in the method for manufacturing a wiring structure according to the first embodiment. In the light element implantation step, the light element is implanted in a state where the mask 70 is patterned on the surface of the substrate having the stacked body 35 on the surface. Due to the light element implantation, a crystal defect occurs in a region of the stacked body 35 where the mask 70 does not exist. Thereby, in the heat processing performed next, the part in which a crystal defect exists becomes easy to be alloyed. Note that at the time of light element implantation, the stacked body 35 is not yet alloyed. The light element implantation step plays a role of promoting alloying by subsequent heat treatment. Here, alloying refers to an energy band structure in which the stacked body 35 has a quantum well in which a conductive two-dimensional electron gas layer 45 is easily formed at the junction interface, and does not have such a quantum well. It means that the two-dimensional electron gas layer 45 is changed to a non-conductive region having no conductivity, that is, is insulated.

Further, the light element to be implanted in the light element implantation step is, for example, He ⁺ , He ²⁺ , H ^+, etc., and may be implanted by, for example, an accelerator.

  The light element implantation step is not an essential step in the method for manufacturing the wiring structure according to the present embodiment, and may be performed as necessary.

  FIG. 4D is a diagram illustrating an example of a heating process of the manufacturing method of the wiring structure according to the first embodiment. In the heating step, heat treatment is performed from the entire upper surface of the stacked body 35 on which the mask 70 is formed, and heat is supplied to the stacked body 35 including the two-dimensional electron gas layer 45. The heat treatment may be performed, for example, by irradiating the entire upper surface of the laminated body 35 with a laser or the like and performing the heat treatment at 400 ° C. for about 5 minutes, or by other means using a heater or the like. It may be broken. Due to the heat treatment, the stacked body 35 including the two-dimensional electron gas layer 45 is alloyed, and no charge is accumulated at the interface between the InAlAs layer 15 and the InGaAs layer 25 in a region other than the region below the mask 70 of the heat insulating material. This is because when the two-dimensional electron gas layer 45 is formed, a quantum well in which electrons are likely to accumulate is formed in the energy band structure at the interface between the stacked body 35 of the InAlAs layer 15 and the InGaAs layer 25. This is probably because the InAlAs layer 15 and the InGaAs layer 25 react with each other by the heat treatment, and the quantum well portion disappears. By the heat treatment, a non-conductive region 55 is formed in a region other than the portion covered with the mask 70.

  Thus, in the heating process, since the non-conductive region 55 is formed using the mask 70, the wiring structure can be formed with high accuracy. The wiring width that can be formed can be smaller than the mask pattern width 200 [nm]. That is, by increasing the heating time, the non-conductive region 55 can be enlarged, so that the wiring width can be made smaller than the mask width. For example, a wiring having a width of 10 nm can be formed. Is possible.

  In addition, since the selective heating of the stacked body 35 including the two-dimensional electron gas layer 45 is performed in the steps illustrated in FIGS. 4B to 4D, these series of steps may be referred to as a selective heating step. In the selective heating step, the light element implantation step may be provided as necessary as described in FIG. 4C.

  In the first embodiment, the selective heating process has been described with reference to an example using the mask 70. However, if the stacked body 35 including the two-dimensional electron gas layer 45 can be selectively heated, the other heating process is performed. It may be by a method. For example, in the case where selective heating is possible without providing the mask 70 with a highly directional heating means, it is possible to omit the mask formation step and perform only the heating step. In addition, since the InAlAs layer 15 as the first material layer and the InGaAs layer 25 as the second material layer do not have conductivity as they are, for example, not from the surface of the stacked body 35 but from the side surface. If there is a method capable of heating and heating only the two-dimensional electron gas layer 45, the wiring structure may be formed by alloying only the two-dimensional electron gas layer 45 by such a method. In principle, since only the two-dimensional electron gas layer 45 is a conductive region, if only the two-dimensional electron gas layer 45 can be heated and insulated without heating all of the laminate 35, the wiring structure Formation is possible.

  FIG. 4E is a diagram illustrating an example of a mask removal process of the method for manufacturing a wiring structure according to the first embodiment. In the mask removal step, the mask 70 is removed from the surface of the stacked body 35 after the heating step. The removal of the mask 70 may be performed by various methods, but may be performed by etching, for example.

  FIG. 4F is a diagram illustrating an example of the protective film forming step of the method for manufacturing the wiring structure according to the first embodiment. In the protective film forming step, the protective film 65 is formed on the surface of the stacked body 35, that is, the surface of the InGaAs layer 25 that is the second material layer. The InAs layer including the InGaAs layer 25 used in this example generates and / or accumulates charges on the surface when it comes into contact with the atmosphere, which may cause leakage between wirings. Therefore, when the surface material of the stacked body 35 is a material that generates charge or accumulates when exposed, it is preferable to form a protective film 65 on the surface to suppress leakage current between wirings. In this step, the protective film 65 is formed.

  In addition, you may make it provide a protective film formation process as needed according to the property of the surface material of the laminated body 35. FIG.

  In the wiring structure manufacturing method according to the first embodiment, an example in which a single-phase wiring structure is manufactured has been described. However, a multilayer structure having two or more layers may be used. As illustrated in FIG. 4, various laminated structures can be adopted.

  Specifically, in order to manufacture the wiring structure shown in FIG. 2A, after the mask removing step shown in FIG. 4E, the laminate 35 or the laminate 35 is further formed on the surface of the laminate 35. By forming different laminates and repeating the two-dimensional electron gas layer forming step of FIG. 4A, the selective heating step of FIGS. 4B to 4D, and the mask removing step of FIG. 4E, a multilayered wiring structure can be manufactured. it can. If the protective film 65 needs to be formed after the multilayer wiring structure is formed, the protective film forming step shown in FIG. 4F may be performed last. Thereby, a multilayer wiring structure can also be easily manufactured.

  A manufacturing method for manufacturing the wiring structure shown in FIG. 2B will be described with reference to FIG.

  FIG. 5 is a diagram showing an example of a two-dimensional electron gas layer forming process for manufacturing the multilayer wiring structure shown in FIG. As shown in FIG. 5, in the two-dimensional electron gas layer forming step, a third material layer 13a is further stacked on the stacked body 35 to form a stacked body 33a. Then, the two-dimensional electron gas layer 43a is formed at the bonding interface between the InGaAs layer 25 and the third material layer 13a on the surface of the stacked body 35.

  Thereafter, the selective heating step shown in FIGS. 4B to 4D, the mask removal step shown in FIG. 4E, and the protective film formation step shown in FIG. A wiring structure having wiring can be manufactured. That is, by forming the mask 70 on the surface of the stacked body 33a in FIG. 5, that is, on the third material layer 13a, and subsequently performing the steps shown in FIGS. 4B to 4E, wiring of the stacked body 33 is unnecessary. The portions can be alloyed together to form multi-layered conductive regions 45 and 43a and a non-conductive region 55.

  Similarly, in the two-dimensional electron gas layer forming step, a multilayer structure having three or more layers can be manufactured by forming a laminate having a larger number of layers.

  In the method for manufacturing a wiring structure according to the first embodiment, a general method for manufacturing a wiring regardless of the use has been described. However, a semiconductor material is used for the first material layer 15 and / or the second material layer 25. If the wiring structure of the semiconductor device is manufactured, the manufacturing method of the wiring structure according to the first embodiment can be used for the manufacturing method of the semiconductor device.

  According to the manufacturing method of the wiring structure according to the first embodiment, the desired structure can be obtained with high accuracy by a simple manufacturing process that is substantially composed of two processes of a two-dimensional electron gas layer forming process and a selective heating process. A wiring structure can be easily formed.

  6A to 6E are views showing a series of steps in the method for manufacturing a wiring structure according to the second embodiment of the present invention. In the method for manufacturing a wiring structure according to the second embodiment, a method for manufacturing the wiring structure according to FIGS. 3A and 3B will be described. Therefore, the same reference numerals are assigned to the same components as those in FIG. In the wiring structure manufacturing method according to the second embodiment, an example in which an AlSb layer is used for the first material layer 14 and an InAs layer is used for the second material layer 24 will be described. As other materials, a combination of InAlAs and InGaAs, GaAs and AlGaAs, GaN and AlGaN, or the like may be used, and various materials can be applied as long as the materials are combinations of materials in which charge accumulation occurs at the junction interface. It is the same. In addition, as an example, a manufacturing method of a wiring structure including a single wiring layer (conductive region) is shown, but a wiring structure including a multilayer wiring layer may be used as in the first embodiment.

  FIG. 6A is a diagram illustrating an example of a two-dimensional electron gas layer forming step of the method for manufacturing a wiring structure according to the second embodiment. In the two-dimensional electron gas layer forming step, the first material layer 14 is formed by forming InAs of the second material layer 24 on the AlSb of the first material layer 14 by molecular beam epitaxy, thereby forming the first material. A conductive two-dimensional electron gas layer 44 is formed at the bonding interface between the layer 14 and the second material layer 24. The layer thickness may be, for example, about 10 [nm] for AlSb of the first material layer 14 and about 10 [nm] for InAs of the second material layer. In addition, another material such as an AlGaSb layer may be present as a supporting substrate under the first material layer 14. In the following FIGS. 6A to 6E, only the first material layer 14 and the second material layer 24 are described for simplification.

  FIG. 6B is a diagram illustrating an example of a mask forming process of the method for manufacturing a wiring structure according to the second embodiment. In the mask formation step, an etching mask 71 is formed on the surface of the second material layer 24, which is the surface of the stacked body 34, according to the wiring shape, and mask patterning is performed. For example, a resist may be used for the mask 71. The mask 71 may be formed with a thickness of about 200 nm and a width of about 200 nm, for example.

  FIG. 6C is a diagram illustrating an example of the etching process of the manufacturing method of the wiring structure according to the second embodiment. In the etching process, the second material layer 24 is completely etched to form a laminated structure of the laminated body 34 only at a portion below the mask 71. Note that by performing isotropic etching, the formable wiring width can be made smaller than the mask pattern width of 200 [nm]. That is, by extending the etching time, it is possible to remove the region below the mask 71 from the side and reduce the wiring width. For example, it is possible to form a wiring having a width of 10 [nm].

  FIG. 6D is a diagram illustrating an example of a mask removing process in the method for manufacturing a wiring structure according to the second embodiment. In the mask removing step, the mask 71 is removed, and a wiring structure in which the two-dimensional electron gas layer 44 that is a conductive region is formed is completed. As a result, the wiring structure shown in FIG. 2A is manufactured. The removal of the mask 71 may be performed by, for example, etching.

  FIG. 6E is a diagram illustrating an example of a protective film forming step in the method for manufacturing a wiring structure according to the second embodiment. In the protective film forming step, the protective film 60 is formed so as to cover the exposed surface of the first material layer 14, the surface of the second material layer 24, and the side surface of the two-dimensional electron gas layer 44. For example, since the InAs layer described in this embodiment generates and / or generates charges on the surface when exposed to the atmosphere, there is a risk of leakage between the wirings. Therefore, in the case where the surface material is a material having a property of generating or accumulating charges by exposure, a protective film 60 is formed on the surface to suppress leakage current between wirings. In addition, you may make it provide a protective film formation process as needed.

  According to the method for manufacturing a wiring structure according to the second embodiment, it is possible to easily manufacture a wiring structure in which space saving is achieved by etching.

  7A to 7E are diagrams illustrating an example of a series of steps of the method for manufacturing a wiring structure according to the third embodiment of the present invention. In the method for manufacturing a wiring structure according to the third embodiment, a wiring structure is formed on a semiconductor substrate, and a gate electrode of a MOS (Metal Oxide Semiconductor) transistor or a high electron mobility transistor (HEMT) is manufactured. A method for manufacturing the apparatus will be described.

  In the wiring structure manufacturing method according to the third embodiment, an example in which InAs and AlSb are used as materials for forming the gate electrode will be described. However, charges are accumulated at the junction interface when stacked. As long as it is a combination of materials, the combination of various kinds of different materials can be used as described above. For example, a combination of InAlAs and InGaAs, GaAs and AlGaAs, GaN and AlGaN, or the like may be used.

  FIG. 7A is a diagram illustrating an example of an ion implantation step in the method for manufacturing a wiring structure according to the third embodiment. In the ion implantation step, impurity ions are implanted into the region of the substrate 3 where the source region 4 and the drain region 5 are to be formed. The ion implantation may be performed by an ion implantation method in a state where a mask 72 is formed on the surface of a region of the substrate 3 where the source region 4 and the drain region 5 are not formed. As the substrate 3, semiconductor substrates made of various semiconductor materials can be applied. For example, InAlAs may be used. For the mask 72, for example, a resist may be used. The size of the mask 72 may be determined according to design specifications such as gate length and gate width. For example, the mask 72 has a thickness of 1 [μm] and a width (source-drain distance) of about 25 [μm]. There may be. Also, as the impurity to be implanted, appropriate ions may be selected depending on the application, but, for example, Si may be implanted.

  FIG. 7B is a diagram illustrating an example of a mask removal process and a diffusion process in the method for manufacturing a wiring structure according to the third embodiment. In the mask removal process, the mask 72 is removed by etching or the like. In the diffusion process, the substrate 3 is heated, and the implanted impurities in the source region 4 and the drain region 5 are thermally diffused.

  FIG. 7C is a diagram illustrating an example of the first material layer stacking process of the manufacturing method of the wiring structure according to the third embodiment. In the first material layer stacking step, the first material layer 16 is stacked on the entire surface of the substrate 3. As described above, for example, InAs may be used for the first material layer 16. The lamination of the first material layer 16 may be performed by various methods, but may be performed by, for example, a molecular beam epitaxy method.

  FIG. 7D is a diagram illustrating an example of a two-dimensional electron gas layer forming step of the method for manufacturing the wiring structure according to the third embodiment. In the two-dimensional electron gas layer forming step, the second material layer 26 is stacked on the entire surface of the first material layer 16 to form a stacked body 36, and the first material layer 16 and the second material are formed. A two-dimensional electron gas layer 46 filled with an interface charge is formed at the bonding interface with the layer 26. As a result, a two-dimensional wiring layer is formed. As described above, for example, AlSb may be used for the second material layer. By this step, an interface charge is generated at the interface between the InAs layer and the AlSb layer. The second material layer 26 may be stacked by various methods, for example, a molecular beam epitaxy method.

  FIG. 7E is a diagram illustrating an example of the etching process of the manufacturing method of the wiring structure according to the third embodiment. In the etching step, after a mask 73 is formed in a region where a gate electrode is to be formed on the surface of the second material layer 26, etching is performed from the entire upper surface of the second material layer 26. Etching is performed for the depth of the stacked body 36, whereby unnecessary portions of the second material layer 26 and the first material layer 16 are removed. For example, when the stacked body 36 has a thickness of 20 [nm], etching is performed by a depth of 20 [nm]. By the etching process, in the region other than the mask 73, the AlSb / InAs interface forming the two-dimensional electron gas layer 46 disappears, and the interface charge contained therein disappears. As a result, the gate electrode is formed in a desired shape.

  FIG. 7F is a diagram illustrating an example of a mask removal process of the method for manufacturing a wiring structure according to the third embodiment. In the mask removal process, the mask 73 is removed by etching or the like. As a result, a semiconductor device is completed in which the remaining two-dimensional electron gas layer 46 existing at the junction interface between the first material layer 16 and the second material layer 26 functions as a gate electrode.

  Since the gate electrode using the two-dimensional electron gas layer 46 can be formed to a thickness of 10 [nm] or less, a gate having a thickness of about 100 [nm] formed of a conventional metal or polysilicon is used. The thickness can be made much thinner than the electrodes. Thereby, the device (semiconductor device) manufactured can be reduced in size.

  FIG. 8 is a diagram showing an example of a wiring structure according to Example 4 of the present invention. FIG. 8A is an example of a cross-sectional view of the wiring structure according to the fourth embodiment, and FIG. 8B is an example of a perspective view of the wiring structure according to the fourth embodiment. In the wiring structure according to the fourth embodiment, an external electrode lead-out structure when a two-dimensional wiring is formed will be described.

  8A, the wiring structure according to Example 4 includes a first material layer 17, a second material layer 27, and an extraction electrode 80. A second material layer 27 is stacked on the first material layer 17 to form a stacked portion 37, and a two-dimensional electron gas layer 47 is formed at the bonding interface between the first material layer 17 and the second material layer 27. The formed point is the same as the wiring structure described so far. In the wiring structure according to the fourth embodiment, the stacked portion 37 is formed not on the entire surface of the first material layer 17 but on a part thereof, and the extraction electrode 80 is provided so as to straddle the end of the stacked portion 37. This is different from the wiring structure described so far. A part of the extraction electrode 80 is brought into contact with the two-dimensional electron gas layer 45 constituting the two-dimensional wiring, and part of the extraction electrode 80 is exposed. As a result, the two-dimensional electron gas layer 47 can be connected to an external electrode or wiring via the extraction electrode 80, and power can be supplied to the two-dimensional electron gas layer 47 from the outside.

  Note that the extraction electrode 80 may be formed of, for example, a metal thin film. The extraction electrode 80 can be made thin, and can be easily formed using metal deposition or the like.

  8B, the right extraction electrode 80 in FIG. 8A is shown as a perspective view. As shown in FIG. 8B, the second material layer 27 is formed on a part of the first material layer 17 using the first material layer 17 as a substrate, and the stacked portion 37 is alloyed. It includes a region that has become a non-conductive region 57 and a two-dimensional electron gas layer 47 that becomes a wiring in the conductive region. The two-dimensional electron gas layer 47 is formed at the bonding interface between the first material layer 17 and the second material layer 27. In addition, the extraction electrode 80 is formed in the boundary region of the stacked portion 37 on the surface of the first material layer 17 so that a part thereof is in contact with the two-dimensional electron gas layer 47 and a part thereof is exposed. With this configuration, the exposed portion of the extraction electrode 80 can be used for connection to an external electrode or wiring.

  As described above, the wiring structure according to the fourth embodiment has a two-dimensional wiring external electrode extraction structure by the two-dimensional electron gas layer 47, and the power supply to the two-dimensional electron gas layer 47 is easy. Yes. Conventionally, the external electrode lead-out structure is configured with a complicated configuration using ohmic diffusion, but according to the wiring structure according to the fourth embodiment, the external electrode lead-out structure can be configured with a simple configuration.

  Various materials can be used as the material used for the extraction electrode 80. For example, Al may be used. Further, the thickness of the extraction electrode 80 may be variously varied depending on the application, but may be about 100 [nm], for example.

  The extraction electrode 80 is formed by previously forming a metal thin film on the surface of the first material layer 17 by metal vapor deposition or the like, and then laminating the second material layer 27 on the first material layer 17. If the laminated portion 37 is formed, the wiring structure according to the fourth embodiment can be manufactured.

  FIG. 9 is a diagram showing an example of a cross-sectional configuration of the wiring structure according to the fifth embodiment of the present invention. Similar to the wiring structure according to the fourth embodiment, the wiring structure according to the fifth embodiment has an external electrode extraction structure, but the configuration of the external electrode extraction structure is different.

  In FIG. 9, the wiring structure according to Example 5 includes a first material layer 18, a second material layer 28, a two-dimensional electron gas layer 48, a nonconductive region 56, an extraction electrode 81, and a contact. And a hole 81. The first material layer 18 and the second material layer 28 are laminated to form a laminated portion 38, and a two-dimensional electron gas layer 48 is formed at the bonding interface. The point which has the part which contacts the layer 48, and the part which exists in the exterior of the laminated body 38 is the same as that of the wiring structure which concerns on Example 4. FIG. The wiring structure according to the fifth embodiment is different from the wiring structure according to the fourth embodiment in that a non-conductive region 56 is formed outside the stacked portion 38 and the extraction electrode 81 is not exposed. The wiring structure according to the fifth embodiment has a contact hole 82 connected to the extraction electrode 81, and is configured to be connectable to an external electrode or wiring through a conductor such as metal filled in the contact hole 82. This is different from the wiring structure according to the fourth embodiment.

  As described above, the extraction electrode 81 may not necessarily be exposed if there is a portion existing outside the stacked portion 38. As shown in FIG. 9, if a wiring means such as a contact hole 82 connected to the extraction electrode 81 is provided, it is possible to connect to an external electrode or wiring through such a wiring means.

  In the wiring structure according to Example 5, the metal thin film to be the extraction electrode 81 is formed on the first material layer 18 and then the second material layer 28 is laminated, and the side is selectively heated to form an alloy. The non-conductive region 56 may be used. Since the extraction electrode 81 is composed of a metal thin film, even if heat treatment is performed, the extraction electrode 81 does not become an alloy but exists as a metal thin film as it is. Thereafter, a contact hole 82 is formed above the extraction electrode 81 by selective etching, and the contact hole 82 is filled with a conductor by plating, vapor deposition, or the like, whereby the wiring structure according to the fifth embodiment can be manufactured.

  According to the wiring structure according to the fifth embodiment, it is possible to easily make an electrical connection to the outside using the contact hole 82 while adopting an external electrode extraction structure in which the surface is not exposed.

  FIG. 10 is a diagram illustrating an example of a cross-sectional configuration of a wiring structure according to the sixth embodiment of the present invention. Similar to the wiring structures according to the fourth and fifth embodiments, the wiring structure according to the sixth embodiment has an external electrode extraction structure, but the extraction electrode 83 is not a metal thin film but a metal piece. This is different from the wiring structures according to Example 4 and Example 5.

  In FIG. 10, the wiring structure according to Example 6 includes the first material layer 19, the second material layer 29, the two-dimensional electron gas layer 48, and the extraction electrode 83. A stacked portion 39 is formed by stacking the first material layer 19 and the second material layer 29, and a two-dimensional electron gas layer 48 is formed at the bonding interface between the first material layer 19 and the second material layer 29. The extraction electrode 83 is partly in contact with the two-dimensional electron gas layer 48 and partly outside the stacked portion 29, similar to the wiring structure according to the fourth and fifth embodiments. is there. The wiring structure according to Example 6 is different from the wiring structures according to Example 4 and Example 5 in that the exposed portions of the extraction electrode 83 are exposed on both surfaces and are not supported by the first material layer 19. Is different.

  Thus, both the front and back surfaces of the exposed portion of the extraction electrode 83 may be exposed. However, in this case, since the extraction electrode 83 cannot be configured as a metal thin film, it is preferably a metal piece that can maintain its shape without support. Depending on the application, the wiring structure may be configured in this way. Connection to the two-dimensional electron gas layer 48 can be performed more directly.

  FIG. 11 is a diagram showing an example of a cross-sectional configuration of the wiring structure according to the seventh embodiment of the present invention. The wiring structure according to the seventh embodiment is the same as the wiring structure according to the fourth embodiment in the configuration of the first layer and the second layer, but the third material layer 13b is further formed above the second material layer 27. Is different from the wiring structure according to the fourth embodiment in that are stacked. In FIG. 11, the same components as those in the wiring structure according to the fourth embodiment are denoted by the same reference numerals, and the description thereof is omitted.

  In FIG. 11, in the wiring structure according to Example 7, the second material layer 27 is laminated on the first wiring layer 17, and the two-dimensional electron gas layer 47 is formed at the bonding interface. The wiring structure according to the fourth embodiment is the same as the wiring structure according to the fourth embodiment in that the extraction electrode 80 that contacts the layer 47 is provided. In the wiring structure according to the ninth embodiment, the third material layer 13b is stacked on the second material layer 27, and the stacked portion 33b is configured as a whole. A second two-dimensional electron gas layer 43b is formed at the bonding interface between the second material layer 27 and the third material layer 13b, and a part of the second two-dimensional electron gas layer 43b is in contact with the second two-dimensional electron gas layer 43b. In addition, a second extraction electrode 84 that is partially exposed is provided.

  Thus, the external electrode lead-out structure can be applied to a multilayer wiring structure. Also in this case, as in the fifth embodiment, the surface of the extraction electrodes 80 and 84 may not be exposed, and a connection means such as a contact hole 82 may be used for connection to the outside. As in the sixth embodiment, a configuration in which both surfaces of the extraction electrodes 80 and 84 are exposed may be adopted.

  In the seventh embodiment, the example of the wiring structure including the two two-dimensional electron gas layers 80 and 84 has been described. However, a wiring structure including a larger number of wiring layers may be used.

  According to the wiring structure according to the seventh embodiment, even in a multilayer wiring structure, a simple extraction electrode can be provided to increase the degree of freedom in wiring design.

  The preferred embodiments of the present invention have been described in detail above. However, the present invention is not limited to the above-described embodiments, and various modifications and substitutions can be made to the above-described embodiments without departing from the scope of the present invention. Can be added.

  The present invention can be used for a wiring structure that requires various wirings. For example, the present invention can be used for a wiring structure of a semiconductor device.

1, 3 substrate 4 source region 5 drain region 10, 11, 12, 14-19 first material layer 13, 13a, 13b third material layer 20-29 second material layer 30-33, 33a, 33b, 34, 37, 38, 39 Laminating part 35, 36 Laminate 40-43, 43a, 43b, 44-48 Two-dimensional electron gas layer 50-56 Non-conductive region 60, 65 Protective film 70, 71, 72 Mask 80, 81, 83, 84 Extraction electrode 82 Contact hole

Claims (10)

A two-dimensional electron gas layer forming step of forming a laminate by stacking different materials that generate charge accumulation at the junction interface, and forming a two-dimensional electron gas layer at the junction interface of the laminate;
A selective heating step of selectively heating the two-dimensional electron gas layer to selectively form a non-conductive region in the two-dimensional electron gas layer and forming a predetermined wiring structure with the non-heated conductive region A method for manufacturing a wiring structure, comprising: The selective heating step includes a mask forming step of forming a heat-insulating mask on the surface of the stacked body above the position where the conductive region is formed;
The method of manufacturing a wiring structure according to claim 1, further comprising: a heating step of supplying heat from above the mask to perform heat treatment.   The selective heating step further includes a light element injection step of injecting a light element into the surface of the stacked body between the mask formation step and the heating step, and generating a crystal defect in a region where the mask does not exist. The method of manufacturing a wiring structure according to claim 2, comprising:   4. The method according to claim 1, further comprising a protective film forming step of forming a protective film on the surface of the stacked body above the conductive region after the selective heating step. 5. The manufacturing method of the wiring structure as described.   A method for manufacturing a wiring structure, comprising: repeating the method for manufacturing a wiring structure according to any one of claims 1 to 3 to form a multilayer wiring including a plurality of the conductive regions. A laminated portion made of a different material having a conductive two-dimensional electron gas layer at the bonding interface;
A wiring structure comprising: a portion in contact with the two-dimensional electron gas layer; and a take-out electrode having a portion existing outside the stacked portion. The laminated portion is configured by partially laminating a second material layer on the first material layer,
The wiring structure according to claim 6, wherein the extraction electrode is a metal thin film formed on the first material layer.   The wiring structure according to claim 6 or 7, wherein a portion of the extraction electrode existing outside the stacked portion is exposed. On the upper layer of the extraction electrode, a non-conductive region is formed,
The wiring structure according to claim 7, wherein a contact hole electrically connected to the extraction electrode is formed in the non-conductive region.   The wiring structure according to claim 7 or 9, wherein the stacked portion has a multilayer structure in which the first material layers and the second material layers are alternately stacked.

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