JP2011118751A - Microcomputer and control method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a microcomputer which quickly sets the optimal frequency, in particular, when being restarted after a pause, and a control method thereof. <P>SOLUTION: The microcomputer 1 includes: an operation part 18 to which the supply of a clock signal is stopped by a request from the outside or the inside; a clock signal generation part 16 which changes a frequency of the clock signal supplied from the outside to generate one or more clock signals different in frequency; a voltage detection part which detects an operation voltage of the microcomputer regardless of an operation state of the operation part; a selection part 17 which selects either of clock signals generated by the clock signal generation part 16 and the clock signal supplied from the outside and supplies the selected clock signal to the operation part 18; and a selection signal generation part 14 which generates a selection signal 34 by which the selection part 17 selects a clock signal on the basis of the detection result of the voltage detection part regardless of the operation state of the operation part 18. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a microcomputer and a control method thereof, and more particularly to a microcomputer that sets a frequency with respect to an operating voltage and a control method thereof.

  Conventionally, in a system where batteries are used for power supply, a microcomputer that has a range of operating voltage in consideration of a decrease in power supply voltage, in other words, an operable frequency band corresponding to the operating voltage (hereinafter referred to as a microcomputer) is set. Is used).

  Such a microcomputer measures the operating voltage supplied to the microcomputer, and according to the measurement result, if the operating voltage decreases, the operating frequency band is set so that the upper limit of the operating frequency of the microcomputer is lower (the microcomputer operation is slower). select.

  In addition, in such a system where a battery is used for power supply, when the operation of the microcomputer is not necessary (when the key input is not detected for a long time by the remote controller, etc.), the microcomputer is stopped and the oscillator for operating the microcomputer is also stopped. By doing so, current consumption is reduced.

  The system power supply voltage continues to decrease and the operating voltage supplied to the microcomputer continues to decrease even while the microcomputer is inactive, but the operating voltage cannot be measured while the microcomputer is inactive. Therefore, the microcomputer sets an operating frequency when restarting when the microcomputer is stopped, and operates at the operating frequency set before stopping when the microcomputer is restarted. Here, in order to avoid that the operating voltage when the microcomputer is restarted falls below the corresponding operating voltage of the operating frequency set when the microcomputer is stopped, the operating frequency when restarting the microcomputer is set to Set to the slowest operating frequency and then pause. Therefore, when the microcomputer is restarted, operation starts at the slowest operating frequency of the microcomputer regardless of the operating voltage.

  However, if the operating frequency at the time of reactivation is the lowest as in the prior art, the microcomputer will be reactivated at an operating frequency lower than necessary if the drop in operating voltage during the pause of the microcomputer is fine. In addition, it is necessary to measure the operating voltage and set an appropriate operating frequency using a microcomputer operating in a low operating frequency band after the microcomputer is restarted.

  FIG. 3 is a table showing the operating frequency band of the microcomputer described in Non-Patent Document 1 and the corresponding operating voltage. The microcomputer shown as an example in Table 100 supports an operating voltage range of 1.8V to 5.5V. Operation is possible at a frequency of 20 MHz from 5.5 V to 4.0 V, 10 MHz from 4.0 V to 2.7 V, and 5 MHz from 1.8 V to 2.7 V.

  FIG. 4 is a diagram showing a clock signal generation circuit 102 according to the prior art. The clock signal generation circuit 102 is supplied with a clock signal having a frequency fxp from the high-speed system clock oscillator 101. The clock signal generation circuit 102 uses a prescaler (frequency divider) 103 and a selector 104 to change the supplied clock signal to a CPU clock frequency (frequency fcpu) shown in Table 100 based on the magnitude of the operating voltage. .

  FIG. 5 is a diagram showing a microcomputer 105 according to the prior art. During operation, the microcomputer 105 uses the AD converter 106 to convert the voltage of the power supply 107 into a digital numerical value and measure it.

  FIG. 6 is a diagram showing details of the microcomputer 108 according to the conventional technique. The microcomputer 108 includes a CPU 113, a pause / operation control unit 110 that controls supply and stop of supply of the clock signal 122 supplied to the CPU 113, a prescaler 111 that changes the frequency of the clock signal 122, and a frequency change by the prescaler 111. The selector 112 that selects and outputs one of the plurality of clock signals 126 or the clock signal 122 supplied from the outside, and the selector control register 109 that controls the selector 112 are provided.

  The CPU 113 measures the voltage of the power supply 121 of the microcomputer 108 using an AD converter (not shown) and outputs the voltage to the selector control register 109.

  The selector control register 109 selects the clock signal 127 output from the selector 112 based on the measurement result of the power supply 121.

  The suspension / operation control unit 110 controls the supply and suspension of the clock signal 122 to the CPU 108 based on the suspension request signal 125, the operation request signal 124, and the request signal 123 input from the outside.

  FIG. 7 is a flowchart showing an operation for determining a change in the frequency of the clock signal according to the prior art. First, analog-digital conversion of the power supply voltage is performed by an AD converter (not shown) in the microcomputer 108 of FIG. 6 (step S201). Wait until the analog-digital conversion is completed (step S202). Next, the CPU 113 measures the power supply voltage 121 (step S203), and outputs the result to the selector control register 109 (step S204).

  As described above, in the conventional microcomputer 108, when determining the operating frequency, it is necessary to use an AD converter and wait until the analog-digital conversion of the operating voltage is completed.

  Next, a problem that occurs when the conventional microcomputer 108 pauses and resumes operation will be described. In the conventional microcomputer 108, the CPU 113 monitors the operating voltage for adjusting the operating frequency. Therefore, the operating voltage can be monitored and the operating frequency can be adjusted only while the microcomputer 108 is operating, and the operating voltage cannot be monitored while the microcomputer 108 is inactive. Therefore, when the microcomputer 108 is suspended, it is necessary to set the operating frequency at the time of re-operation to 5 MHz, which is the slowest operating frequency, in consideration of a decrease in the operating voltage.

  FIG. 8 is a flowchart showing the flow from the pause to the restart of the operation of the conventional microcomputer 108. First, it is assumed that the user performs a process related to the operation of the system (step S301), and the microcomputer 108 is suspended (step S301: Yes). The microcomputer 108 sets the lowest 5 MHz as the frequency of the clock signal 127 when the operation is resumed next (step S303) immediately before the suspension (step S304). The supply of the clock signal 122 is suspended and the microcomputer 108 is deactivated (step S305).

  When the predetermined time has elapsed and the microcomputer 108 is restarted (step S306: Yes), the clock signal 122 is supplied to the microcomputer 108 (step S308).

  The frequency of the clock signal 127 supplied to the CPU 113 when the microcomputer 108 is restarted is 5 MHz. The reactivated microcomputer 108 measures the operating voltage 121 (step S308), and resets the frequency of the clock signal 127 supplied to the microcomputer 108 based on the measured operating voltage 121 (step S309).

  Incidentally, a microcomputer having a power fail circuit for detecting an operating voltage outside the microcomputer is described in Patent Document 1. The microcomputer disclosed in Patent Document 1 includes a clock signal output circuit, a clock generation circuit that receives the output of the clock signal output circuit, generates a clock having a frequency lower than the operation clock of the microcomputer, and an external power fail detection circuit And an interrupt signal output circuit for outputting an interrupt signal for changing the clock signal supplied to the microcomputer to a clock signal having a frequency lower than that of the operation clock. In the microcomputer described in Patent Document 1, when the microcomputer external power fail circuit detects a decrease in operating voltage, an interrupt signal output circuit in the microcomputer outputs an interrupt signal based on the detection result, and is supplied to the microcomputer. It controls to lower the frequency of the clock signal. As a result, it is possible to prevent the microcomputer from being stopped when the operating voltage rapidly decreases in the event of an abnormality.

JP-A-3-130812

NEC Electronics, “User's Manual 78K0 / KE2 8-bit single-chip microcontroller”, December 2006, P632

  The problems of the prior art will be described below. Here, let us consider a case where the operating voltage does not drop to the voltage threshold corresponding to the lowest operating frequency band of the microcomputer 108 between the time when the microcomputer 108 shown in FIG. FIG. 9 is a graph showing a change in operating voltage applied to a conventional microcomputer, an operating state of the microcomputer, whether or not the operating voltage can be detected, and an operating frequency of the microcomputer. FIG. 9A shows a case where the operating voltage drops to 2.7 V or less during the pause of the microcomputer 108 (between timings t1 and t2). FIG. 9B shows a case where the operating voltage has not dropped to 2.7 V or less during the pause of the microcomputer 108. The microcomputer 108 performs a normal operation from the timing t0 to the timing t2, and the microcomputer 108 is suspended from the timing t1 to the timing t2. The operation of the microcomputer 108 resumes at timing t2, and the microcomputer 108 measures the operating voltage from timing t2 to t3 to determine the operating frequency corresponding to the operating voltage.

  As shown in FIG. 9A, when the operating voltage drops to 2.7 V or less while the microcomputer 108 is at rest, the frequency corresponding to the operating voltage immediately after the operation of the microcomputer 108 resumes at the timing t2. A clock signal 127 can be supplied to the CPU 113. However, as shown in FIG. 9B, when the operating voltage does not drop to 2.7 V or less during the pause of the microcomputer 108, that is, when the pause period is short, the timing t2 in FIG. When the operation is resumed, the operable frequency of the microcomputer 108 is 10 MHz. However, the frequency of the clock signal supplied when the operation of the microcomputer 108 is resumed in step S303 in FIG. 8 is set to 5 MHz. The conventional microcomputer 108 does not operate at the originally optimal frequency of 10 MHz, but operates at the minimum operating frequency of 5 MHz from the timing t2 to the timing t3.

  As described above, in the conventional microcomputer, the operating voltage cannot be measured while the microcomputer is paused. Therefore, the operating frequency must be set to the minimum operating frequency before the pause. Therefore, when the conventional microcomputer is restarted from the sleep state, it restarts at the lowest operating frequency even when the operating voltage is high. As a result, the processing performance of the microcomputer decreases immediately after the microcomputer is restarted. In addition, even if the voltage when the microcomputer is restarted is suitable for the minimum frequency and it is not necessary to change the operating frequency, it is necessary to measure the operating voltage immediately after restarting and reset the operating frequency. . As a result, between the time when the microcomputer is restarted and the time when the operating frequency is reset, the processing that the user originally intended to perform with the microcomputer is delayed, and detection of input signals such as key inputs is delayed and missed. There is a problem.

  Further, since the microcomputer described in Patent Document 1 has a power fail circuit outside, it is possible to measure the operating voltage before the operation of the microcomputer resumes. However, in order to use the detection result of the operating voltage of the external power fail circuit to change the frequency of the clock signal, the frequency of the clock signal corresponding to the operating voltage is determined using the interrupt signal output circuit inside the microcomputer. There is a need. Therefore, in order to determine the frequency of the clock signal, the microcomputer waits for the operation of the microcomputer to stabilize. As described above, there is a problem that the operation of the frequency setting microcomputer is delayed and the response to the user input is delayed.

  The microcomputer according to the present invention changes the frequency of the clock signal supplied from the calculation unit and the clock signal supplied from the outside in response to a request from the outside or the inside, and adds one or more clock signals having different frequencies. A clock signal generator to be generated, a voltage detector for detecting the operating voltage of the microcomputer regardless of the operating state of the arithmetic unit, a clock signal generated by the clock signal generator or a clock signal supplied from the outside A selection unit that selects one of them and supplies it to the calculation unit, and a selection signal generation that generates a selection signal for the selection unit to select a clock signal based on the detection result of the voltage detection unit regardless of the operation state of the calculation unit A clock signal is selected by a selection signal in response to a request from outside or inside, regardless of the operating state of the arithmetic unit, It is supplied to the calculation unit. Thereby, even when the clock signal is not supplied to the microcomputer, the operating voltage of the microcomputer can be detected, and a clock signal having a frequency corresponding to the operating voltage can be supplied to the arithmetic unit immediately after the microcomputer is restarted.

  According to the present invention, it is possible to supply a microcomputer that can start operation with an optimum clock frequency setting for the operating voltage supplied to the microcomputer immediately after the microcomputer operation is resumed.

1 is a diagram illustrating a configuration of a microcomputer according to a first embodiment; 3 is a flowchart showing the operation of the microcomputer according to the first exemplary embodiment; It is a table | surface which shows the operating frequency band of the microcomputer concerning a prior art, and the operating voltage corresponding to it. It is a figure which shows the clock signal generation circuit 102 concerning a prior art. It is a figure which shows the microcomputer 105 concerning a prior art. It is a figure which shows the detail of the microcomputer 108 concerning a prior art. It is a flowchart which shows the operation | movement which determines the change of the frequency of the clock signal concerning a prior art. It is a flowchart which shows the flow from the rest of operation | movement of the conventional microcomputer 108 to restart. It is a graph which shows the change of the operating voltage concerning the conventional microcomputer, the operating state of a microcomputer, whether the operating voltage is detectable, and the operating frequency of the microcomputer.

Embodiment 1
Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a diagram showing a configuration of a microcomputer 1 according to the present invention. The microcomputer 1 includes a CPU 18 as a calculation unit, a prescaler 16 as a clock signal generation unit, comparators 10 and 11 and a comparator data buffer 13 as voltage detection units, a selector 17 as a selection unit, and a selection signal generation unit. Selector control register 14, suspension / operation control unit 15, and latch circuit 12.

  The CPU 18 stops supplying the clock signal 32 in response to an external request signal 24 or a pause request signal 26 from the CPU 18.

  The prescaler 16 changes the frequency of the clock signal 27 supplied from the outside, and generates clock signals 28 and 29 having different frequencies. The comparators 10 and 11 detect the operating voltage of the microcomputer 1 regardless of the operating state of the CPU 18.

  The comparator data buffer 13 outputs the detection result of the operating voltage to the selector control register 14 regardless of the operating state of the CPU 18.

  The selector 17 selects one of the clock signals 28 and 29 generated by the prescaler 16 or the clock signal 27 supplied from the outside, and supplies it to the CPU 18.

  The selector control register 14 generates and holds a selection signal 34 for selecting the clock signal 32 that the selector 17 supplies to the CPU 18 based on the detection results of the comparators 10 and 11 regardless of the operating state of the microcomputer 1. The latch circuit 12 inputs the latch signal 33 to the selector control register 14. When receiving the latch signal 33 from the latch circuit 12, the selector control register 14 outputs the held selection signal 34 to the selector 17. The selector 17 supplies a clock signal 32 to the CPU 18 based on the selection signal 34.

  When the supply of the clock signal 32 to the CPU 18 is stopped, the latch circuit 12 outputs a latch signal 33 to the selector control register 14 according to the request signal 24 from the outside or the operation request signal 25 output from the CPU 18.

  When the clock signal 32 is supplied to the CPU 18, the latch circuit 12 outputs a latch signal 33 to the selector control register 14 in response to the frequency change signal 31 from the CPU 18.

  Thereby, when the supply of the clock signal 32 to the CPU 18 is stopped, the microcomputer 1 can select the clock signal 32 by the request signal 24 from the outside or the operation request signal 25 from the CPU 18, and the clock signal is sent to the CPU 18. When 32 is supplied, the clock signal 32 can be selected by the frequency change signal 31 from the CPU 18.

  Here, the microcomputer 1 according to the present embodiment will be described in detail. The microcomputer 1 has an operating frequency band based on the operating voltage. In this embodiment, operating frequencies of 5 MHz, 10 MHz, and 20 MHz are made to correspond to three operating voltage bands of operating voltages of 1.8 V to 2.7 V, 2.7 V to 4 V, 4 V to 5.5 V. And Further, the microcomputer 1 controls the suspension / operation control unit 15 by the request signal 24 from the outside or the suspension request signal 26 from the CPU 18, and stops the operation by stopping the supply of the clock signal 32 supplied to the CPU 18. To do.

  The operating power supply 21 of the microcomputer 1 is connected to the CPU 18 and the comparators 10 and 11 that are comparators.

  The comparators 10 and 11 output 0 when detecting that the voltage is equal to or higher than a predetermined voltage. The comparators 10 and 11 detect different voltages.

  The comparators 10 and 11 detect the operating voltage regardless of the supply state of the clock signal 27 to the inside of the microcomputer 1, in other words, during the operation of the CPU 18 and during the suspension of the CPU 18. Update.

  The comparator 10 detects the operating voltage, and outputs the detection signal 22Lo (0) to the comparator data buffer 13 when it is 4V or more, and the detection signal 22Hi (1) when it is 4V or less.

  The comparator 11 detects the operating voltage, and outputs the detection signal 23Lo (0) to the comparator data buffer 13 when the detection signal 23Lo (0) is 2.7V or less when the operation voltage is 2.7V or more. .

  The comparator data buffer 13 outputs the detection signals 22 and 23 of the comparators 10 and 11 to the selector control register 14 as detection results. The comparator data buffer 13 outputs a detection result to the selector control register 14 every time the detection signals 22 and 23 output from the comparators 10 and 11 change.

  The selector control register 14 receives operating voltage information from the comparator data buffer 13. The selector control register 14 has an operating voltage of 4V to 5.5V when the detection result output from the comparator data buffer 13 is (00), and 2.7V to 4V when (10). In this case, assuming that the voltage is 1.8V to 2.7V, the selector 17 generates and holds a selection signal 34 for selecting the clock signal 32 to be output to the CPU 18 based on the information on the operating voltage.

  The prescaler 16 sets the frequency of the clock signal to 1/2 or 1/4 and supplies it to the selector 17.

  The selector 17 receives a clock signal 28 that is a quarter frequency of the clock signal 27 supplied from the outside, a clock signal 29 that is a half frequency, and a clock signal 30 that is a 1/1 frequency. . The selector 17 selects one of the clock signals 28 to 30 based on the selection signal 34 from the selector control register 14 and supplies the selected signal to the CPU 18.

  When receiving the latch signal 33 from the latch circuit 12, the selector control register 14 outputs the held selection signal 34 to the selector 17.

  When the detection results output from the comparator data buffer 13 are (11), (10), and (00), respectively, the selection signal 34 is 1/4, 1/2, or 1/1 of the frequency of the clock signal 27, respectively. The selector 17 selects the clock signals 28, 29 and 30 having the frequencies.

  The latch circuit 12 is a selector control register based on the operation request signal 25 input from the CPU 18 or the request signal 24 requesting the operation of the microcomputer 1 input from the outside, and the frequency change signal 31 output during operation of the CPU 18. When the latch signal 33 is output to 14 and the latch signal 33 is input, the selector control register 14 outputs the selection signal 34 held to the selector 17.

  The suspension / operation control unit 15 supplies or stops the clock signal 27 supplied to the inside of the microcomputer 1 based on the request signal 24 from the outside or the operation request signal 25 and the suspension request signal 26 from the CPU 18.

  The CPU 18 controls the supply of the clock signal 27 supplied to the inside of the microcomputer 1 by outputting the operation request signal 25 or the suspension request signal 26 to the suspension / operation controller 15, thereby controlling the suspension and operation of the CPU 18. To do.

  The operation request signal 25 and the suspension request signal 26 are the same signal. The operation request signal 25 and the suspension request signal 26 are in operation and in the hi (1) operation, respectively, but in this embodiment, they are described separately for explaining the operation. The operation request signal 25 and the stop request signal 26 are output by, for example, a microcomputer mounting function (such as a timer).

  During operation, the CPU 18 outputs a frequency change signal 31 to the latch circuit 12 at a constant cycle as necessary for the operation of the microcomputer 1. The frequency change signal 31 causes the latch circuit 12 to output the latch signal 33, the latch signal 33 causes the selector control register 14 to output the selection signal 34, and the selector 17 selects the clock signal 32 by the selection signal 34. The

  In the present embodiment, since the operating voltage is detected regardless of the operating state of the microcomputer 1, when the microcomputer 1 is restarted, the operation of selecting the optimum clock signal frequency after completion of the measurement of the operating voltage is performed. The response of the operation of the microcomputer 1 is improved.

  Here, the operation of the microcomputer 1 will be described in more detail. FIG. 2 is a flowchart showing the operation of the microcomputer 1 according to the present embodiment.

  First, user processing related to the system is performed (step S31). If the user process does not pause the operation of the CPU 18 (step S32: No), the microcomputer 1 returns to the normal operation.

  If the user process is to pause the CPU 18 (step S32: Yes), the CPU 18 outputs a pause request signal 26, and the pause / operation control unit 15 pauses the supply of the clock signal 27 (step S33).

  The CPU 18 pauses until either the external request signal 24 or a certain condition is satisfied (step S34). The fixed condition is, for example, a setting for restarting by a timer in the microcomputer 1. Here, even in step S34 in which the CPU 18 is inactive, the detection of the operating voltage is continued by the comparators 10 and 11 regardless of the supply state of the clock signal 27 to the inside of the microcomputer 1, and the operating voltage information of the comparator data buffer 13 Is updated.

  When the request signal 24 is input from the outside or the restart condition is generated (step S35: Yes), the CPU 18 starts the operation (step S36).

  While the CPU 18 is in a dormant state, an external request signal 24 or an operation request signal 25 from the CPU 18 is issued, and at the same time, an operation request signal 25 is output to the latch circuit 12. As soon as the operation request signal 25 is input, the latch circuit 12 outputs a latch signal 33 to the comparator data buffer 13.

  The selector control register 14 updates the operating voltage information even when the CPU 18 is in an inactive state, and always holds the selection signal 34. Therefore, the selection signal 34 is input to the selector 17 as soon as the latch signal 33 is input.

  According to the present embodiment, by including the comparators 10 and 11 that can always detect the operating voltage regardless of the supply state of the clock signal 27 to the inside of the microcomputer 1 and the operating state of the microcomputer 1, The operating voltage can be detected. Further, the microcomputer 1 has a comparator data buffer 13 that updates information on the operating voltage regardless of the operating state of the microcomputer 1, and a selector control register 14 that always holds the selection signal 34 based on the detection result of the paralator buffer 13. Have. Therefore, an external request signal 24 for starting the microcomputer 1 and an operation request signal 25 from the CPU 18 cause the comparator data buffer 13 to output the selection signal 34 almost simultaneously via the latch circuit 12. Therefore, it is possible to switch to an operating frequency that matches the operating voltage when the microcomputer 1 is restarted. As described above, when the microcomputer is stopped, the control for switching to the slowest frequency assuming the lowest voltage is considered in consideration of the operating voltage drop. Therefore, the operating voltage is measured and the operating frequency is selected when the microcomputer 1 is restarted. Thus, the switching process becomes unnecessary, so that the start of the corresponding process immediately after the re-operation is accelerated.

  Further, according to the present embodiment, the lost time is lost due to the conversion waiting time when the AD converter is used, and the response of the user process is improved.

  In addition, since the circuit for detecting the operating voltage is composed of simple circuits such as the comparators 10 and 11 and the comparator data buffer 13, the user software processing for detecting the operating voltage becomes unnecessary, reducing the load on the user software and processing time. Can be shortened.

  Note that the present invention is not limited to the above-described embodiment, and can be changed as appropriate without departing from the spirit of the present invention. For example, the number of comparators and the number of operation bands may be increased.

DESCRIPTION OF SYMBOLS 1 Microcomputer 10, 11 Comparator 12 Latch circuit 13 Comparator data buffer 14 Selector control register 15 Pause / operation control part 16 Prescaler 17 Selector 18 CPU
21 Operation power supply 22, 23 Detection signal 24 Request signal 25 Operation request signal 26 Pause request signal 27 Clock signal 28 Clock signal (frequency 1/4)
29 Clock signal (frequency 1/2)
30 clock signals (frequency 1/1)
31 Frequency change signal 32 Clock signal 33 Latch signal 34 Selection signal 101 High-speed system clock generator 102 Clock generation circuit 103 Prescaler 104 Selector 105 Microcomputer 106 AD converter 107 Power supply 108 Microcomputer 109 Selector control register 110 Pause / operation control unit 111 Prescaler 112 Selector 113 CPU
121 operation power supply 122 clock signal 123 request signal 124 operation request signal 125 pause request signal 126, 127 clock signal 128 selector control signal

Claims (8)

An arithmetic unit that stops supply of a clock signal in response to a request from the outside or the inside,
A clock signal generator for changing the frequency of a clock signal supplied from the outside and generating one or more clock signals of different frequencies;
A voltage detector that detects the operating voltage of the microcomputer regardless of the operating state of the arithmetic unit;
A selection unit that selects either the clock signal generated by the clock signal generation unit or the clock signal supplied from the outside and supplies the selection to the arithmetic unit;
A selection signal generation unit that generates a selection signal for the selection unit to select a clock signal based on the detection result of the voltage detection unit regardless of the operating state of the arithmetic unit;
A microcomputer in which a clock signal is selected by the selection signal in response to a request from the outside or inside regardless of the operating state of the arithmetic unit, and is supplied to the arithmetic unit. The selection signal generator is
The microcomputer according to claim 1, wherein the detection result detected by the voltage detection unit is converted into the selection signal and held, and the selection signal is output to the selection circuit in response to a request from the outside or the inside.   3. The microcomputer according to claim 1, wherein the voltage detection unit includes a comparator that outputs 0 when it is detected that the voltage is equal to or higher than a predetermined voltage, and detects the operating voltage. The voltage detector is
4. The microcomputer according to claim 1, further comprising a plurality of comparators that detect different voltages, and measuring the operating voltage based on a result output from the plurality of comparators.   5. The clock signal according to claim 1, wherein when a clock signal is supplied to the arithmetic unit, a clock signal is selected by the selection signal in response to a request from the arithmetic unit and supplied to the arithmetic unit. Microcomputer. A control method of a microcomputer having a calculation unit in which supply of a clock signal is stopped by a request from outside or inside,
Change the frequency of the clock signal supplied from outside, generate one or more clock signals with different frequencies,
Detect the operating voltage of the microcomputer regardless of the operating state of the arithmetic unit,
Based on the detection result regardless of the operation state of the arithmetic unit, generating a selection signal for selecting either a clock signal supplied from the outside or a clock signal having a different frequency generated,
A microcomputer control method for selecting a clock signal by the selection signal and supplying the selected clock signal to the arithmetic unit in response to a request from outside or inside regardless of the operating state of the arithmetic unit.   When generating the selection signal, the detection result is converted into the selection signal and held in the selection signal generation unit, and the selection signal held in the selection signal generation unit in response to a request from the outside or the inside 7. The microcomputer control method according to claim 6, wherein the microcomputer is output.   When a clock signal is selected based on the selection signal and supplied to the arithmetic unit, if the supply of the clock signal to the arithmetic unit is suspended, the arithmetic unit can be requested by an external or internal request. 8. The microcomputer control method according to claim 6, wherein when the clock signal is supplied, the clock signal is selected in response to a request from the arithmetic unit.

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