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JP2011108710A - Semiconductor package - Google Patents

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JP2011108710A
JP2011108710A JP2009259571A JP2009259571A JP2011108710A JP 2011108710 A JP2011108710 A JP 2011108710A JP 2009259571 A JP2009259571 A JP 2009259571A JP 2009259571 A JP2009259571 A JP 2009259571A JP 2011108710 A JP2011108710 A JP 2011108710A
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semiconductor
package
lt
thin
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Junichi Kasai
Masao Sakuma
正夫 佐久間
純一 河西
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Sk Link:Kk
株式会社SKLink
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor package which reduces the assembly cost sharply by reducing the constituent members and the number of assembly steps, can make thin the semiconductor package, and can attain the thickness of 1 mm or less even in case of a 10-tiered POP structure. <P>SOLUTION: The semiconductor package can be made thin by eliminating the need for the constituent members of a conventional semiconductor package, i.e. a lead frame, a substrate and a wire, and the adhesive. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は半導体パッケージに関するものである。 The present invention relates to a semiconductor package.

従来、金属のリードフレームを外部電極に使用する半導体パッケージの構造として、 Conventionally, the structure of a semiconductor package using a metal lead frame to an external electrode,
半導体チップの外部端子(パッド)と2次実装に使用される外部電極(リードフレーム)は金属のワイヤーで接続されており、外部電極を除いた部分は樹脂で覆われている。 External electrodes to be used in the secondary mounting external terminals of the semiconductor chip (pads) (lead frame) are connected with metal wire, a portion excluding the external electrode is covered with resin.

このように構成された半導体パッケージは単体でプリント基板に実装されて使用され、実装スペースは半導体パッケージの平面的面積が必要となり実装密度を高めることはできない。 Configured semiconductor packages thus is used mounted on a printed circuit board alone, the mounting space can not increase the packing density is required planar area of ​​the semiconductor package. また、リードフレームを使用し金属ワイヤー接続を必要とすることからパッケージ組立て費用は高価となる。 Also, the package assembly cost since it requires the use of a lead frame metal wires connected becomes expensive.

また、従来の半導体パッケージではパッケージを縦型に積み重ねて1つのシステムとするパッケージオンパッケージ(POP)の構造がある。 Further, in the conventional semiconductor package has the structure of a package on package (POP) to the vertical type stacked one system package. POPに使用されるパッケージはボールグリッドアレイ(BGA)タイプが主流であるがその構造は、サブストレート(配線基板)の上に半導体チップを搭載しサブストレート上に被着された配線と半導体チップ上のパッドを金属ワイヤーで接続し樹脂で覆われている、なお、サブストレート上の配線からサブストレート下面に設けられたボール(半導体パッケージの外部電極)へ電気的に接続されている。 Its structure package is mainly ball grid array (BGA) type used for POP, the substrate (wiring substrate) is deposited on the substrate by mounting a semiconductor chip on the wiring and the semiconductor chip and the pad is covered with a resin connected by metal wires, yet are electrically connected to the wiring on the substrate to the ball provided on the substrate lower surface (semiconductor package external electrodes).

このように構成された半導体パッケージは複数の高価な構成部材が必要であり、また、パッケージの厚さも複数の構成部材を使用するため厚くなる(0.5mm以上)ことからPOPとした場合でも2段重ねまでの構造が主流である。 Configured semiconductor package in this way requires more expensive components, also becomes thicker (0.5mm or more) to the thickness of the package also use multiple components even when the POP since 2 structure up to stage pile is the mainstream.

前述のごとく従来の半導体パッケージでは複数の構成部材が必要であり、組立工程も複雑であることから高価なものとなっている。 In the conventional semiconductor package as described above requires a plurality of components, it has become expensive since the assembly process is complicated. また従来の半導体パッケージを使用して実装密度を高めるためにはBGAを積み重ねたPOPの構造となるが、BGAのパッケージを2段に積み重ねるのが実用上の限界であり、期待されるほどの実装密度は達成されていない。 Although the structure of the POP a stack of BGA in order to increase the packing density by using the conventional semiconductor package, a limit practical that stacking BGA package in two stages, the implementation of as expected density has not been achieved. 本発明は、上記の点に鑑みてなされたものであり、構成部材および組立工程数を減らすことにより半導体パッケージの組立費用を大幅に低減し、さらには半導体パッケージの厚さを薄化することが可能となり、10段重ねのPOPとした場合でも1ミリメートル以下の厚さを達成する半導体パッケージを提供することを目的とする。 The present invention has been made in view of the above, it is possible to greatly reduce the assembling cost of the semiconductor package by reducing the number of components and assembly processes, further thinning the thickness of the semiconductor package possible and it is an object to provide a semiconductor package that achieve one millimeter thickness even when a ten-tiered POP.

本発明は、上記の課題を解決するために、次に述べる手段を講じたことを特徴とするものである。 The present invention, in order to solve the above problems, is characterized in that took measures as described below. 請求項1の発明は、半導体パッケージにおいて半導体チップの周囲を電気的絶縁材料にてパッケージングする際に平面的に見て半導体チップの大きさよりも広範囲にパッケージングし、半導体チップの範囲外のパッケージ部にパッケージの表裏を貫通する孔を設け、当該孔の壁面に金属膜を被着しパッケージの表裏を孔の壁面によって電気的に導通し外部電極とする構造をもつことを要旨とする。 The invention according to claim 1, extensively packaged than the size of the semiconductor chip in plan view when packaging periphery of the semiconductor chip by an electric insulating material in the semiconductor package, outside of the package of the semiconductor chip part provided a hole penetrating the front and back of the package, and summarized in that having a structure in which an electrically conductive and outer electrodes by the wall surface of the front and back of the hole in the package and depositing a metal film on the wall of the hole. 従って従来の半導体パッケージ構造に使用されているリードフレーム又はサブストレートが不要となる。 Thus the lead frame or substrate used in conventional semiconductor packaging structure is not required.

請求項2の発明は、半導体パッケージにおいて半導体チップの周囲を電気的絶縁材料にてパッケージングする際に平面的に見て半導体チップの大きさよりも広範囲にパッケージングし、半導体チップの範囲外のパッケージ部にパッケージの表裏を貫通する孔を設け、当該孔に導電性の材料を埋め込みパッケージの表裏を孔の内部に埋め込んだ導電性材料によって電気的に導通し外部電極とする構造をもつこと要旨とする。 According to a second aspect of the invention, extensively packaged than the size of the semiconductor chip in plan view when packaging periphery of the semiconductor chip by an electric insulating material in the semiconductor package, outside of the package of the semiconductor chip part provided a hole penetrating the front and back of the package, the subject matter have a structure in which an electrically conductive and external electrodes by a conductive material embedded sides of the package buried conductive material in the holes inside the hole to. 従って従来の半導体パッケージ構造に使用されているリードフレーム又はサブストレートが不要となる。 Thus the lead frame or substrate used in conventional semiconductor packaging structure is not required.

請求項3の発明は、半導体パッケージにおいて半導体チップ表面の電極パッドに導電性のポストを形成し当該ポストの一部をパッケージの表面に露出させ、当該露出部と請求項1および請求項2に記載された外部電極をパッケージの表面に被着された配線によって電気的に導通させたことを要旨とする。 The invention of claim 3, a portion to form the conductive posts to the electrode pads of the semiconductor chip surface of the post in the semiconductor package is exposed to the surface of the package, according to claim 1 and claim 2 and the exposed portion and gist that is electrically connected by a wiring which is deposited an external electrode on the surface of the package that is. 従って従来の半導体パッケージ構造に使用されている金属ワイヤーを使用しないため、半導体パッケージの部材数及び組立工程数を低減することが可能となり大幅にコストダウンすることができる。 Thus it does not use the metal wires used in conventional semiconductor packaging structure, it is possible to reduce costs greatly it is possible to reduce the number of members and the number of assembling steps of the semiconductor package.

請求項4の発明は、半導体パッケージの表裏を貫通した孔の壁面に被着する金属膜を、イオンプレーティング法により形成したその金属膜の結晶状態が不定形(アモルファスなど)であることを要旨とする。 The invention according to claim 4, summarized in that a metal film deposited on the wall of the hole penetrating the front and back of the semiconductor package, the crystal state of the metal film formed by ion plating is amorphous (such as amorphous) to. イオンプレーティング法であれば貫通孔の壁面に金属膜を被着することが容易であり、被着した金属膜の密着強度は印刷法やメッキ法によって被着された金属膜よりも強力である。 It is easy to deposit a metal film on the wall surface of the through hole if an ion plating method, the adhesion strength of the metal film deposited is stronger than metal films deposited by a printing method or a plating method .

請求項5の発明は、半導体パッケージの表面に被着する配線材料をイオンプレーティング法により形成したその金属膜の結晶状態が不定形(アモルファスなど)であることを要旨とする。 The invention of claim 5 is summarized in that the crystalline state of the metal film of the wiring material is formed by an ion plating method to deposit on the surface of the semiconductor package is the custom (such as amorphous). イオンプレーティング法であればパッケージの表面に金属膜を被着することが容易であり、被着した金属膜の密着強度は印刷法やメッキ法によって被着された金属膜よりも強力である。 If ion plating method, it is easy to deposit a metal film on the surface of the package, the adhesion strength of the metal film deposited is stronger than metal films deposited by a printing method or a plating method.

請求項1および請求項2に記載の発明によれば、半導体チップとパッケージの外縁部の間に2次実装用の外部電極を設けるため、パッケージの外側に突出する外部リードが不要となる。 According to the invention described in claims 1 and 2, for providing the external electrodes for secondary mounting between the outer edge of the semiconductor chip and the package, the external leads is not necessary to protrude the outside of the package. このために従来の半導体パッケージに必要であった金属リードフレームおよびサブストレートが不要となり、半導体パッケージを構成する部材数および組立工程数の低減がなされ大幅なコストダウンを達成する、とともにリードフレームおよびサブストレートを使用しないためパッケージ厚さの薄化(半導体パッケージ厚さ0.1ミリメートル以下)が可能となる。 The metal lead frame and substrate were required for the conventional semiconductor package for becomes unnecessary, reducing the number of members and the number of assembling steps to achieve a significant cost reduction is made to the semiconductor package, together with the lead frame and the sub because it does not use a straight package thickness thinning (semiconductor package thickness of 0.1 millimeters or less) it is possible.

請求項3に記載の発明によれば、従来の半導体パッケージの構成に不可欠であった金属ワイヤーが不要となる。 According to the invention described in claim 3, the metal wire was essential to the structure of a conventional semiconductor package is not required. このために従来の半導体パッケージに比較し、半導体パッケージを構成する部材数および組立工程数の低減がなされ大幅なコストダウンを達成する。 This compared with a conventional semiconductor package for a reduction in the number of members and the number of assembling steps to achieve a significant cost reduction is made to the semiconductor package.

請求項4に記載の発明によれば、半導体パッケージの表裏を貫通した孔の壁面に金属膜をイオンプレーティング法によって被着するが、イオンプレーティング法により被着された金属膜の密着強度は、印刷法やメッキ法によって被着された金属膜よりも強力であり信頼性の高い半導体パッケージを提供することが可能となる。 According to the invention of claim 4, deposited by ion plating a metal film on the wall of the hole penetrating the front and back of the semiconductor package, the adhesive strength of the deposited metal film by ion plating , it is possible to provide a powerful and highly reliable semiconductor package than the deposited metal film by a printing method or a plating method.

請求項5に記載の発明によれば、パッケージの表面に被着する配線材料をイオンプレーティング法により被着するが、イオンプレーティング法により被着された金属膜の密着強度は、印刷法やメッキ法によって被着された金属膜よりも強力であり信頼性の高い半導体パッケージを提供することが可能となる。 According to the invention of claim 5, although depositing a wiring material deposited on the surface of the package by an ion plating method, the adhesion strength of the metal films deposited by ion plating method, a printing method Ya by plating it is possible to provide a a potent highly reliable semiconductor package than the deposited metal film. さらにはイオンプレーティング法であれば配線のラインアンドスペース(線幅と線間の距離)を、従来の印刷法に比較して微細化が可能となる。 Further line-and-space lines if an ion plating method (the distance between the line width and the line), and can be miniaturized as compared with the conventional printing methods.

本発明に係わる半導体パッケージの例を示す平面図である。 Is a plan view showing an example of a semiconductor package according to the present invention. 本発明に係わる半導体パッケージの例を示す図である。 Is a diagram illustrating an example of a semiconductor package according to the present invention. 本発明に係わる半導体パッケージにてPOPシステムを構成した図である。 At a semiconductor package according to the present invention is a diagram obtained by constituting the POP system. 本発明に係わる半導体パッケージの組立工程の実施例を示す図である。 It illustrates an embodiment of an assembly process of the semiconductor package according to the present invention. リードフレームを使用した半導体パッケージの例を示す図である。 Is a diagram illustrating an example of a semiconductor package using a lead frame. サブストレートを使用した半導体パッケージの例を示す図である。 Is a diagram illustrating an example of a semiconductor package using the substrate. 従来のパッケージにてPOPシステムを構成した図である Is a diagram obtained by constituting the POP system in a conventional package

本発明による半導体パッケージ1は、半導体チップ2、パッケージング樹脂3、表裏貫通孔4、孔壁面被着膜5、電極パッド6、ポスト7、配線8、外部電極9から構成される。 The semiconductor package 1 according to the present invention, the semiconductor chip 2, the packaging resin 3, the front and rear through-holes 4, the hole wall under-deposit 5, the electrode pads 6, post 7, wiring 8, and an external electrode 9.

半導体チップ2に設けられた電極パッド6には導電性のポスト7が立てられており、半導体チップ2の回路のない背面が露出するようにパッケージング樹脂3によってパッケージされている、このときポスト7の一部はパッケージの表面から露出している。 The electrode pads 6 provided on the semiconductor chip 2 is erected the posts 7 of conductive, rear without circuit of the semiconductor chip 2 are packaged by the packaging resin 3 so as to expose, at this time post 7 some of are exposed from the surface of the package.

パッケージング樹脂3は平面的に半導体チップ2の大きさよりも相当大きい範囲をパッケージしており、半導体チップ2とパッケージの端部との間には表裏貫通孔4が設けられ、当該貫通孔の内面には導電性材料により孔壁面被着膜5が被着されている。 Packaging resin 3 is packaged a substantially greater range than the size of the plane to semiconductor chip 2, the front and rear through-holes 4 are provided between the semiconductor chip 2 and the package end, the inner surface of the through hole hole wall under-deposit 5 is adhered by a conductive material on. また、当該貫通孔に導電性材料を埋め込むことでも同じ効果が得られる。 Also, by embedding a conductive material into the through hole the same effect is obtained.

表裏貫通孔4の表側の縁と裏側の縁には孔壁面被着膜5を介して電気的に導通するようになされた導電性の材料にて外部電極9を設けており、導電性材料を被着した配線8によってポスト7と外部電極9は電気的に結ばれている。 The front edge and rear edge of the front and rear through-holes 4 are provided external electrodes 9 in made conductive material so as to be electrically conductive via hole wall under-deposit 5, the conductive material post 7 and the external electrode 9 by the wiring 8 was deposited are linked electrically.

本発明による半導体パッケージ1の製造方法の1実施例としては、枠21に張力をもった状態(弛みのない状態)で粘着テープ22を貼り付けておき、粘着テープ22へ、ポスト7を形成し終え且つ個片化された半導体チップ2を搭載する。 As an example of a manufacturing method of the semiconductor package 1 according to the present invention, in a state with a tension to the frame 21 (the absence of slack) paste them to adhesive tape 22, the adhesive tape 22, to form a post 7 finishing and mounting the singulated semiconductor chip 2. このとき半導体チップ2は粘着テープ22に接着固定されており、隣接するチップ同士の距離は少なくとも半導体パッケージ1の外形サイズより大きくする。 In this case the semiconductor chip 2 is bonded and fixed to the adhesive tape 22, the distance of the chip adjacent to the larger than at least the outer size of the semiconductor package 1.

さらに、半導体チップ2及びポスト7をパッケージング樹脂3で覆いつくし、樹脂の硬化後に枠21および粘着テープ22を取り去りポスト7の一部が露出するまで表面を削り取る。 Furthermore, exhaustively cover the semiconductor chip 2 and the post 7 in the packaging resin 3 etches the surface until a portion of the post 7 deprived of frame 21 and adhesive tape 22 after curing of the resin is exposed.

その後、外部電極9の位置にパッケージの表裏貫通孔4を設け、孔壁面被着膜5、配線8、外部電極9をイオンコーティングにて形成する。 Thereafter, the formed front and rear through-holes 4 of the package to the position of the external electrodes 9 are formed holes wall under-deposit 5, wiring 8, the external electrodes 9 by ion coating.

さらに、隣接する半導体チップ2の間にて各々を切り離すことにより半導体パッケージ1が完成する。 Furthermore, the semiconductor package 1 is completed by disconnecting each at between adjacent semiconductor chips 2.

本発明による半導体パッケージ1の構造は従来の半導体パッケージ(図4および図5)に比較してリードフレームやサブストレートが不要となるため構成部材が少なくなっており1/5以下への薄型化が可能となる、また、ワイヤーボンディングの工程が不要となり大幅なコストの低減と信頼性の向上を実現することができる。 Structure of the semiconductor package 1 according to the present invention is thinner to a conventional semiconductor package (FIGS. 4 and 5) compared to 1/5 has become less components for the lead frame or substrate is not required in following the it can become, also, it is possible to achieve an improvement in reducing the reliability of the significant cost process of wire bonding is unnecessary.

1 本発明による半導体パッケージ 2 半導体チップ 3 パッケージング樹脂 4 表裏貫通孔 5 孔壁面被着膜 6 電極パッド 7 ポスト 8 配線 9 外部電極 10 リードフレーム 11 ワイヤー12 ステージ13 接着剤14 サブストレート15 実装用半田ボール16 パッケージ範囲17 個片化された本発明による半導体パッケージ18 10段重ねPOP 1 invention semiconductor package 2 semiconductor chip 3 packaging resin 4 sides through holes 5 holes wall under-deposit sixth electrode pads 7 post 8 lines 9 external electrode 10 lead frame 11 wire 12 stage 13 adhesive 14 solder substrate 15 mounted by the semiconductor package 18 10 tiered POP by the ball 16 packages range 17 pieces have been present invention
19 2段重ねPOP 19 2-tiered POP

Claims (5)

  1. 半導体チップの周囲を電気的絶縁材料にてパッケージングする際に平面的に見て半導体チップの大きさよりも広範囲にパッケージングし、半導体チップの範囲外のパッケージ部にパッケージの表裏を貫通する孔を設け、当該孔の壁面に金属膜を被着しパッケージの表裏を孔の壁面によって電気的に導通し外部電極とする構造をもつことを特徴とする半導体パッケージ。 Extensively packaged than the size of the semiconductor chip in plan view the periphery of the semiconductor chip in an electrically insulating material at the time of packaging, the hole penetrating the front and back of the package to the package part of the outside of the semiconductor chip provided, the semiconductor package characterized by having a structure in which an electrically conductive and external electrodes on the wall of the hole by the wall surface of the front and rear holes of the metal film is deposited package.
  2. 半導体チップの周囲を電気的絶縁材料にてパッケージングする際に平面的に見て半導体チップの大きさよりも広範囲にパッケージングし、半導体チップの範囲外のパッケージ部にパッケージの表裏を貫通する孔を設け、当該孔に導電性の材料を埋め込みパッケージの表裏を孔の内部に埋め込んだ導電性材料によって電気的に導通し外部電極とする構造をもつことを特徴とする半導体パッケージ。 Extensively packaged than the size of the semiconductor chip in plan view the periphery of the semiconductor chip in an electrically insulating material at the time of packaging, the hole penetrating the front and back of the package to the package part of the outside of the semiconductor chip provided, the semiconductor package characterized by having a structure in which an electrically conductive and external electrodes by a conductive material embedded sides of the package buried conductive material in the holes inside the hole.
  3. 請求項1及び請求項2に記載された半導体チップ表面の電極パッドに導電性のポストを形成し当該ポストの一部をパッケージの表面に露出させ、当該露出部と請求項1および請求項2に記載された外部電極をパッケージの表面に被着された配線によって電気的に導通させたことを特徴とする半導体パッケージ。 Exposed to claims 1 and 2 by forming a conductive post on the electrode pads of the semiconductor chip surface portion of the package surface of the post according to, with the exposed portion to claims 1 and 2 semiconductor package is characterized in that is electrically connected by being applied to the described external electrodes on the surface of the package wiring.
  4. 請求項1においてパッケージの表裏を貫通した孔の壁面に被着する金属膜をイオンプレーティング法により形成したその金属膜の結晶状態が不定形(アモルファスなど)であることを特徴とする半導体パッケージ。 Semiconductor package, characterized in that the crystalline state of the metal film and the metal film formed by ion plating to deposit on the wall surface of the front and back of the through-hole of the package in claim 1 is the custom (such as amorphous).
  5. 請求項3においてパッケージの表面に被着する配線材料をイオンプレーティング法により形成したその金属膜の結晶状態が不定形(アモルファスなど)であることを特徴とする半導体パッケージ。 Semiconductor package, wherein the crystalline state of the metal film of the wiring material is formed by an ion plating method to deposit on the surface of the package according to claim 3 is the custom (such as amorphous).
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KR101321534B1 (en) 2011-09-30 2013-10-28 (주)마이크로인피니티 Stacked sensor package

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JPH1154938A (en) * 1997-07-31 1999-02-26 Kyocera Corp Multilayered wiring board
JP2004342883A (en) * 2003-05-16 2004-12-02 Oki Electric Ind Co Ltd Semiconductor device and its fabricating process
JP2005310954A (en) * 2004-04-20 2005-11-04 Nec Corp Semiconductor package and its manufacturing method
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