JP2011040590A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thyristor capable of improving voltage rise rate (dV/dt) resistance in a high temperature, and capable of preventing malfunction. <P>SOLUTION: On one main surface of a semiconductor layer (20), a first main electrode (11) is formed on a first semiconductor layer (21) having a first conductivity type (p-type), and a second semiconductor layer (24) having a second conductivity type (n-type) opposite to the first conductivity type and partially formed in the first semiconductor layer and a gate electrode (13) connected to the second semiconductor layer and the first semiconductor layer are formed in a portion where the first main electrode is not formed, and on the other main surface of the semiconductor layer, a second main electrode (12) is formed, and the electric current flows between the first main electrode and the second main electrode, and the semiconductor device works as the thyristor. The semiconductor device includes a bidirectional diode connected between the gate electrode and the first main electrode and constituted by SBD (31, 32). <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

The present invention relates to a semiconductor device that controls current using a pn junction, and more particularly, to a thyristor and triac structure.

A thyristor is known as a semiconductor device that controls on / off of current using a plurality of pn junctions. In the thyristor, the gate-current is used as a trigger to control the turning on of the current between the anode and the cathode. Further, a triac (bidirectional thyristor) having a configuration in which reverse thyristors are connected in parallel and formed on the same semiconductor substrate is also widely used. Thyristors and triacs are widely used in power supply circuits and the like because they can pass a large current.

In thyristors and triacs, if no gate voltage is applied, the current flowing between the anode and cathode is negligibly small. When the gate voltage exceeds the trigger voltage, the gate current exceeds a certain value (trigger current). A current flows between the anode and the cathode, which are electrodes (in the triac, between the main electrodes). This current continues to flow even if the gate current is subsequently reduced to zero.

The operation of the triac will be described with reference to a plan view (FIG. 4 (a)) viewed from the top surface of the triac and a cross-sectional view in the CC direction (FIG. 4 (b)). The electrodes that control the triac 80 are a T1 electrode 81, a T2 electrode 82, and a gate electrode 83, which are main electrodes. As shown in the figure, the semiconductor layer 90 constituting the triac 80 includes a P1 layer (p-type layer: base) 91, an N1 layer (n-type layer: base) 92, a P2 layer (p-type layer: base) 93, N2 A layer (n-type layer: emitter) 94, an N3 layer (n-type layer: emitter) 95, and an N4 layer (n-type layer) 96. A current (operating current) switched in the triac 80 flows between the T1 electrode 81 and the T2 electrode 82. The T1 electrode 81 is formed on the upper surface of the semiconductor layer 90 so as to be in contact with both the P1 layer (p-type layer) 91 and the N2 layer 94, and the gate electrode 83 is in contact with both the P1 layer 91 and the N4 layer 96. Formed as follows. The planar shapes of the T1 electrode 81 and the gate electrode 83 are as shown in FIG. 4A, and the area of the T1 electrode 81 through which a large current (operating current) flows is larger. On the other hand, the T2 electrode 82 through which a large current flows is formed over the entire lower surface of the semiconductor layer 90 and is in contact with both the P2 layer 93 and the N3 layer 95. In this case, the first main thyristor including the T1 electrode 81, the N2 layer 94, the P1 layer 91, the N1 layer 92, the P2 layer 93, and the T2 electrode 82, the T1 electrode 81, the P1 layer 91, the N1 layer 92, and P2 The second main thyristor including the layer 93, the N3 layer 95, and the T2 electrode 82 is formed in parallel in the opposite direction. Further, an auxiliary thyristor including the gate electrode 83, the N4 layer 96, the P1 layer 91, the N1 layer 92, the P2 layer 93, and the T2 electrode 82 is formed as an auxiliary thyristor that assists the operations of these two main thyristors.

When the triac is turned from the off state to the on state, that is, when a current flows between the T1 electrode 81 and the T2 electrode 82, when considering the potential of the T1 electrode 81 as a reference, (1) the T2 electrode 82 is positive, gate electrode 83 is positive, (2) T2 electrode 82 is positive, gate electrode 83 is negative, (3) T2 electrode 82 is negative, gate electrode 83 is negative, (4) T2 electrode 82 is negative, gate There are four cases where the electrode 83 is positive. In any case, the trigger is that a gate current flowing in the P1 layer 91 between the T1 electrode 81 and the gate electrode 83 causes a voltage drop with a large time constant in the P1 layer 91. Due to this voltage drop, the pn junction between the P1 layer 91 and the N2 layer 94 or the pn junction between the P1 layer 91 and the N4 layer 96 becomes the forward direction, and electrons are injected into the P1 layer 91, whereby the triac 80 Turns on. Even when the gate current is subsequently reduced to zero, electrons continue to be injected into the P1 layer 91 while the current flows between the T1 electrode 81 and the T2 electrode 82, so this state is maintained. Even when the gate current is set to zero, the ON state is maintained.

In the above operation, the triac is turned on when a gate current is passed from the gate electrode 83. However, actually, when a sudden voltage change occurs between the T1 electrode 81 and the T2 electrode 82 ( When dV / dt is large), the gate electrode 83 may be turned on (falsely fired) even though no gate current is flowing from the gate electrode 83. By increasing the voltage increase rate (dV / dt), the malfunction tolerance of the triac can be improved.

The main cause of false ignition is that when there is a sudden voltage change, a displacement current (charging current) that flows through the capacitance of the pn junction in the base flows, and this also flows in the P1 layer 91. Become. It is clear that if the trigger current or trigger voltage is set large, such false firing is suppressed, but in this case, a large current (large voltage) is required to perform the original switching operation. It is not preferable. That is, there is a trade-off relationship between reducing the trigger current and increasing the resistance to false firing (dV / dt tolerance) when dV / dt is large, and a technique for achieving both is required. ing.

As such a technique, for example, there is a technique described in Patent Document 1. In the technique described in Patent Document 1, in the triac, by optimizing the distance in the horizontal direction between the N2 layer 94 and the N3 layer 95 serving as the emitter of each thyristor and the distance between the N4 layer 96 and the T1 electrode 81. It is described that a resistance component is provided between the T1 electrode 81 and the N4 layer 96 on the surface of the semiconductor layer 90 to reduce a current component (reactive current) that does not contribute to a voltage drop in the P1 layer 91. As a result, the trigger current can be reduced, or when the trigger current is not reduced, false firing can be further suppressed.

JP-A-8-97407

However, as shown in FIG. 5, when the thyristor (and triac) becomes high due to the environmental temperature or its own operation, the gate trigger current (IGT) becomes small due to the influence of the increase of thermally excited carriers and the like. The dV / dt resistance is reduced. In recent years, it has been required to increase the compensation temperature of the thyristor operation, and to improve the dV / dt resistance at high temperatures.

Accordingly, the present invention is to provide a thyristor capable of improving the withstand voltage rise rate (dV / dt) resistance at a high temperature and preventing malfunction.

In order to solve the above problems, an insulated gate semiconductor device according to the present invention provides:
The semiconductor layer (20) includes a first main electrode (11), a second main electrode (12), and a gate electrode (13) connected to each other. The first main electrode is formed on a first semiconductor layer (21) having one conductivity type (P type), and has a second conductivity type (N type) opposite to the first conductivity type. The second semiconductor layer (26) locally formed in the first semiconductor layer, and the gate electrode connected to the second semiconductor layer and the first semiconductor layer include the first semiconductor layer. Is formed at a place where the main electrode is not formed,
On the other main surface of the semiconductor layer, the second main electrode is formed,
Operation as a thyristor in which current flows between the first main electrode and the second main electrode when a voltage applied between the gate electrode and the first main electrode exceeds a trigger voltage A semiconductor device that performs
A bidirectional diode comprising a Schottky barrier diode (31, 32) is provided between the gate electrode and the first main electrode.

Since the present invention is configured as described above, it is possible to provide a thyristor capable of improving the withstand voltage rise rate (dV / dt) resistance at a high temperature and preventing malfunction.

It is the top view (a) and sectional drawing (b) of the triac which concern on the 1st Embodiment of this invention. It is a figure which shows an example of the electric current-temperature characteristic of the triac which concerns on the 1st Embodiment of this invention. It is the top view (a) and sectional drawing (b) of the triac which concern on the 2nd Embodiment of this invention. It is the top view (a) and sectional drawing (b) of the conventional triac. It is a figure which shows an example of the operation characteristic of the conventional triac.

Hereinafter, a triac will be particularly described as a semiconductor device according to an embodiment of the present invention. However, the drawings are schematic and different from actual ones.

In the triac according to the first embodiment, a diode is connected between the gate electrode and the first main electrode (T1 electrode). FIG. 1A is a plan view of a triac according to an embodiment of the present invention, and FIG.

A substrate (not shown) is formed of a material such as silicon (Si), silicon carbide (SiC), sapphire, or ceramic.

The electrodes for controlling the triac 10 are a T1 electrode (first main electrode) 11, a T2 electrode (second main electrode) 12, and a gate electrode 13 which are main electrodes. As shown in the drawing, the semiconductor layer 20 constituting the triac 10 includes a P1 layer (first semiconductor layer: p-type layer: base) 21, an N1 layer (n-type layer: base) 22, and a P2 layer (p-type layer). : Base) 23, N2 layer (third semiconductor layer: n-type layer: emitter) 24, N3 layer (n-type layer: emitter) 25, and N4 layer (second semiconductor layer: n-type layer) 26. The Each of these layers is appropriately formed by methods such as impurity diffusion, ion implantation, and epitaxial growth.

The operating current of the triac 10 flows between the T1 electrode 11 and the T2 electrode 12. The T1 electrode 11 is formed on the upper surface (one main surface) of the semiconductor layer 20 so as to be in contact with both the P1 layer (p-type layer) 21 and the N2 layer 24, and the gate electrode 13 includes the P1 layer 21 and the N4 layer. The layer 26 is formed so as to contact both. The planar shapes of the T1 electrode 11 and the gate electrode 13 are as shown in FIG. 1A, and the area of the T1 electrode 11 through which a large current (operating current) flows is larger. On the other hand, the T2 electrode 12 through which a large current flows is formed over almost the entire bottom surface of the semiconductor layer 20 (the other main surface) and is in contact with both the P2 layer 23 and the N3 layer 25. In this case, the first main thyristor including the T1 electrode 11, the N2 layer 24, the P1 layer 21, the N1 layer 22, the P2 layer 23, and the T2 electrode 12, the T1 electrode 11, the P1 layer 21, the N1 layer 22, and the P2 The layer 23, the N3 layer 25, and the second main thyristor including the T2 electrode 12 are formed in parallel. Further, an auxiliary thyristor including the gate electrode 13, the N4 layer 26, the P1 layer 21, the N1 layer 22, the P2 layer 23, and the T2 electrode 12 is formed as an auxiliary thyristor that assists the operations of these two main thyristors. The above is the configuration of the main body of the triac 10, which is the same as that of the conventional triac (FIG. 4) and the operation thereof is also the same. Note that the voltage (trigger voltage) between the gate electrode 13 and the T1 electrode 11 necessary for turning on the triac is about 0.9V.

When the triac 10 is turned on from the off state, that is, when a current flows between the T1 electrode 11 and the T2 electrode 12, when considering the potential of the T1 electrode 11 as a reference, (1) the T2 electrode 12 is positive, gate electrode 13 is positive, (2) T2 electrode 12 is positive, gate electrode 13 is negative, (3) T2 electrode 12 is negative, gate electrode 13 is negative, (4) T2 electrode 12 is negative, gate There are four cases where the electrode 13 is positive.

In the triac 10, in addition to the main body, Schottky barrier diodes (hereinafter referred to as SBDs) 31 and 32 are arranged between the gate electrode 13 and the T1 electrode 11 outside the triac main body so that the rectification directions are different from each other. Installed in series. That is, a bidirectional diode is connected between the gate electrode 13 and the T1 electrode 11. As is well known, the forward voltage (Vf) of the SBD is about 0.2 V, so it is sufficiently smaller than the trigger voltage of the thyristor, and the leakage current of the SBD increases as the temperature of the Schottky junction increases. Therefore, the bidirectional diode composed of the SBDs 31 and 32 allows a current corresponding to the Schottky junction temperature to flow bidirectionally when a voltage larger than the forward voltage is applied.

In this triac 10, the SBDs 31 and 32 increase the apparent gate trigger current (IGT) by bypassing the gate current flowing between the gate electrode 13 and the T1 electrode 11 to the outside of the triac body. At this time, since the current flowing through the SBDs 31 and 32 does not directly affect the firing of the triac 10, it can be called a reactive current. Therefore, the triac 10 increases the withstand voltage increase rate (dV / dt) by passing a reactive current between the gate electrode 13 and the T1 electrode 11. This mechanism will be described below.

As described above, in the conventional triac 80 shown in FIG. 4, a voltage drop occurs in the P1 layer 91 due to the gate current flowing between the T1 electrode 81 and the gate electrode 83, and the T1 electrode 81 and the T2 electrode 82 A current flows between them, that is, an on state is established. Here, even when the T1 electrode 81 is grounded and no voltage is applied to the gate electrode 83, if dV / dt is large, a displacement current (charging current) flowing through the capacitance of the pn junction in the base is generated. This flows through the P1 layer 91 and reaches the T1 electrode 81. Since this current is equivalent to the gate current, it creates an on state and causes false firing.

On the other hand, in the triac 10 according to the first embodiment of the present invention shown in FIG. 1, when a potential difference is generated between the gate electrode 13 and the T1 electrode 11 due to the displacement current flowing in the P1 layer 21, the gate electrode 13 The potential difference is also generated at both ends of the bidirectional diode formed between the T1 electrode 11. Due to this potential difference, the SBD 31 is forward-biased and the SBD 32 is reverse-biased. When the forward bias voltage due to the potential difference becomes larger than the forward voltage of the SBD 31, the SBD 31 becomes conductive, and a current equal to the leakage current of the SBD 32 flows in the bidirectional diode. In this way, a part of the displacement current flowing between the gate electrode 13 and the T1 electrode 11 is bypassed to the outside of the triac body, thereby preventing an increase in the displacement current flowing in the P1 layer 21. That is, the triac 10 can increase the apparent gate trigger current.

Since the SBDs 31 and 32 constituting the bidirectional diode have the above-described effects in the triac 10, it is preferable that the SBDs 31 and 32 are housed in the same mold material as that of the triac main body to ensure good thermal bondability.

2 shows a gate trigger current (IGT) in the triac 10 according to the first embodiment indicated by a solid line, an SBD leakage current (Ir) indicated by a one-dot chain line, and a gate trigger current in a conventional triac 80 indicated by a broken line. It is a figure which shows the temperature characteristic of (IGT). It can be seen that the reduction in the gate trigger current of the triac 10 at a high temperature is suppressed as compared with the gate trigger current in the conventional triac 80. Therefore, the triac 10 according to the first embodiment improves the temperature characteristics of the gate trigger current by flowing the SBD leakage current, improves the withstand voltage rise rate (dV / dt) at high temperature, and prevents malfunction. can do.

Further, since the SBDs 31 and 32 constitute a bidirectional diode, erroneous firing at a high temperature can be prevented in any of the above four cases where the triac 10 is turned on from the off state.

Further, since the reactive current flowing through the bidirectional diode is small when the SBD junction temperature is relatively low, a decrease in efficiency due to the reactive current can be suppressed at low temperatures.

FIG. 3A is a plan view showing the structure of a triac 50 according to the second embodiment, and FIG. 3B is a cross-sectional view in the BB direction. The T1 electrode 51, T2 electrode 52, gate electrode 53, semiconductor layer 60, P1 layer 61, N1 layer 62, P2 layer 63, N2 layer 64, N3 layer 65, N4 layer (n-type layer) 66 constituting this triac 50 And the relationship between them are the same as in the first embodiment. Therefore, the description is omitted.

In the triac 50, the SBDs 31 and 32 in the first embodiment are formed in the semiconductor substrate 60. Therefore, an ND1 layer (fourth semiconductor layer) 71 is newly formed in the P1 layer 61 layer, and an ND2 layer (fifth semiconductor layer) 72 is newly formed in the N2 layer 64 with respect to the structure of FIG. . Further, a metal wiring 73 is formed on the semiconductor substrate 60 via an insulating layer (silicon oxide film) 74, and a barrier metal is provided between the metal wiring 73 and the ND1 layer 71 and between the metal wiring 73 and the ND2 layer 72. Layer 75 is formed. Thus, two SBDs having different rectification directions are formed between the ND1 layer 71 and the barrier metal layer 75 and between the ND2 layer 72 and the barrier metal layer 75, and the two SBDs connected in series by the metal wiring 73 are Functions as a bidirectional diode.

The ND1 layer 71 and the ND2 layer 72 have the same conductivity type as the N1 layer 62 and the N2 layer 64, but have different impurity concentrations. Further, the metal wiring 73 in the present embodiment is made of Al (aluminum), and the barrier metal wiring 73 is made of V (vanadium) or Mo (molybdenum). In order to obtain a desired leakage current in a small SBD formation region, V is preferably formed. These structures constituting the bidirectional diode can be formed by well-known techniques such as photolithography, ion implantation, and vapor deposition with respect to the conventional triac.

Therefore, in the above structure, not only the same effect as the triac 10 according to the first embodiment is obtained, but also a diode for bypassing is formed on the same substrate as the triac main body. No need to connect. Therefore, compared with the triac 10 according to the first embodiment, when the triac 50 is mounted, the size can be further reduced.

Further, by forming the triac body and the bypass diode in the same semiconductor layer 60, the thermal coupling property is improved. Therefore, the triac 50 can more reliably improve the voltage rise rate (dV / dt) resistance at a high temperature and prevent malfunctioning than the triac 10 of the first embodiment.

In any of the above-described embodiments, triacs have been described. However, from the principle of operation, it is obvious that the present invention is not limited to triacs and is similarly used for a single thyristor. In that case, at least one SBD may be provided between the gate electrode and the cathode electrode of the thyristor. Specifically, an SBD having a rectification direction from the cathode electrode of the thyristor toward the gate electrode may be provided.

As mentioned above, although an example of embodiment of this invention was demonstrated, this invention is not limited to the specific embodiment which concerns, and it is various within the range of the summary of this invention described in the claim. Modifications and combinations of the embodiments or modifications are possible. In the above example, when the P1 layer 21 is the first semiconductor layer, its conductivity type (first conductivity type) is p-type, and the opposite conductivity type (second conductivity type: n-type). The case where the N2 layer (third semiconductor layer) 24 having N, the N4 layer (second semiconductor layer) 26, etc. are formed is shown. On the other hand, it is clear that a similar thyristor or triac can be configured even in a configuration in which the p-type and the n-type are replaced in the above configuration, and the material of the barrier metal wiring 73 for forming the SBDs 31 and 32 is used. Obviously, it can be changed appropriately.

10, 50, 80 Triac 11, 51, 81 T1 electrode (first main electrode)
12, 52, 82 T2 electrode (second main electrode)
13, 53, 83 Gate electrode 20, 60, 90 Semiconductor layer 21, 61, 91 P1 layer (p-type layer: first semiconductor layer)
22, 62, 92 N1 layer (n-type layer)
23, 63, 93 P2 layer (p-type layer)
24, 64, 94 N2 layer (n-type layer: third semiconductor layer)
25, 65, 95 N3 layer (n-type layer)
26, 66, 96 N4 layer (n-type layer: second semiconductor layer)
31, 32 SBD
71 ND1 layer (fourth semiconductor layer)
72 ND2 layer (fifth semiconductor layer)
73 Barrier metal wiring 74 Insulating layer (silicon oxide film)

Claims (4)

A first main electrode, a second main electrode, and a gate electrode are connected to the semiconductor layer, and on one main surface of the semiconductor layer, on the first semiconductor layer having the first conductivity type A second semiconductor layer having a second conductivity type opposite to the first conductivity type and locally formed in the first semiconductor layer; and The gate electrode connected to the second semiconductor layer and the first semiconductor layer is formed at a location where the first main electrode is not formed,
On the other main surface of the semiconductor layer, the second main electrode is formed,
Operation as a thyristor in which current flows between the first main electrode and the second main electrode when a voltage applied between the gate electrode and the first main electrode exceeds a trigger voltage A semiconductor device that performs
A semiconductor device comprising a bidirectional diode formed of a Schottky barrier diode, connected between the gate electrode and the first main electrode.
The semiconductor device according to claim 1, wherein the Schottky barrier diode is formed in the semiconductor layer.
The semiconductor device according to claim 1, wherein the Schottky barrier diode is configured separately from the semiconductor layer, and the diode and the semiconductor layer are integrated and provided in a molding material.
On one main surface of the semiconductor layer, a third semiconductor layer having the second conductivity type is locally formed in the first semiconductor layer, and the first main electrode is formed of the first main electrode. Connected to the semiconductor layer and the third semiconductor layer;
ON / OFF of a bidirectional current flowing between the first main electrode and the second main electrode is controlled by a voltage applied between the gate electrode and the first main electrode. The semiconductor device according to any one of claims 1 to 3.

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