JP2011028768A - Raid system using semiconductor storage device and method for controlling the same - Google Patents

Raid system using semiconductor storage device and method for controlling the same Download PDF

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JP2011028768A
JP2011028768A JP2010203243A JP2010203243A JP2011028768A JP 2011028768 A JP2011028768 A JP 2011028768A JP 2010203243 A JP2010203243 A JP 2010203243A JP 2010203243 A JP2010203243 A JP 2010203243A JP 2011028768 A JP2011028768 A JP 2011028768A
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semiconductor memory
semiconductor
data
raid system
combination
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JP5284327B2 (en
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Kenji Hirohata
Minoru Mukai
Takahiro Omori
稔 向井
隆広 大森
賢治 廣畑
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Toshiba Corp
株式会社東芝
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a RAID system using a semiconductor storage device which averages a mechanical load and an electric load which are assumed with respect to semiconductor memories which distribute and store data. <P>SOLUTION: The RAID system 100 which transfers data to/from host equipment 200 is equipped with: a plurality of semiconductor storage devices 10 having a plurality of semiconductor memories mounted thereon; a semiconductor memory selection part 20 which selects combination of the semiconductor memories when the data are distributed and stored in the plurality of semiconductor storage devices 10; and a memory control part 30 which access a semiconductor memory selected by the semiconductor memory selection part 20, in response to the request of the host equipment 200. The semiconductor memory selection part 20 selects the combination of the semiconductor memories 20 so that the mechanical load to be received by the semiconductor memories is averaged. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a RAID system using a plurality of semiconductor memory devices and a control method thereof.

  In recent years, RAID (Redundant Array of Inexpensive Disks) using an HDD (Hard Disk Drive) has been widely used as a typical mass storage device. RAID combines a plurality of inexpensive HDDs and distributes data while providing redundancy, so that a high-speed and highly reliable storage device can be realized at low cost.

  In an HDD, data is recorded on a magnetic material on a disk-shaped disk by a magnetic head. There are many factors that affect the life of the HDD, but the disk serving as the storage unit is disk-shaped, and the location where defects occur on the disk is highly random. Therefore, there is a high possibility that the probability of data loss depending on the physical information recording position is the same. For this reason, from the viewpoint of failure, the physical location where data is recorded on the disk inside the HDD is not a big problem. Even in the case of HDDs constituting a RAID, the positions of data to be distributedly recorded in the HDDs do not pose a major problem.

  On the other hand, the capacity of semiconductor memory devices using nonvolatile semiconductor memories is rapidly increasing. In a semiconductor memory device, data is stored in a semiconductor memory mounted on a substrate. Unlike the HDD disk, the semiconductor memory is not necessarily mounted on the substrate with physical symmetry. Therefore, the probability that a defect will occur varies depending on the physical position of the semiconductor memory. For this reason, it is not sufficient to use only distributed recording with redundancy in consideration of data restoration.

  In the case of a semiconductor memory, since there is a limit on the number of times of writing, a device has been devised for leveling the number of times of erasing. For example, in a RAID configured with a plurality of flash memory modules, a method of leveling the number of erasures over a plurality of modules has been proposed (see, for example, Patent Document 1). This is intended to extend the life of the storage device by RAID by leveling across a plurality of modules in a state in which the RAID is configured in order to avoid the limitation on the number of times of writing peculiar to the semiconductor memory.

JP 2007-265265 A

  When a RAID is configured with a semiconductor memory device and data is distributed and stored without considering the physical arrangement of the semiconductor memory, the semiconductor memory in each semiconductor memory device has a different probability of occurrence of a defect. When data is stored in each semiconductor memory device, there is a possibility that the data is selectively distributed to a semiconductor memory having a high probability of occurrence of a defect at that time. As a result, compared to HDD RAID, there is a problem that there is a higher possibility of data loss due to the occurrence of defects more than RAID redundancy at a time.

  The problem to be solved by the present invention is to equalize an assumed mechanical load and electrical load on a semiconductor memory that stores data in a distributed manner.

  In order to solve the above problem, a RAID system using a semiconductor storage device that transfers data to and from a host device, the plurality of semiconductor storage devices including a plurality of semiconductor memories, and the plurality of the plurality of semiconductor storage devices When data is distributed and stored among semiconductor memory devices, a semiconductor memory selection unit that selects a combination of the semiconductor memories, and the semiconductor device selected by the semiconductor memory selection unit is requested by the host device. A memory control unit that performs access in accordance with the semiconductor memory, the semiconductor memory selection unit calculates the mechanical load received by the semiconductor memory in advance or at the time of data storage, the value of the calculated load is averaged Thus, the combination of the semiconductor memories is selected.

1 is a block diagram showing a configuration of a RAID system using a semiconductor memory device according to an embodiment of the present invention. 1 is a schematic diagram showing a schematic configuration of a semiconductor memory device according to an embodiment of the present invention. 1 is a schematic diagram showing an example of a RAID system using a semiconductor memory device according to an embodiment of the present invention. It is a figure explaining the combination of the optimized semiconductor memory. It is a figure explaining the example of preservation | save of the distributed data. It is a flowchart which shows the flow of a process until the combination determination of a semiconductor memory. It is a figure explaining how to determine the representative distance. It is a block diagram which shows the structure of the RAID system using the semiconductor memory device which concerns on 3rd Embodiment. It is a flowchart which shows the flow of a process until the combination determination of a semiconductor memory. It is a block diagram which shows the structure of the RAID system using the semiconductor memory device which concerns on 4th Embodiment. It is a flowchart which shows the flow of a process until the combination determination of a semiconductor memory.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings. In the drawings, the same portions are denoted by the same reference numerals, and redundant description is omitted.

(First embodiment)
FIG. 1 is a block diagram showing a configuration of a RAID system using a semiconductor memory device according to an embodiment of the present invention. The RAID system 100 includes a plurality of semiconductor storage devices 10, a memory control unit 30, and a semiconductor memory selection unit 20, and is connected to a host device 200 as an external device. As will be described later, the semiconductor memory device 10 has a plurality of semiconductor memories mounted on a mounting substrate. The semiconductor memory selection unit 20 selects a combination of semiconductor memories when data is distributed and stored among a plurality of semiconductor memory devices 10. The semiconductor memory selection unit 20 selects a combination of semiconductor memories so that the mechanical loads received by the semiconductor memories in the respective semiconductor memory devices 10 are averaged. In the first embodiment, the mechanical load information 40 received by the semiconductor memory is taken into the semiconductor memory selection unit 20. The memory control unit 30 accesses the semiconductor memory selected by the semiconductor memory selection unit 20 according to the request of the host device 200, and executes writing of distributed data and the like. Examples of the host device 200 include electronic devices such as personal computers.

  FIG. 2 is a schematic diagram showing a schematic configuration of the semiconductor memory device 10 according to the embodiment of the present invention. In FIG. 2, a control IC 5 for control is disposed slightly to the right from the center on the mounting substrate 1. Around the control IC 5, a capacitor 6, a sensor 7, and a power source 8 are arranged. The sensor 7 measures a physical variation of the mounting substrate 1 or its surrounding environment, and is arranged for monitoring. The physical quantity to be measured may be any one of acceleration, strain, temperature, resistance, impedance, or a plurality.

  Further, eight semiconductor memories 4 are arranged so as to surround them. Therefore, the distance connecting the position where each semiconductor memory 4 is arranged and the control IC 5 is different. The semiconductor memory 4 is preferably, for example, a binary NAND flash memory or a multi-level NAND flash memory. In FIG. 2, the number of semiconductor memories 4 mounted is eight, but the number of semiconductor memories 4 mounted on one semiconductor memory device 10 is not limited to this. A connector 2 is disposed at one end of the mounting substrate 1. The semiconductor memory device 10 may be packaged by resin sealing or the like.

  A RAID system 100 as shown in FIG. 3 is constructed using n semiconductor memory devices 10 as shown in FIG. FIG. 3 is a schematic diagram illustrating an example of the RAID system 100. In the RAID system 100 shown in FIG. 3, one data is distributed into n blocks and stored in each semiconductor memory device 10. The method for distributing data is not limited to a specific method, and various known methods can be adopted depending on the level of redundancy of RAID. That is, when data is divided into n parts without storing redundancy (RAID 0), when n copies of the data itself are stored (RAID 1), the data is divided and stored, and the parity of the divided data is also stored. In the case of saving (RAID 5, 6), etc.

  In the first embodiment of the present invention, the writing to the semiconductor memory 4 is optimized with respect to the thermal fluctuation (thermal load) caused by the heat generated by the control IC 5. Generally, the control IC 5 used in the semiconductor memory device 10 is accompanied by a large amount of heat generation. When there is a large thermal fluctuation in the mounted components on the mounting substrate 1, a large thermal stress is generated at the solder joint that connects the semiconductor memory 4 and the mounting substrate 1 when the power is turned on and off.

  In the semiconductor memory device 10 shown in FIG. 2, the temperature on the mounting substrate 1 decreases as the distance from the control IC 5 increases. Therefore, in each semiconductor memory device 10 constituting the RAID system 100, the combination is determined so that the representative distances from the control IC 5 of the semiconductor memories 4 that store data in a distributed manner are averaged as much as possible. Thereby, the influence of the thermal fluctuation can be averaged over the entire semiconductor memory 4 constituting the RAID system 100. As the representative distance, a distance from the center of the control IC 5 to the center of each semiconductor memory 4 or a distance from the center of the control IC 5 to the solder joint of each semiconductor memory closest to the center is preferable.

  A combination for averaging the representative distance can be determined when the semiconductor memory device 10 is designed. However, the combination prioritization can be changed at any time in consideration of information such as deterioration of the semiconductor memory 4, for example, the number of times of writing.

As a specific method for determining the combination of the semiconductor memories 4, the representative distance between each semiconductor memory 4 and the control IC 5 can be used to determine the combination optimization from the viewpoint of combination optimization. In the k-th semiconductor memory device 10, the representative distance from the control IC 5 to each semiconductor memory 4 is d ki (k = 1... n, i = 1... 8), and 1 to 8 of the semiconductor memory device A. B (i), C (i),..., N (i) (B (i), C (i) are combinations of semiconductor memories of other semiconductor storage devices that store data in combination with the semiconductor memory 4. ,..., N (i) ε {1... 8}, i = 1... 8), the method for determining the combination is reduced to solving the following optimization problem.

min. f represents minimizing the function f.

  Equation (1) can be solved by a general optimization algorithm such as a genetic algorithm. FIG. 4 shows a state in which the order of the semiconductor memories 4 is rearranged in consideration of combinations of the semiconductor memories 4 that record data in a distributed manner. As shown in FIG. 4, the RAID system 100 includes N semiconductor memory devices 10, and each semiconductor memory device 10 is equipped with eight semiconductor memories 4. In the semiconductor memory devices B to N, the semiconductor memory devices 4 are arranged in a state where the semiconductor memory devices 4 are rearranged by the optimization algorithm. Data is distributed and recorded as shown in FIG. 5 for the optimized combination of semiconductor memories 4 in FIG. As shown in FIG. 5, for the semiconductor memory A1 that records the distributed data a1, the distributed data b1 is recorded in the semiconductor memory B (1) selected as a combination, and the semiconductor memory C (1) selected as the combination is recorded. Distributed data c1. The distributed data n1 is recorded in the same manner.

According to the present embodiment, since the mechanical load such as heat received from the control IC or the like is considered in the combination of the semiconductor memories that record the distributed data, the risk of data loss can be reduced (second embodiment). )
As a second embodiment according to the present invention, a case of performing write optimization with respect to an external load or vibration will be described. As shown in FIG. 2, in the mounting substrate 1 in which the support portion (boss hole) 3 is formed, the load is transmitted to the mounting substrate 1 through the support portion 3 when a load or vibration is applied from the outside. The When a load is applied via the support part 3, generally, the curvature of the mounting substrate tends to increase as the distance from the support part 3 increases. A larger stress is generated at the solder joint between the semiconductor memory 4 and the mounting board 1 as the curvature of the mounting board 1 at the solder joint is larger.

  Therefore, in the second embodiment, data is distributed and stored so that the representative distances to the respective semiconductor memories 4 and the support portions 3 are averaged. As the representative distance, it is preferable to select the distance from the center of the support portion 3 to the center of each semiconductor memory 4 or the distance from the center of the support portion 3 to the solder joint portion of each semiconductor memory 4 that is closest. By setting the representative distance according to the above equation (1) and reducing it to the optimization problem, a combined solution can be obtained.

  A combination for averaging the representative distance can be determined when the semiconductor memory device 10 is designed. However, the combination prioritization can be changed at any time in consideration of information such as deterioration of the semiconductor memory 4, for example, the number of times of writing.

  Here, the flow of processing up to the determination of the combination of the semiconductor memories 4 in the first and second embodiments will be described with reference to FIG.

First, the position of the heat source and the boss hole to be the reference position is determined (step S61). Here, the heat source is the control IC 5 or the power source 8, and the boss hole is the support portion 3. A representative distance d KI to each semiconductor memory 4 is determined (step S62). The determination of the representative distance d ki is not limited to one method. Therefore, for example, it is preferable to determine as shown in FIG. FIG. 7 is a diagram for explaining how to determine the representative distance. As shown in FIG. 7, the shortest distance d ts from the control IC 5 serving as the heat source to the solder joint 9 of the semiconductor memory 4, the shortest distance d tc from the control IC 5 serving as the heat source to the center of the semiconductor memory 4, and the boss hole 3 from the shortest distance d ms to solder joint 9 of the semiconductor memory 4, may be either the shortest distance d mc from the boss hole 3 to the center portion of the semiconductor memory 4.

After determining the representative distance d ki , the optimization problem is solved to determine the combination of the semiconductor memories 4 (step S63). The determined combination of the semiconductor memories 4 is stored in the memory control unit 30 provided in the RAID system 100 (step S64).

(Third embodiment)
As a third embodiment according to the present invention, a damage value accumulated in a solder joint portion of each semiconductor memory 4 is estimated while measuring a physical state, and writing optimization is performed based on the estimated damage value. The case will be described. FIG. 8 is a block diagram showing a configuration of a RAID system 100 using the semiconductor memory device according to the third embodiment of the present invention. The RAID system 100 includes a plurality of semiconductor storage devices 10, a memory control unit 30, and a semiconductor memory selection unit 20, and is connected to a host device 200 as an external device. Furthermore, in the third embodiment, the fatigue characteristic database 50 is prepared in advance. In this fatigue characteristic database 50, for example, data representing the relationship between the strain range and the life of the solder joint 9 is accumulated. The database 50 uses the design information of the mounting substrate 1 and the information of the material used to perform a phenomenon analysis on the semiconductor memory device 10 on which the semiconductor memory 4 is mounted, and is generated at the solder joint 9. By predicting the load, it is possible to calculate and construct a relationship related to breakage of the solder joint 9.

  As described in the first embodiment and the second embodiment, the solder joint 9 is damaged by a mechanical load. When certain damage accumulates, the solder joint 9 is electrically disconnected due to fatigue. In the present embodiment, the damage value of the solder joint 9 of each semiconductor memory 4 is calculated by comparing the physical quantity measured by the sensor 7 with a separately stored fatigue characteristic database 50. Based on the information 51 on the damage value, the semiconductor memory selection unit 20 determines the combination of the semiconductor memories 4 into which the distributed data is written. The frequency of updating the combination of the semiconductor memories 4 may be the case of garbage collection timing in the semiconductor memory after each file write, after a certain period of use. Further, by replacing the representative distance calculated in the first and second embodiments with a damage value, a combination of the semiconductor memories 4 for distributing data can be obtained by solving an optimization problem.

  Here, the flow of processing up to the determination of the combination of the semiconductor memories 4 in the third embodiment will be described with reference to FIG.

First, information from the sensor 7 is acquired (step S91). The acquired sensor information is stored in the sensor information database 60 at regular intervals (step S92). In order to determine whether or not the combination of the semiconductor memories 4 needs to be updated, a combination update event is detected (step S93). If no combination update event has been detected, the process returns to step S91. If a combination update event has been detected, the sensor information database 60 in which sensor information is stored and the fatigue characteristic database 50 in which fatigue characteristics are stored are used. Then, the damage value of the solder joint portion 9 of each semiconductor memory 4 is calculated (step S94). Next, the damage value of the solder joint 9 having the largest damage value in each semiconductor memory 4 is set as the representative damage value d ki (step S95). From the representative damage value d ki , the optimization problem is solved to determine the combinations B (i)... N (i) of the semiconductor memory 4 (step S96). The determined combination of the semiconductor memories 4 is stored in the memory control unit 30 provided in the RAID system (step S97). Thereafter, the combination of data stored in each semiconductor memory 4 is updated (step S98), and the process returns to step S91.

(Fourth embodiment)
Next, a fourth embodiment according to the present invention will be described. FIG. 10 is a block diagram showing a configuration of a RAID system 100 using the semiconductor memory device according to the fourth embodiment. The RAID system 100 includes a plurality of semiconductor storage devices 10, a memory control unit 30, and a semiconductor memory selection unit 20, and is connected to a host device 200 as an external device. Further, in the fourth embodiment, a fatigue characteristic database 50 and a write count database 70 storing the write count information 71 to each semiconductor memory 4 are prepared in advance. In general, in the semiconductor memory 4, the number of recordings of the storage element is finite, and the storage element deteriorates after about several million times and writing becomes impossible. On the other hand, information is written or erased in units of blocks that are collections of storage elements. Therefore, the number of times of writing in a certain block is recorded separately, and used as a reference when determining the block to be written next, so that the number of times of writing is distributed and writing is prevented from concentrating on a specific block. .

Therefore, in the present embodiment, information on the deterioration of the storage element of each semiconductor memory 4 is taken into consideration, and both the total number of writing times of each semiconductor memory 4 and an index indicating the possibility of mechanical damage are used. Thus, the combination of the semiconductor memories 4 to be written is determined. For example, in the k-th semiconductor memory device 10, when the total number of writes in the i-th semiconductor memory 4 is d ki , the combination can be determined by an optimization problem such as the following equation (2).

α represents a positive constant. By determining the function g (D ki ) and the constant α, it is possible to balance mechanical damage and deterioration due to writing of the memory element. As an example, a function intended for averaging can be selected as in the case of mechanical damage, as in the following Expression (3).

  Here, the flow of processing up to the determination of the combination of the semiconductor memories 4 in the fourth embodiment will be described with reference to FIG.

First, information from the sensor 7 is acquired (step S111). The acquired sensor information is stored in the sensor information database 60 at regular intervals (step S112). In order to determine whether or not the combination of the semiconductor memories 4 needs to be updated, a combination update event is detected (step S113). If a combination update event is not detected, the process returns to step S111. If a combination update event is detected, a sensor information database 60 storing sensor information and a fatigue characteristic database 50 storing fatigue characteristics are used. Then, the damage value of the solder joint portion 9 of each semiconductor memory 4 is calculated (step S114). Next, the damage value of the solder joint 9 having the largest damage value in each semiconductor memory 4 is set as the representative damage value d ki (step S115). After determining the representative damage value d ki , from the semiconductor memory write count Dki stored in the semiconductor memory write count database 70, the optimization problem is solved and the combinations B (i)... N (i) of the semiconductor memories 4 are determined. Determination is made (step S116). The determined combination of semiconductor memories is stored in the memory control unit 30 provided in the RAID system 100 (step S117). Thereafter, the combination of data stored in each semiconductor memory 4 is updated (step S118), and the process returns to step S111.

  According to the present embodiment, the risk of data loss due to mechanical destruction caused by storing data in a specific combination of semiconductor memories in the RAID system 100 configured by semiconductor memory device arrays is reduced. Can do.

  Although several embodiments of the present invention have been described, these embodiments are presented by way of example and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms, and various omissions, replacements, and changes can be made without departing from the scope of the invention. These embodiments and modifications thereof are included in the scope and gist of the invention, and are included in the invention described in the claims and the equivalents thereof.

  DESCRIPTION OF SYMBOLS 1 ... Mounting board, 2 ... Connector, 3 ... Boss hole, 4 ... Semiconductor memory, 5 ... Control IC, 6 ... Capacitor, 7 ... Sensor, 8 ... Power source, 9 ... solder joint, 10 ... semiconductor memory device, 20 ... semiconductor memory selection unit, 30 ... memory control unit, 50 ... fatigue property database, 60 ... sensor information database , 70... Semiconductor memory write count database, 100... RAID system using semiconductor memory device, 200.

Claims (5)

  1. A RAID system using a semiconductor storage device that transfers data to and from a host device,
    A plurality of semiconductor memory devices each including a plurality of semiconductor memories;
    A semiconductor memory selection unit that selects a combination of the semiconductor memories when data is distributed and stored among the plurality of semiconductor storage devices;
    A memory control unit that accesses the semiconductor memory selected by the semiconductor memory selection unit according to a request of the host device;
    The semiconductor memory selection unit calculates a mechanical load received by the semiconductor memory in advance or when storing data, and selects the combination of the semiconductor memories so that the calculated load value is averaged. A RAID system using a semiconductor memory device.
  2.   2. The RAID using a semiconductor memory device according to claim 1, wherein the magnitude of the mechanical load is determined based on a distance between the semiconductor memory mounted on the mounting board and a heat source on the mounting board. system.
  3.   3. The semiconductor according to claim 2, wherein a distance between the semiconductor memory and a heat source on the mounting substrate is a shortest distance between the mounting substrate on which the semiconductor memory is mounted, a solder joint of the semiconductor memory, and the heat source. A RAID system using a storage device.
  4.   3. The RAID system using a semiconductor memory device according to claim 2, wherein the distance between the semiconductor memory and the heat source on the mounting substrate is the shortest distance between the center of the semiconductor memory and the heat source.
  5. A control method in a RAID system that performs data transfer with a host device and uses a plurality of semiconductor memory devices each including a plurality of semiconductor memories,
    When data is distributed and stored among the plurality of semiconductor memory devices, the mechanical load received by the semiconductor memory is calculated in advance or at the time of data storage, and the calculated load value is averaged. Select the combination of the semiconductor memories,
    A control method in a RAID system using a semiconductor memory device, wherein the selected semiconductor memory is accessed according to a request of the host device.
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JP2005174203A (en) * 2003-12-15 2005-06-30 Internatl Business Mach Corp <Ibm> Data transfer rate controller for performing setting related with memory access, information processor, control method, program and recording medium
JP2007102533A (en) * 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd Heat radiator for information processor
JP2008112452A (en) * 2006-10-30 2008-05-15 Intel Corp Memory module thermal management
JP2010170403A (en) * 2009-01-23 2010-08-05 Toshiba Corp Raid system using semiconductor memory device, and control method therefor

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2004240669A (en) * 2003-02-05 2004-08-26 Sharp Corp Job scheduler and multiprocessor system
JP2005174203A (en) * 2003-12-15 2005-06-30 Internatl Business Mach Corp <Ibm> Data transfer rate controller for performing setting related with memory access, information processor, control method, program and recording medium
JP2007102533A (en) * 2005-10-05 2007-04-19 Matsushita Electric Ind Co Ltd Heat radiator for information processor
JP2008112452A (en) * 2006-10-30 2008-05-15 Intel Corp Memory module thermal management
JP2010170403A (en) * 2009-01-23 2010-08-05 Toshiba Corp Raid system using semiconductor memory device, and control method therefor

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