JP2010529649A5 - - Google Patents
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- JP2010529649A5 JP2010529649A5 JP2010510379A JP2010510379A JP2010529649A5 JP 2010529649 A5 JP2010529649 A5 JP 2010529649A5 JP 2010510379 A JP2010510379 A JP 2010510379A JP 2010510379 A JP2010510379 A JP 2010510379A JP 2010529649 A5 JP2010529649 A5 JP 2010529649A5
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- 238000000034 method Methods 0.000 description 6
- 238000009792 diffusion process Methods 0.000 description 2
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US11/757,338 US7949985B2 (en) | 2007-06-01 | 2007-06-01 | Method for compensation of process-induced performance variation in a MOSFET integrated circuit |
| US11/757,338 | 2007-06-01 | ||
| PCT/US2008/051355 WO2008150555A1 (en) | 2007-06-01 | 2008-01-17 | Method for compensation of process-induced performance variation in a mosfet integrated circuit |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| JP2010529649A JP2010529649A (ja) | 2010-08-26 |
| JP2010529649A5 true JP2010529649A5 (https=) | 2013-02-21 |
| JP5261479B2 JP5261479B2 (ja) | 2013-08-14 |
Family
ID=40087455
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010510379A Active JP5261479B2 (ja) | 2007-06-01 | 2008-01-17 | Mosfet集積回路におけるプロセスによって誘起される性能変動の補償方法 |
Country Status (7)
| Country | Link |
|---|---|
| US (2) | US7949985B2 (https=) |
| EP (1) | EP2153239A4 (https=) |
| JP (1) | JP5261479B2 (https=) |
| KR (1) | KR101159305B1 (https=) |
| CN (1) | CN101675348A (https=) |
| TW (1) | TWI392028B (https=) |
| WO (1) | WO2008150555A1 (https=) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7949985B2 (en) * | 2007-06-01 | 2011-05-24 | Synopsys, Inc. | Method for compensation of process-induced performance variation in a MOSFET integrated circuit |
| US8176444B2 (en) * | 2009-04-20 | 2012-05-08 | International Business Machines Corporation | Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance |
| US20120042292A1 (en) * | 2010-08-10 | 2012-02-16 | Stmicroelectronics S.A. | Method of synthesis of an electronic circuit |
| US8776005B1 (en) | 2013-01-18 | 2014-07-08 | Synopsys, Inc. | Modeling mechanical behavior with layout-dependent material properties |
| US8832619B2 (en) * | 2013-01-28 | 2014-09-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Analytical model for predicting current mismatch in metal oxide semiconductor arrays |
| US9665675B2 (en) | 2013-12-31 | 2017-05-30 | Texas Instruments Incorporated | Method to improve transistor matching |
| CN105740572B (zh) * | 2016-02-26 | 2019-01-15 | 联想(北京)有限公司 | 一种电子设备 |
| EP3760196B1 (en) * | 2018-02-28 | 2024-12-18 | Petroeuroasia Co., Ltd. | Reduced coenzyme q10-containing composition and method for producing same |
| CN119997585B (zh) * | 2025-04-14 | 2025-07-22 | 合肥晶合集成电路股份有限公司 | 一种半导体器件的制作方法 |
Family Cites Families (32)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3882391A (en) * | 1973-06-25 | 1975-05-06 | Ibm | Testing the stability of MOSFET devices |
| US4138666A (en) * | 1977-11-17 | 1979-02-06 | General Electric Company | Charge transfer circuit with threshold voltage compensating means |
| US5412263A (en) * | 1992-09-30 | 1995-05-02 | At&T Corp. | Multiple control voltage generation for MOSFET resistors |
| KR970001564U (ko) * | 1995-06-21 | 1997-01-21 | 자동차용 후부차체의 보강구조 | |
| US5748534A (en) * | 1996-03-26 | 1998-05-05 | Invox Technology | Feedback loop for reading threshold voltage |
| JPH1074843A (ja) * | 1996-06-28 | 1998-03-17 | Toshiba Corp | 多電源集積回路および多電源集積回路システム |
| EP0919121A4 (en) * | 1996-07-08 | 2000-11-22 | Dnavec Research Inc | IN VIVO ELECTROPORATION METHOD FOR ANIMAL EARLY EMBRYONS |
| US6287926B1 (en) * | 1999-02-19 | 2001-09-11 | Taiwan Semiconductor Manufacturing Company | Self aligned channel implant, elevated S/D process by gate electrode damascene |
| JP3324588B2 (ja) * | 1999-12-22 | 2002-09-17 | 日本電気株式会社 | 半導体装置及びその製造方法 |
| US6598214B2 (en) * | 2000-12-21 | 2003-07-22 | Texas Instruments Incorporated | Design method and system for providing transistors with varying active region lengths |
| US20040038489A1 (en) | 2002-08-21 | 2004-02-26 | Clevenger Lawrence A. | Method to improve performance of microelectronic circuits |
| JP4408613B2 (ja) * | 2002-09-25 | 2010-02-03 | Necエレクトロニクス株式会社 | トランジスタの拡散層長依存性を組み込んだ回路シミュレーション装置およびトランジスタモデル作成方法 |
| US6928635B2 (en) * | 2002-09-25 | 2005-08-09 | Numerical Technologies, Inc. | Selectively applying resolution enhancement techniques to improve performance and manufacturing cost of integrated circuits |
| JP4202120B2 (ja) * | 2002-12-27 | 2008-12-24 | セイコーインスツル株式会社 | 集積回路の最適化設計装置 |
| US7487474B2 (en) * | 2003-01-02 | 2009-02-03 | Pdf Solutions, Inc. | Designing an integrated circuit to improve yield using a variant design element |
| JP2004241529A (ja) * | 2003-02-05 | 2004-08-26 | Matsushita Electric Ind Co Ltd | 半導体回路装置及びその回路シミュレーション方法 |
| US7263477B2 (en) * | 2003-06-09 | 2007-08-28 | Cadence Design Systems, Inc. | Method and apparatus for modeling devices having different geometries |
| JP2005166741A (ja) * | 2003-11-28 | 2005-06-23 | Sharp Corp | 半導体記憶素子の特性評価方法及びモデルパラメータ抽出方法 |
| US20050144576A1 (en) * | 2003-12-25 | 2005-06-30 | Nec Electronics Corporation | Design method for semiconductor circuit device, design method for semiconductor circuit, and semiconductor circuit device |
| US7174532B2 (en) * | 2004-11-18 | 2007-02-06 | Agere Systems, Inc. | Method of making a semiconductor device by balancing shallow trench isolation stress and optical proximity effects |
| JP4833544B2 (ja) * | 2004-12-17 | 2011-12-07 | パナソニック株式会社 | 半導体装置 |
| JP2006178907A (ja) * | 2004-12-24 | 2006-07-06 | Matsushita Electric Ind Co Ltd | 回路シミュレーション方法および装置 |
| US7441211B1 (en) * | 2005-05-06 | 2008-10-21 | Blaze Dfm, Inc. | Gate-length biasing for digital circuit optimization |
| JP2006329824A (ja) * | 2005-05-26 | 2006-12-07 | Matsushita Electric Ind Co Ltd | 回路シミュレーション方法 |
| US7337420B2 (en) * | 2005-07-29 | 2008-02-26 | International Business Machines Corporation | Methodology for layout-based modulation and optimization of nitride liner stress effect in compact models |
| KR100628247B1 (ko) * | 2005-09-13 | 2006-09-27 | 동부일렉트로닉스 주식회사 | 반도체 소자 |
| JP2007123442A (ja) * | 2005-10-26 | 2007-05-17 | Matsushita Electric Ind Co Ltd | 半導体回路装置、その製造方法及びそのシミュレーション方法 |
| US7716612B1 (en) * | 2005-12-29 | 2010-05-11 | Tela Innovations, Inc. | Method and system for integrated circuit optimization by using an optimized standard-cell library |
| JP4922623B2 (ja) * | 2006-02-22 | 2012-04-25 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
| US7321139B2 (en) * | 2006-05-26 | 2008-01-22 | Taiwan Semiconductor Manufacturing Co., Ltd. | Transistor layout for standard cell with optimized mechanical stress effect |
| US7761278B2 (en) * | 2007-02-12 | 2010-07-20 | International Business Machines Corporation | Semiconductor device stress modeling methodology |
| US7949985B2 (en) | 2007-06-01 | 2011-05-24 | Synopsys, Inc. | Method for compensation of process-induced performance variation in a MOSFET integrated circuit |
-
2007
- 2007-06-01 US US11/757,338 patent/US7949985B2/en not_active Expired - Fee Related
-
2008
- 2008-01-17 EP EP08713812A patent/EP2153239A4/en not_active Withdrawn
- 2008-01-17 KR KR1020097022852A patent/KR101159305B1/ko active Active
- 2008-01-17 WO PCT/US2008/051355 patent/WO2008150555A1/en not_active Ceased
- 2008-01-17 JP JP2010510379A patent/JP5261479B2/ja active Active
- 2008-01-17 CN CN200880014239A patent/CN101675348A/zh active Pending
- 2008-01-23 TW TW097102499A patent/TWI392028B/zh active
-
2011
- 2011-05-20 US US13/112,837 patent/US8219961B2/en active Active
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