JP2010529649A5 - - Google Patents

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JP2010529649A5
JP2010529649A5 JP2010510379A JP2010510379A JP2010529649A5 JP 2010529649 A5 JP2010529649 A5 JP 2010529649A5 JP 2010510379 A JP2010510379 A JP 2010510379A JP 2010510379 A JP2010510379 A JP 2010510379A JP 2010529649 A5 JP2010529649 A5 JP 2010529649A5
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JP2010510379A
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JP2010529649A (ja
JP5261479B2 (ja
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JP2010510379A 2007-06-01 2008-01-17 Mosfet集積回路におけるプロセスによって誘起される性能変動の補償方法 Active JP5261479B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US11/757,338 US7949985B2 (en) 2007-06-01 2007-06-01 Method for compensation of process-induced performance variation in a MOSFET integrated circuit
US11/757,338 2007-06-01
PCT/US2008/051355 WO2008150555A1 (en) 2007-06-01 2008-01-17 Method for compensation of process-induced performance variation in a mosfet integrated circuit

Publications (3)

Publication Number Publication Date
JP2010529649A JP2010529649A (ja) 2010-08-26
JP2010529649A5 true JP2010529649A5 (https=) 2013-02-21
JP5261479B2 JP5261479B2 (ja) 2013-08-14

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JP2010510379A Active JP5261479B2 (ja) 2007-06-01 2008-01-17 Mosfet集積回路におけるプロセスによって誘起される性能変動の補償方法

Country Status (7)

Country Link
US (2) US7949985B2 (https=)
EP (1) EP2153239A4 (https=)
JP (1) JP5261479B2 (https=)
KR (1) KR101159305B1 (https=)
CN (1) CN101675348A (https=)
TW (1) TWI392028B (https=)
WO (1) WO2008150555A1 (https=)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7949985B2 (en) * 2007-06-01 2011-05-24 Synopsys, Inc. Method for compensation of process-induced performance variation in a MOSFET integrated circuit
US8176444B2 (en) * 2009-04-20 2012-05-08 International Business Machines Corporation Analyzing multiple induced systematic and statistical layout dependent effects on circuit performance
US20120042292A1 (en) * 2010-08-10 2012-02-16 Stmicroelectronics S.A. Method of synthesis of an electronic circuit
US8776005B1 (en) 2013-01-18 2014-07-08 Synopsys, Inc. Modeling mechanical behavior with layout-dependent material properties
US8832619B2 (en) * 2013-01-28 2014-09-09 Taiwan Semiconductor Manufacturing Co., Ltd. Analytical model for predicting current mismatch in metal oxide semiconductor arrays
US9665675B2 (en) 2013-12-31 2017-05-30 Texas Instruments Incorporated Method to improve transistor matching
CN105740572B (zh) * 2016-02-26 2019-01-15 联想(北京)有限公司 一种电子设备
EP3760196B1 (en) * 2018-02-28 2024-12-18 Petroeuroasia Co., Ltd. Reduced coenzyme q10-containing composition and method for producing same
CN119997585B (zh) * 2025-04-14 2025-07-22 合肥晶合集成电路股份有限公司 一种半导体器件的制作方法

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US6598214B2 (en) * 2000-12-21 2003-07-22 Texas Instruments Incorporated Design method and system for providing transistors with varying active region lengths
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JP4408613B2 (ja) * 2002-09-25 2010-02-03 Necエレクトロニクス株式会社 トランジスタの拡散層長依存性を組み込んだ回路シミュレーション装置およびトランジスタモデル作成方法
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US7321139B2 (en) * 2006-05-26 2008-01-22 Taiwan Semiconductor Manufacturing Co., Ltd. Transistor layout for standard cell with optimized mechanical stress effect
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US7949985B2 (en) 2007-06-01 2011-05-24 Synopsys, Inc. Method for compensation of process-induced performance variation in a MOSFET integrated circuit

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