JP2010283817A - Galvanic isolator - Google Patents

Galvanic isolator Download PDF

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JP2010283817A
JP2010283817A JP2010126041A JP2010126041A JP2010283817A JP 2010283817 A JP2010283817 A JP 2010283817A JP 2010126041 A JP2010126041 A JP 2010126041A JP 2010126041 A JP2010126041 A JP 2010126041A JP 2010283817 A JP2010283817 A JP 2010283817A
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Prior art keywords
coil
pulse
galvanic isolator
circuit
pad
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JP2010126041A
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JP5456583B2 (en
Inventor
Richard A Baumgartner
Julie E Fouquet
Gek Yong Ng
ゲク・ヨン・ウー
ジュリー・イー・フーケ
リチャード・エイ・バウムガートナー
Original Assignee
Avago Technologies Ecbu Ip (Singapore) Pte Ltd
アバゴ・テクノロジーズ・イーシービーユー・アイピー(シンガポール)プライベート・リミテッド
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Priority to US12/477,078 priority Critical patent/US8385043B2/en
Priority to US12/477,078 priority
Application filed by Avago Technologies Ecbu Ip (Singapore) Pte Ltd, アバゴ・テクノロジーズ・イーシービーユー・アイピー(シンガポール)プライベート・リミテッド filed Critical Avago Technologies Ecbu Ip (Singapore) Pte Ltd
Publication of JP2010283817A publication Critical patent/JP2010283817A/en
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B5/00Near-field transmission systems, e.g. inductive loop type
    • H04B5/0025Near field system adaptations
    • H04B5/005Near field system adaptations for isolation purposes
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00Fixed transformers or mutual inductances of the signal type
    • H01F19/04Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00Fixed transformers or mutual inductances of the signal type
    • H01F19/04Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • H01F19/08Transformers having magnetic bias, e.g. for handling pulses
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/28Coils; Windings; Conductive connections
    • H01F27/2804Printed windings
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45179Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using MOSFET transistors as the active amplifying circuit
    • H03F3/45183Long tailed pairs
    • H03F3/45192Folded cascode stages
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F3/00Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/45Differential amplifiers
    • H03F3/45071Differential amplifiers with semiconductor devices only
    • H03F3/45076Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
    • H03F3/45475Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using IC blocks as the active amplifying circuit
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H11/00Networks using active elements
    • H03H11/02Multiple-port networks
    • H03H11/26Time-delay networks
    • H03H11/265Time-delay networks with adjustable delay
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/52One-way transmission networks, i.e. unilines
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04BTRANSMISSION
    • H04B5/00Near-field transmission systems, e.g. inductive loop type
    • H04B5/0075Near-field transmission systems, e.g. inductive loop type using inductive coupling
    • H04B5/0093Near-field transmission systems, e.g. inductive loop type using inductive coupling with one coil at each side, e.g. with primary and secondary coils
    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00Baseband systems
    • H04L25/02Details ; Arrangements for supplying electrical power along data transmission lines
    • H04L25/0264Arrangements for coupling to transmission lines
    • H04L25/0266Arrangements for providing Galvanic isolation, e.g. by means of magnetic or capacitive coupling
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type
    • H01F17/0006Printed inductances
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F17/00Fixed inductances of the signal type
    • H01F17/0006Printed inductances
    • H01F17/0013Printed inductances with stacked layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F19/00Fixed transformers or mutual inductances of the signal type
    • H01F19/04Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range
    • H01F19/08Transformers having magnetic bias, e.g. for handling pulses
    • H01F2019/085Transformer for galvanic isolation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F27/00Details of transformers or inductances, in general
    • H01F27/40Structural association with built-in electric component, e.g. fuse
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01FMAGNETS; INDUCTANCES; TRANSFORMERS; SELECTION OF MATERIALS FOR THEIR MAGNETIC PROPERTIES
    • H01F38/00Adaptations of transformers or inductances for specific applications or functions
    • H01F38/14Inductive couplings
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45Indexing scheme relating to differential amplifiers
    • H03F2203/45008Indexing scheme relating to differential amplifiers the addition of two signals being made by a resistor addition circuit for producing the common mode signal
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45Indexing scheme relating to differential amplifiers
    • H03F2203/45101Control of the DC level being present
    • HELECTRICITY
    • H03BASIC ELECTRONIC CIRCUITRY
    • H03FAMPLIFIERS
    • H03F2203/00Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
    • H03F2203/45Indexing scheme relating to differential amplifiers
    • H03F2203/45586Indexing scheme relating to differential amplifiers the IC comprising offset generating means

Abstract

<P>PROBLEM TO BE SOLVED: To provide a galvanic isolator adapted to improve resistance to electric noise. <P>SOLUTION: The galvanic isolator includes a substantially planar, electrically insulating substrate with opposing first and second surfaces, the substrate including an electrically insulating, low dielectric loss material and having a transmitter coil disposed on the first surface and a receiving coil disposed on the second surface. A transmitter circuit is operably connected to the transmitter coil. The transmitter circuit includes a first detector that detects a rising edge of an input signal, a first pulse generator that generates a plurality of first pulses upon detection of the rising edge, a second detector that detects a falling edge of the input signal, and a second pulse generator that generates a plurality of second pulses upon detection of the falling edge. A receiver circuit is operably connected to the second receiving coil. The receiver circuit generates a signal that is substantially similar to the input signal based on the first pulses and the second pulses. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

RELATED APPLICATIONS This application claims the priority and other benefits of US patent application Ser. No. 12 / 059,979 filed Mar. 31, 2008 (titled “Galvanic Isolators and Coil Transducers”). And it is a continuation-in-part of the same application. No. 11 / 512,034 filed Aug. 28, 2006 (subject “Improved Galvanic Isolator”, Fouquet et al.) And U.S. patent filed May 10, 2007. This is a continuation-in-part of application No. 11 / 747,092 (subject “Miniature Transformers Adapted for Use in Galvanic Isolators and the Like”, Fouquet et al.). In addition, this application is based on US patent application Ser. No. 12 / 059,747 filed on the same day as the present application (subject to “Coil Transducer with Reduced Arcing and Improved High Voltage Performance Characteristic” et al.). To form part of this specification.

  High voltage insulation communication elements known in the prior art include optical elements, magnetic elements, and capacitive elements. Prior art optical devices typically transmit and receive optical signals by using LEDs and corresponding photodiodes to achieve high voltage isolation, usually requiring high power levels, and multiple communication channels There is an operational and design constraint when it is necessary.

  Prior art magnetic elements typically achieve high voltage isolation using opposing inductive coupling coils and typically require high power levels (especially when high data rates are required) Requires the use of at least three separate integrated circuits or chips, and is often subject to electromagnetic interference (“EMI”).

  The capacitive element of the prior art achieves voltage insulation using a plurality of transmission / reception electrode pairs, for example, performs transmission / reception of data using the first electrode pair and refreshes a transmission signal using the second electrode pair or Do maintenance. Such capacitive elements typically have poor high voltage holdoff (or high voltage breakdown) characteristics.

  Designing a small, high-speed galvanic isolator has a number of technical challenges, for example, electromagnetic interference (EMI) and large-scale while maintaining high voltage breakdown characteristics and acceptable data (or power) transfer rates. There are challenges such as how to deal with fast transitions in amplitude and other forms of electrical noise.

  What is needed is a high voltage insulation communication element that is compact, consumes less power, can transmit data at a relatively high data rate, and improves high voltage breakdown performance. It is a high voltage isolated communication element that can be manufactured at a lower cost or has other advantages that will become apparent upon reading and understanding the present specification and accompanying drawings.

  A galvanic isolator is disclosed herein. One embodiment of a galvanic isolator includes a substantially planar, electrically insulating substrate that includes opposing first and second surfaces, the substrate having electrical insulation and low dielectric loss. The transmitter coil is disposed on the first surface and the receiver coil is disposed on the second surface. A transmitter circuit is operatively connected to the transmitter coil. The transmission circuit detects a rising edge of the input signal, a first pulse generator that generates a plurality of first pulses when the rising edge is detected, and a falling edge of the input signal. A second detector, and a second pulse generator for generating a plurality of second pulses upon detection of a falling edge. A receiving circuit is operatively connected to the second receiving coil. The receiving circuit generates a signal substantially similar to the input signal based on the first pulse and the second pulse.

  Various aspects of various embodiments of the invention will become apparent from the following specification, drawings, and claims.

It is a figure which shows one Embodiment of a galvanic isolator. It is a figure which shows one Embodiment of a galvanic isolator. FIG. 2 is a top plan view of an embodiment of a coil configuration of the isolator of FIG. 1. FIG. 6 is a perspective view of another embodiment of the coil configuration of the isolator of FIG. 1. It is a top view of the coil structure of FIG. It is a plot of S 21 characteristics of the coil arrangement of FIG. FIG. 4 is a plot of S 21 characteristics of the coil configuration of FIG. 3. 1 is a block diagram of one embodiment of a galvanic isolator including a power transformer and a data transformer. FIG. 3 illustrates one embodiment of a galvanic isolator package. FIG. 3 illustrates one embodiment of a galvanic isolator package. FIG. 6 illustrates another embodiment of a galvanic isolator package. FIG. 6 illustrates yet another embodiment of a galvanic isolator package. FIG. 3 is a schematic diagram illustrating one embodiment of data transfer via a galvanic isolator. It is a figure which shows one Embodiment of the data signal input into the galvanic isolator of FIG. FIG. 14 is a timing diagram illustrating an embodiment of signals output by the positive pulse generator and the negative pulse generator of FIG. 13. FIG. 14 is a schematic diagram of one embodiment of the edge detector of FIG. 13. It is the schematic of the circuit used for the pulse generator of FIG. FIG. 18 is a schematic diagram of an embodiment of a driver disposed between the circuit of FIG. 17 and a transmission coil. It is a figure which shows one Embodiment of a common mode removal circuit. FIG. 3 is a detailed view of one embodiment of a two-stage common mode amplifier. FIG. 3 is a diagram illustrating a circuit configured to separate voltage levels into gate drive for PMOS output elements and gate drive for NMOS output elements. FIG. 3 shows a sequence of pulses transmitted and received at various portions of a deployed circuit in one embodiment of a galvanic isolator 20. FIG. 3 is a block diagram of an embodiment of the receiving circuit 22 of FIG. 2. FIG. 23 is a schematic diagram of an embodiment of the preamplifier of FIG. 22. FIG. 24 is a schematic diagram of an embodiment of the amplifier of FIG. FIG. 23 is a schematic diagram of one embodiment of the comparator of FIG. FIG. 26 is a schematic diagram of an embodiment of the delay element of FIG. 25. FIG. 23 is a schematic diagram of an embodiment of the decoder of FIG.

  The drawings are not necessarily to scale. Unless otherwise noted, like reference numerals refer to like elements or steps throughout the drawings.

  In the following, specific details will be described so that a sufficient understanding can be obtained about galvanic isolators and various embodiments of circuits for transmitting and receiving signals using galvanic isolators. However, one of ordinary skill in the art, after reading and understanding the specification, claims, and accompanying drawings, describes several embodiments of the present invention as described in the specific embodiments described herein. It will be understood that it may be practiced without following some of the details. Moreover, in order to avoid obscuring the present invention, some well-known circuits, materials, and methods applied in the present invention are not disclosed in detail herein.

  The drawings illustrate some, but not all, possible embodiments of the invention, which may not be to scale.

  As used herein, the term “horizontal” is defined as a plane substantially parallel to a plane or surface in the normal sense, regardless of the actual orientation of the substrate of the present invention in space. ing. The term “vertical” means a direction substantially perpendicular to the horizontal defined above. “On”, “above”, “below”, “bottom”, “top”, “side”, “sidewall” ) "," Higher "," lower "," upper "," over "," under ", etc. It is defined with reference to the horizontal plane.

  Referring to FIGS. 1 and 2, substrate 33, coil transducer 39, coil 23, and coil 24 form a high voltage insulated data signal transfer element or power transformer element, which is referred to herein as a galvanic isolator 20. Called. Depending on the case, the coil 23 is referred to as a first coil or a transmission coil, and the coil 24 is referred to as a second coil or a reception coil. As shown in FIG. 2, the transmit coil 23 is separated from the receive coil 24 by at least some portions of the substrate 33, the transmit coil 23 and the receive coil 24 having a gap or dielectric barrier disposed therebetween. Beyond that, it is spatially arranged and configured in such an interrelationship that at least one of a power signal and a data signal can be transmitted from the transmitting coil 23 to the receiving coil 24. It includes a low dielectric loss material that is non-metallic and non-semiconductor, and at least some portions of the substrate 33 are formed from this dielectric barrier. In one embodiment, such a dielectric barrier includes a coil transducer 39 that includes a substrate 33 and electrically insulating layers 34 and 37 disposed above and below the substrate 33. The input circuit or transmission circuit 21 is operatively connected to the first coil (transmission coil) 23, and the output circuit or reception circuit 22 is operatively connected to the second coil (reception coil) 24.

  The coil transducer 39 and the substrate 33 disposed therein can include some of several types of non-metallic, non-semiconductor, low dielectric loss materials, which will be described in detail later. In a preferred embodiment, the coil transducer 39 and the substrate 33 can withstand a potential difference of several kilovolts between the input side and output side of the isolator 20 and thus exhibit high voltage breakdown performance characteristics.

  The transmission circuit 21 converts the incoming signal waveform into a signal having a waveform suitable for driving the primary transmission coil 23. The receiving circuit 22 is configured to return the signal output from the secondary receiving coil 24 to a waveform like the incoming signal. The transmitter circuit 21, the receiver circuit 22, and the coil transducer 39 are preferably packaged in a format compatible with standard electronic component assembly methods (eg, printed circuit board assembly methods). In some embodiments, the packaging includes sacrificial metal leads by mounting the various components of the galvanic isolator 20 to a lead frame, wire bonding the components together, and enclosing them with mold material. After being separated from the lead frame and formed as standard integrated circuit leads, all are secured together. For magnetic transducers, the lead frame design is important to avoid performance degradation of the galvanic isolator 20.

  As shown in FIGS. 1 and 2, the galvanic isolator 20 includes a transmitter circuit 21 and a receiver circuit 22, which in one embodiment include coils 23 and 24 disposed on opposing top and bottom surfaces of a substrate 33, respectively. Contains. In another embodiment, the coils 23 and 24 are disposed on the same surface of the substrate 33.

  In the embodiment shown in FIGS. 1 and 2, circuits 21 and 22 are connected to bond pads 37, 38, and 47 on the top surface of layer 34. Alternatively, the transmitter circuit 21 and the receiver circuit 22 can be attached to a lead frame and connected to bond pads attached to the coils 23 and 24 by wire bonds. Other packaging embodiments are also contemplated. In one embodiment, the coils 23 and 24 are made by lithographically patterning a metal layer on the surface of the substrate 33, although various other methods of forming the coils 23 and 24 are anticipated. For example, there is a method in which the coils are arranged in separate layers or substrates and the substrates or layers are stacked together. Alternatively, a layer or substrate that is electrically insulating, non-metallic, non-semiconductor, and has low dielectric loss can be placed under the coils 23 and 24. In the preferred embodiment, the transmission circuit 21 and the reception circuit 22 are integrated circuits or chips.

  The substrate 33 and / or the coil transducer 39 is formed from a suitable material that is electrically insulating, non-metallic, non-semiconductor, and has low dielectric loss. In one embodiment, such suitable materials have a dielectric loss tangent at room temperature of less than about 0.05, or less than about 0.01, or less than about 0.001, or less than about 0.0001. Even when the material used to form the substrate 33 of the present invention is a non-semiconductor material, the inventors of the present invention know the value of dielectric loss tangent associated with the material in the present specification for the novel substrate material of the present invention. It is defined to be equivalent to the semiconductor material. For details on dielectric loss tangent and associated material-specific and non-material-specific losses, see “Loss Characteristics of Silicon Substrate with Different Resistivities” (Yang et al., Pp. 1773-76, vol. 48). 9, Sept 2006, Microwave and Optical Technology Letters). Yang et al. Divide the dielectric loss into a loss tangent inherent to silicon and a non-material specific loss related to the leakage loss of the substrate, and discuss theoretically and experimentally, not material specific as the doping level of silicon increases. This demonstrates that losses also increase.

  Some (but not limited) examples of materials suitable for forming the substrate 33 and / or the coil transducer 39 include FR4 as a printed circuit board material and glass fiber, glass, ceramic, polyimide, as other printed circuit board materials, One or more of polyimide thin films, polymer, organic material, organic filler (such as epoxy) and inorganic solid (such as glass) combination, epoxy as flex circuit material, epoxy resin, plastic as printed circuit board material , DUPONT (TM) KAPTON (TM), DUPONT (TM) PYRALUX AB (TM) laminates and ROGERS (TM) materials such as PTFE (polytetrafluoroethylene) and glass, PTFE and ceramic, PTFE and glass Graphics and ceramic or thermosetting plastic, may also be mentioned. The specific choice of material for forming the substrate 33 generally depends on the cost, the degree or amount of electrical or voltage breakdown protection required, the specific application at hand, and other factors. Or it depends on what you need to consider. For example, a glass substrate or a ceramic substrate is suitable for applications involving high voltage. A flex circuit board may be used to reduce manufacturing and processing costs.

  In some embodiments, the substrate 33 has sufficient thickness between the upper and lower horizontal planes to withstand the relatively high breakdown voltages that are designed for the galvanic isolator 20 and the coil transducer 39, and appropriate electrical isolation. Has characteristics. For example, in one embodiment, the breakdown voltage between the transmit coil 23 and the receive coil 24 exceeds approximately 2000 volts RMS when applied for approximately 1 minute. In other embodiments, the breakdown voltage between the transmit coil 23 and the receive coil 24 is greater than about 2000 volts RMS when applied over 6 minutes or 24 hours. In other embodiments, the coil transducer 39, the substrate 33, and the galvanic isolator 20 can withstand higher breakdown voltages, eg, about 2500 for about 1 minute, 6 minutes, and / or 24 hours. It can withstand volt RMS, about 3000 volt RMS, about 4000 volt RMS, and about 5000 volt RMS.

  In some embodiments, the thickness between the upper and lower horizontal surfaces of the substrate 33 and / or the coil transducer 39 ranges from about 0.5 mil to about 10 mil (about 0.0127 mm to about 0.254 mm), or about 0.5 mil. It is in the range of about 25 mils (about 0.0127 mm to about 0.635 mm). In one embodiment, the thickness of substrate 33 and / or coil transducer 39 is greater than about 1.5 mils. In another embodiment, the substrate 33 and / or the coil transducer 39 includes multiple layers, at least one of which includes a low dielectric loss material. As can be seen, the coil transducer 39 is generally thicker than the substrate 33. For example, in one embodiment, the thickness of the coil transducer 39 is 19 mils (0.4826 mm) and the thickness of the substrate 33 disposed therein is 10 mils (0.254 mm).

  Still referring to FIGS. 1 and 2, each of the coils 23 and 24 has an outer end and an inner end. Each of these ends is connected to an appropriate terminal of the transmitter circuit or receiver circuit associated with it. In one embodiment, in each coil, the first electrical connection uses the first pattern formed by the first coil when the metal layer patterning the first coil is etched. And a second electrical connection is established with the first coil using a patterned metal layer on the outer surface of the coil transducer 39. For example, the electrical connection to the inner end 26 of the transmitter coil 23 passes through the pattern 25 disposed on the top surface of the electrically insulating layer 34, and a vertical via to the lower conductor 26 (forming the transmitter coil 23). 35 established. Similarly, electrical connection to the outer end of the transmit coil 23 is established through a pattern 27 disposed within the electrically insulating layer 34 and through a vertical via 36 to an upper bond pad 47. Electrical connection to the outer end of the transmission coil 23 is made through a pattern 27, and the pattern 27 can be patterned from the same layer as the transmission coil 23. The pattern 27 is electrically connected to the circuit 22 by a via 36 disposed through the layer 34. The circuit 21 is electrically connected to the outer end of the receiving coil 24 by the pattern 29 and the via 30. The pattern 29 can be patterned with the same metal layer as the receiving coil 24. The inner end of the receiving coil 24 is electrically connected to the circuit 21 by a pattern 28 and a via 31 disposed on the bottom surface of the electrical insulating layer 37. In order to avoid establishing electrical contact between the patterns 25 and 28 and any external conductors or surfaces that could otherwise come into contact with the patterns 25 and 28, An insulating layer can be added above or below, and the patterns 25 and 28 can be enclosed in the insulating layer (arranged inside the insulating layer).

  To facilitate the introduction of wire bonding technology into the manufacture of the galvanic isolator 20 or coil transducer 39, two different metal layers may be placed on a single substrate 33 to simplify the structure shown in FIGS. Is possible. In such an embodiment, the coil transducer 39 can be constructed from two metal layers that are arranged and patterned on both sides of the substrate 33. For example, the upper surface metal layer can be patterned so that the transmission coil 23 and various connection pads used by the transmission circuit 21 and the reception circuit 22 are provided on the upper surface of the substrate 33. In addition, the receiving coil 24 can be formed by using the bottom metal layer, and the receiving coil 24 is in the lower layer of the transmitting coil 23 and forms the second coil of the transformer on the bottom surface of the substrate 33. Further, it is possible to provide a pattern for connecting the receiving coil 24 and the wire bond pad disposed on the upper surface of the substrate 33 via a vertical via by patterning the bottom metal layer. By these, it is possible to connect the transmission coil 23 and the transmission circuit 21 with wire bonds, and it is possible to connect the reception coil 24 and the reception circuit 22 with patterns patterned from the upper surface metal layer and wire bonds. It is. In a preferred embodiment, the wire bond pad is electroplated. Various connection pads for connecting the coil transducer 39 to each of the external circuits insulated by the coil transducer 39 can also be patterned from the upper metal layer.

  In one embodiment, the structure shown in FIGS. 1 and 2 can be manufactured on a conventional printed circuit board production line. As a result, the manufacturing cost of the coil transducer 39 can be made much cheaper than when the coil transducer is made of silicon in the semiconductor manufacturing line. Also, the silicon substrate is a known conductor or semiconductor, but does not exhibit the low dielectric loss characteristics of the substrate and coil transducer of the present invention. It is particularly preferred to implement the coil transducer 39 using flexible organic and / or inorganic or organic substrates. Printed circuit boards or circuit carriers are known in the art and need not be described in detail here. However, it should be emphasized that forming the substrate 33 and coil transducer 39 of the present invention from a printed circuit board material is an excellent low-cost alternative to silicon-based materials. Printed circuit board materials are less expensive than silicon-based materials, are easier to handle, and are more amenable to sudden changes in design or manufacture. The printed circuit board manufacturing method will be described to the extent that it meets the purpose of this description. The printed circuit board is formed by depositing a thin metal layer on some flexible organic / inorganic substrate formed of glass fibers impregnated with epoxy resin ( Or by attaching a thin metal layer) and converting this metal layer into a plurality of individual conductors by conventional photolithography techniques. After covering this thin metal layer with an intervening electrically insulating layer or coating, it is possible to add further metal layers above the thin metal layer.

  It is also possible to form the substrate 33 and / or the coil transducer 39 of the galvanic isolator 20 using flex circuit technology, in which case the substrate 33 and / or the coil transducer 39 is made from an organic material such as polyimide. This type of thin film and laminate is commercially available from DUPONT ™ and uses a substrate material called KAPTON ™ made of polyimide. In some cases, the substrate 33 and / or the coil transducer 39 can be formed by laminating a plurality of polyimide layers with an adhesive. This type of circuit carrier or printed circuit board is significantly less expensive than those based on conventional silicon semiconductor materials, and is used to provide a substrate 33 and / or a high breakdown voltage and other desirable high voltage insulation properties. Alternatively, the coil transducer 39 can be realized. In applications where signal loss between the primary coil 23 and the secondary coil 24 must be minimized, the substrate 33 and / or coil transducer 39 is preferably thin. For example, in one embodiment of the substrate 33 and / or coil transducer 39, a KAPTON ™ substrate 33 having a thickness of 2 mils (0.0508 mm) using a PYRALUX AP ™ laminate made of DUPONT ™. Then, a conductive copper layer and a copper pattern are added to the top and bottom surfaces of the substrate 33.

  It should be noted that the coils 23 and 24 may have any of several different structural configurations, any of which are within the scope of the present invention. For example, the coils 23 and 24 may have the circular or elliptical spiral shape shown in FIGS. 1 and 2, or various other shapes (eg, rectangle, square, triangle, pentagon, hexagon, seven Square or octagonal wound shape), arranged as a horizontal plane, arranged as conductors sandwiched in the horizontal plane, arranged as one or more tortuous conductors in the horizontal plane, etc. It may be arranged in the style of Coils 23 and 24 may be of any suitable structural configuration so long as the magnetic field radiated from one coil can be received and detected satisfactorily by the other opposing coil.

  Hereinafter, two types of coil configurations having different bandwidths will be described. A first coil configuration 50 is shown in FIG. The coil configuration 50 includes both the transmission coil 23 and the reception coil 24. Coil configuration 50 represents a transmit coil 23 in two layers and a receive coil 24 in another two layers.

  The coil configuration 50 is an elliptical configuration and can occupy different layers within the substrate. In the embodiment of FIG. 3, the number of turns of the first layer (first metal) is 1 and 3/8. The number of turns of the second layer is 7/8. The first metal pattern and the second metal pattern are connected by the first via, and the first via pad 51 corresponding to the first via is shown in FIG. A second via pad corresponding to the first via may be disposed opposite the first via pad 51. A second via may connect the third metal and the fourth metal. The third via pad 57 corresponds to the second via. According to FIG. 3, the transmission coil 23 occupies two layers (metal). The reception coil 24 has the same configuration as the transmission coil 23 and occupies the third metal and the fourth metal. The isolation between the coil 23 and the coil 24 described above will therefore take place between the second metal and the third metal.

  In the embodiment of FIG. 3, the via pad diameter P is about 150 μm and the pattern width T is about 35 μm. There is an opening in the center of this coil configuration, the horizontal length OPX (as viewed from FIG. 3) of the opening is about 70 μm, and the vertical length OPY is about 35 μm. The length OPY shown in FIG. 3 is a length viewed from a direction substantially perpendicular to the galvanic isolator 20. However, since the length OPY spans between different layers, the actual length is longer than 35 μm. The length OPX / 2 is the distance between the two segments. The first segment is an tangential segment extending between the circumference of the via pad 51 and the circumference of the via pad 57, selected such that both the via pad 51 and the via pad 57 are located on the same side of the segment. The second segment is the inner edge of the nearest pattern shown. The length OPX is twice this distance. The bandwidth characteristics of the coil configuration 50 will be described in detail later. In one embodiment, the distance OPX / 2 is the shortest distance between these segments. In another embodiment, a second of these segments extends along at least a portion of the substantially linear pattern, the substantially linear pattern being the first segment relative to the other pattern. Located closest to.

  A second coil configuration 52 is shown in FIGS. 4 is a perspective view, and FIG. 5 is a plan view. The dimensions of the coil configuration 52 are the same as those of the coil configuration 50, except that the number of turns in the upper layer of the coil configuration 52 is 2 and 3/8. The number of turns of other metal layers has increased accordingly. As will be shown later, for the isolator 20 of FIG. 2, the number of coils provides various bandwidth characteristics.

The S parameters for coil configurations 50 and 52 are shown in the graphs of FIGS. The first plot 53 (FIG. 7) shows the S 21 characteristic of the first coil configuration 50. As shown in plot 53, a transmission peak appears at frequency f2. This peak is so wide that this coil transmission has a wide bandwidth. The second plot 54 (FIG. 6) shows the S 21 characteristic of the coil configuration 52. As shown, the peak frequency is at the lower f1, and the absolute value of the peak is larger. This peak is also wide, but the bandwidth is narrower than plot 53. That is, when the number of turns of the coil is increased, the absolute value of the transmission throughput is increased, but the peak frequency is lowered and the bandwidth is narrowed. Increasing the number of turns may be detrimental to coil design. In some embodiments, a coil configuration 52 is used in the galvanic isolator 20.

  In some embodiments, the galvanic isolator 20 can include a plurality of transformers, in which case the electronic and electrical components on one side of the substrate (insulation barrier) 33 are on the opposite side of the substrate 33. Power is supplied by the arranged power source. Next, referring to FIG. 8, the galvanic isolator 20 includes a power unit 150 and a data transfer unit 160. The data transfer unit 160 includes an insulation gap, which suppresses a transient phenomenon between a circuit arranged on the transmission side of the insulation gap and a circuit arranged on the reception side of the insulation gap, and / or Alternatively, voltage shift is performed.

  The galvanic isolator 20 uses two transformers. The transformer 162 provides an insulation barrier for data transfer between the transmission circuit 21 and the reception circuit 22. The transformer 153 is used to transfer power from the power supply 151 disposed on the transmission side of the insulation gap to the power supply 155 disposed on the reception side of the insulation gap.

  The power supply unit 150 includes an optional power supply 151 configured to supply power to circuits on both sides of the insulation gap. The inverter 152 generates an AC (or oscillating) power signal from the DC power supplied by the power source 151. This AC (or vibratory) power signal is transferred by the power transformer 153 to the receiving side of the insulation gap. The output of the secondary winding of the power transformer 153 is rectified by the converter 154 and supplied to the insulated power source 155 for feeding the reception circuit 22. The DC potential supplied from the power supplies 151 and 155 may or may not be the same depending on the design of the individual galvanic isolator and the immediate application. One advantage of various embodiments of the present invention is that power can be safely and conveniently supplied across the substrate 33 and / or the coil transducer 39, and thus the present invention is useful for medical applications and other electrical applications. It is suitable for an application where it is difficult or expensive to supply the insulated power. The power transformer 153 can increase or decrease the voltage to facilitate the generation of various output voltages. Alternatively, power can be extracted from a pulse train applied to the power transformer 153 from a power supply external to the galvanic isolator 20.

  Thus far, it has been understood that various embodiments of the galvanic isolator 20, the coil transducer 39, and the substrate 33 can be configured as a high voltage isolation data transfer device, a power transformer, or both. Further, as used herein, the term “transformer” or “transducer” refers to a power or data signal (or power signal and data signal) across a gap or dielectric barrier formed from an electrically insulating material. Note that this means a device capable of transmitting and receiving).

  Next, FIGS. 9 and 10 show a top view and a side view, respectively, of one embodiment of the galvanic isolator 20, where the input lead frame 71 and output lead frame 73 are in the lower layer, and the substrate 33 and coil transducer. It extends below a portion of 39. In the input lead frame 71 and the output lead frame 73, the conductive portion of the input lead frame 71 and the conductive portion of the output lead frame 73 are positioned directly below the transmitting coil 23 or the receiving coil 24 under the substrate 33 and the coil transducer 39. It is preferable to be connected to the coil transducer 39 so that it does not extend to the place where it is to be.

  In the embodiment shown in FIGS. 9 and 10, the input lead frame 71 and the output lead frame 73 are coiled so that the input lead frame 71 and the output lead frame 73 are mechanically connected to the underside of the coil transducer 39. A transducer 39 is connected. However, in another embodiment, the input lead frame 71 and the output lead frame 73 are mechanically connected to the opposing top and bottom surfaces of the coil transducer 39, for example, as shown in FIG.

If the metal layer is too close to the horizontal plane of each of the coils 23 and 24, the magnetic field lines transmitted or sensed by the coils 23 and 24 are disturbed, and the efficiency (throughput S 21 ) is reduced. Furthermore, the input lead frame 71 and the output lead frame 73 must be sufficiently separated to prevent the transmission circuit 21 and the reception circuit 22 from being electrically connected due to the occurrence of an arc. Therefore, when designing the lead frames 71 and 73, the input side of the lead frame extends to the extent that the bond pad is positioned on the lead frame under the coil transducer 39 so that wire bonding is easy. It is desirable not to extend as far as directly under 23 and 24. Therefore, the transmission circuit (integrated circuit) 21 or the inverter 152 can be mounted on the input side of the lead frame 71 immediately adjacent to the input side of the coil transducer 39, and the reception circuit (integrated circuit) 22 or the converter 154 can be mounted. Can be mounted on the output side of the lead frame 73, immediately adjacent to the output side of the coil transducer 39.

  Still referring to FIGS. 9 and 10, the potential difference between the lead frames 71 and 73 and the coil transducer 39 may be several kV, and in some embodiments, the lead frames 71 and 73 may be grounded or Note that it can be held near the ground. Mounting integrated circuits 21 and 22 to lead frames 71 and 73 is possible by using epoxies 68 and 69. In order to reduce the possibility of unnecessary short circuiting through the epoxy, the epoxies 68 and 69 are preferably non-conductive. The transmission circuit 21 is preferably wire bonded to the input side of the coil transducer 39 by wire bonds 41 and 48. The receiving circuit 22 is preferably wire bonded to the output side of the coil transducer 39 by wire bonds 42 and 43.

  As described above, the substrate 33 and / or the coil transducer 39 is preferably made to have a sufficient thickness between the respective top and bottom surfaces so that no high voltage arc is generated. As an advantage of the materials used to form the substrate 33 and / or coil transducer 39 of the present invention, the substrate 33 and / or coil transducer 39 is generally possible (or costly) for commercial applications using conventional semiconductor materials and manufacturing processes. (Thus possible), it can be considerably thicker. For example, the thickness of the substrate 33 and / or coil transducer 39 may be from about 1 mil to about 25 mils (about 0.0254 mm to about 0.635 mm), or from about 1.5 mils to about 25 mils (about 0.0381 mm to about 0.635 mm). ), Or in the range of about 2 mils to about 25 mils (about 0.0508 mm to about 0.635 mm). Polyimide processes that are compatible with silicon IC processes are typically much thinner than silicon IC processes and withstand voltages close to the high voltages that some embodiments of substrate 33 and / or coil transducer 39 can withstand. I can't. As a feature of some embodiments of the substrate 33 and coil transducer 39, the high insulation thickness (DTI) value provides desirable performance indicators in various electrical isolator applications and is mostly from the relevant standards bodies. The approval conditions are easily satisfied. Conversely, the substrate 33 and / or the coil transducer 39 can be made very thin (eg, below 0.5 mil (0.0127 mm)) and still provide relatively high voltage breakdown performance characteristics. It is possible.

  In addition, the substrate 33 and / or coil transducer 39 of the present invention may include several different manufacturing processes and the above-described materials that are electrically insulating, non-metallic, non-semiconductor, and low dielectric loss. Note that any can be used to form. These processes and materials are suitable for processing large amounts of electrically insulating materials and do not require the expensive and elaborate procedures required for processing semiconductor materials such as silicon. Furthermore, the substrate 33 and the coil transducer 39 of the present invention have high voltage breakdown characteristics superior to silicon-based devices due to their large insulator thickness (detailed). The substrate 33 and coil transducer 39 of the present invention have significantly greater insulation thickness and thickness compared to prior art galvanic isolators having a silicon substrate (typically limited to less than 1 mil (0.0254 mm) in thickness). As such, the substrate 33 can be configured to share substantial mechanical stiffness and strength with the coil transducer 39 and the galvanic isolator 20. Unlike prior art, relatively fragile and thin silicon substrates, the substrate 33 and coil transducer 39 of the present invention are mechanically robust and robust and can be mounted directly on a lead frame, with particular attention. It is possible to handle without.

  In addition, it is theoretically possible to create a substrate or coil transducer from a semiconductor material and form a conductor with a metallization layer on both sides, but such a structure is obtained when a substrate made of a semiconductor material is used. Because it is generally fragile, it is actually rarely seen (if at all). As a result, substrates or coil transducers formed from semiconductor materials are typically handled such that a metallization layer or other layer can only be formed on one side of such a substrate. On the other hand, in the substrate 33 and / or the coil transducer 39 of the present invention, coils or other parts can be easily formed or mounted on both sides of the substrate 33 and / or the coil transducer 39. This is because the manufacturing process for forming the substrate 33 and / or the coil transducer 39 and the nature of the materials used are essentially different.

  Still referring to FIGS. 9 and 10, by stacking multiple channels side by side along the long dimension of a package such as an SO-16 wide body, all channels share the same input lead frame and ground, Multiple channels can be housed in a single package so that all channels share the same output lead frame and ground.

  Next, FIG. 11 shows a flip lead frame arrangement for the dual galvanic isolator 20. Each of the integrated circuits 21 and 22 includes two channels. This design results in two channels, unlike the single channel configuration shown in FIGS. The lead frames 71 and 73 are designed to be flipped (inverted), as are the various optical isolator lead frames commonly used today. First, the integrated circuits 22a and 22b and the ends of the adjacent coil transducers 39a and 39b are attached to the corresponding portions of the lead frame 73 and wire-bonded. The integrated circuits 21 a and 21 b are attached to the lead frame 71. Next, the lead frame 73 is turned over to the position shown in FIG. 11, and the other ends of the coil transducers 39a and 39b are attached to the corresponding sides of the lead frame 71, and finally wire bonded together. Various other configurations are possible, as will be appreciated by those skilled in the art. For example, the dual channel element can be configured such that the transmission circuit chip 21 and the reception circuit chip 22 are separated for each channel.

  FIG. 12 shows another embodiment of the package of the present invention, also configured to have two channels. The embodiment shown in FIG. 12 is a small format package design that includes two coil transducers 39a and 39b, dual channel transmit ICs 21a, 21b, and dual channel receive ICs 22a, 22b.

  Even if the internal high voltage breakdown performance characteristics of the substrate 33 and / or the coil transducer 39 are good, such a substrate 33 may be used unless all paths that may cause arcs in the isolator 20 are removed or blocked. And / or the isolator 20 based on the coil transducer 39 may not exhibit good high voltage breakdown performance characteristics. To reduce the possibility of arcing, it is preferable to use a thick coverlay for the package. There should be no gap between the galvanic isolator 20 and / or the coil transducer 39 or between the various components of the isolator 20 and the coverlay. The adhesion between the different layers of the coil transducer 39 must remain strong so that delamination does not occur during die splitting. To avoid conduction between the bus bars along the sides of the coil transducer 39, it is recommended that the bus bars be collected and electroplated by a suitable wire bond pad.

  In the case of an optical isolator, the space between the LED and the receiver that houses the photodetector is typically filled with an optically transparent insulating material (such as silicone). In the case of a magnetic induction galvanic isolator, it is not essential to be optically transparent, but silicone can be advantageously used. Silicone is a much better electrical insulator than air and adheres well to various other materials, so that the air gap between various parts of the galvanic isolator 20 and / or coil transducer 39 during thermal cycling. It can be advantageously used to suppress the formation of. Furthermore, silicone does not interfere with the operation of coils 23 and 24 because it has low dielectric loss characteristics. Thus, in a preferred embodiment, silicone is installed around at least portions of the coil transducer 39 and / or galvanic isolator 20 to enhance the electrical insulation properties of the isolator 20. This step may be omitted to reduce cost, but performance may be compromised if silicone is not used.

  The galvanic isolator 20 and / or the coil transducer 39 is preferably overmolded. In one embodiment, lead frame 71, coil transducer 39, and lead frame 73 are connected together, wire bonded, and placed in a mold. A molten, electrically insulating mold material (such as epoxy) is poured into the mold to encapsulate at least portions of the package. The mold material can then be cooled and cured to substantially enhance the structural rigidity of the resulting package. The mold material preferably has an appropriate dielectric constant and low dielectric loss so that the electrical performance of the galvanic isolator 20 is not degraded. Next, the lead is trimmed and bent.

  The packaging examples described and illustrated herein do not cover all possibilities for packaging the galvanic isolator 20 of the present invention, and various different variations and permutations are anticipated.

  Various embodiments of galvanic isolators 20 configured for isolated signal transfer as disclosed herein are AC (or vibratory) signal elements, which are generally used for incoming signal transitions. Acts like a differentiator in response. In order to increase the efficiency of data transfer through the galvanic isolator 20, the data takes the form of converted signals, as schematically shown in the block diagram of FIG. In short, a pulse sequence is transmitted via the galvanic isolator 20 instead of an impulse type signal. Since these pulses have a lower frequency spectrum than the impulse type signal, better transmission through the galvanic isolator 20 becomes possible.

  Signals or data are input from the input 202 to the edge detector 200. The data is binary data having a logic 1 or logic 0 state generally used in data transfer technology. The edge detector 200 has a positive output 204 and a negative output 206. The positive output 204 is activated when the input signal transitions from logic 0 to logic 1. This transition is also called the front edge. The negative output 206 is activated when the input signal transitions from logic 1 to logic 0. This transition is also called the rear edge. In some embodiments, the edge detector 200 is shown as having two parts: a positive edge detector and a negative edge detector. The front edge and the rear edge described in this specification are described as examples. In some embodiments, the leading edge is a logic 1 to logic 0 transition and the trailing edge is a logic 0 to logic 1 transition.

  The positive output 204 is connected to the positive pulse generator 210. Similarly, the negative output 206 is connected to the negative pulse generator 212. In one embodiment, the positive pulse generator 210 is activated when the positive output 204 is activated. Similarly, when the negative output 206 is activated, the negative pulse generator 212 is activated. When activated, the positive pulse generator 210 generates a plurality of positive pulses. Specifically, the positive polarity pulse generator 210 generates a plurality of positive polarity pulses when the front edge of the data signal is detected at the input 202. When activated, the negative polarity pulse generator 212 generates a plurality of negative polarity pulses. Similar to the positive pulse generator 210, the negative pulse generator 212 generates a plurality of negative pulses when the rear edge of the data signal is detected at the input 202. The pulse generators 210, 212 can be active for a time corresponding to a length shorter than half of the pulse width.

  The pulses generated by the positive pulse generator 210 and the negative pulse generator 212 are used to drive the transmission coil 23. A driver can be disposed between the pulse generators 210 and 212 and the transmission coil 23. The pulses are composed of spectral frequencies that match the coils 23, 24, thereby increasing the energy transferred to the coils 23, 24. For example, due to this matching, the energy reflected from the transmission coil 23 is reduced. In a conventional galvanic isolator, a coil is driven by a signal having a high frequency component such as an impulse function or a step function. These high frequency components are not successfully transferred to the coils used in galvanic isolators. On the other hand, the pulses generated by the positive polarity pulse generator 210 and the negative polarity pulse generator 212 have a low frequency component that matches the transmission coil 23. Thus, more energy can be transferred to the transmit coil 23 and ultimately to the receive coil 24.

  The receiving circuit 22 receives data from the receiving coil 24. This is an inverted signal of the signal driving the receiving coil 24. Therefore, the receiving circuit 22 receives a plurality of negative pulses indicating that the front edge has been detected by the edge detector 200. The receiving circuit 22 receives a plurality of positive pulses indicating that the rear edge is detected by the edge detector 200. The receiving circuit 22 reconstructs the original data signal received at the input 202 based on the signal received from the receiving coil 24.

  An example of a data signal that can be input to the input 202 of the edge detector 200 is shown in FIG. Referring also to FIG. 13, a data signal 216 is received at input 202. The data signal 216 in FIG. 14 is a single binary pulse and is used for illustration purposes. It should be understood that the signal received at input 202 may be a stream of data. Data signal 216 has a leading edge 218 and a trailing edge 220. The width of the data signal is the time between the leading edge 218 and the trailing edge 220. In the embodiment described herein, the width of the data signal 216 is 10 nanoseconds.

  Illustration 224 shows a pulse generated based on detection of data signal 216 by edge detector 200. In this embodiment, edge detector 200 detects forward edge 218 and activates positive output 204 for 3.5 nanoseconds. This active state is indicated by pulse 226. After 3.5 nanoseconds, the positive output 204 is deactivated. When the edge detector 200 detects the trailing edge 220, the negative output 206 generates a pulse 228. Pulse 228 indicates that negative output 206 is active for 3.5 nanoseconds.

  One embodiment of the outputs of the positive pulse generator 210 and the negative pulse generator 212 is shown in FIG. In the embodiment described herein, the positive pulse generator 210 and the negative pulse generator 212 each generate three pulses during the 3.5 nanosecond duration of the aforementioned pulse. The positive polarity pulse generator 210 is almost the same as the negative polarity pulse generator 212. The positive pulse generator 210 generates three pulses that are 2.5 nanoseconds in length and overlap each other. When the first pulse having a pulse width of 2.5 nanoseconds is generated, the signal 230 of FIG. 15 is obtained. When a second pulse having a pulse width of 2.5 nanoseconds is generated after 0.5 nanosecond, a signal 232 is obtained. Note that the amplitudes of these pulses are different for the convenience of illustration. In practice, these amplitudes may be the same. Further, after the final 0.5 nanosecond has elapsed, a signal 234 is obtained by generating a third pulse having a pulse width of 2.5 nanoseconds. As shown, the signal for driving the coil 23 is composed of three overlapping pulses. It should be understood that the use of three overlapping pulses is for illustration only and that there may be more or less than three overlapping pulses.

  As shown in FIG. 15, the current for driving the transmission coil 23 is constant at 9 mA. However, other values of current can be used. The amplitude of the first pulse 230 is 9 mA. The amplitudes of the two pulses 232 are 4.5 mA each, and the combined current is 9 mA. The amplitudes of the three pulses 234 are each 3 mA, and the combined current is 9 mA.

  Referring to FIGS. 14 and 13, the transmitter coil 23 induces a current in the receiver coil 24, which is detected by the receiver circuit 22, as will be described in detail later. Next, the receiving circuit 22 regenerates the data signal received at the input 202. For example, the receiving circuit 22 can detect three pulses that indicate the leading edge 218 of the data signal 216. Next, the receiving circuit 22 can output a logic one. When the receiving circuit 22 receives three pulses indicating the trailing edge 220 of the data signal 216, the receiving circuit 22 can output a logic zero. Thus, the output of the receiving circuit 22 is the same as the data signal at the input 202. It should be noted that the current passing through the transmission coil 23 can remain at 3 mA. This is because the inductive characteristic of the coil works to keep the current constant for a plurality of short pulses input to the transmission coil 23.

  While embodiments of the galvanic isolator 20 have been described, individual components are described in further detail below.

  One embodiment of a circuit 250 constituting each part of the edge detector 200 is shown in FIG. Input 202 branches to inverter 252 and delay circuit 254. A circuit connected to the output of the inverter 252 detects the forward edge 218 of the data signal 216 and generates a positive output 204. A circuit connected to the output of the delay circuit 254 detects the trailing edge 216 of the data signal 216 and outputs a negative output 206. The delay circuit 254 generates a signal delay equivalent to that of the inverter 252 and matches the timing between the upper circuit and the lower circuit. The upper circuit and the lower circuit can be regarded as independent edge detectors.

  Referring to the upper circuit, the inverter 252 outputs a negative transition due to the forward edge (positive transition) received at the input 202. The output of the inverter 252 is connected to the clock input of the flip-flop 256. The flip-flop 256 may be an edge triggered D flip-flop. When flip-flop 256 is triggered, output Q transitions to an H (high) or logic 1 level and remains in this state until flip-flop 256 is reset. The inverted output QB of the flip-flop 256 is connected to the delay element 258. Delay element 258 is triggered by the falling transition of inverted output QB. The output Q of the delay element 258 transitions over time based on the input Idly. This delay may be 2.5 nanoseconds, which corresponds to the duration of the pulse generated by the pulse generator. When the output Q transits through this delay, a reset is transmitted to the flip-flop 256 via the NAND gate 260. One input of NAND gate 260 is coupled to a master reset. When flip-flop 256 is reset, positive output 204 returns to a logic zero state, thereby deactivating positive pulse generator 210 of FIG. The lower circuit operates in the same way as the upper circuit, but is triggered on the trailing edge received at input 202 because there is no inverter 252.

  Up to this point, the edge detector 200 has been described. Next, the pulse generators 210 and 212 will be described. One embodiment of circuits 270, 272 that can be used in pulse generators 210, 212 is shown in FIG. Circuit 270 generates a positive pulse and circuit 272 generates a negative pulse. Here, the circuit 270 will be described in detail. The operation of the circuit 272 is almost the same as that of the circuit 270. In short, the pulse generation circuit 270 is composed of a plurality of delay elements, which in the embodiment of FIG. 17 are a plurality of inverters connected in series.

  The output 204 of the edge detector 200 is connected to the input 276 of the circuit 270. The output 206 of the edge detector 200 is connected to the input 278 of the circuit 272. Input 276 is divided into two sections. The first section is referred to as feed 280 and the second section is referred to as return 282. Feed 280 drives transmit coil 23 and return 282 provides a return path.

  Feed 280 and return 282 each have four delay stages, referred to as first delay 284, second delay 286, third delay 288, and fourth delay 290, respectively. Each delay has a terminal (output) connected to a driver that drives the transmission coil 23. As will be described in detail later, each output pair is connected to the driver of the transmission coil 23. For example, the outputs P1 and N1 operate to provide a current path for driving the transmission coil 23, as will be described later. In the circuit 270, three delays are created so that the second delay and the third delay occur simultaneously. In other embodiments, the circuit 270 may have three delays so that no delays occur at the same time. These three delays are used as examples. Other embodiments may use more or less than three delays.

  Feed 280 is the same as return 282 except that feed 280 has an additional inverter. Instead of this additional inverter, the return 282 has a delay element 284, and the delay amount of the delay element 284 is substantially the same as that of the inverter. The delay element 284 operates to trigger corresponding outputs at opposite logic levels simultaneously. For example, when the state of input 276 changes, the states of output P1 and output N1 change at the same logic level at the same time. The same applies to all outputs. Thus, output out Px provides drive and output out Nx provides a return path.

  The current drawn by the transmitter coil can be very large. Therefore, it is possible to arrange a driver between the pulse generators 210 and 212 and the transmission coil 23. One embodiment of the driver 300 is shown in the schematic diagram of FIG. As will be described later, the driver 300 uses current mirrors in a plurality of bridges to drive the transmission coil 23. The amount of current that can be drawn is set by the bias current Ib.

  The transmission coil 23 is connected to each of the outputs txtp and txn. A first lead of the transmission coil 23 is connected to each of the outputs txp, and a second lead of the transmission coil 23 is connected to each of the outputs txn. Therefore, the outputs txtp are connected in parallel, and the outputs txn are connected in parallel. The bridge determines the polarity of the pulses generated in the transmission coil 23 by controlling the direction of the current through the transmission coil 23.

  The driver 300 includes a plurality of bridges, which are referred to as a first bridge 302, a second bridge 304, a third bridge 306, and a fourth bridge 308, respectively. Note that the outputs of the circuits 270 and 272 in FIG. 17 are the inputs of the gates in the driver 300. Here, the first bridge 302 is referred to. The rest of the bridge is similar. When the front edge is detected by the edge detector 200 of FIG. 13, the output P1 transitions to logic 1, and the output N1 transitions to logic 0. The outputs P1, N1 turn on the gate 310 and the gate 312, thereby allowing these gates to pass current. Gates 314 and 316 are off and do not conduct current. Based on the state of each gate of the first bridge 302, current flows from the txp lead of the transmission coil 23 to the txn lead. The first bridge 302 supplies a predetermined current (which may be about 3 mA) to the transmission coil 23. As the remaining delay in circuit 210 is activated, the remaining bridge in driver 300 is turned on, supplying current to transmitter coil 23. Due to the configuration of the pulses that drive the transmit coil, the current supplied by the second bridge 304 and the third bridge 306 is half of the current supplied by the first bridge 302 and the fourth bridge 308. Each time the circuit 210 is activated, current flows from the output txp to the transmit coil 23 and returns to the output txn. Therefore, the direction in which the current flows through the transmission coil 23 is constant.

  Note that the second bridge 304 and the third bridge 306 operate simultaneously in order to provide the circuit 300 with redundancy. In some embodiments, three bridges can be provided so that none of the bridges operate simultaneously.

  When the edge detector 200 in FIG. 13 detects a rear edge, the same processing as described above is applied. The difference is that current flows from the txn terminal through the transmission coil 23 and returns via the txt terminal. More specifically, the gate 310 and the gate 312 are turned off, so that no current can flow. Gates 314 and 316 are turned on and can conduct current. The direction in which the current flows through the transmission coil 23 is the direction in which the current flows from the txn terminal and returns via the txt terminal, which is the reverse of the above-described current flow. Therefore, when the edge detector 200 detects the front edge, the current flows in the transmission coil 23 in the first direction. When the edge detector 200 detects a rear edge, current flows in the transmitter coil 23 in the second direction (opposite to the first direction). Based on the different current directions, the reception circuit 21 can determine whether the signal transmitted via the isolator 20 is the front edge or the rear edge.

  Isolation circuits can vary greatly, where various portions of the galvanic isolator 20 and / or coil transducer 39 can occur (eg, due to DC voltage differences, power line voltage differences, ground potential differences, etc.). Allows operation at potential. As described above, high voltage insulation is required between the coils 23 and 24 of the galvanic isolator 20 and the coil transducer 39, which can be achieved by forming the substrate 33 using the above-described materials. It is. One difficulty with common mode signals is the high-speed transition that occurs between the ground of the transmitter circuit 21 and the ground of the receiver circuit 22. A unique capacitance exists between the patterns arranged on both sides of the substrate 33 (and particularly between the coil 23 and the coil 24). This intrinsic capacitance includes capacitive coupling between the primary side and the secondary side of the galvanic isolator / transformer 20.

Assume that the capacitance between the transmission coil 23 and the reception coil 24 is about 1 pF. When a 1 kV common mode transient occurs between the transmitter circuit 21 and the receiver circuit 22 with a gradient of 50 kV / μs, the resulting current flows as follows.
I = C * dV / dt = 1 pF * 50 kV / μsec = 50 mA (Formula 1)

The duration during which this current flows is as follows.
t = V step / (dV / dt) = 1 kV / (50 kV / μsec) = 20 ns (Formula 2)

  The common mode design of the galvanic isolator 20 is preferably configured to absorb such a short time transient signal while maintaining proper signal transmission performance characteristics. There is a trade-off between the magnetic coupling through the coil transducer 39 and the spacing between the transmission coil 23 and the reception coil 24. As a result, common mode removal (CMR) design of the galvanic isolator 20 is particularly challenging.

  To maintain the common mode voltage of the transmitter circuit output and receiver circuit input so that the transmitter circuit output and receiver circuit input are within the system operating power rail, the change in ground potential difference between the transmitter circuit and receiver circuit The common mode current must be absorbed or supplied depending on the direction in which the common mode current caused by the current flows. Compensation of the common mode current can be achieved by a common mode amplifier having an output capable of handling a large amount of generated common mode current.

  One embodiment of such a CMR compensation circuit is shown in FIG. Here, the common mode voltage at the transmitter circuit output and the receiver circuit input is established by a resistive divider network driven by a common mode amplifier opmAB. In the embodiment shown in FIG. 19, the amplifier opmAB is configured to provide unity gain feedback by driving the center tap of the resistive divider network to the common mode reference voltage vcm. In order for the system to operate normally, it is preferable to set vcm within the operating power supply range. Ideally, vcm should be set to the midpoint of the operating power supply range so that the signal swings optimally in both the transmitter and receiver circuits. Since the amplitude of the common mode current can be in the range of tens of milliamps (depending on the coupling capacitance across the isolator channel), the voltage drop across the resistor during a common mode event causes the transmitter circuit output and receiver circuit input to The resistors R1, R2 are preferably low impedance (eg, 10 ohms or less) so that the operating power supply range is never exceeded (however, a higher resistance impedance (eg, about 100 ohms or less, or about It is also expected to have 250 ohms or less). If the signal swing in either the transmit circuit or the receive circuit is allowed to exceed the operating power supply range, the data transmitted over this channel will be corrupted. In addition, these resistors must match well so that there is no mismatch between the two resistors and it is not converted to an abnormal differential signal. The output stage of the common mode amplifier is typically designed to handle up to a specified amount of common mode current, so that the isolator 20 when the magnitude of the common mode current exceeds the design specification. For further protection, ESD diodes can be placed at the transmit circuit output and the receive circuit input.

  FIG. 20A shows in detail one embodiment of the two-stage class AB common mode amplifier opmAB shown in FIG. The amplifier opmAB is a common mode current compensation amplifier that is operatively connected to both the transmitter circuit 21 and the receiver circuit 22. The common mode current that the amplifier opmAB sinks or sources during a common mode event can easily drive the signal level to a positive or negative power supply value, resulting in a loss of the data signal through the isolated channel .

Still referring to FIG. 20A, the left side of the amplifier configuration, there is a bias system that is referred to as the bias current i b. This bias current is generated in another part of the isolator 20. The bias voltage occurs on the left side of FIG. 20A. In one embodiment, the inputs of amplifier opmAB are a pair of NMOS elements that drive a folded cascode structure to the right of the input pair. With such a configuration, a high gain is achieved at a high impedance level connected to the output stage. For example, Paul R., et al., Which describes a similar circuit topology in detail. Gray and Robert G. See also pages 752-756 of Meyer “Analysis and Design of Analog Integrated Circuits”, 2nd edition, John Wiley and Sons, New York, 1984.

  FIG. 20B shows a circuit configured to separate the voltage level into the gate drive of the PMOS output element PM4 and the gate drive of the NMOS output element NM3. The circuit shown in FIG. 20B allows large output elements to be biased (ie, achieve class AB operation) at a quiescent current level that is less than their full current sourcing (or current sinking) capability. The voltage difference between the pgate signal and the ngate signal is controlled by the PM12 element and the NM13 element. If the amplifier output has a load that needs to source or sink more current, either the PM12 or NM13 is off because the ngate value is higher than vn or the pgate value is lower than vp It is possible to become. An element that remains on keeps the first stage cascode structure within the proper operating region and keeps output elements that are not in high current demand on at least with a minimum quiescent current level. The PM12 element and the NM13 element also have special AC signal characteristics. Gate bias levels vn and vp are bypassed to ground by a capacitor. These two elements operate as an additional common gate stage, further raising the first stage gain at the input of the second stage (ie, the output element). As a further feature of this circuit configuration, the basic unipolar roll-off of the first stage circuit is maintained. These interface elements are unique in that they provide a means to control the crossover characteristics of the class AB output stage and provide minimal delay and phase shift to the signals driving the output elements. As a result, it becomes easy to stabilize the entire amplifier with respect to the AC signal, and the amplifier circuit significantly increases the gain in the intermediate frequency range up to several megahertz.

  Still referring to FIG. 20B, the common mode output of the amplifier must be capable of sinking or sourcing very large currents during common mode transients. The previous description of common mode transients has shown that it responds very quickly to sudden transients and that the midpoint of the signal is near 1.25 volts (or according to one embodiment of the invention, Emphasizes the need to maintain at the midpoint of the operating range. Amplifier performance can also be enhanced by proper design and selection of output elements. In order to keep costs down, it is preferable to manufacture the required elements in an integrated circuit process that is inherently digital and has some additional analog functionality. If a special process having a plurality of types of device characteristics such as a BiCMOS process or a CMOS process is required, the number of masking levels (and thus manufacturing costs) may rise to an excessive level. Such special processes are unsuitable for the production of basic insulating parts that are optimally inexpensive enough to be used in low-cost applications. The output device circuits shown in some of the drawings herein are selected to use devices that can be manufactured in a low-cost CMOS manufacturing process, but that can achieve the required performance characteristics with careful design.

With further reference to FIG. 20B, in order to achieve the required fast response performance characteristics, the isolator 20 must have a large G m to increase its bandwidth. It has been found that fast response to fast transients can be achieved by using a very short feedback path (in terms of time delay) so that all or most of the transient can be suppressed. The element capability of the output element in the case of the conventional CMOS process is sufficient to achieve this purpose if the feedback element returning from the output to the gate of the output NMOS element or PMOS element is a capacitor. This very short feedback path provides a frequency response of up to about 2 GHz for common mode voltage correction. Attempts to achieve a corrected response to the fast transients sensed at the output using a feedback path through the first stage of the amplifier circuit have been found to be unsuccessful due to the excessive time delay introduced thereby. Thus, in a preferred embodiment, the output stage achieves fast transient suppression using local feedback in the output elements PM4 and NM3. Drain-gate capacitors C0 and C1 provide such a fast response path. Capacitors C0 and C1 also serve to stabilize the overall frequency response of the amplifier. There is some flexibility in selecting capacitors C0 and C1 so that the gain bandwidth of this amplifier configuration is around 2 MHz. Another aspect of the operational amplifier design shown in FIG. 20B is a local feedback circuit around the output elements PM4 and NM3, which controls transients. At the same time, the overall response of the amplifier is also relatively easily stabilized by the first stage cascode configuration.

  When a data signal is transmitted via the galvanic isolator 20 and the coil transducer 39, various types of encoding methods can be used. For example, it is possible to represent a rising transition of a user waveform using a series of two pulses, and it is possible to represent a falling transition with one pulse (for example, “iCoupler Products with isoPower Technology: Signal and Power”). “Transfer Across Isolation Barrier Using Microtransformers” (see Baoxing Chen, ADI Inc.)). The embodiments described herein are relatively simple and code capable of operating at high data rates using some aspects of the basic physical nature of the design and operation of the isolator 20 and coil transducer 39. Provides a conversion method. The input transient is converted into a single pulse having a polarity corresponding to the rising or falling transition of the input signal. Since there is only one pulse corresponding to the input transient, the maximum transmission frequency is limited by the size of the individual transmission pulses and not by the additional time required to generate multiple same polarity pulses for transmission. The differential operation of the isolated channel transformer produces multiple pulse outputs for the sequence of input pulses. According to one embodiment of the receiving circuit 22, this pulse sequence can also be checked for data integrity verification.

  One possible pulse sequence is shown in FIG. The sequence of pulses used for information transfer through the isolation channel is initiated by the transition of the input signal, converted in the transmitter circuit into current pulses that drive the transmitter coil 23, passes through the coil transducer 39, and in the receiver coil 24. Differentiated as shown. The peak of the output voltage is sensed and read by the receiving circuit 22 and used to construct the output pulse sequence. To reconstruct the input waveform, the comparator output is processed through a decoder. The decoder generates a rising edge or a falling edge at the rising edge of the second pulse of each series of pulse pairs input to the comparator as a positive or negative output.

  The output of the coil transducer 39 is shown as “coil voltage output” in FIG. Due to the nature of the coil transducer 39, the input current pulse on the primary side (“input data” in FIG. 21) is converted into a series of pulses at the secondary output. FIG. 21 shows that the “coil voltage output” signal occurs in the form of a pulse pair. A negative pulse is immediately followed by a positive pulse (or a positive pulse is followed immediately by a negative pulse, which depends on the winding and configuration type of the coil transducer 39). In one embodiment, the second pulse of such a pulse pair is detected for a short period of time (eg, about 10 nanometers) after the first pulse is generated to be detected by the receiver circuit 22 as a data pulse rather than noise. Second, or similar time). In other words, if the second pulse of a pulse pair does not occur within a predetermined time window after the first pulse of such a pulse pair, a single pulse generated outside that predetermined time window Does not represent a valid data pulse and is blocked or ignored.

  Further, with continued reference to the “coil voltage output” signal of FIG. 21, in one embodiment, an additional test for the accuracy of the pulses detected by the receiver circuit 22 may be performed. After the negative (-) pulse and the positive (+) pulse, it must be followed by the positive (+) pulse and the negative (-) pulse (and depending on the winding and configuration type of the coil transducer 39) Thus, a plus (+) pulse must be followed by a minus (-) pulse, followed by a minus (-) pulse and a plus (+) pulse). If such sequences are not detected by the receiving circuit 22, even if signals that are not such sequences are sensed, they do not represent valid data and cannot pass through the decoder.

  Thus far, the novel transmitter and receiver circuits of the present invention provide several advantages over prior art galvanic isolators configured to transfer data signals across dielectric barriers. Will be understood. One such advantage is that the signaling scheme used in the transmitter circuit 21 and the receiver circuit 22 is very simple and robust compared to the prior art signaling methods used in such elements, It shows excellent CMR performance. The receiving circuit 22 can handle an excessive current and identify a true data signal from a noise signal. Both such performance characteristics are required when high CMR performance must be achieved in the presence of interfering noise pulses. As comparative examples, US Patent Publication No. 2005 / 0,057,277 filed Mar. 17, 2005 (Chen et al., Subject “Signal Isolators Using Micro-Transformers”), and December 8, 2005. See the relatively complex data signal transfer scheme described in US Patent Publication No. 2005 / 0,272,378 (Dupuis, subject “Spread Spectrum Isolator”). It will be appreciated that the above-mentioned Chen and Dupuis documents employ data encoding and decoding schemes that are significantly more complex than those described herein.

  Referring to FIG. 2, the receiving circuit 22 monitors the differential signal transmitted through the isolator 20, and generates as an output the input signal input to the transmitting circuit 21 with a minimum delay. And can be configured to do. The output of the receiving circuit 22 is a delayed input signal of the transmitting circuit 21, but the pulse width of the input signal must be maintained so that the integrity of the signal is maintained. The common mode voltage of the input of the receiving circuit can be set by the common mode method described above with respect to the common mode signal of the transmitting circuit.

  A block diagram of one embodiment of the receiver circuit 22 is shown in FIG. In the embodiment of FIG. 22, the receiver circuit 22 re-directs the clamp circuit 320 (sometimes referred to as a common mode hold circuit), a fully differential preamplifier 332, a fully differential high speed comparator 334, and a received signal. It has a decoding stage 336 to build. The receiving circuit 22 accurately reproduces the input signal supplied to the galvanic isolator 20. Each component of the receiving circuit 22 will be described in detail later.

  The reception coil 24 is connected to the two terminals T1 and T2 of the reception circuit 22. The resistors R1 and R2 are connected in series between the terminal T1 and the terminal T2. The clamp circuit 320 includes a differential amplifier 338 and two resistors R1 and R2. The values of resistors R1 and R2 may each be about 25 ohms. The output of the amplifier 338 and the resistors R1 and R1 are connected to each other at the node N1. Resistors R1 and R2 in combination with amplifier 338 keep the voltage at node N1 at a preselected voltage. For example, in a 2.5 volt system, node N1 is kept at about 1.25 volts.

One embodiment of the circuit 340 of the preamplifier 332 of FIG. 22 is shown in FIG. In short, this embodiment of the circuit 340 includes a high performance Cherry Hoper [Chris D. et al. Holdenried, Michael W. Lynch, and James W. Haslett, "Modified CMOS Cherry-Hooper Amplifiers with Source Follower Feedback in 0.35 um technology", Proceedings of the 29 th European Solid-State Circuits Conference, pp. 553-556, 2003], including circuit topology, provides a gain of about 6 with a bandwidth of about 1 GHz.

  Preamplifier 332 is optimized for high speed signal performance. Preamplifier 332 provides some gain to the incoming signal so that the resolution requirements of subsequent comparator 334 (FIG. 22) are relatively modest. Due to the high bandwidth of the circuit 340, narrow output pulses generated by the receiving coil 24 can pass with minimal attenuation. As described above with respect to the transmitter circuit 21, multiple overlapping current pulses that drive the transmitter coil 23 spread the energy of the transmit pulse over a longer time than when using a single current pulse. These overlapping pulses allow the bandwidth of the receiving circuit 22 to be optimized. In order to achieve high data rate throughput, the bandwidth of the preamplifier 332 must be higher than the bandwidth of the signal transmitted through the preamplifier 332. If the bandwidth is too high, unnecessary power is wasted and noise enters the system. This bandwidth is also a physical factor limited by process performance and implementation costs. Thus, the bandwidth of the preamplifier 332 in the embodiments described herein can be designed to be just enough for the system to achieve its required data baud rate. .

  In addition, the possibility of residual common mode signals from the receive coil 24 causing problems in the preamplifier 332 is greatly reduced by the low frequency offset correction amplifier that drives the second input set of the Cherry Hooper amplifier. This offset correction mechanism further provides a DC balanced input to subsequent comparators.

  Terminals T 1 and T 2 from the receiving coil 24 are connected to an input of a Cherry Hooper amplifier 342. Here, amplifiers other than Cherry Hooper can also be used. Terminals T 1 and T 2 provide a differential input to amplifier 342. Low frequency integrator 346 provides feedback to amplifier 342. In short, the low frequency integrator 346 includes a differential amplifier 348 having capacitive feedback. The output of the low frequency integrator 346 provides the offset correction described above to the amplifier 342.

FIG. 24 is a schematic diagram of one embodiment of the amplifier 342 of FIG. Amplifier 342 uses an NMOS design for the Cherry Hooper gain stage. A plurality of unique thresholds elements, and for better matching of the relatively high gain G m of these elements, N number of elements have been used. Such coupling provides better high frequency common mode rejection when used with the low frequency feedback amplifier shown in FIG. Amplifier 342 allows a fairly large common mode input range while providing a constant output common mode rate that is optimized for subsequent comparator circuits.

  FIG. 25 is a schematic diagram of one embodiment of the comparator 334 of FIG. In the embodiment shown in FIG. 25, the comparator 334 is a fully differential design having a current mirror load structure with a differential output gain of approximately 80. This fully differential design provides good common mode rejection. This is important not only for removing noise during normal operation, but also for preventing common-mode transients from being converted into differential signals during common-mode events and disrupting the operation of the receiver circuit. It is.

  The current mirror output structure provides positive feedback to the comparator operation with hysteresis by having additional feedback from the subsequent inverter stage. The threshold value of the comparator is set to about 80 mV so as to be appropriately separated from the noise level. A hysteresis window of about 30 mV further increases the noise immunity of the system. After the comparator, there is an additional gain due to another inverter stage. As the input to the subsequent decoding circuit of the comparator, a small, uniform pulse of controlled width is desirable. This fixed pulse width turns off the pulse after 1.5 nanoseconds using controlled delay elements 350, 352 with a delay of 1.5 nanoseconds and a feedback line back to the first inverter stage. Has been achieved by

  Based on the foregoing, the input + and input − of the comparator 334 are coupled to the output + and output − of the amplifier 342 of FIG. When the input voltage exceeds 80 mV (or other value set by the design of the comparator 334), a pulse is generated at each output CP and CN. Hysteresis is used, which in this embodiment is 30 mV. The output pulse triggers the delay circuits 350, 352, thereby resetting the outputs CP and CN after a preselected time. In the embodiment of FIG. 25, the preselected time is about 1.5 nanoseconds. Therefore, the maximum pulse width generated by the comparator 334 is 1.5 nanoseconds.

  FIG. 26 is a schematic diagram of one embodiment of one of the controlled delay elements 350, 352 of FIG. Delay element 350 has an initial inverter stage 360 followed by an inverter 362 controlled between bias currents between node X1 and node X2. The two elements at the center of the current-controlled inverter 362 normally operate as an inverter stage, and the amount of current used during the transition is controlled by upper and lower current source elements 364 and 366.

  Capacitor C0 is connected between VSA and node X2. The timing from the node X1 to the node X2 is mainly controlled by a combination of the value of the bias current entering the node BB1 and the value of the capacitor C0 connected to the node X2. Two subsequent inverter stages 370 reduce the output load effect on node X2. The four-element column in inverter stage 370 includes two central elements connected to node X2, and the circuit with the gates of the two central elements connected to node X3 is a non-retrigger prevention circuit. . When the delay generation sequence is started, these elements forcibly terminate the delay time before the timing at which a subsequent event can be started. This mechanism is essentially a very fast filter that blocks repeated input pulses. Variations in temperature, process, and power supply voltage can cause large variations in the delay value of the inverter train. These delay elements are designed so that the delay is symmetrical between the rising input edge and the falling input edge.

  The bias current is used as a temperature compensation mechanism. As the temperature increases, the intrinsic delay of delay element 350 increases due to the TC of the element. The bias current applied outside the delay element 350 is designed with a positive TC so that the delay is constant even when the temperature rises. Also, the determination of the delay by the combination of the bias current and the capacitor C0 of the node X2 also reduces the susceptibility to process variations. The fluctuation of the power supply voltage is mainly reduced by the operation of the delay element and the core of the transmission circuit and the reception circuit with respect to the voltage of the internal stabilization power supply.

  The delay element 350 incorporates secondary side power supply fluctuation elimination. This embodiment of the delay element is used in both the transmitting circuit chip and the receiving circuit chip of the isolator 20.

  FIG. 27 is a schematic diagram of one embodiment of the decoder 336 of FIG. Decoder 336 receives inputs from the comparators and reconstructs the initial data signal input of isolator 20 based on these inputs. Decoder 336 receives inputs CP and CN from comparator 334. As described above, preamplifier 332 and comparator 334 convert a falling pulse followed by a pair of rising pulses (or vice versa) into a plurality of short pulses. In the embodiment described here, these pulses are approximately 1.5 nanoseconds in length and there is a characteristic spacing between the pulse pairs representing either of the two types of sequences.

  There are two outputs CP and CN from the comparator 334. The output CP represents the received positive pulse, and the output CN represents the received negative pulse. Decoder 336 needs to determine which pulse pairs represent valid input positive transitions for isolator 20 and which pulse pairs represent valid input negative transitions. Invalid detection results need to be discarded by the decoder 336.

  Information for determining whether a given pulse pair is a valid representation of a transition is included in the timing. In order for two pulses to be a valid pulse pair, several conditions must be met. The time between the first pulse and the following pulse must be shorter than the preselected value T1. If it is longer than T1, it means that the detection of the first edge is wrong or the second edge of the pulse is not detected. Since both the transmitter circuit 21 and the receiver circuit 22 use the same type of controlled delay structure, this timing requirement can be implemented fairly accurately.

  Another test for valid pulse pairs determines if the pulses alternate. For example, CP must be followed by CN (or vice versa). If no pulse pair is received, an error has occurred. In some embodiments, the decoder 336 observes invalid alternating sequences and ignores them until a proper pair is received.

  The embodiment of circuit 380 is divided into four columns of logic elements and controlled delay elements. The first and second columns are examined for valid pulse pair sequences. For the first column, the CP pulse is used as the clock for the first flip-flop 382 following the inverter 384. The first flip-flop 382 may be a D flip-flop. The D input ARM_P2 of flip-flop 382 is at an appropriate level such that the first flip-flop is activated. This activation causes a positive transition in the Q output of the flip-flop and a negative transition in the QB output. This QB output triggers a controlled delay element 386. There is no output from the controlled delay element 386 for a duration T1 (= 6 nanoseconds). After T1 occurs, a negative transition occurs in QB, which is fed back through NAND gate 388 to reset first flip-flop 382. During the T1 duration, the Q output of the first flip-flop 382 is in a state to enable the D input of the second flip-flop 390. When a CN pulse is generated from the comparator 334 during the time T1, the state of the second flip-flop 390 also changes (that is, the Q output makes a positive transition). NAND gate 392 generates a falling pulse indicating that a valid pulse pair has been received.

  The pulse generated at NAND gate 392 does not go directly to the output, but goes to the fourth column of circuit 380 to determine whether the pulse is alternating. The first three gates of the third and fourth columns of circuit 380 are state RS flip-flops that keep track of what type of pulse pair is required next. The first gates 396A (third column) and 396B (fourth column) are active only at the first power-up. The purpose of this is to place the system in a known state at power up so that the decoder 336 operates properly for subsequent inputs. Third logic gate 394 in the fourth column is half of an arm state flip-flop comprised of gate 394B and gate 394A shown directly above it. This flip-flop 394 sets up a test for alternating pulse sequences. The P1_OUT pulse generated by the circuit in the first column changes the state of the RS arm flip-flop 394 so that ARM_N1 is active. The next expected pulse pair is a CN pulse followed by a CP pulse. The ARM_N1 signal passes through several additional circuits in the fourth column and appears as ARM_N2 as described below. This signal is used to enable the second row of circuits so that the combination of the CN pulse followed by the CP pulse is detected immediately by the second row.

  At the same time that the state of arm flip-flops 394A, B changes, the ARM_P1 signal goes to the last inverter 396 in the first column, which generates the OUT1 signal to the decoder. In this case, the output is a positive transition.

  The second column circuit operates similar to the first column circuit for a series of CN pulse followed by CP pulse pairs. When a valid CN pulse and CP pulse pair passes through the second column of circuits, the state of the arm state flip-flop changes, which causes a positive transition of the ARM_P1 signal, which in turn causes a negative transition of OUT1. . Therefore, the positive polarity transition of OUT1 and the subsequent negative polarity transition follow the user input which is the desired result. The second output OUT2 is the inverse of OUT1 and is provided as an optional output.

  The D flip-flops, delay elements, and gates of the remaining circuits of the third and fourth columns are deterrent circuits for repeated CP and CN pulse pairs or repeated CN and CP pulse pairs. It is. For illustration purposes, CN is generated following a valid CP. As a result, ARM_N1 is in the active state and a CN pulse and a subsequent CP pulse are expected to occur next. However, this is not the case, and a CP pulse and a subsequent CN pulse are generated. Since the ARM_P1 signal is inactive, the CF pulse does nothing for the first column of circuits. However, the latter half of this series is a CN pulse that activates the circuits in the second column. In this situation, there is little potential for confusion in the decoder 336 if the system is operating near the maximum signal rate. One way to eliminate ambiguity is to use the CP pulse again, and use it to suppress the next subsequent CN pulse if it is a CP and CN pulse pair. The arm signal actually connected to the second column is the ARM_N2 signal from the circuit in the fourth column. The ARM_N1 signal activates the D flip-flop, which triggers a 2.5 nanosecond delay element 398, which in combination with the NAND gate 400, has a duration T0 (= 2.5 nanoseconds). An ARM_NQ signal is generated, and the ARM_NQ signal prevents the ARM_N2 signal from being activated when a CN pulse of a CP pulse and a CN pulse pair exists. This deterrent circuit is in the rear part of the fourth column. For the case where the CN pulse and CP pulse pair is repeated, a similar suppression circuit is in the third column.

  Since the transformer only transmits AC (or oscillatory) signal information across the channel, a DC refresh circuit should be included in the system so that the DC level is accurate when there is no transition in the data signal being transmitted. Is preferred. In one embodiment, the DC refresh circuit includes a watchdog timer. The watchdog timer is arranged in the transmission circuit 21 and configured to monitor the transition of the input signal. If no signal transition occurs after a certain (or programmed) timeout or time, the watchdog circuit initiates an internal “keep alive” pulse to activate the channel so that the DC state of the output is maintained Keep in state. On the other hand, a watchdog circuit may be included in the receiving circuit 22 to monitor signal transitions at the receiving circuit input. If a signal transition does not occur after a certain (or programmed) timeout or time (which is usually longer than the watchdog timeout of the transmitter circuit), the receiver watchdog circuit defaults the output. Set to state. In one embodiment, the “keep alive” pulse uses a double edge coding scheme. For example, the refresh for the high level is 1 to 0 and then 0 to 1. The refresh for the low level is 0 to 1, then 1 to 0. The internal “keep alive” pulse travels through the same channel as the external input signal, so a separate refresh channel is not required. Such “keep alive” pulses may be finally filtered by the receiver circuit 22 so that they do not appear in the final output.

  As used herein, the terms “vertical” and “horizontal” refer to the relative orientation of the capacitor plane when relating the capacitor plane to the upper or lower ground plane substrate 60. . Thus, an element made in accordance with the teachings of the present invention actually has a plurality of coplanar digital data communication electrodes arranged in a single plane, the single plane being oriented vertically. However, such elements are included within the scope of the present invention, even if they are parallel or nearly parallel to the ground plane substrate.

  Further, according to an embodiment of the present invention, a first substrate is provided, and a first coil 23 and a second coil 24 are sandwiched between the first dielectric plate 23 and the second substrate. Has been placed. Thus, in such an embodiment, the first substrate is located under both the transmit coil 23 and the receive coil 24, and these coils and the second substrate are created on the first substrate. .

  Furthermore, methods (and methods) for creating the various components, elements, and systems described herein are also within the scope of the present invention.

  Each of the above-described embodiments should be considered as examples of the invention and should not be considered as limiting the scope of the invention. By examining the detailed description and the accompanying drawings, it is understood that there are other embodiments of the present invention in addition to the foregoing embodiments of the present invention. Accordingly, various combinations, permutations, variations and modifications of the above-described embodiments of the present invention that are not explicitly described herein are also within the scope of the present invention.

Claims (22)

  1. A substantially planar substrate having first and second surfaces facing each other and having electrical insulation, comprising a material having electrical insulation and low dielectric loss, the first surface comprising: A substrate on which a transmission coil is disposed and a reception coil is disposed on the second surface;
    A transmission circuit operatively connected to the transmission coil,
    A first detector for detecting a rising edge of the input signal;
    A first pulse generator for generating a plurality of first pulses upon detection of the rising edge;
    A second detector for detecting a falling edge of the input signal;
    A second pulse generator that generates a plurality of second pulses upon detection of the falling edge; and
    A receiver circuit operatively connected to the second receiver coil;
    With
    The receiving circuit generates a signal substantially similar to the input signal based on the first pulse and the second pulse;
    Galvanic isolator.
  2.   The galvanic isolator according to claim 1, wherein at least one of the first pulses and at least a second one of the first pulses overlap.
  3.   The galvanic isolator according to claim 1, wherein the current generated by the first pulse generator is kept substantially constant during the generation of the first pulse.
  4.   The galvanic isolator according to claim 1, wherein the input signal has a pulse length, and the first pulse is generated during a time shorter than half of the pulse length.
  5.   The first edge detector generates a signal that enables the first pulse generator during a time period in which the first pulse generator generates the first pulse. Galvanic isolator.
  6.   The first pulse generator includes a plurality of delay circuits connected in series, and a first delay circuit of the delay circuits includes a second delay circuit of the delay circuits. The galvanic isolator of claim 1 that triggers.
  7.   The galvanic isolator according to claim 6, wherein at least one of the delay circuits comprises two inverters connected in series.
  8.   The galvanic isolator according to claim 1, further comprising at least one driver connected between the first pulse generator and the transmission coil.
  9.   The galvanic isolator of claim 8, wherein the at least one driver comprises at least one current mirror.
  10.   A plurality of drivers, each of the plurality of drivers having an input and an output; the inputs of the plurality of drivers are connected to the pulse generator; and the outputs of the plurality of drivers are connected in parallel The galvanic isolator according to claim 1, wherein the galvanic isolator is connected and connected to the transmission coil.
  11.   The galvanic isolator of claim 1, wherein the transmit coil has an associated peak transmit frequency, and the spectrum of the pulse is substantially coincident with the peak transmit frequency.
  12.   The galvanic isolator according to claim 1, wherein the spectral component of the pulse falls within a transmission bandwidth of the transmission coil.
  13.   The galvanic isolator according to claim 1, wherein a configuration of the transmission coil is substantially the same as a configuration of the reception coil.
  14.   The transmit coil is disposed in two metal layers connected by a first via, the first via having an associated first pad and a second pad, the first pad being The first metal layer, the second pad is in the second metal layer, and the portion of the transmit coil disposed in the first metal layer includes the transmit coil, approximately 2 and The galvanic isolator according to claim 1, having a pattern of 3/8 turns.
  15. A second via having an associated third pad;
    A first segment that is an intertangent segment extending between a circumference of the first pad and a circumference of the third pad, wherein the first pad and the third pad are The first segment selected to be on the same side of the segment;
    A second segment extending along at least a portion of the substantially linear pattern, the substantially linear pattern being located closest to the first segment relative to the other patterns; The second segment;
    Further comprising
    The shortest distance between the first segment and the second segment is about 35 μm;
    The galvanic isolator according to claim 14.
  16. Further comprising a first via and a second via;
    The first via has an associated first pad, the second via has an associated third pad, and when viewed from a direction perpendicular to the galvanic isolator, the first via The galvanic isolator according to claim 1, wherein a shortest distance between a pad circumference and the third pad circumference is about 35 μm.
  17.   The galvanic isolator of claim 1, wherein the transmit coil has an associated via pad, and the diameter of the first pad is about 150 μm.
  18.   The galvanic isolator of claim 1, wherein the transmit coil has at least one pattern associated with the width of the at least one pattern is about 35 μm.
  19.   The galvanic isolator according to claim 1, wherein the receiving circuit includes an element that checks validity of a signal received from the receiving coil.
  20.   The galvanic isolator according to claim 1, wherein the receiving circuit is connected to a voltage clamp circuit.
  21.   The galvanic isolator according to claim 1, wherein the receiving circuit comprises a device for discriminating between transmission of a front edge and transmission of a rear edge of the input signal.
  22.   The receiver coil is coupled to an amplifier, a DC bias voltage is applied to the amplifier input, the DC bias voltage varies, and the DC bias voltage is corrected to maintain a DC voltage at the amplifier output. The galvanic isolator according to claim 1.
JP2010126041A 2006-08-28 2010-06-01 Galvanic isolator Expired - Fee Related JP5456583B2 (en)

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US8385043B2 (en) 2013-02-26
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DE102010029470B4 (en) 2016-11-24
DE102010029470A1 (en) 2010-12-09

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