JP2010283054A5 - - Google Patents

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Publication number
JP2010283054A5
JP2010283054A5 JP2009133970A JP2009133970A JP2010283054A5 JP 2010283054 A5 JP2010283054 A5 JP 2010283054A5 JP 2009133970 A JP2009133970 A JP 2009133970A JP 2009133970 A JP2009133970 A JP 2009133970A JP 2010283054 A5 JP2010283054 A5 JP 2010283054A5
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JP
Japan
Prior art keywords
transition
circuit
delay circuit
signal including
output signal
Prior art date
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Granted
Application number
JP2009133970A
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English (en)
Japanese (ja)
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JP5452983B2 (ja
JP2010283054A (ja
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Priority to JP2009133970A priority Critical patent/JP5452983B2/ja
Priority claimed from JP2009133970A external-priority patent/JP5452983B2/ja
Publication of JP2010283054A publication Critical patent/JP2010283054A/ja
Publication of JP2010283054A5 publication Critical patent/JP2010283054A5/ja
Application granted granted Critical
Publication of JP5452983B2 publication Critical patent/JP5452983B2/ja
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

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JP2009133970A 2009-06-03 2009-06-03 プロセスモニタ回路およびプロセス特性の判定方法 Expired - Fee Related JP5452983B2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009133970A JP5452983B2 (ja) 2009-06-03 2009-06-03 プロセスモニタ回路およびプロセス特性の判定方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009133970A JP5452983B2 (ja) 2009-06-03 2009-06-03 プロセスモニタ回路およびプロセス特性の判定方法

Publications (3)

Publication Number Publication Date
JP2010283054A JP2010283054A (ja) 2010-12-16
JP2010283054A5 true JP2010283054A5 (https=) 2012-04-19
JP5452983B2 JP5452983B2 (ja) 2014-03-26

Family

ID=43539570

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009133970A Expired - Fee Related JP5452983B2 (ja) 2009-06-03 2009-06-03 プロセスモニタ回路およびプロセス特性の判定方法

Country Status (1)

Country Link
JP (1) JP5452983B2 (https=)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5752577B2 (ja) 2011-12-07 2015-07-22 株式会社東芝 半導体集積回路
JP6545564B2 (ja) * 2015-08-06 2019-07-17 ルネサスエレクトロニクス株式会社 半導体装置
US10191106B2 (en) * 2015-09-25 2019-01-29 Qualcomm Incorporated Techniques to identify a process corner

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02194372A (ja) * 1989-01-24 1990-07-31 Oki Electric Ind Co Ltd 伝播遅延時間の測定方法
US5068547A (en) * 1990-09-05 1991-11-26 Lsi Logic Corporation Process monitor circuit
JP2001250916A (ja) * 2000-03-03 2001-09-14 Mitsubishi Electric Corp 半導体集積回路
JP2002359289A (ja) * 2001-03-29 2002-12-13 Mitsubishi Electric Corp プロセスモニタ回路を備えた半導体装置、その試験方法、並びにその製造方法
JP2003023055A (ja) * 2001-07-10 2003-01-24 Matsushita Electric Ind Co Ltd 半導体装置
JP2004158631A (ja) * 2002-11-06 2004-06-03 Nec Electronics Corp 半導体装置
JP4367225B2 (ja) * 2004-05-11 2009-11-18 ソニー株式会社 半導体集積回路
JP2010278332A (ja) * 2009-05-29 2010-12-09 Renesas Electronics Corp 半導体集積回路およびその動作方法

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