JP2010266643A - Method of designing mask pattern, method of producing mask set, and method of manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve various problems by allowing boundaries of drawing areas of a plurality of masks to coincide with one another. <P>SOLUTION: When designing mask patterns of a plurality of masks for exposure used in a plurality of photolithography processes of the method of manufacturing a semiconductor device, the arrangement of boundaries of the drawing fields F1, F2, F3 upon the pattern drawing is performed such that at least part of positions of the boundaries of the drawing fields become positions different from one another among the plurality of photolithography processes and, thereby the mask pattern of each drawing field is designed from the total pattern data to be drawn. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a mask pattern design method, a mask set manufacturing method, and a semiconductor device manufacturing method, and in particular, a mask pattern design method, a mask set manufacturing method, and a semiconductor used in manufacturing a semiconductor device having a repetitive pattern. The present invention relates to a device manufacturing method.

  In a lithography process used for manufacturing a semiconductor element, a set of exposure masks (mask sets) is used for the manufacturing process. Here, in the manufacture of the semiconductor device, there may be a defect in circuit operation characteristics due to the exposure mask. As a specific content of the defect, it has been confirmed that fixed pattern noise caused by the exposure mask occurs in the display element and the imaging element. For example, Patent Document 1 points out that uneven noise occurs in the display element.

  The reason why the above noise occurs will be described. In general, in pattern drawing of an exposure mask, patterning is performed on a photosensitive agent (resist) using an electron beam or laser light, and a circuit pattern is formed by etching the photosensitive agent using the mask.

  Here, there is a certain upper limit in the irradiation region of the electron beam or the laser beam, and there are cases where, for example, the dimension on the mask is about 1 mm. This is determined from the viewpoints of both pattern accuracy and drawing throughput, and an upper limit is set in the deflection region as a range in which necessary accuracy can be maintained. The shape of the region differs depending on the drawing method, but is, for example, a band shape or a square shape.

  However, since the entire mask cannot be drawn in the above-described region, the drawing is actually performed while moving the stage. Therefore, a plurality of unit drawing areas exist for the mask drawn by such a method, and a boundary portion of the area naturally occurs.

  In general, it is known that the boundary portion has a large error in pattern size or position accuracy. This is because the boundary portion is the portion where the deflection amount of the laser beam or the electron beam is the largest, and the influence of, for example, aberration is the largest.

  For this reason, a portion having a large error locally exists in the mask. Furthermore, since the drawing area is generally not random and has a certain shape regularity as described above, the above errors are also regularly distributed.

  The reason why the semiconductor element is adversely affected when there is a size or position error in the mask pattern will be described. For example, when a dimensional error occurs locally in an exposure mask used in the gate formation process, device characteristics such as a threshold voltage and on-resistance at the corresponding location change. For this reason, for example, a difference occurs in the output result between the normal part and the abnormal part for the display element and the imaging element, and this is recognized by the evaluator as noise.

  By the way, regarding visual devices such as display devices, it is important to reduce noise recognized by humans. According to Non-Patent Document 1, it has been reported that the noise that can be detected by humans can be detected even at a noise level that is lower by about 8 dB than the random one. Therefore, when the regularly distributed error existing in the above-described mask appears as noise on the device characteristics, this influence becomes extremely large. When such a problem occurs, it is necessary to identify a mask that becomes a factor and to take improvement measures such as reducing the error level at the drawing boundary.

  As an example of the improvement measure, Patent Document 1 proposes to reduce the drawing boundary error by drawing the same pattern a plurality of times while changing the drawing start position.

  In Patent Document 2, one mask pattern is divided into a plurality of regions, and after setting the drawing boundary position in each pattern, the divided boundary positions are randomly drawn by drawing each divided pattern. It has been proposed that

  However, it has been difficult to specify a mask that is a factor and reduce errors in the drawing boundary position for the following reasons.

  The drawing area generally uses the same drawing apparatus, and the position of the drawing area is the same when the pattern drawing area is the same. Therefore, when the same drawing apparatus is used in a plurality of steps and the same drawing area is set, the boundary positions coincide with each other with a plurality of masks.

  For this reason, even if a failure occurrence location can be identified from the device characteristic result, if there are a plurality of processes having a drawing boundary at the failure location, it is not possible to identify which process is the problem.

  In order to solve this problem, it is effective to change the drawing device to change the size of the unit drawing area or to change the drawing target area. However, the mask drawing apparatus is generally determined from the lithography margin, minimum line width, and the like necessary in the process. In particular, in the critical process, since it is desired to form a pattern with high accuracy, it is difficult to change the drawing apparatus.

  Also, regarding the setting of the drawing area in the mask surface, since there are peripheral patterns such as alignment marks and monitor marks, the maximum size that can be drawn is generally specified. Therefore, conventionally, it has been difficult to set an arbitrary drawing area for each process.

  Furthermore, the presence of a boundary at the same position in multiple steps can cause another problem.

  The problem is that locations with large pattern errors are consistent in multiple processes. As a single process, even a small amount of errors accumulate, resulting in a device It is a point that the characteristics are greatly affected.

  In the example of Patent Document 1, it has been shown that errors near the drawing boundary can be reduced by performing multiple drawing. However, even if such a method is actually used, an error at the drawing boundary remains. This may adversely affect the device operating characteristics.

In the method of Patent Document 2, the drawing boundary is different for each mask, which is advantageous in terms of alleviating adverse effects on device characteristics.
However, in the method of Patent Document 2, drawing for connecting circuit patterns is essential, and there is a risk that a size or position error increases at a connecting portion.

JP 2000-47363 A JP-A-7-209854

Nishida, et al. Television Society Report Vol. 14, No 21

  The problem to be solved is that the boundary between the drawing areas of a plurality of masks causes various problems.

  According to the mask pattern designing method of the present invention, when designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps of a semiconductor device manufacturing method, at least a part of a boundary of a drawing field at the time of pattern drawing. Are arranged so as to be different from each other in the plurality of photolithography processes, and a mask pattern for each drawing field is designed from the entire pattern data to be drawn.

  The above-described mask pattern design method of the present invention is a method for designing mask patterns of a plurality of exposure masks used in a plurality of photolithography steps of a semiconductor device manufacturing method. The mask pattern of each drawing field is designed from the entire pattern data to be drawn by arranging at least a part of the drawing field boundary at the time of pattern drawing to be different from each other in a plurality of photolithography processes. .

  According to the mask set manufacturing method of the present invention, when designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps of a semiconductor device manufacturing method, at least a part of a boundary of a drawing field at the time of pattern drawing Are arranged so that their positions are different from each other in the plurality of photolithography processes, and a mask pattern of each drawing field is designed from the entire pattern data to be drawn, and the set of the plurality of exposure masks is set. To manufacture.

The above-described mask set manufacturing method of the present invention is a method of manufacturing a plurality of exposure mask sets by designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps of a semiconductor device manufacturing method. It is.
Design the mask pattern of each drawing field from the entire pattern data to be drawn by arranging so that at least part of the border of the drawing field at the time of pattern drawing will be different from each other in multiple photolithography processes. Thus, a set of a plurality of exposure masks is manufactured.

  According to the semiconductor device manufacturing method of the present invention, when designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography processes of the semiconductor device manufacturing method, at least a part of a boundary of a drawing field at the time of pattern drawing Are arranged such that the positions of the plurality of exposure masks are different from each other in the plurality of photolithography steps, and a mask pattern of each drawing field is designed from the entire pattern data to be drawn, and the plurality of exposure masks A semiconductor device having a repeated pattern is manufactured by performing a plurality of photolithography processes using the semiconductor device.

In the semiconductor device manufacturing method of the present invention described above, a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps of the semiconductor device manufacturing method is designed, and a plurality of photo is used using the plurality of exposure masks. A lithography process is performed. This is a method for manufacturing a semiconductor device having a repeated pattern.
Design the mask pattern of each drawing field from the entire pattern data to be drawn by arranging at least a part of the drawing field boundary at the time of pattern drawing to be different from each other in the plurality of photolithography processes. To do. A plurality of photolithography processes are performed using the obtained plurality of exposure masks to manufacture a semiconductor device having a repetitive pattern.

  In the mask pattern design method of the present invention, the boundaries of the drawing areas of a plurality of masks are shifted from mask to mask, so that matching the boundaries can improve various problems.

  In the mask set manufacturing method of the present invention, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

  In the method of manufacturing a semiconductor device according to the present invention, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

1A and 1B are plan views showing a drawing field according to the first embodiment of the present invention. FIG. 2 is a plan view showing a drawing field according to the second embodiment of the present invention. 3A and 3B are plan views showing a drawing field according to the third embodiment of the present invention. 4A and 4B are plan views showing a drawing field according to the fourth embodiment of the present invention. FIG. 5 is a plan view showing a drawing field according to the fourth embodiment of the present invention. FIG. 6A is a plan view of the display device according to the fourth embodiment, and FIGS. 6B and 6C are cross-sectional views taken along the lines YY ′ and XX ′ of the display device obtained by simulation. The corresponding signals S _Y and S _X. 7 (a) is a plan view of a display device according to a fifth embodiment, FIG. 7 (b) is a signal S _Y corresponding to a cross section taken along Y-Y 'of the resulting display device by simulation.

  Embodiments of a semiconductor device according to the present invention will be described below with reference to the drawings.

The description will be given in the following order.
1. First Embodiment (Method of lengthening one side of a drawing field for each mask)
2. First embodiment (display device)
3. Second embodiment (solid-state imaging element)
4). Third embodiment (semiconductor memory)
5). Second embodiment (mask for semiconductor chip)
6). Third embodiment (method of shifting the drawing start origin)
7). Fourth Embodiment (Method Using Identification Mark)
8). Fourth embodiment (simulation 1)
9. Example 5 (Simulation 2)

<First Embodiment>
[Overall description of mask pattern design method by lengthening one side of drawing field for each mask]
The mask pattern design method of the present embodiment is a method of designing mask patterns of a plurality of exposure masks used in a plurality of photolithography steps of the semiconductor device manufacturing method.
The mask pattern of the exposure mask is, for example, in pattern drawing of the exposure mask, by patterning into a photosensitive agent (resist) with an electron beam or laser light, etc., and performing etching using the photosensitive agent as a mask, A circuit pattern is formed.

Here, a certain upper limit exists in the irradiation region of the electron beam or the laser beam, and for example, it has a square shape of about 1 mm in terms of a mask conversion dimension.
In the present embodiment, the positions of at least a part of the boundary of the drawing field at the time of pattern drawing are arranged so as to be different from each other in a plurality of photolithography processes, and each drawing field is determined from the entire pattern data to be drawn. Design the mask pattern.

Here, preferably, in designing a mask pattern of an exposure mask in a plurality of photolithography processes using the same drawing apparatus, at least a part of the drawing field boundary at the time of pattern drawing is different from each other. Arrange so that
In the case of different exposure apparatuses, a certain amount of misalignment is included. In the case of using the same exposure apparatus, it is more effective to arrange such that the positions of at least part of the boundary of the drawing field are different from each other in a plurality of photolithography processes.

Preferably, when designing the mask pattern of the exposure mask, the area of the drawing field is changed for each photolithography process.
Specifically, the length of one side of the square-shaped drawing field is changed for each photolithography process.
Thereby, the positions of at least a part of the boundary of the drawing field at the time of pattern drawing are arranged to be different from each other in the plurality of photolithography processes.

FIG. 1A is a plan view showing a drawing field according to the present embodiment.
The length of one side of the other drawing fields F2 and F3 is set longer than the drawing field F1.
For example, by using the areas indicated by F1, F2, and F3 as the respective drawing fields in a plurality of photolithography processes, the positions of the borders of the drawing fields are different from each other in the plurality of photolithography processes.

FIG. 1B is a plan view showing a drawing field according to this embodiment, and is a plan view showing a state in which a plurality of drawing fields of FIG.
The length of one side of the other drawing fields F2a to F2d and F3a to F3d is set longer than the certain drawing fields F1a to F1d.
For example, by using regions indicated by F1a to F1d, F2a to F2d, and F3a to F3d as the respective drawing fields in a plurality of photolithography processes, the positions of the borders of the drawing fields are different from each other in the plurality of photolithography processes. Become.

For example, the drawing field is set as follows.
First, with respect to the mask for each process, an area that can be drawn is referred to. However, as described above, this region is the same for each process. Next, an additional conversion area is set in the area including the area.

However, if the additional area is an area outside the drawable range, it is sufficient that no circuit pattern exists in this area.
For example, the width of the additional region is set to x: 0.2 mm and y: 0.2 mm as shown in FIG. However, as shown in FIG. 1A, the additional region is one side in each of the xy directions of the pattern arrangement region.

  In a plurality of masks using the same drawing apparatus, drawing pattern data is generated so that the boundary areas of the drawing fields are arranged at different positions for each mask. As a result, since the portion where the mask error is maximized can be dispersed between the processes, the adverse effect on the device characteristics can be reduced.

  In the mask pattern design method of the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

[Description of mask set manufacturing method]
A mask set can be manufactured using the mask pattern design method of the present embodiment. This is a method of manufacturing a set of a plurality of exposure masks by designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps of the method for manufacturing a semiconductor device.
Arrangement is made such that at least a part of the border of the drawing field at the time of pattern drawing is different from each other in a plurality of photolithography processes. A mask pattern for each drawing field is designed from the entire pattern data to be drawn, and a plurality of exposure mask sets are manufactured.

  In the mask set manufacturing method of the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted from mask to mask, so that matching the boundaries can improve various problems.

[Description of Manufacturing Method of Semiconductor Device]
Moreover, a semiconductor device can be manufactured using the mask pattern design method of the present embodiment.
A mask pattern of a plurality of exposure masks used in a plurality of photolithography processes in the method for manufacturing a semiconductor device is designed, and a plurality of photolithography processes are performed using the plurality of exposure masks. This is a method of manufacturing a semiconductor device having a repetitive pattern.
The mask pattern of each drawing field is designed from the entire pattern data to be drawn by arranging so that at least a part of the border of the drawing field at the time of pattern drawing is different from each other in the plurality of photolithography processes. To do. A plurality of photolithography processes are performed using the obtained plurality of exposure masks to manufacture a semiconductor device having a repetitive pattern.

  In the method for manufacturing a semiconductor device according to the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, so that matching the boundaries can improve various problems.

<First embodiment: display device>
As a first embodiment, an example in which the present invention is applied to a display element will be described below.
The process for manufacturing the display element includes, for example, an element separation process, a gate electrode formation process, a contact formation process, and an ITO electrode formation process.
First, it is examined whether or not the same drawing apparatus is used for a mask necessary for device fabrication.
This method may be performed by referring to a list database of masks used for each process, for example. In this case, processes using the same drawing apparatus are the element isolation process, the gate electrode forming process, the contact forming process, and the ITO electrode forming process.
Therefore, regarding these steps, the drawing boundary is changed for the gate electrode formation step, the contact formation step, and the ITO electrode formation step with respect to the element isolation step.

Next, the drawing boundary position in the above four steps is changed. The drawing boundary position is determined when the mask pattern data is converted into data unique to the drawing apparatus. This time, the conversion area at the time of the conversion is changed. In the subsequent steps, the additional area is set in the same manner.
As the width values of the additional regions indicated by x and y, the gate electrode formation step is +0.2 mm, the contact formation step is +0.4 mm, and the ITO electrode formation step is +0.6 mm with respect to the element isolation step.

  In setting, the pattern area including the additional area is set with the corner on the side of the additional area as the origin. Therefore, the mask for the gate electrode formation process, the contact formation process, and the ITO electrode formation process has different drawing boundary positions with respect to the element isolation process in which the sizes of the regions are different.

  Next, an exposure mask having the drawing boundary position defined above is produced. What is necessary is just to produce the mask for exposure by the method similar to the past.

  Subsequently, a semiconductor device is manufactured using these masks. Also here, the fabrication is performed by the same process as the conventional one.

  Next, an operation test is performed on the semiconductor device thus manufactured. In a conventional method, that is, in a display element that does not change the drawing boundary position in a mask using the same drawing apparatus, streak-like noise is generated in a part of the display result. On the other hand, in the present invention, since the drawing boundary positions are dispersed, the portions where the mask pattern errors are concentrated are dispersed, so that the streak-like noise is eliminated.

<Second Embodiment: Solid-State Image Sensor>
As a second embodiment of the present invention, an example applied to an image sensor is shown.
However, since the flow of the second embodiment does not change even if the device type to be applied is different, only the main points are described here.
First, a drawing apparatus for each process is specified. Here, in this case, processes using the same drawing apparatus are an element isolation process, an ion implantation process, a gate electrode formation process, and an intralayer lens formation process.
Therefore, with respect to these processes, the drawing boundary is changed with respect to the element isolation process in the ion implantation process, the gate electrode formation process, and the intralayer lens formation process.

  As the width values of the additional regions indicated by x and y, the ion implantation step is +0.2 mm, the gate electrode formation step is +0.4 mm, and the intra-layer lens formation step is +0.6 mm with respect to the element isolation step. .

  About the process after this, what is necessary is just to implement the process similar to the conventional image pick-up element preparation. As for the imaging device manufactured according to this example, it was possible to prevent the generation of streak-like noise as in the case of Example 1.

<Third Embodiment: Semiconductor Memory>
As a third embodiment of the present invention, an example applied to a semiconductor memory is shown. In the conventional method, data retention failure has been confirmed in an area that coincides with the mask drawing boundary. In order to cope with this, the device characteristics were improved with the same flow as the first and second embodiments.

First, a drawing apparatus for each process is specified. Here, in this case, processes using the same drawing apparatus are an element isolation process, a gate electrode formation process, a capacitor formation process, and a wiring formation process.
Therefore, with respect to these steps, the drawing boundary is changed for the gate electrode formation step, the capacitor formation step, and the wiring formation step with respect to the element isolation step.

  As the width values of the additional regions indicated by x and y, the gate electrode formation step is +0.2 mm, the capacitor formation step is +0.4 mm, and the wiring formation step is +0.6 mm with respect to the element isolation step.

  For the subsequent processes, the same method as before was applied. For the semiconductor memory fabricated according to this example, the data retention failure that occurred at a specific location was eliminated.

<Second Embodiment>
[Overall description of mask pattern design method for semiconductor chip]
FIG. 2 is a plan view showing a drawing field according to the present embodiment.
The present embodiment is a mask MK on which patterns of semiconductor chips C1 to C4 are formed.
In the first embodiment, the additional region D indicated by the widths x and y is added to the semiconductor chips C1 to C4 in the mask MK, and the drawing boundary position is changed.

  First, a mask using the same drawing apparatus is specified. The specific method may be the same as that shown in the first embodiment. Next, the drawing boundary position is changed. In this case, unlike the first embodiment, the boundary position is not changed over the entire drawable area in the mask. Instead, the position of the drawing boundary is changed for each of the plurality of circuit chips arranged in the mask.

  The changing method is the method described in the first embodiment. First, a pattern generation area in each chip is referred to. Next, a pattern generation area is additionally set in each area. In this case, an additional area of 0.2 mm is generated for one side of xy in the drawing area.

  Here, the size of the additional area of each chip may be the same or different. However, it is necessary that the process does not coincide with other processes using the same drawing apparatus. Thereafter, the same procedure as in the first embodiment may be performed. Moreover, this embodiment can also be applied to an image sensor and a semiconductor memory as shown in the first to third examples.

  In the mask pattern design method of the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

  A mask set can be manufactured using the mask pattern design method of this embodiment. Further, the present invention can be applied to a semiconductor device manufacturing method.

<Third Embodiment>
[Overall description of mask pattern design method by shifting drawing start origin]
FIG. 3A is a plan view showing a drawing field according to the present embodiment.
The position of the starting point of drawing in the other drawing fields F2 and F3 is changed with respect to a certain drawing field F1. Accordingly, the positions of at least a part of the boundary of the drawing field at the time of pattern drawing are arranged to be different from each other in the plurality of photolithography processes.
Specifically, the drawing start origin P2 of the drawing field F2 is shifted by 0.2 mm in the x and y directions with respect to the drawing start origin P1 of the drawing field F1, and the drawing start of the drawing field F3 is started. The origin P3 is shifted by 0.4 mm in the x and y directions.
For example, by using regions indicated by F1, F2, and F3 as respective drawing fields in a plurality of photolithography processes, the positions of the borders of the drawing fields are different from each other in the plurality of photolithography processes.

FIG. 3B is a plan view showing a drawing field according to the present embodiment.
FIG. 4 is a plan view showing a state in which a plurality of drawing fields in FIG.
The drawing start origin (P1 to P3, etc.) is shifted in the x and y directions in the other drawing fields F2a to F2d and F3a to F3d with respect to a certain drawing field F1a to F1d.
For example, by using regions indicated by F1a to F1d, F2a to F2d, and F3a to F3d as the respective drawing fields in a plurality of photolithography processes, the positions of the borders of the drawing fields are different from each other in the plurality of photolithography processes. Become.

For example, the drawing field is set as follows.
First, a mask using the same drawing apparatus is specified. The specific method may be the same as that shown in the first embodiment. Next, the drawing boundary position is changed. In this case, unlike the previous case, the change region is not changed for each process. Instead, the origin of the conversion area is changed for each process.
Specifically, in the case of the display device shown in the first embodiment, it is assumed that the same drawing apparatus is used for the element isolation step, the gate electrode formation step, the contact formation step, and the ITO electrode formation step.
Here, with respect to these processes, the drawing boundary was changed with respect to the element isolation process for the gate electrode formation process, the contact formation process, and the ITO electrode formation process.
Specifically, the position of the origin (P1 to P3 etc.) of the drawing boundary generation is set to be shifted in the x direction and the y direction.
As the values of the widths shifted in the x and y directions, the gate electrode formation step is +0.2 mm, the contact formation step is +0.4 mm, and the ITO electrode formation step is +0.6 mm with respect to the element isolation step.
The subsequent processes are the same as those exemplified in the first embodiment. Further, the present embodiment can also be applied to an image sensor and a semiconductor memory as shown in the second and third examples.

  In the mask pattern design method of the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

  A mask set can be manufactured using the mask pattern design method of this embodiment. Further, the present invention can be applied to a semiconductor device manufacturing method.

<Fourth embodiment>
[First Design Method of Mask Pattern by Method Using Identification Mark]
For example, when applied to a display device, a solid-state imaging device, or the like, a semiconductor device has pixels arranged in a matrix in an effective pixel region.
In the present embodiment, when designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps of the semiconductor device manufacturing method, an identification pixel is arranged outside the effective pixel region, and the mask is formed. Design the pattern.

FIG. 4A is a plan view showing a drawing field according to the present embodiment.
Pixels PIX are arranged in a matrix in the effective pixel region R. A pixel for identification is provided for each drawing boundary unit from the drawing boundary origin outside the effective pixel region R. The identification pixel is an identification mark MC.
In the present embodiment, an identification mark is arranged for each exposure mask. For example, one identification mark is provided for one process.

In the prior art, regarding the location of a problem, it has been difficult to identify the position even if noise occurs in the display element.
For this reason, even if there is a problem with the mask, it is difficult to compare the defective part on the mask with the defective part on the device.
In the case of a display element, generally, circuit elements are arranged in a matrix, and the inside of this matrix is a display portion, and any identification mark is not allowed to be arranged. As a result, the position of a defect generated in the matrix is determined. Because it was not possible to specify accurately.

In Patent Document 1, the position of the drawing boundary is the same between processes, and it is difficult to identify the problem process even if a problem occurs.
Also, in the method of Patent Document 2, as in Patent Document 1, when a defect in device characteristics occurs, it is difficult to identify the factor process because there is no way to identify the process.

For example, when a display device similar to that of the first embodiment is provided, the exposure process is performed using the same exposure apparatus in the element isolation step, the gate electrode formation step, the contact formation step, and the ITO electrode formation step.
For example, four pixel patterns are arranged so as to correspond to the above four steps.
However, since these pixel patterns are required to operate as devices, additional patterns are arranged at the same position for all masks.
If the size of the drawing area is 730 μm, the same mark is arranged every 730 μm.

  For a plurality of photomask groups used in a lithography process for manufacturing an electronic device, at least a plurality of drawing boundary positions at the time of pattern drawing are arranged at different positions for each process step. Further, this position is stored in a storage device, and the trouble occurrence position specified based on the device operation result is compared with the drawing boundary position to identify the problem process.

  In addition, a pixel is added or deleted for identification outside the effective area as a device so as to identify the area boundary position. The problem process can be easily identified by comparing the identification pixel and the defective part in the device operation.

  In addition, a drawing boundary position is stored in an external storage device or the like in a database, and a defective part generated in a device operation test is compared with the database to clarify a process that causes a defect.

  In the mask pattern design method of the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

  A mask set can be manufactured using the mask pattern design method of this embodiment. Further, the present invention can be applied to a semiconductor device manufacturing method.

[Second Design Method of Mask Pattern by Method Using Identification Mark]
FIG. 4B is a plan view showing a drawing field according to the present embodiment.
In the display element of this embodiment, pixels outside the region are arranged on the outer periphery of the effective pixel region, and a portion where no pixel outside the region is provided is arranged as an identification mark.
The out-of-region pixel is formed as an incomplete pixel and does not function as a pixel, but it is possible to identify the position of the pixel. The specific method may be the same as described above.
Next, the drawing boundary position is changed.

Next, the process proceeds to installation of identification marks.
The identification mark is to remove an element at a location that coincides with a drawing boundary with respect to an element pattern in a region outside the effective pixel. Specifically, in the case of the display device as in the first embodiment, one element pattern is removed as shown in FIG.
Hereinafter, 2, 3 and 4 patterns are excluded from the gate electrode forming step, the contact forming step, and the ITO electrode forming step. As for the exclusion, as in the first embodiment, the corresponding element patterns in all the processes are targeted.

By doing in this way, the generation | occurrence | production position of a stripe noise can be specified from a device operation result.
This method can be applied to any of the first to third embodiments.

FIG. 5 is a plan view showing a drawing field according to the present embodiment.
As shown in the first embodiment, this corresponds to a mask pattern design method in which one side of the drawing field is lengthened for each mask.
Pixels PIX are arranged in a matrix in the effective pixel area. By the method of lengthening one side of the drawing field for each mask, the drawing field is set as F1, F2, F3 corresponding to the mask, for example.
Here, pixels serving as identification marks are provided at end positions of the respective F1, F2, and F3. In this way, pixels are added or deleted for identification outside the effective area as a device so that the area boundary position can be specified. The problem process can be easily identified by comparing the identification pixel and the defective part in the device operation.

  In the mask pattern design method of the present embodiment, the boundaries of the drawing areas of a plurality of masks are shifted for each mask, and therefore, matching the boundaries can improve various problems.

  A mask set can be manufactured using the mask pattern design method of this embodiment. Further, the present invention can be applied to a semiconductor device manufacturing method.

<Fourth embodiment: Simulation 1>
An example in which the present invention is applied to a display element will be described below. In this case, a semiconductor device is manufactured by the same method as in the first embodiment, and the operation result is defective.

The flow up to the fabrication of the semiconductor device is the same as that of the first embodiment. That is, the semiconductor device manufacturing process includes an element isolation process, a gate electrode formation process, a contact formation process, and an ITO electrode formation process, which are processed by the same exposure apparatus.
6 (a) is a plan view of a display device, and FIG. 6 (b) is the signal S _Y corresponding to a cross section taken along Y-Y 'of the resulting display device by simulation, FIG. 6 (c) This is the signal S _X corresponding to the cross section at XX ′ of the display device.
In this case, the result of the operation test of the semiconductor device is as shown in FIG. 6, and streaky noise was found at a certain location in the chip. Therefore, the generation position of the noise is specified.

  As a method for identifying streak noise, a method of referring to the process identification mark described above was adopted. That is, an operation for specifying an identification mark in the vicinity of a portion where a streak occurs is performed.

  Specifically, streak noise is generated, and the display output of the location near the identification mark is enlarged on the screen, so that the location where the streak noise occurs is near where the identification mark is located. We investigated whether it occurred.

  As a result, it was found that streak-like noise was generated at two locations of the identification mark. Therefore, it has been found that the gate electrode formation process is a main factor of noise generation. Therefore, it was decided to take corrective measures such as reducing the mask error level or reviewing the design pattern for this mask.

  In the present embodiment, the drawing boundary position changing method performed in the first embodiment is applied, but the present embodiment is applicable to other embodiments or embodiments.

<5th Example: Simulation 2>
In this embodiment, the identification mark at the drawing boundary position is not used. A specific example is shown below by taking a device for display elements as an example. First, a process using the same drawing apparatus is referred to. In this case as well, as in the first embodiment, the four steps of the element isolation step, the gate electrode formation step, the contact formation step, and the ITO electrode formation step were targeted.

  Next, the drawing boundary position is changed for each process. For this method, the method described in each of the above embodiments may be used. However, the changed drawing boundary position is registered in advance in a database such as an external storage device.

  Next, using the mask, a device is manufactured and an operation test is performed. In this operation test, streak-like noise was generated, so the noise generation position is specified. In a specific method, output signals are integrated in the streak generation direction, and the relative relationship between the element position and the streak generation position is examined.

7 (a) is a plan view of a display device, FIG. 7 (b) is a signal S _Y corresponding to a cross section taken along Y-Y 'of the resulting display device by simulation.
Specifically, in the graph of FIG. 7, a steep peak is recognized at the streak noise occurrence position. Therefore, the Y coordinate of the peak position is acquired. In the case of this example, the Y coordinate has a streak at a location such as 0.93 mm, 1.66 mm, and 2.39 mm with the origin at the upper right corner of the chip, that is, a position of 0.2 + 0.73 n (n is a natural number of 1 or more) mm. Noise was generated.

  Next, the generation position of the streak noise is compared with the above-described database of the mask drawing boundary position. At this time, a process in which the generation position of the streak noise coincides with the drawing boundary position becomes a factor process. Here, referring to the drawing boundary position from the database, it was found that the drawing boundary position of the gate electrode formation process coincided with the streak noise generation position.

  Therefore, corrective measures such as reducing the mask error level or reviewing the design pattern were taken for this mask.

  In the present embodiment, the drawing boundary position changing method performed in the first embodiment is applied, but the present embodiment is applicable to other embodiments or embodiments.

  According to the present invention, the location where the mask error is maximized can be dispersed for each process by arranging the drawing boundary position at a different position for each process. As a result, it is possible to prevent problems caused by the mask on the device characteristics without using a highly accurate and expensive mask process and without increasing the writing time.

  In addition, even if there is a problem with the device characteristics, it is possible to easily extract the process in question by comparing the process identification mark placed outside the pixel effective area with the defect occurrence location. it can. Therefore, it is possible to deal with only the process causing the defect, and a cost at the time of the defect and a time merit until improvement are born.

  Furthermore, even if the process identification mark as described above is not used, the problem boundary process can be easily identified by creating a database of the drawing boundary positions and comparing the drawing boundary positions with the location where the defect occurs in the device characteristics.

According to the semiconductor device manufacturing method of the present embodiment, the following effects can be obtained.
In the mask pattern design method of the present invention, the boundaries of the drawing areas of a plurality of masks are shifted from mask to mask, so that matching the boundaries can improve various problems.
In addition, by comparing the process identification mark arranged outside the pixel effective area with the defect occurrence location, it is possible to easily extract the problematic process.

The present invention is not limited to the above description.
For example, the display device can be applied to various display devices in addition to a liquid crystal display device. As a solid-state imaging device, it can be applied to both a CMOS sensor and a CCD device. The memory can be applied to various semiconductor memories in addition to DRAM.
In addition, various modifications can be made without departing from the scope of the present invention.

  F1 to F3, F1a to F1d, F2a to F2d, F3a to F3d ... Drawing field, C1 to C4 ... Semiconductor chip, MK ... Mask, D ... Additional area, MC, MC1 to MC3 ... Identification mark

Claims (11)

When designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps in a method for manufacturing a semiconductor device, the position of at least a part of a boundary of a drawing field at the time of pattern drawing is the plurality of photolithography steps In the mask pattern design method, the mask patterns for each drawing field are designed from the entire pattern data to be drawn by arranging them at different positions in FIG. When designing the mask pattern of the exposure mask, the position of at least a part of the boundary of the drawing field at the time of pattern drawing is different from each other in the plurality of photolithography processes using the same drawing apparatus. The mask pattern design method according to claim 1, wherein the mask pattern is arranged as follows. When designing the mask pattern of the exposure mask, by changing the area of the drawing field for each photolithography process, the position of at least a part of the boundary of the drawing field at the time of pattern drawing is changed to the plurality of photo The method for designing a mask pattern according to claim 1, wherein the mask patterns are arranged so as to be at different positions in a lithography process. When designing the mask pattern of the exposure mask, by changing the length of one side of the square-shaped drawing field for each photolithography step, the position of at least a part of the boundary of the drawing field at the time of pattern drawing The mask pattern design method according to claim 3, wherein the mask patterns are arranged so as to be different from each other in the plurality of photolithography processes. When designing the mask pattern of the exposure mask, by changing the drawing start origin of the drawing field for each photolithography process, the position of at least a part of the boundary of the drawing field at the time of pattern drawing is The mask pattern design method according to claim 1, wherein the mask patterns are arranged so as to be at different positions in a plurality of photolithography processes. When designing mask patterns for a plurality of exposure masks used in a plurality of photolithography processes in a method for manufacturing a semiconductor device in which pixels are arranged in a matrix in an effective pixel area, identification is performed outside the effective pixel area. The mask pattern design method according to claim 1, wherein the mask pattern is designed by arranging a mark for use. The mask pattern design method according to claim 6, wherein pixels are additionally arranged as the identification marks. The mask pattern design method according to claim 6, wherein an out-of-region pixel is arranged on an outer periphery of the effective pixel region, and a portion where the out-of-region pixel is not provided is arranged as the identification mark. When designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps in a method for manufacturing a semiconductor device, the position of at least a part of a boundary of a drawing field at the time of pattern drawing is the plurality of photolithography steps In the mask set manufacturing method, the mask patterns for each drawing field are designed from the entire pattern data to be drawn by arranging them at positions different from each other, and manufacturing the plurality of exposure mask sets. When designing a mask pattern of a plurality of exposure masks used in a plurality of photolithography steps in a method for manufacturing a semiconductor device, the position of at least a part of a boundary of a drawing field at the time of pattern drawing is the plurality of photolithography steps In order to design the mask pattern of each drawing field from the overall pattern data to be drawn,
A semiconductor device manufacturing method for manufacturing a semiconductor device having a repeated pattern by performing a plurality of photolithography processes using the plurality of exposure masks. The method for manufacturing a semiconductor device according to claim 10, wherein the semiconductor device is a display element, a solid-state imaging element, or a solid-state memory element.

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