JP2010246322A - Dc/dc power converter - Google Patents

Dc/dc power converter Download PDF

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JP2010246322A
JP2010246322A JP2009094524A JP2009094524A JP2010246322A JP 2010246322 A JP2010246322 A JP 2010246322A JP 2009094524 A JP2009094524 A JP 2009094524A JP 2009094524 A JP2009094524 A JP 2009094524A JP 2010246322 A JP2010246322 A JP 2010246322A
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voltage
circuit
voltage side
high
low
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JP5222775B2 (en
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Matahiko Ikeda
Masaru Kobayashi
Hirotoshi Maekawa
Tatsuya Okuda
Yuya Tanaka
Takahiro Urakabe
博敏 前川
達也 奥田
勝 小林
又彦 池田
隆浩 浦壁
優矢 田中
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Mitsubishi Electric Corp
三菱電機株式会社
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Abstract

<P>PROBLEM TO BE SOLVED: To reduce the size and weight of a reactor in a DC/DC power converter that transfers energy via the reactor by turning on/off a semiconductor switching element. <P>SOLUTION: A DC/DC power converter includes a multiplier circuit 5 having a first circuit 3 composed of a series of MOSFETs connected between low voltage-side voltage terminals VL and Vcom, a second series 4 composed of diodes connected in series to the high voltage side of the first circuit 3, and an LC series LC12 connected between the first series 3 and the second series 4. Furthermore, a PWM circuit 6 composed of a series of MOSFETs is connected between the low voltage-side voltage terminals VL and Vcom, a capacitor Cs for PWM is connected between the PWM circuit 6 and a high voltage-side terminal Vm of the second circuit 4, and a reactor is connected between the high voltage-side terminal Vm and a high voltage-side voltage terminal VH. A boosting operation is carried out by controlling the multiplier circuit 5 and the MOSFETs of the PWM circuit 6. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a DC / DC power conversion device that converts a DC voltage into a DC voltage that is stepped up or stepped down.

  A DC / DC converter as a conventional DC / DC power converter is composed of a smoothing capacitor provided between input and output terminals, a reactor, a semiconductor switch, and a diode, and is connected to the reactor by an on / off operation of the semiconductor switch. By controlling the storage and release of energy, the voltage is stepped up or down to a predetermined voltage and supplied to the electric load (for example, see Non-Patent Document 1).

The Institute of Electrical Engineers of Japan, Semiconductor Power Conversion System Research Committee: "Power Electronics Circuit", Ohmsha, pp. 245-265, 2000

  In such a conventional DC / DC power conversion apparatus, a predetermined voltage is obtained by controlling the accumulation and release of energy in the reactor by the on / off operation of the semiconductor switch. However, both the voltage applied to the reactor and the current flowing through the reactor are large, and a large reactor is required. In addition, the semiconductor switch element requires a voltage determined from the high voltage side and a current capacity determined from the low voltage side, and a semiconductor switch element having a large rating needs to be used. In addition, when such a highly rated semiconductor switch element is used, there is a problem that loss becomes large and high-frequency operation becomes difficult, and the reactor becomes larger.

  The present invention has been made to solve the above-described problems, and is a DC / DC power converter that transfers energy through a reactor by an on / off operation of a semiconductor switch element. The purpose is to reduce the size of the reactor by reducing the voltage applied to and the current flowing through the reactor. It is also intended to obtain a small and highly efficient DC / DC power conversion device by enabling high-frequency operation with low loss using a semiconductor switching element with a low capacity and a small rated value, and further reducing the size of the reactor. To do.

  A DC / DC power converter according to the present invention includes a low-voltage side smoothing capacitor connected between both low-voltage side input / output terminals, and a high-voltage side input / output both terminal having a common low-voltage side input / output terminal and negative-electrode side terminal. A first circuit comprising a high-voltage side smoothing capacitor connected between, a first series body of a low-voltage side element comprising a semiconductor switch element and a high-voltage side element, connected between the low-voltage side input / output terminals; a diode A second circuit formed by serially connecting a second series body of a low-voltage side element and a high-voltage side element, each of which is connected to the high-voltage side of the first circuit, and an intermediate point of the first series body and the second And a constant multiplier circuit having a capacitor connected between the intermediate points of the two series bodies. A PWM circuit comprising a series body of a low-voltage side semiconductor switch element and a high-voltage side semiconductor switch element, connected between the low-voltage side input / output terminals; an intermediate point of the PWM circuit; and a high-voltage side of the second circuit A PWM capacitor connected between the terminals and a reactor connected between the high-voltage side terminal of the second circuit and the positive-side terminals of the high-voltage side input / output terminals. The boosting operation is performed by transferring energy from between the low-voltage side input / output terminals to the high-voltage side input / output terminals.

  The DC / DC power converter according to the present invention includes a low voltage side smoothing capacitor connected between the low voltage side input / output terminals, and the high voltage side input / output terminals having the common low voltage side input / output terminals and negative electrode side terminals. A first circuit formed by connecting a first series body of a high-voltage side smoothing capacitor, a low-voltage side element composed of a diode element, and a high-voltage side element, between the low-voltage side input / output terminals; a semiconductor; A second circuit formed by serially connecting a second series body of a low-voltage side element and a high-voltage side element made of a switch element to the high-voltage side of the first circuit; and an intermediate point of the first series body and the above-mentioned And a constant multiplication circuit having a capacitor connected between the intermediate points of the second series bodies. A PWM circuit comprising a series body of a low-voltage side semiconductor switch element and a high-voltage side semiconductor switch element, connected between the low-voltage side input / output terminals; an intermediate point of the PWM circuit; and a high-voltage side of the second circuit A PWM capacitor connected between the terminals and a reactor connected between the high-voltage side terminal of the second circuit and the positive-side terminals of the high-voltage side input / output terminals. The step-down operation is performed by transferring energy from between the high-voltage input / output terminals to the low-voltage input / output terminals.

  The DC / DC power converter according to the present invention includes a low voltage side smoothing capacitor connected between the low voltage side input / output terminals, and the high voltage side input / output terminals having the common low voltage side input / output terminals and negative electrode side terminals. A first circuit formed by connecting a first series body of a high-voltage side smoothing capacitor connected between the low-voltage side element and the high-voltage side element composed of a semiconductor switch element between the low-voltage side input / output terminals; A second circuit formed by serially connecting a second series body of a low-voltage side element and a high-voltage side element made of a semiconductor switch element to the high-voltage side of the first circuit; and an intermediate point of the first series body; A constant multiplication circuit having a capacitor connected between the intermediate point of the second series body. A PWM circuit comprising a series body of a low-voltage side semiconductor switch element and a high-voltage side semiconductor switch element, connected between the low-voltage side input / output terminals; an intermediate point of the PWM circuit; and a high-voltage side of the second circuit A PWM capacitor connected between the terminals and a reactor connected between the high-voltage side terminal of the second circuit and the positive-side terminals of the high-voltage side input / output terminals. Then, energy is transferred between the low-voltage side input / output terminals and between the high-voltage side input / output terminals, and one or both of the step-up and step-down operations are performed.

  According to the present invention, the energy is transferred between the PWM capacitor and the low-voltage input / output terminals by using the charge / discharge of the capacitor in the constant-magnification circuit, and the on / off operation of the semiconductor switch element in the PWM circuit results in the PWM. The energy is transferred between the low-voltage side input / output terminals and the high-voltage side input / output terminals by repeatedly storing and releasing the energy in the reactor by using the energy of the capacitor. For this reason, the voltage applied to the reactor and the current flowing through the reactor can be reduced, and the reactor can be downsized. Further, the semiconductor switch element in the PWM circuit may be an element having a small rating like the semiconductor switch element in the constant-magnification circuit, and high-frequency driving is possible with low loss. For this reason, the reactor can be further reduced in size by reducing the inductance value of the reactor, and a highly efficient DC / DC power conversion device that is greatly promoted in size and weight reduction can be obtained.

It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 1 of this invention. It is a figure which shows the gate signal waveform by Embodiment 1 of this invention, and the voltage current waveform of each part. It is the figure which showed the average electric current value which flows into the reactor by Embodiment 1 of this invention with the comparative example. It is the figure which showed the inductance value of the reactor by Embodiment 1 of this invention with the comparative example. It is the figure which showed (inductance value) x (average current value) 2 of the reactor by Embodiment 1 of this invention with the comparative example. It is a figure which shows the gate signal waveform by Embodiment 2 of this invention, and the voltage current waveform of each part. It is the figure which showed (inductance value) x (average current value) 2 of the reactor by Embodiment 2 of this invention with the comparative example. It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 3 of this invention. It is a figure which shows the gate signal waveform by Embodiment 3 of this invention, and the voltage current waveform of each part. It is a figure which shows the gate signal waveform by Embodiment 4 of this invention, and the voltage current waveform of each part. It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 5 of this invention. It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 6 of this invention. It is a figure which shows the gate signal waveform by the 1st case of Embodiment 6 of this invention, and the voltage current waveform of each part. It is the figure which showed the average electric current value which flows into the reactor by the 1st case of Embodiment 6 of this invention with the comparative example. It is the figure which showed the inductance value of the reactor by the 1st case of Embodiment 6 of this invention with the comparative example. It is the figure which showed (inductance value) * (average current value) 2 of the reactor by the 1st case of Embodiment 6 of this invention with the comparative example. It is a figure which shows the gate signal waveform by the 2nd case of Embodiment 6 of this invention, and the voltage current waveform of each part. It is the figure which showed (inductance value) x (average current value) 2 of the reactor by the 2nd case of Embodiment 6 of this invention with the comparative example. It is a figure which shows the circuit structure of the DC / DC power converter device by Embodiment 7 of this invention. It is a figure which shows the gate signal waveform by the 1st case of Embodiment 7 of this invention, and the voltage current waveform of each part. It is a figure which shows the gate signal waveform by the 2nd case of Embodiment 7 of this invention, and the voltage current waveform of each part.

Embodiment 1 FIG.
A DC / DC power converter according to Embodiment 1 of the present invention will be described below.
FIG. 1 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 1 of the present invention. As shown in FIG. 1, the DC / DC power conversion apparatus is composed of a DC / DC power conversion main circuit 1 and a control circuit 2, and a voltage V1 inputted between both low-voltage input / output terminals (VL, Vcom). Has a DC / DC power conversion function for performing a step-up operation in which a voltage V2 boosted to 2.0 × V1 to 2.5 × V1 is output between both high-voltage side input / output terminals (VH, Vcom). The negative terminal Vcom of the low voltage side input / output terminals (VL, Vcom) is the same as the negative terminal Vcom of the high voltage side input / output terminals (VH, Vcom). Hereinafter, the low-voltage input / output terminals (VL, Vcom) and the high-voltage input / output terminals (VH, Vcom) are simply referred to as voltage terminals VL, Vcom and voltage terminals VH, Vcom.

  The DC / DC power conversion main circuit 1 is connected between the voltage terminals VL and Vcom and connected between the voltage terminals VH and Vcom, and the smoothing capacitor CL as a low-voltage side smoothing capacitor for smoothing the input voltage V1 and the output voltage. A smoothing capacitor CH as a high-voltage side smoothing capacitor for smoothing V2 and a first series body (S1d, S1u) connected between voltage terminals VL and Vcom, a second series body ( D2d, D2u) is composed of a second circuit 4 that is connected in series to the high-voltage side of the first circuit 3, and an LC series body LC12 that functions as an energy transfer element and that is composed of a series circuit of a capacitor Cr12 and an inductor Lr12. Constant magnification circuit 5.

  The first series body (S1d, S1u) constituting the first circuit 3 is configured by connecting in series a low-voltage side element S1d and a high-voltage side element S1u made of MOSFETs as semiconductor switching elements. It operates as a drive circuit. The second series body (D2d, D2u) constituting the second circuit 4 is configured by connecting in series a low-voltage side element D2d and a high-voltage side element D2u made of a diode element. Operate. The LC series body LC12 includes a connection point between the low-voltage side element S1d and the high-voltage side element S1u, which is an intermediate point of the first series body (S1d, S1u), and an intermediate point of the second series body (D2d, D2u). Between the connection point of the low-voltage side element D2d and the high-voltage side element D2u. Hereinafter, the low voltage side element S1d and the high voltage side element S1u made of MOSFET are simply referred to as S1d and S1u, and the low voltage side element D2d and the high voltage side element D2u made of a diode element are simply referred to as D2d and D2u.

Further, the DC / DC power conversion main circuit 1 is configured by connecting a series body (Spd, Spu) in which a low-voltage side semiconductor switch element Spd and a high-voltage side semiconductor switch element Spu made of MOSFETs are connected in series between the voltage terminals VL and Vcom. And a capacitor Cs as a PWM capacitor, and a reactor Lc. The capacitor Cs is connected between a connection point of the low-voltage side semiconductor switch element Spd and the high-voltage side semiconductor switch element Spu, which is an intermediate point of the PWM circuit 6, and the high-voltage side terminal Vm of the second circuit 4, and the reactor Lc is The voltage terminals VH and Vcom are connected between the voltage terminal VH which is the positive terminal and the high voltage terminal Vm of the second circuit 4. Hereinafter, the low-voltage side semiconductor switch element Spd and the high-voltage side semiconductor switch element Spu made of MOSFET are simply referred to as Spd and Spu.
Each MOSFET is a power MOSFET in which a parasitic diode is formed between the source and drain.

Details of connection in such a DC / DC power converter will be described.
Both terminals of the smoothing capacitor CL are connected to voltage terminals VL and Vcom, respectively, and the voltage terminal Vcom is grounded. The low voltage side terminal of the smoothing capacitor CH is connected to the voltage terminal Vcom, and the high voltage side terminal is connected to the voltage terminal VH. The source terminal of S1d is connected to the voltage terminal Vcom, the drain terminal is connected to the source terminal of S1u, and the drain terminal of S1u is connected to the voltage terminal VL. The source terminal of Spd is connected to the voltage terminal Vcom, the drain terminal is connected to the source terminal of Spu, and the drain terminal of Spu is connected to the voltage terminal VL. The anode terminal of D2d is connected to the voltage terminal VL, the cathode terminal is connected to the anode terminal of D2u, and the cathode terminal of D2u is connected to one side of the reactor Lc and the high voltage side of the capacitor Cs.

One end of the LC serial body LC12 is connected to a connection point between S1d and S1u, and the other end is connected to a connection point between D2d and D2u. One end of the capacitor Cs is connected to the connection point of Spd and Spu, and the other end is connected to one of the cathode terminal of D2u and the reactor Lc. The other of the reactors Lc is connected to the high voltage side of the smoothing capacitor CH and the voltage terminal VH.
The gate terminals of S1d, S1u, Spd, and Spu and the voltage terminals VH and Vcom are connected to the control circuit 2. Gate signals GS1d, GS1u, GSpd, and GSpu based on the voltage of the source terminal of each MOSFET are input from the control circuit 2 to the gate terminals of S1d, S1u, Spd, and Spu, and the voltage terminal VH is input to the control circuit 2 , Vcom voltage is input.

  Next, an operation of boosting the voltage V1 input between the voltage terminals VL and Vcom to a voltage V2 that is 2 × V1 to 2.5 × V1 and outputting the voltage between the voltage terminals VH and Vcom will be described. An electric load is connected between the voltage terminals VH and Vcom, and energy is transferred through the paths of the voltage terminals VL and Vcom to the voltage terminals VH and Vcom and consumed. Further, the capacitance values of the smoothing capacitors CL and CH and the capacitor Cs are set to sufficiently large values as compared with the capacitance value of the capacitor Cr12 of the LC serial body LC12.

FIG. 2 shows the gate signals GS1d and GS1u of each MOSFET in the constant multiplier circuit 5, the gate signals GSpd and GSpu of each MOSFET in the PWM circuit 6, the current ILr flowing through the LC series body LC12, and the second circuit 4 Each waveform of the voltage of the high-voltage side terminal Vm (shown as Vm) and the current ILc of the reactor Lc is shown. The MOSFETs (S1d, S1u, Spd, Spu) are turned on when the gate signal is at a high voltage. As shown in FIG. 2, the gate signals GS1d and GS1u for the constant multiplication circuit 5 have the same or slightly larger period than the resonance period T determined by the capacitance value of the capacitor Cr12 of the LC series body LC12 and the inductance value of the inductor Lr12. This is an on / off signal of one pulse per cycle with a duty ratio of about 50%. The gate signals GSpd and GSpu for the PWM circuit 6 are on / off signals of one pulse per cycle determined in accordance with the boosting rate in the same cycle that is synchronized with the gate signals GS1d and GS1u for the constant multiplier circuit 5.
A voltage of about 2 × V1 is stored in the capacitor Cs, and the voltage V1 is stored in the capacitor Cr12 on an average by repeating the operation described below. The initial charging operation for the capacitor Cs will be described later.

  In the period t1, the gate signal GS1d is at a high voltage, the gate signal GS1u is at a low voltage, the gate signal GSpu is at a high voltage, and the gate signal GSpd is at a low voltage. When S1d is turned on, energy is transferred to the capacitor Cr12 through a path of the smoothing capacitor CL → D2d → inductor Lr12 → capacitor Cr12 → S1d. On the other hand, when Spu is turned on, the capacitor Cs is connected in series to the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 3 × V1. As a result, the energy is transferred to the smoothing capacitor CH via the reactor Lc through the path of the smoothing capacitor CL → Spu → capacitor Cs → reactor Lc → smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while increasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period t2, the gate signal GS1d is at a high voltage, the gate signal GS1u is at a low voltage, the gate signal GSpu is at a low voltage, and the gate signal GSpd is at a high voltage. While S1d remains on, the energy transfer operation to the capacitor Cr12 continues from the period t1. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 2 × V1. Thereby, the energy accumulated in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CH through the path of the reactor Lc → smoothing capacitor CH → Spd → capacitor Cs. The current ILc flowing through the reactor Lc flows while decreasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period t3, the gate signal GS1d is a low voltage, the gate signal GS1u is a high voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. While Spd remains on, the energy transfer operation from reactor Lc to smoothing capacitor CH continues from period t2. Further, when S1d is turned off and S1u is turned on, the energy stored in the capacitor Cr12 is transferred to the capacitor Cs through a path of the capacitor Cr12 → the inductor Lr12 → D2u → the capacitor Cs → Spd → the smoothing capacitor CL → S1u. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12.

By repeating this series of operations, the voltage is boosted and output.
The constant multiplier circuit 5 operates with the first circuit 3 as a drive circuit and the second circuit 4 as a rectifier circuit, and performs energy transfer from the smoothing capacitor CL to the capacitor Cr12 and energy transfer from the capacitor Cr12 to the capacitor Cs. Repeat. The PWM circuit 6 is connected to the reactor Lc with the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5, being 3 × V1 in the period t1 and 2 × V1 in the other periods. By doing so, energy is transferred to the smoothing capacitor CH through the reactor Lc.

By adjusting the length of the period t1, the height of the output voltage V2, that is, the step-up rate can be controlled. The output voltage V2 is high when the period t1 is long, and low when the period t1 is short. It is necessary to provide a period of 1/2 of the resonance period T as an energy accumulation period in the capacitor Cs, during which S1u and Spd are in the on state. Therefore, if the period of the gate signals GS1d, GS1u, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the period t1 that is the on period of Spu is T / 2 or less. That is, the maximum value of the adjustable output voltage is 2.5 × V1.
The control circuit 2 determines the length of the period t1 in advance according to the desired boosting rate, and generates one pulse of the gate signals GSpd and GSpu in one cycle. Further, in the control circuit 2, each voltage of the voltage terminals VH and Vcom is input, and when the gate signals GSpd and GSpu are generated according to the voltage between the voltage terminals VH and Vcom, the length of the period t1 which is the pulse width thereof is generated. Adjust the height. That is, the desired output voltage V2 can be reliably obtained by adjusting the length of the period t1 so as to suppress the fluctuation of the output voltage V2 that is the voltage between the voltage terminals VH and Vcom.

  Next, an initial charging operation for the capacitor Cs will be described. The capacitor 2 needs to store a voltage 2 × V1. In the initial charging operation, Spd is turned on and Spu is turned off in the PWM circuit 6, and S1d and S1u are alternately turned on and off in the period T in the fixed multiplier circuit 5. With this operation, the capacitor Cs can be charged with the voltage 2 × V1.

The specifications (characteristics) of the reactor Lc used in the DC / DC power converter according to this embodiment will be described below. For example, the output when the ratio (ΔI / Iave) of the ripple current pp value ΔI of the current ILc flowing through the reactor Lc to the average current value Iave (ΔI / Iave) is 0.8, with a frequency of 10 kHz, V1 = 250 V, output power of 10 kW The relationship between the voltage V2 and the characteristics of the reactor Lc is illustrated together with a comparative example. In particular, the average current value Iave of the reactor Lc is shown in FIG. 3, the inductance value L of the reactor Lc is shown in FIG. 4, and the product of the inductance value L and the square of the average current value Iave is a measure of the size of the reactor Lc. L × Iave 2 is shown in FIG.
As a comparative example, the conventional DC / DC power converter described above as background art, that is, a smoothing capacitor provided between input and output terminals, a reactor, a semiconductor switch, and a diode, The reactor of the DC / DC power converter which controls the accumulation | storage and discharge | release of the energy to a reactor by on-off operation is used.

As shown in the figure, compared with the comparative example, the average current value Iave of the reactor Lc according to this embodiment is small, and the inductance value L is small in each stage on the low output voltage level side. In addition, L × Iave 2 that is a guide for the size of the reactor Lc is also significantly reduced. As described above, according to this embodiment, the size of the reactor, which has conventionally been a large component, can be made smaller, and the DC / DC power converter can be reduced in size and weight.

In the conventional DC / DC power converter described above, the applied voltage of the switch element that controls the accumulation and release of energy to the reactor is the output voltage on the high voltage side. In this embodiment, the voltage level connected to the reactor Lc and the voltage applied to Spd and Spu in the PWM circuit 6 for controlling the period are the voltage between the voltage terminals VL and Vcom on the low voltage side, that is, the input voltage V1. Therefore, the applied voltage of the conventional switch element can be greatly reduced. For this reason, an element having a low withstand voltage can be used for Spd and Spu in the PWM circuit 6, and the on-resistance is small and the loss can be reduced.
In the conventional DC / DC power converter, the current flowing through the switching element is a current depending on the input voltage on the low voltage side, but the current flowing through Spd and Spu in the PWM circuit 6 according to this embodiment is as follows. Since the current depends on the output voltage V2 on the high voltage side, the current is significantly small. For this reason, the loss of Spd and Spu in the PWM circuit 6 can be further reduced.

As described above, the MOSFETs (Spd, Spu) in the PWM circuit 6 can use elements with a small rating, and the loss is small, similarly to the MOSFETs (S1d, S1u) in the constant multiplier circuit 5. Therefore, each MOSFET can be driven at a high frequency with each stage. As a result, the inductance value L of the reactor Lc can be reduced, and the reactor Lc can be made smaller and lighter.
In addition, in the characteristic of the reactor Lc shown using FIGS. 3-5, in order to show both the conventional comparative examples, the drive frequency was set to 10 kHz. However, in this embodiment, each stage has a frequency higher than that. It can be driven.

Further, in this embodiment, in the constant multiplication circuit 5, an LC series body LC12 of the capacitor Cr12 and the inductor Lr12 is used to transfer energy from the smoothing capacitor CL to the capacitor Cr12 and energy transfer from the capacitor Cr12 to the capacitor Cs. LC resonance is used. This resonance period T is determined by the capacitance value of the capacitor Cr12 and the inductance value of the inductor Lr12, and the resonance current becomes zero current at the phase of the resonance period T of 0 (T) and T / 2. In this embodiment, the driving period of each MOSFET is the same as or slightly larger than the resonance period T. When the driving period of each MOSFET is larger than the resonance period T, the resonance current flows for a period of T / 2, and after the current value becomes zero, the second time until the ON / OFF state of the MOSFET (S1d, S1u) changes. Backflow is prevented by each diode element (D2d, D2u) in the circuit 4, and no current flows.
For this reason, when the MOSFETs (S1d, S1u) are switched, the value of the current flowing through the MOSFETs (S1d, S1u) is zero, no switching loss occurs, and a highly efficient energy transfer with low loss is possible. Further, in order to efficiently transfer energy using the resonance current, the capacitance value of the capacitor Cr12 and the inductance value of the inductor Lr12 may be small, and the capacitor Cr12 and the inductor Lr12 can use small elements with small ratings.

  In this embodiment, the LC series body LC12 of the capacitor Cr12 and the inductor Lr12 is used, but the midpoint of the first series body (S1d, S1u) and the midpoint of the second series body (D2d, D2u). The inductor Lr12 may be connected in the charge / discharge path of the capacitor Cr12 connected between the two and the LC resonance can be used in the same manner, and the same effect can be obtained.

  Further, the inductor Lr12 may be omitted. In this case, in the constant multiplier circuit 5, a high-efficiency energy transfer using the resonance current is not achieved. However, as described above, the MOSFET (Spd , Spu) can use an element with a small rating, enables high-frequency driving, and makes the reactor Lc smaller and lighter at each stage. For this reason, the highly efficient DC / DC power converter device with which size reduction and weight reduction were greatly accelerated | stimulated is obtained.

Embodiment 2. FIG.
Next, a DC / DC power conversion apparatus that performs different control with the same circuit configuration as that of the first embodiment will be described.
In this embodiment, the voltage V1 input between the voltage terminals VL and Vcom is boosted to a voltage V2 of 1.5 × V1 to 2 × V1 and output between the voltage terminals VH and Vcom. As in the first embodiment, an electrical load is connected between the voltage terminals VH and Vcom, and energy is transferred and consumed along the paths of the voltage terminals VL and Vcom to the voltage terminals VH and Vcom.

FIG. 6 shows the gate signals GS1d and GS1u of the MOSFETs in the constant multiplier circuit 5, the gate signals GSpd and GSpu of the MOSFETs in the PWM circuit 6, the current ILr flowing through the LC series body LC12, and the second circuit 4 Each waveform of the voltage of the high-voltage side terminal Vm (shown as Vm) and the current ILc of the reactor Lc is shown. The MOSFETs (S1d, S1u, Spd, Spu) are turned on when the gate signal is at a high voltage. As shown in FIG. 6, the gate signals GS1d and GS1u for the constant multiplier circuit 5 have the same or slightly larger period than the resonance period T determined by the capacitance value of the capacitor Cr12 of the LC series body LC12 and the inductance value of the inductor Lr12. This is an on / off signal of one pulse per cycle with a duty ratio of about 50%. The gate signals GSpd and GSpu for the PWM circuit 6 are on / off signals of one pulse per cycle determined in accordance with the boosting rate in the same cycle that is synchronized with the gate signals GS1d and GS1u for the constant multiplier circuit 5.
A voltage of about V1 is stored in the capacitor Cs, and the voltage V1 is stored in the capacitor Cr12 on an average by repeating the operation described below. The initial charging operation for the capacitor Cs will be described later.

  In the period tt1, the gate signal GS1d is a low voltage, the gate signal GS1u is a high voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S1u is turned on, the energy stored in the capacitor Cr12 is transferred to the capacitor Cs through a path of the capacitor Cr12 → the inductor Lr12 → D2u → the capacitor Cs → Spu → S1u. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12. On the other hand, when Spu is turned on, the capacitor Cs is connected in series to the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 2 × V1. As a result, the energy is transferred to the smoothing capacitor CH via the reactor Lc through the path of the smoothing capacitor CL → Spu → capacitor Cs → reactor Lc → smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while increasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period tt2, the gate signal GS1d is at a high voltage, the gate signal GS1u is at a low voltage, the gate signal GSpu is at a high voltage, and the gate signal GSpd is at a low voltage. The energy transfer operation to the smoothing capacitor CH via the reactor Lc is continued from the period tt1 while the Spu is kept on. On the other hand, when S1u is turned off and S1d is turned on, energy is transferred to the capacitor Cr12 through the path of the smoothing capacitor CL → D2d → inductor Lr12 → capacitor Cr12 → S1d.

  In the period tt3, the gate signal GS1d is at a high voltage, the gate signal GS1u is at a low voltage, the gate signal GSpu is at a low voltage, and the gate signal GSpd is at a high voltage. The energy transfer operation to the capacitor Cr12 is continued from the period tt2 while S1d is kept on. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 1 × V1. Thereby, the energy accumulated in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CH through the path of the reactor Lc → smoothing capacitor CH → Spd → capacitor Cs. The current ILc flowing through the reactor Lc flows while decreasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

By repeating this series of operations, the voltage is boosted and output.
The constant multiplier circuit 5 operates with the first circuit 3 as a drive circuit and the second circuit 4 as a rectifier circuit, and performs energy transfer from the smoothing capacitor CL to the capacitor Cr12 and energy transfer from the capacitor Cr12 to the capacitor Cs. Repeat. In addition, the PWM circuit 6 sets the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5, to 2 × V1 in the period (tt1 + tt2), and 1 × V1 in the other periods, and the reactor Lc By connecting to, energy is transferred to the smoothing capacitor CH via the reactor Lc.

By adjusting the length of the period (tt1 + tt2), the height of the output voltage V2, that is, the step-up rate can be controlled. The output voltage V2 is high when the period (tt1 + tt2) is long, and low when the period is short. It is necessary to provide a half period of the resonance period T as an energy accumulation period in the capacitor Cs, and S1u and Spu are in an on state during that period. Therefore, if the period of the gate signals GS1d, GS1u, GSpd, and GSpu, that is, the drive period of each MOSFET and the resonance period T are substantially the same, the length of the period (tt1 + tt2) that is the ON period of Spu is T / 2 to T It is adjusted in the range. That is, the minimum value of the adjustable output voltage is 1.5 × V1.
The control circuit 2 determines the length of the period (tt1 + tt2) in advance according to the desired boosting rate, and generates the gate signals GSpd and GSpu with one pulse per cycle. Further, in the control circuit 2, each voltage of the voltage terminals VH and Vcom is input, and a period (tt1 + tt2) having a pulse width when generating the gate signals GSpd and GSpu according to the voltage between the voltage terminals VH and Vcom. Adjust the length. That is, the desired output voltage V2 can be reliably obtained by adjusting the length of the period (tt1 + tt2) so as to suppress the fluctuation of the output voltage V2 that is the voltage between the voltage terminals VH and Vcom.

  Next, an initial charging operation for the capacitor Cs will be described. The capacitor Cs needs to store the voltage V1. In the initial charging operation, Spd is turned off and Spu is turned on in the PWM circuit 6, and S1d and S1u are alternately turned on and off in the period T in the fixed multiplication circuit 5. With this operation, the capacitor Cs can be charged with the voltage V1.

The specifications (characteristics) of the reactor Lc used in the DC / DC power converter according to this embodiment will be described below. For example, the output when the ratio (ΔI / Iave) of the ripple current pp value ΔI of the current ILc flowing through the reactor Lc to the average current value Iave (ΔI / Iave) is 0.8, with a frequency of 10 kHz, V1 = 250 V, output power of 10 kW A relationship between the voltage V2 and the characteristics of the reactor Lc is shown in FIG. 7 together with a comparative example. The comparative example is the same as the conventional comparative example shown in the first embodiment. As shown in the figure, the product of the inductance value L of the reactor Lc and the square of the average current value Iave is a measure of the size of the reactor Lc, and L × Iave 2 is significantly smaller than the comparative example. . For example, when adjusting at an output voltage V2 = 375V with a boost rate of 1.5, it becomes about 1/2, and when adjusting with an output voltage V2 = 475V at a boost rate of 1.9, it becomes about 1/10. In this way, the size of the reactor, which has conventionally been a large component, can be made smaller, and the DC / DC power converter can be reduced in size and weight.

  Also in this embodiment, as in the first embodiment, the voltage level connected to the reactor Lc and the voltage applied to Spd and Spu in the PWM circuit 6 for controlling the period and the Spd and Spu The flowing current can be reduced as compared with the conventional one, and the loss can be reduced. Also, the MOSFETs (Spd, Spu) in the PWM circuit 6 can use elements with a small rating, like the MOSFETs (S1d, S1u) in the constant multiplier circuit 5, and each MOSFET is driven at a high frequency with each stage. can do. As a result, the inductance value L of the reactor Lc can be reduced, and the reactor Lc can be made smaller and lighter.

  Further, in the fixed-magnification circuit 5, LC resonance is used for energy transfer, and the driving cycle of each MOSFET is the same as or slightly larger than the resonance cycle T. For this reason, when the MOSFETs (S1d, S1u) are switched, the current value flowing through the MOSFETs (S1d, S1u) is zero, and a high-efficiency energy transfer with little loss is possible. In addition, since the energy is efficiently transferred using the resonance current, a small element with a small rating can be used for the capacitor Cr12 and the inductor Lr12.

In this embodiment, similarly to the first embodiment, the inductor Lr12 may be connected to the charge / discharge path of the capacitor Cr12, and the same effect can be obtained.
Further, the inductor Lr12 may be omitted. In this case, in the fixed-multiplier circuit 5, a high-efficiency energy transfer using the resonance current is not achieved, but the MOSFET (Spd, Spu) in the PWM circuit 6 is rated. The effect that the high-frequency drive is possible and the reactor Lc can be made smaller and lighter at each stage can be obtained in the same manner.

  Further, the voltage V1 input between the voltage terminals VL and Vcom is boosted to 2 × V1 to 2.5 × V1 in the first embodiment, and 1.5 × V1 to 2 × V1 in the second embodiment. However, the control circuit 2 selects and uses the control shown in the first embodiment or the second embodiment in accordance with the boosting rate, thereby boosting the voltage to 1.5 × V1 to 2.5 × V1. Can be output between the voltage terminals VH and Vcom.

Embodiment 3 FIG.
Next, a DC / DC power converter according to Embodiment 3 of the present invention will be described.
FIG. 8 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 3 of the present invention. As shown in FIG. 8, the DC / DC power conversion device is constituted by a DC / DC power conversion main circuit 1a and a control circuit 2a, and a voltage V2 inputted between both high-voltage input / output terminals (VH, Vcom). Is converted to a voltage V1 stepped down to 0.4 × V2 to 0.5 × V2 and has a DC / DC power conversion function for performing a step-down operation to output between the low-voltage side input / output terminals (VL, Vcom). The negative side terminal Vcom of the low voltage side input / output terminals (voltage terminals VL, Vcom) is the same as the negative side terminal Vcom of the high voltage side input / output terminals (voltage terminals VH, Vcom).

  The DC / DC power conversion main circuit 1a is connected between the voltage terminals VL and Vcom and is connected between the voltage terminals VH and Vcom and the smoothing capacitor CL as a low-voltage side smoothing capacitor that smoothes the output voltage V1. A smoothing capacitor CH as a high-voltage side smoothing capacitor for smoothing V2 and a first circuit 3a formed by connecting a first series body (D1d, D1u) between voltage terminals VL and Vcom, a second series body ( S2d, S2u) is composed of a second circuit 4a formed by serially connecting to the high-voltage side of the first circuit 3a, and an LC series body LC12 functioning as an energy transfer element, composed of a series circuit of a capacitor Cr12 and an inductor Lr12. Constant magnification circuit 5a.

  The second series body (S2d, S2u) constituting the second circuit 4a is configured by connecting in series a low-voltage side element S2d and a high-voltage side element S2u, which are MOSFETs as semiconductor switching elements, and within the constant multiplier circuit 5a. It operates as a drive circuit. The first series body (D1d, D1u) constituting the first circuit 3a is configured by connecting a low-voltage side element D1d and a high-voltage side element D1u made of diode elements in series, and as a rectifier circuit in the constant multiplier circuit 5a. Operate. The LC series body LC12 includes a connection point between the low-voltage side element S2d and the high-voltage side element S2u, which is an intermediate point of the second series body (S2d, S2u), and an intermediate point of the first series body (D1d, D1u). Between the connection point of the low voltage side element D1d and the high voltage side element D1u. Hereinafter, the low voltage side element S2d and the high voltage side element S2u made of MOSFET are simply referred to as S2d and S2u, and the low voltage side element D1d and the high voltage side element D1u made of a diode element are simply referred to as D2d and D2u.

Similarly to the first embodiment, the DC / DC power conversion main circuit 1a is formed by connecting a series body (Spd, Spu) composed of MOSFETs Spd and Spu connected in series between the voltage terminals VL and Vcom. Between the PWM circuit 6, the capacitor Cs as a PWM capacitor connected between the intermediate point of the PWM circuit 6 and the high-voltage side terminal Vm of the second circuit 4a, and the voltage terminal VH and the high-voltage side terminal Vm. And a connected reactor Lc.
Each MOSFET is a power MOSFET in which a parasitic diode is formed between the source and drain.

Details of connection in such a DC / DC power converter will be described. Note that portions similar to those of the first embodiment are omitted.
The source terminal of S2d is connected to the voltage terminal VL, the drain terminal is connected to the source terminal of S2u, and the drain terminal of S2u is connected to one side of the reactor Lc and the high voltage side of the capacitor Cs. The anode terminal of D1d is connected to the voltage terminal Vcom, the cathode terminal is connected to the anode terminal of D1u, and the cathode terminal of D1u is connected to the voltage terminal VL. One end of the LC serial body LC12 is connected to a connection point between S2d and S2u, and the other end is connected to a connection point between D1d and D1u.

  The gate terminals of S2d, S2u, Spd, and Spu and the voltage terminals VL and Vcom are connected to the control circuit 2a. Gate signals GS2d, GS2u, GSpd, and GSpu based on the voltage at the source terminal of each MOSFET are input from the control circuit 2a to the gate terminals of S2d, S2u, Spd, and Spu, and the voltage terminal VL is input to the control circuit 2a. , Vcom voltage is input.

  Next, an operation of stepping down the voltage V2 input between the voltage terminals VH and Vcom to a voltage V1 of 0.4 × V2 to 0.5 × V2 and outputting the voltage between the voltage terminals VL and Vcom will be described. An electric load is connected between the voltage terminals VL and Vcom, and energy is transferred through the path from the voltage terminals VH and Vcom to the voltage terminals VL and Vcom and consumed. Similarly to the first embodiment, the capacitance values of the smoothing capacitors CL and CH and the capacitor Cs are set to a sufficiently large value as compared with the capacitance value of the capacitor Cr12 of the LC series body LC12.

FIG. 9 shows the gate signals GS2d and GS2u of each MOSFET in the constant multiplier circuit 5a, the gate signals GSpd and GSpu of each MOSFET in the PWM circuit 6, the current ILr flowing through the LC series body LC12, and the second circuit 4a. Each waveform of the voltage (Vm) of the high-voltage side terminal Vm and the current ILc of the reactor Lc is shown. The MOSFETs (S2d, S2u, Spd, Spu) are turned on when the gate signal is high. As shown in FIG. 9, the gate signals GS2d and GS2u for the constant multiplier circuit 5a have the same or slightly longer period than the resonance period T determined by the capacitance value of the capacitor Cr12 of the LC series body LC12 and the inductance value of the inductor Lr12. This is an on / off signal of one pulse per cycle with a duty ratio of about 50%. The gate signals GSpd and GSpu for the PWM circuit 6 are on / off signals of one pulse per cycle determined in accordance with the step-down rate in the same cycle that is synchronized with the gate signals GS2d and GS2u for the multiplier circuit 5a.
A voltage of about 2 × V1 is stored in the capacitor Cs, and the voltage V1 is stored in the capacitor Cr12 on an average by repeating the operation described below. The initial charging operation for the capacitor Cs will be described later.

  In the period s1, the gate signal GS2d is a high voltage, the gate signal GS2u is a low voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S2d is turned on, the energy stored in the capacitor Cr12 is transferred to the smoothing capacitor CL through a path of the capacitor Cr12 → the inductor Lr12 → S2d → the smoothing capacitor CL → D1d. On the other hand, when Spd is turned off and Spu is turned on, the capacitor Cs is connected in series to the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 3 × V1. As a result, the energy accumulated in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CL through the path of the reactor Lc → the capacitor Cs → Spu → the smoothing capacitor CL → the smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while decreasing in absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc (in the figure, the current is expressed as a negative current).

  In the period s2, the gate signal GS2d is at a high voltage, the gate signal GS2u is at a low voltage, the gate signal GSpu is at a low voltage, and the gate signal GSpd is at a high voltage. The energy transfer operation to the smoothing capacitor CL is continued from the period s1 while keeping S2d on. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 2 × V1. As a result, energy is transferred to the capacitor Cs through the path of the smoothing capacitor CH → reactor Lc → capacitor Cs → Spd via the reactor Lc, and at the same time, energy is accumulated in the reactor Lc. The current ILc flowing through the reactor Lc flows while increasing the absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period s3, the gate signal GS2d is a low voltage, the gate signal GS2u is a high voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. While Spd remains on, the energy transfer operation to the capacitor Cs via the reactor Lc continues from the period s2. Further, when S2d is turned off and S2u is turned on, the energy accumulated in the capacitor Cs is transferred to the capacitor Cr12 through a path of the capacitor Cs → S2u → inductor Lr12 → capacitor Cr12 → D1u → smoothing capacitor CL → Spd. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12.

By repeating this series of operations, the voltage is stepped down and output.
The constant multiplication circuit 5a operates by using the second circuit 4a as a drive circuit and the first circuit 3a as a rectifier circuit, and performs energy transfer from the capacitor Cs to the capacitor Cr12 and energy transfer from the capacitor Cr12 to the smoothing capacitor CL. Repeat. In addition, the PWM circuit 6 sets the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5a, to 2 × V1 in the period (s2 + s3) and 3 × V1 in the other periods, and to the reactor Lc By connecting to, energy is transferred from the smoothing capacitor CH to the capacitor Cs and the smoothing capacitor CL via the reactor Lc.

By adjusting the length of the period (s2 + s3), the height of the output voltage V1, that is, the step-down rate can be controlled. The output voltage V1 is high when the period (s2 + s3) is long, and it is low when the period is short. It is necessary to provide a half period of the resonance period T as an energy storage period in the capacitor Cr12, during which S2u and Spd are in the on state. Therefore, if the period of the gate signals GS2d, GS2u, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the period (s2 + s3) that is the Spd on period is T / 2 to T It is adjusted in the range. That is, the adjustable output voltage V1 is (0.4 × V2) ≦ V1 ≦ (0.5 × V2).
The control circuit 2a determines the length of the period (s2 + s3) in advance according to a desired step-down rate, and generates one-pulse gate signals GSpd and GSpu in one cycle. Further, in the control circuit 2a, each voltage of the voltage terminals VL and Vcom is input, and when generating the gate signals GSpd and GSpu according to the voltage between the voltage terminals VL and Vcom, a period (s2 + s3) which is a pulse width of the gate signals GSpd and GSpu Adjust the length. That is, the desired output voltage V1 can be reliably obtained by adjusting the length of the period (s2 + s3) so as to suppress the fluctuation of the output voltage V1, which is the voltage between the voltage terminals VL and Vcom.

  Next, an initial charging operation for the capacitor Cs will be described. The capacitor 2 needs to store a voltage 2 × V1. In the initial charging operation, S2d and S2u in the constant multiplying circuit 5a and Spd and Spu in the PWM circuit 6 are turned on and off at a cycle T with the same duty ratio as that in the step-down operation shown in FIG. Thereby, the relationship between the voltage of the capacitor Cs and the voltage V1 can be set to 2: 1. At this time, the voltage V1 is (0.4 × V2) ≦ V1 ≦ (0.5 × V2).

Also in this embodiment, as in the first embodiment, a measure of the size of the reactor Lc by the product of the square of the average current value Iave and the inductance value L of the reactor Lc, L × Iave 2 is conventionally It is significantly smaller than that. For this reason, the size of the reactor, which has conventionally been a large component, can be reduced to various stages, and the DC / DC power converter can be reduced in size and weight.
Further, the voltage level connected to the reactor Lc and the voltage applied to Spd and Spu in the PWM circuit 6 for controlling the period and the current flowing through Spd and Spu can be reduced to each stage compared to the conventional one. Loss can be reduced. In addition, the MOSFET (Spd, Spu) in the PWM circuit 6 can use elements with small ratings, like the MOSFETs (S1d, S1u) in the constant multiplier circuit 5a, and each MOSFET is driven at a high frequency with each stage. can do. As a result, the inductance value L of the reactor Lc can be reduced, and the reactor Lc can be made smaller and lighter.

Further, in the fixed-magnification circuit 5a, LC resonance is used for energy transfer, and the driving cycle of each MOSFET is the same as or slightly larger than the resonance cycle T. When the driving period of each MOSFET is larger than the resonance period T, the resonance current flows for a period of T / 2, and after the current value becomes zero, the first time until the ON / OFF state of the MOSFET (S2d, S2u) changes. Backflow is prevented by each diode element (D1d, D1u) in the circuit 3a and no current flows.
For this reason, when the MOSFETs (S2d, S2u) are switched, the current value flowing through the MOSFETs (S2d, S2u) is zero, and high-efficiency energy transfer with little loss is possible. In addition, since the energy is efficiently transferred using the resonance current, a small element with a small rating can be used for the capacitor Cr12 and the inductor Lr12.

In this embodiment, similarly to the first embodiment, the inductor Lr12 may be connected to the charge / discharge path of the capacitor Cr12, and the same effect can be obtained.
Further, the inductor Lr12 may be omitted. In this case, in the fixed-multiplier circuit 5, a high-efficiency energy transfer using the resonance current is not achieved, but the MOSFET (Spd, Spu) in the PWM circuit 6 is rated. The effect that the high-frequency drive is possible and the reactor Lc can be made smaller and lighter at each stage can be obtained in the same manner.

Embodiment 4 FIG.
Next, a DC / DC power conversion apparatus that performs different control with the same circuit configuration as that of the third embodiment will be described.
In this embodiment, the voltage V2 input between the voltage terminals VH and Vcom is stepped down to a voltage V1 of 0.5 × V2 to 0.67 × V2 and output between the voltage terminals VL and Vcom. As in the third embodiment, an electrical load is connected between the voltage terminals VL and Vcom, and energy is transferred through the path of the voltage terminals VH and Vcom → voltage terminals VL and Vcom and consumed.

FIG. 10 shows the gate signals GS2d and GS2u of each MOSFET in the constant multiplier circuit 5a, the gate signals GSpd and GSpu of each MOSFET in the PWM circuit 6, the current ILr flowing through the LC series body LC12, and the second circuit 4a. Each waveform of the voltage (Vm) of the high-voltage side terminal Vm and the current ILc of the reactor Lc is shown. The MOSFETs (S2d, S2u, Spd, Spu) are turned on when the gate signal is high. As shown in FIG. 10, the gate signals GS2d and GS2u for the constant multiplier circuit 5a have the same or slightly longer period than the resonance period T determined by the capacitance value of the capacitor Cr12 of the LC series body LC12 and the inductance value of the inductor Lr12. This is an on / off signal of one pulse per cycle with a duty ratio of about 50%. The gate signals GSpd and GSpu for the PWM circuit 6 are on / off signals of one pulse per cycle determined in accordance with the step-down rate in the same cycle that is synchronized with the gate signals GS2d and GS2u for the multiplier circuit 5a.
A voltage of about V1 is stored in the capacitor Cs, and the voltage V1 is stored in the capacitor Cr12 on an average by repeating the operation described below. The initial charging operation for the capacitor Cs will be described later.

  In the period ss1, the gate signal GS2d is a low voltage, the gate signal GS2u is a high voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S2u and Spu are turned on, the energy stored in the capacitor Cs is transferred to the capacitor Cr12 through a path of the capacitor Cs → S2u → inductor Lr12 → capacitor Cr12 → D1u → Spu. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12. On the other hand, when Spd is turned off and Spu is turned on, the capacitor Cs is connected in series to the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 2 × V1. As a result, the energy accumulated in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CL and the capacitor Cs through the path of the reactor Lc → the capacitor Cs → Spu → smoothing capacitor CL → smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while decreasing in absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc (in the figure, the current is expressed as a negative current).

  In the period ss2, the gate signal GS2d is at a high voltage, the gate signal GS2u is at a low voltage, the gate signal GSpu is at a high voltage, and the gate signal GSpd is at a low voltage. The energy transfer operation to the smoothing capacitor CL and the capacitor Cs by releasing the energy of the reactor Lc is continued from the period ss1 while the Spu is kept on. On the other hand, when S2u is turned off and S2d is turned on, the energy stored in the capacitor Cr12 is transferred to the smoothing capacitor CL through a path of the capacitor Cr12 → the inductor Lr12 → S2d → the smoothing capacitor CL → D1d.

  In the period ss3, the gate signal GS2d is at a high voltage, the gate signal GS2u is at a low voltage, the gate signal GSpu is at a low voltage, and the gate signal GSpd is at a high voltage. The energy transfer operation to the smoothing capacitor CL is continued from the period ss2 while S2d is maintained in the on state. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC serial body LC12. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 1 × V1. As a result, the energy is transferred to the capacitor Cs through the path of the smoothing capacitor CH → reactor Lc → capacitor Cs → Spd via the reactor Lc, and at the same time, the energy is accumulated in the reactor Lc. The current ILc flowing through the reactor Lc flows while increasing the absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

By repeating this series of operations, the voltage is stepped down and output.
The constant multiplication circuit 5a operates by using the second circuit 4a as a drive circuit and the first circuit 3a as a rectifier circuit, and performs energy transfer from the capacitor Cs to the capacitor Cr12 and energy transfer from the capacitor Cr12 to the smoothing capacitor CL. Repeat. The PWM circuit 6 is connected to the reactor Lc with the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5a, being 1 × V1 in the period ss3 and 2 × V1 in the other periods. By doing so, energy is transferred from the smoothing capacitor CH to the capacitor Cs and the smoothing capacitor CL via the reactor Lc.

By adjusting the length of the period ss3, the height of the output voltage V1, that is, the step-down rate can be controlled. The output voltage V1 is high when the period ss3 is long, and low when the period ss3 is short. It is necessary to provide a period of 1/2 of the resonance period T as an energy storage period in the capacitor Cr12, during which S2u and Spu are in an on state. Therefore, if the period of the gate signals GS2d, GS2u, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the period ss3 that is the Spd on period is T / 2 or less. That is, the adjustable output voltage V1 is (0.5 × V2) ≦ V1 ≦ (0.67 × V2).
The control circuit 2a determines the length of the period ss3 in advance according to a desired step-down rate, and generates one pulse of gate signals GSpd and GSpu in one cycle. In the control circuit 2a, the voltages of the voltage terminals VL and Vcom are input, and when the gate signals GSpd and GSpu are generated according to the voltage between the voltage terminals VL and Vcom, the length of the period ss3 which is the pulse width thereof is generated. Adjust the height. That is, the desired output voltage V1 can be reliably obtained by adjusting the length of the period ss3 so as to suppress the fluctuation of the output voltage V1, which is the voltage between the voltage terminals VL and Vcom.

  Next, an initial charging operation for the capacitor Cs will be described. The capacitor Cs needs to store the voltage V1. In the initial charging operation, S2d and S2u in the constant multiplying circuit 5a and Spd and Spu in the PWM circuit 6 are turned on and off at a cycle T with the same duty ratio as that in the step-down operation shown in FIG. Thereby, the relationship between the voltage of the capacitor Cs and the voltage V1 can be 1: 1. At this time, the voltage V1 is (0.5 × V2) ≦ V1 ≦ (0.67 × V2).

Also in this embodiment, as in the third embodiment, a measure of the size of the reactor Lc by the product of the square of the average current value Iave and the inductance value L of the reactor Lc, L × Iave 2 is conventionally It is significantly smaller than that. For this reason, the size of the reactor, which has conventionally been a large component, can be reduced to various stages, and the DC / DC power converter can be reduced in size and weight.
Further, the voltage level connected to the reactor Lc and the voltage applied to Spd and Spu in the PWM circuit 6 for controlling the period and the current flowing through Spd and Spu can be reduced to each stage compared to the conventional one. Loss can be reduced. In addition, the MOSFET (Spd, Spu) in the PWM circuit 6 can use elements with small ratings, like the MOSFETs (S1d, S1u) in the constant multiplier circuit 5a, and each MOSFET is driven at a high frequency with each stage. can do. As a result, the inductance value L of the reactor Lc can be reduced, and the reactor Lc can be made smaller and lighter.

  Further, in the fixed-magnification circuit 5a, LC resonance is used for energy transfer, and the driving cycle of each MOSFET is the same as or slightly larger than the resonance cycle T. For this reason, when the MOSFETs (S2d, S2u) are switched, the current value flowing through the MOSFETs (S2d, S2u) is zero, and high-efficiency energy transfer with little loss is possible. In addition, since the energy is efficiently transferred using the resonance current, a small element with a small rating can be used for the capacitor Cr12 and the inductor Lr12.

In this embodiment, similarly to the third embodiment, the inductor Lr12 may be connected in the charge / discharge path of the capacitor Cr12, and the same effect can be obtained.
Further, the inductor Lr12 may be omitted. In this case, the constant multiplication circuit 5a does not achieve a high-efficiency energy transfer using the resonance current, but is rated for the MOSFET (Spd, Spu) in the PWM circuit 6. The effect that the high-frequency drive is possible and the reactor Lc can be made smaller and lighter at each stage can be obtained in the same manner.

  Further, the voltage V2 input between the voltage terminals VH and Vcom is stepped down to 0.4 × V2 to 0.5 × V2 in the third embodiment, and 0.5 × V2 to 0 in the fourth embodiment. Although the voltage is stepped down to .67 × V2, the control circuit 2a selects and uses the control shown in the third embodiment or the fourth embodiment according to the step-down rate, so that 0.4 × V2 to 0.67. × V2 can be stepped down and output between voltage terminals VL and Vcom.

Embodiment 5 FIG.
A DC / DC power conversion apparatus according to Embodiment 5 of the present invention will be described below.
FIG. 11 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 5 of the present invention. As shown in FIG. 11, the DC / DC power conversion apparatus includes a DC / DC power conversion main circuit 1b and a control circuit 2b. Then, the voltage V1 input between the low-voltage side input / output terminals (VL, Vcom) is changed to the voltage V2 boosted to 1.5 × V1 to 2.5 × V1, and the high-voltage side input / output terminals (VH, Vcom), and the voltage V2 input between the high-voltage input / output terminals (VH, Vcom) is set to the voltage V1 stepped down to 0.4 × V2 to 0.67 × V2 DC / DC power conversion function with a step-down function output between both side input / output terminals (VL, Vcom). The negative side terminal Vcom of the low voltage side input / output terminals (voltage terminals VL, Vcom) is the same as the negative side terminal Vcom of the high voltage side input / output terminals (voltage terminals VH, Vcom).

  The DC / DC power conversion main circuit 1b is connected between the voltage terminals VL and Vcom and is connected between the voltage terminals VH and Vcom, and the smoothing capacitor CL as a low-voltage side smoothing capacitor for smoothing the output voltage V1. A smoothing capacitor CH as a high-voltage side smoothing capacitor for smoothing V2 and a first series body (S1d, S1u) connected between voltage terminals VL and Vcom, a first circuit body 3b, a second series body ( S2d, S2u) is composed of a second circuit 4b formed by serially connecting to the high-voltage side of the first circuit 3b, and an LC series body LC12 functioning as an energy transfer element, composed of a series circuit of a capacitor Cr12 and an inductor Lr12. Constant magnification circuit 5b.

  The first series body (S1d, S1u) constituting the first circuit 3b and the second series body (S2d, S2u) constituting the second circuit 4b are composed of MOSFETs as semiconductor switching elements. Elements S1d and S2d and high-voltage side elements S1u and S2u are connected in series. In the step-up circuit 5b, during the step-up operation, the first circuit 3b operates as a drive circuit, and the second circuit 4b operates as a rectifier circuit. In the step-down operation, the second circuit 4b operates as a drive circuit, and the first circuit 3b operates as a rectifier circuit. The LC series body LC12 includes a connection point between the low-voltage side element S1d and the high-voltage side element S1u, which is an intermediate point of the first series body (S1d, S1u), and an intermediate point of the second series body (S2d, S2u). Between the connection point of the low voltage side element S2d and the high voltage side element S2u.

In addition, the DC / DC power conversion main circuit 1b is connected between the voltage terminals VL and Vcom, in the same manner as in the first to fourth embodiments, by connecting a series body (Spd, Spu) composed of MOSFETs of Spd and Spu connected in series. A PWM circuit 6, a capacitor Cs as a PWM capacitor connected between the intermediate point of the PWM circuit 6 and the high-voltage side terminal Vm of the second circuit 4 b, and a voltage terminal VH and a high-voltage side terminal Vm And a reactor Lc connected therebetween.
Each MOSFET is a power MOSFET in which a parasitic diode is formed between the source and drain.

  The gate terminal of each MOSFET (S1d, S1u, S2d, S2u, Spd, Spu) and the voltage terminals VL, VH, Vcom are connected to the control circuit 2b. Gate signals GS1d, GS1u, GS2d, GS2u, GSpd, and GSpu based on the voltage of the source terminal of each MOSFET are input from the control circuit 2b to the gate terminals of S1d, S1u, S2d, S2u, Spd, and Spu. Each voltage of voltage terminals VL, VH, and Vcom is input to the circuit 2b.

In this embodiment, the control and operation described in the first and second embodiments are performed during the boosting operation, and the control and operation described in the third and fourth embodiments are performed during the step-down operation. As described above, the step-up / step-down operation is realized by switching between the step-up operation and the step-down operation.
Since the second circuit 4b during the boost operation and the first circuit 3b during the step-down operation are used as rectifier circuits, each MOSFET is turned off and rectified by a parasitic diode between the source and drain. The operation is the same as in the first and second embodiments and the third and fourth embodiments. In the operation as the rectifier circuit, each MOSFET may be turned on in accordance with the conduction timing of the parasitic diode, and the loss becomes smaller.

  As described above, this embodiment has both DC / DC power conversion functions of the step-up function and the step-down function, and, similarly to the above-described embodiments, the MOSFET (Spd, Spu) enables high-frequency driving of each MOSFET using a small-rated element, and the size of the reactor Lc is made smaller in each stage to promote the downsizing and weight reduction of the DC / DC power converter and high efficiency. Energy transfer.

Embodiment 6 FIG.
Hereinafter, a DC / DC power converter according to Embodiment 6 of the present invention will be described.
FIG. 12 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 6 of the present invention. As shown in FIG. 12, the DC / DC power converter is composed of a DC / DC power converter main circuit 1c and a control circuit 2c, and a voltage V1 inputted between both low-voltage input / output terminals (VL, Vcom). Has a DC / DC power conversion function for performing a step-up operation in which a voltage V2 boosted to 2.5 × V1 to 3.5 × V1 is output between the high-voltage side input / output terminals (VH, Vcom). The negative side terminal Vcom of the low voltage side input / output terminals (voltage terminals VL, Vcom) is the same as the negative side terminal Vcom of the high voltage side input / output terminals (voltage terminals VH, Vcom).

The DC / DC power conversion main circuit 1c is connected between the voltage terminals VL and Vcom and is connected between the voltage terminals VH and Vcom, and the smoothing capacitor CL as a low-voltage side smoothing capacitor for smoothing the input voltage V1. A smoothing capacitor CH as a high-voltage side smoothing capacitor for smoothing V2 and a constant multiplier circuit 5c having a first circuit 3c, a second circuit 4c, and LC series bodies LC12 and LC13 functioning as energy transfer elements are provided.
The first circuit 3c includes two first series bodies (S1dA, S1uA) configured by connecting low-voltage side elements S1dA, S1dB, and high-voltage side elements S1uA, S1uB made of MOSFETs as semiconductor switching elements, (S1dB, S1uB) are connected in parallel between the voltage terminals VL and Vcom, and operate as a drive circuit in the constant multiplier circuit 5c. The second circuit 4c includes two second serial bodies (D2d, D2u), (D3d, D3u) configured by connecting low-voltage side elements D2d, D3d, which are diode elements, and high-voltage side elements D2u, D3u in series. ) In series, and a smoothing capacitor CL2 is connected in parallel to the second series body (D2d, D2u) on the low voltage side. Further, the two second series bodies (D2d, D2u), (D3d, D3u) operate as rectifier circuits in the constant multiplier circuit 5c.

  The LC series body LC12 is composed of a series circuit of a capacitor Cr12 and an inductor Lr12, and is between an intermediate point of the first series body (S1dA, S1uA) and an intermediate point of the second series body (D2d, D2u). Connected to. The LC series body LC13 is composed of a series circuit of a capacitor Cr13 and an inductor Lr13, and is connected between the midpoint of the first series body (S1dB, S1uB) and the midpoint of the second series body (D3d, D3u). Is done. Hereinafter, the low-voltage side elements S1dA, S1dB made of MOSFET, the high-voltage side elements S1uA, S1uB are simply S1dA, S1dB, S1uA, S1uB, the low-voltage side elements D2d, D3d made of diode elements, the high-voltage side elements D2u, D3u are simply D2d, They are called D3d, D2u, and D3u.

In addition, the DC / DC power conversion main circuit 1c is formed by connecting a series body (Spd, Spu) in which Spd and Spu made of MOSFETs are connected in series between the voltage terminals VL and Vcom, as in the above embodiments. Between the PWM circuit 6, a capacitor Cs as a PWM capacitor connected between the intermediate point of the PWM circuit 6 and the high-voltage side terminal Vm of the second circuit 4c, and between the voltage terminal VH and the high-voltage side terminal Vm. And a connected reactor Lc.
Each MOSFET is a power MOSFET in which a parasitic diode is formed between the source and drain.

Details of connection in such a DC / DC power converter will be described.
Both terminals of the smoothing capacitor CL are connected to voltage terminals VL and Vcom, respectively, and the voltage terminal Vcom is grounded. The low voltage side terminal of the smoothing capacitor CH is connected to the voltage terminal Vcom, and the high voltage side terminal is connected to the voltage terminal VH. The source terminal of S1dA is connected to the voltage terminal Vcom, the drain terminal is connected to the source terminal of S1uA, and the drain terminal of S1uA is connected to the voltage terminal VL. The source terminal of S1dB is connected to the voltage terminal Vcom, the drain terminal is connected to the source terminal of S1uB, and the drain terminal of S1uB is connected to the voltage terminal VL. The source terminal of Spd is connected to the voltage terminal Vcom, the drain terminal is connected to the source terminal of Spu, and the drain terminal of Spu is connected to the voltage terminal VL. The anode terminal of D2d is connected to the voltage terminal VL, the cathode terminal is connected to the anode terminal of D2u, the cathode terminal of D2u is connected to one of the smoothing capacitors CL2, and the other of CL2 is connected to the voltage terminal VL. The anode terminal of D3d is connected to the cathode of D2u, the cathode terminal is connected to the anode terminal of D3u, and the cathode terminal of D3u is connected to one side of the reactor Lc and the high voltage side of the capacitor Cs.

One end of the LC serial body LC12 is connected to a connection point between S1dA and S1uA, and the other end is connected to a connection point between D2d and D2u. One end of the LC serial body LC13 is connected to a connection point between S1dB and S1uB, and the other end is connected to a connection point between D3d and D3u. One end of the capacitor Cs is connected to a connection point between Spd and Spu, and the other end is connected to one of the cathode terminal of D3u and the reactor Lc. The other of the reactors Lc is connected to the high voltage side of the smoothing capacitor CH and the voltage terminal VH.
The gate terminals of S1dA, S1uA, S1dB, S1uB, Spd, and Spu and the voltage terminals VH and Vcom are connected to the control circuit 2c. Gate signals GS1dA, GS1uA, GS1dB, GS1uB, GSpd, and GSpu based on the voltage at the source terminal of each MOSFET are input to the gate terminals of S1dA, S1uA, S1dB, S1uB, Spd, and Spu from the control circuit 2c. Each voltage of the voltage terminals VH and Vcom is input to the circuit 2c.

As described above, the DC / DC power converter according to this embodiment converts the voltage V1 input between the voltage terminals VL and Vcom to the voltage V2 boosted to 2.5 × V1 to 3.5 × V1. However, the control differs between the first case of boosting to 3 × V1 to 3.5 × V1 and the second case of boosting to 2.5 × V1 to 3 × V1.
First, in the first case, that is, an operation in which the voltage V1 input between the voltage terminals VL and Vcom is boosted to a voltage V2 of 3 × V1 to 3.5 × V1 and output between the voltage terminals VH and Vcom. Will be described. An electric load is connected between the voltage terminals VH and Vcom, and energy is transferred through the paths of the voltage terminals VL and Vcom to the voltage terminals VH and Vcom and consumed. Further, the capacitance values of the smoothing capacitors CL, CL2, CH, and the capacitor Cs are set to sufficiently large values as compared with the capacitance values of the capacitors Cr12 and Cr13 of the LC series bodies LC12 and LC13. Further, the resonance period of the LC series body LC12 determined from Lr12 and Cr12 and the resonance period of the LC series body LC13 determined from Lr13 and Cr13 are almost the same.

FIG. 13 shows the gate signals GS1dA, GS1uA, GS1dB, GS1uB of each MOSFET in the constant multiplier circuit 5c, the gate signals GSpd, GSpu of each MOSFET in the PWM circuit 6, and the current ILr1 flowing through the LC series bodies LC12, LC13. , ILr2, the voltage of the high-voltage side terminal Vm (indicated as Vm) of the second circuit 4c, and the current ILc of the reactor Lc are shown. Each MOSFET is turned on when the gate signal is at a high voltage. As shown in FIG. 13, the gate signals GS1dA, GS1uA, GS1dB, and GS1uB for the constant multiplier 5c are resonances determined by the capacitance values of the capacitors Cr12 and Cr13 of the LC series bodies LC12 and LC13 and the inductance values of the inductors Lr12 and Lr13. It is an on / off signal of one pulse per cycle with a duty ratio of about 50% and a cycle that is slightly larger than the cycle T. The gate signals GSpd and GSpu for the PWM circuit 6 are the same period synchronized with the gate signals GS1dA, GS1uA, GS1dB, and GS1uB for the constant multiplier circuit 5c, and one pulse on / off signal determined in accordance with the boost rate. It is.
The capacitor Cs stores a voltage of about 3 × V1, and the smoothing capacitor CL2 stores a voltage of about V1. Further, by repeating the operation described below, the voltage V1 is accumulated in the capacitor Cr12 and the voltage of about 2 × V1 is accumulated in the capacitor Cr13 on average. The initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described later.

  In the period u1, the gate signal GS1dA is a low voltage, the gate signal GS1uA is a high voltage, the gate signal GS1dB is a high voltage, the gate signal GS1uB is a low voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S1uA and S1dB are turned on, energy is passed through the path of capacitor Cr12 → inductor Lr12 → D2u → smoothing capacitor CL2 → S1uA and smoothing capacitor CL → smoothing capacitor CL2 → D3d → inductor Lr13 → capacitor Cr13 → S1dB. Then, the process proceeds to the smoothing capacitor CL2 and the capacitor Cr13. On the other hand, when Spu is turned on, the capacitor Cs is connected in series to the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 4 × V1. As a result, the energy is transferred to the smoothing capacitor CH via the reactor Lc through the path of the smoothing capacitor CL → Spu → capacitor Cs → reactor Lc → smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while increasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period u2, the gate signal GS1dA is a low voltage, the gate signal GS1uA is a high voltage, the gate signal GS1dB is a high voltage, the gate signal GS1uB is a low voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. The energy transfer operation to the smoothing capacitor CL2 and the capacitor Cr13 is continued from the period u1 while the S1uA and S1dB are kept on. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 3 × V1. As a result, the energy accumulated in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CH through the path of the reactor Lc → smoothing capacitor CH → Spd → capacitor Cs. The current ILc flowing through the reactor Lc flows while decreasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period u3, the gate signal GS1dA is a high voltage, the gate signal GS1uA is a low voltage, the gate signal GS1dB is a low voltage, the gate signal GS1uB is a high voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. Spd is maintained in the ON state, and the energy transfer operation from reactor Lc to smoothing capacitor CH is continued from period u2. When S1dA is turned on and S1uA is turned off, and S1dB is turned off and S1uB is turned on, the energy accumulated in the smoothing capacitor CL and the capacitor Cr13 is changed to the smoothing capacitor CL → D2d → inductor Lr12 → capacitor Cr12 → S1dA path, Transition is made to the capacitor Cr12 and the capacitor Cs through the path of Cr13 → inductor Lr13 → D3u → capacitor Cs → Spd → smoothing capacitor CL → S1uB. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13.

By repeating this series of operations, the voltage is boosted and output.
The constant multiplier circuit 5c has two first series bodies (S1dA, S1uA) and (S1dB, S1uB) of the first circuit 3c as drive circuits, and two second series bodies of the second circuit 4c. (D2d, D2u), (D3d, D3u) are operated as a rectifier circuit, and energy transfer from the smoothing capacitor CL to the capacitors Cr12, Cr13 and the smoothing capacitor CL2 and further to the capacitor Cs is repeated. Further, the PWM circuit 6 is connected to the reactor Lc with the voltage (Vm) of the high-voltage side terminal Vm that is the high-voltage side terminal of the constant multiplier circuit 5c being 4 × V1 in the period u1 and 3 × V1 in other periods. By doing so, energy is transferred to the smoothing capacitor CH through the reactor Lc.

By adjusting the length of the period u1, the height of the output voltage V2, that is, the step-up rate can be controlled. The output voltage V2 is high when the period u1 is long, and low when the period u1 is short. It is necessary to provide a half period of the resonance period T as an energy storage period in the capacitor Cs, and S1dA, S1uB, and Spd are in an on state during that period. Therefore, if the period of the gate signals GS1dA, GS1uA, GS1dB, GS1uB, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the period u1 that is the ON period of Spu is T / 2. It is as follows. That is, the maximum value of the adjustable output voltage is 3.5 × V1.
The control circuit 2c determines the length of the period u1 in advance according to a desired boosting rate, and generates one-pulse gate signals GSpd and GSpu in one cycle. Further, in the control circuit 2c, each voltage of the voltage terminals VH and Vcom is input, and when the gate signals GSpd and GSpu are generated according to the voltage between the voltage terminals VH and Vcom, the length of the period u1 which is the pulse width thereof is generated. Adjust the height. That is, the desired output voltage V2 can be reliably obtained by adjusting the length of the period u1 so as to suppress the fluctuation of the output voltage V2 that is the voltage between the voltage terminals VH and Vcom.

  Next, an initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described. The capacitor Cs needs to store the voltage 3 × V1, and the smoothing capacitor CL2 needs to store the voltage V1. In the initial charging operation, Spd is turned on and Spu is turned off in the PWM circuit 6, and S1dA and S1uA, and S1dB and S1uB are alternately turned on and off in the cycle T in the constant multiplier circuit 5c. With this operation, the capacitor Cs can be charged with the voltage 3 × V1, and at the same time, the smoothing capacitor CL2 can be charged with the voltage V1.

The specifications (characteristics) of the reactor Lc used for the DC / DC power converter that operates in this way will be described below. For example, the output when the ratio (ΔI / Iave) of the ripple current pp value ΔI of the current ILc flowing through the reactor Lc to the average current value Iave (ΔI / Iave) is 0.8, with a frequency of 10 kHz, V1 = 250 V, output power of 10 kW The relationship between the voltage V2 and the characteristics of the reactor Lc is illustrated together with a comparative example. In particular, the average current value Iave of the reactor Lc is shown in FIG. 14, the inductance value L of the reactor Lc is shown in FIG. 15, and the product of the inductance value L and the square of the average current value Iave is a measure of the size of the reactor Lc. L × Iave 2 is shown in FIG. The comparative example is the same as the conventional comparative example shown in the first embodiment.

As shown in the figure, compared with the comparative example, the average current value Iave of the reactor Lc according to this embodiment is small, and the inductance value L is small in each stage on the low output voltage level side. In addition, L × Iave 2 that is a guide for the size of the reactor Lc is also significantly reduced. As described above, according to this embodiment, the size of the reactor, which has conventionally been a large component, can be made smaller, and the DC / DC power converter can be reduced in size and weight.

Next, in the second case, that is, the voltage V1 input between the voltage terminals VL and Vcom is boosted to a voltage V2 of 2.5 × V1 to 3 × V1 and output between the voltage terminals VH and Vcom. The operation will be described.
As in the first case, an electrical load is connected between the voltage terminals VH and Vcom, and energy is transferred through the paths of the voltage terminals VL and Vcom to the voltage terminals VH and Vcom and consumed.

FIG. 17 shows the gate signals GS1dA, GS1uA, GS1dB, GS1uB of each MOSFET in the constant multiplier circuit 5c, the gate signals GSpd, GSpu of each MOSFET in the PWM circuit 6, and the current ILr1 flowing through the LC series bodies LC12, LC13. , ILr2, the voltage of the high-voltage side terminal Vm (indicated as Vm) of the second circuit 4c, and the current ILc of the reactor Lc are shown. As shown in FIG. 17, the gate signals GS1dA, GS1uA, GS1dB, and GS1uB for the constant multiplier 5c are resonances determined by the capacitance values of the capacitors Cr12 and Cr13 of the LC series LC12 and LC13 and the inductance values of the inductors Lr12 and Lr13. It is an on / off signal of one pulse per cycle with a duty ratio of about 50% and a cycle that is slightly larger than the cycle T. The gate signals GSpd and GSpu for the PWM circuit 6 are the same period synchronized with the gate signals GS1dA, GS1uA, GS1dB, and GS1uB for the constant multiplier circuit 5c, and one pulse on / off signal determined in accordance with the boost rate. It is.
The capacitor Cs stores a voltage of about 2 × V1, and the smoothing capacitor CL2 stores a voltage of about V1. Further, by repeating the operation described below, the voltage V1 is accumulated in the capacitor Cr12 and the voltage of about 2 × V1 is accumulated in the capacitor Cr13 on average. The initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described later.

  In the period uu1, the gate signal GS1dA is a high voltage, the gate signal GS1uA is a low voltage, the gate signal GS1dB is a low voltage, the gate signal GS1uB is a high voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S1dA and S1uB are turned on, the energy is transferred from the smoothing capacitor CL → D2d → inductor Lr12 → capacitor Cr12 → S1dA to the capacitor Cr13 → inductor Lr13 → D3u → capacitor Cs → Spu → S1uB. And transition to capacitor Cs. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13. On the other hand, when Spu is turned on, the capacitor Cs is connected in series with the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 3 × V1. As a result, the energy is transferred to the smoothing capacitor CH via the reactor Lc through the path of the smoothing capacitor CL → Spu → capacitor Cs → reactor Lc → smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while increasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period uu2, the gate signal GS1dA is a low voltage, the gate signal GS1uA is a high voltage, the gate signal GS1dB is a high voltage, the gate signal GS1uB is a low voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. The energy transfer operation to the smoothing capacitor CH via the reactor Lc is continued from the period uu1 while the Spu is kept on. On the other hand, when S1uA and S1dB are turned on, the energy is changed from capacitor Cr12 → inductor Lr12 → D2u → smoothing capacitor CL2 → S1uA and smoothing capacitor CL → smoothing capacitor CL2 → D3d → inductor Lr13 → capacitor Cr13 → S1dB. The path moves to the smoothing capacitor CL2 and the capacitor Cr13.

  In the period uu3, the gate signal GS1dA is a low voltage, the gate signal GS1uA is a high voltage, the gate signal GS1dB is a high voltage, the gate signal GS1uB is a low voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. The energy transfer operation to the smoothing capacitor CL2 and the capacitor Cr13 continues from the period uu2 while S1uA and S1dB remain on. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 2 × V1. Thereby, the energy accumulated in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CH through the path of the reactor Lc → smoothing capacitor CH → Spd → capacitor Cs. The current ILc flowing through the reactor Lc flows while decreasing at a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

By repeating this series of operations, the voltage is boosted and output.
The constant multiplier circuit 5c has two first series bodies (S1dA, S1uA) and (S1dB, S1uB) of the first circuit 3c as drive circuits, and two second series bodies of the second circuit 4c. (D2d, D2u), (D3d, D3u) are operated as a rectifier circuit, and energy transfer from the smoothing capacitor CL to the capacitors Cr12, Cr13 and the smoothing capacitor CL2 and further to the capacitor Cs is repeated. Further, the PWM circuit 6 sets the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5c, to 3 × V1 in the period (uu1 + uu2), and 2 × V1 in the other periods, and the reactor Lc By connecting to, energy is transferred to the smoothing capacitor CH via the reactor Lc.

By adjusting the length of the period (uu1 + uu2), the height of the output voltage V2, that is, the step-up rate can be controlled. The output voltage V2 is high when the period (uu1 + uu2) is long, and low when the period is short. It is necessary to provide a half period of the resonance period T as an energy accumulation period in the capacitor Cs, and S1dA, S1uB, and Spu are in an on state during that period. Therefore, if the period of the gate signals GS1dA, GS1uA, GS1dB, GS1uB, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the period (uu1 + uu2) that is the Spu on period is T It is adjusted in the range of / 2 to T. That is, the minimum value of the adjustable output voltage is 2.5 × V1.
The control circuit 2c determines the length of the period (uu1 + uu2) in advance according to the desired boosting rate, and generates one-pulse gate signals GSpd and GSpu in one cycle. In the control circuit 2c, the voltages at the voltage terminals VH and Vcom are input, and the period (uu1 + uu2) corresponding to the pulse width when the gate signals GSpd and GSpu are generated according to the voltage between the voltage terminals VH and Vcom. Adjust the length. That is, the desired output voltage V2 can be reliably obtained by adjusting the length of the period (uu1 + uu2) so as to suppress the fluctuation of the output voltage V2, which is a voltage between the voltage terminals VH and Vcom.

  Next, an initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described. The capacitor Cs needs to store the voltage 2 × V1, and the smoothing capacitor CL2 needs to store the voltage V1. In the initial charging operation, Spd is turned off and Spu is turned on in the PWM circuit 6, and S1dA and S1uA, and S1dB and S1uB are alternately turned on and off in the cycle T in the constant multiplier circuit 5c. By this operation, the voltage 2 × V1 can be charged to the capacitor Cs, and at the same time, the voltage V1 can be charged to the smoothing capacitor CL2.

The specifications (characteristics) of the reactor Lc used for the DC / DC power converter that operates in this way will be described below. For example, the output when the ratio (ΔI / Iave) of the ripple current pp value ΔI of the current ILc flowing through the reactor Lc to the average current value Iave (ΔI / Iave) is 0.8, with a frequency of 10 kHz, V1 = 250 V, output power of 10 kW A relationship between the voltage V2 and the characteristics of the reactor Lc is shown in FIG. 18 together with a comparative example. The comparative example is the same as the conventional comparative example shown in the first embodiment. As shown in the figure, the product of the inductance value L of the reactor Lc and the square of the average current value Iave is a measure of the size of the reactor Lc, and L × Iave 2 is significantly smaller than the comparative example. . In this way, the size of the reactor, which has conventionally been a large component, can be made smaller, and the DC / DC power converter can be reduced in size and weight.

  Further, in both the first case and the second case described above, as in the first embodiment, the voltage level connected to the reactor Lc is applied to Spd and Spu in the PWM circuit 6 for controlling the period. Voltage and the current flowing through Spd and Spu can be reduced in stages compared to the conventional one, and loss can be reduced. As the MOSFET (Spd, Spu) in the PWM circuit 6, an element with a small rating can be used similarly to the MOSFET in the constant multiplier circuit 5 c, and each MOSFET can be driven at a high frequency with each stage. As a result, the inductance value L of the reactor Lc can be reduced, and the reactor Lc can be made smaller and lighter.

  Further, in the constant multiplication circuit 5c, LC resonance is used for energy transfer, and the driving period of each MOSFET is made the same as or slightly larger than the resonance period T. For this reason, at the time of MOSFET switching, the current value flowing through the MOSFET is zero, and high-efficiency energy transfer with low loss becomes possible. Further, since energy is efficiently transferred using the resonance current, small elements with small ratings can be used for the capacitors Cr12 and Cr13 and the inductors Lr12 and Lr13.

In this embodiment, similarly to the first embodiment, the inductor Lr12 may be connected to the charge / discharge path of the capacitor Cr12, and the inductor Lr13 may be connected to the charge / discharge path of the capacitor Cr13. can get.
In addition, the inductors Lr12 and Lr13 may be omitted. In this case, in the constant multiplier circuit 5c, high-efficiency energy transfer using the resonance current is not achieved, but MOSFETs (Spd, Spu) in the PWM circuit 6 are not used. An element having a small rating can be used, and high-frequency driving is possible, and the effect of reducing the size and weight of the reactor Lc can be obtained in the same manner.

  Further, the voltage V1 inputted between the voltage terminals VL and Vcom is boosted to 3 × V1 to 3.5 × V1 in the first case, and 2.5 × V1 to 3 × V1 in the second case. However, when the control circuit 2c selects and uses the control shown in the first or second case according to the boosting rate, the voltage is boosted to 2.5 × V1 to 3.5 × V1. Can be output between the voltage terminals VH and Vcom.

Embodiment 7 FIG.
Next, a DC / DC power converter according to Embodiment 7 of the present invention will be described.
FIG. 19 shows a circuit configuration of a DC / DC power conversion apparatus according to Embodiment 7 of the present invention. As shown in FIG. 19, the DC / DC power conversion device is constituted by a DC / DC power conversion main circuit 1d and a control circuit 2d, and a voltage V2 inputted between both high-voltage input / output terminals (VH, Vcom). Is converted to a voltage V1 stepped down to 0.29 × V2 to 0.4 × V2, and has a DC / DC power conversion function for performing a step-down operation for outputting the voltage between both low-voltage input / output terminals (VL, Vcom). The negative side terminal Vcom of the low voltage side input / output terminals (voltage terminals VL, Vcom) is the same as the negative side terminal Vcom of the high voltage side input / output terminals (voltage terminals VH, Vcom).

The DC / DC power conversion main circuit 1d is connected between the voltage terminals VL and Vcom and is connected between the voltage terminals VH and Vcom, and the smoothing capacitor CL as a low-voltage side smoothing capacitor for smoothing the input voltage V1 and the output voltage. A smoothing capacitor CH as a high-voltage side smoothing capacitor for smoothing V2 and a constant multiplier circuit 5d having a first circuit 3d, a second circuit 4d, and LC series bodies LC12 and LC13 functioning as energy transfer elements are provided.
The first circuit 3d includes two first series bodies (D1dA, D1uA), (D1dB, D1uB) configured by connecting low-voltage side elements D1dA, D1dB, which are diode elements, and high-voltage side elements D1uA, D1uB in series. ) Are connected in parallel between the voltage terminals VL and Vcom, and operate as a rectifier circuit in the constant multiplier circuit 5d. The second circuit 4d includes two second series bodies (S2d, S2u) configured by connecting low-voltage side elements S2d, S3d, and high-voltage side elements S2u, S3u, which are NOSFETs as semiconductor elements, in series. S3d, S3u) are connected in series, and a smoothing capacitor CL2 is connected in parallel to the second series body (S2d, S2u) on the low voltage side. Further, the two second serial bodies (S2d, S2u) and (S3d, S3u) operate as drive circuits in the constant multiplier circuit 5d.

  The LC series body LC12 is composed of a series circuit of a capacitor Cr12 and an inductor Lr12, and is between an intermediate point of the first series body (D1dA, D1uA) and an intermediate point of the second series body (S2d, S2u). Connected to. The LC series body LC13 is composed of a series circuit of a capacitor Cr13 and an inductor Lr13, and is connected between the midpoint of the first series body (D1dB, D1uB) and the midpoint of the second series body (S3d, S3u). Is done. Hereinafter, the low voltage side elements S2d, S3d made of MOSFET, the high voltage side elements S2u, S3u are simply S2d, S3d, S2u, S3u, the low voltage side elements D1dA, D1dB made of diode elements, the high voltage side elements D1uA, D1uA are simply D1dA, They are called D1dB, D1uA, and D1uA.

In addition, the DC / DC power conversion main circuit 1d is formed by connecting a series body (Spd, Spu) in which Spd and Spu made of MOSFETs are connected in series between the voltage terminals VL and Vcom, as in the above embodiments. Between the PWM circuit 6, the capacitor Cs as a PWM capacitor connected between the intermediate point of the PWM circuit 6 and the high voltage side terminal Vm of the second circuit 4d, and between the voltage terminal VH and the high voltage side terminal Vm. And a connected reactor Lc.
Each MOSFET is a power MOSFET in which a parasitic diode is formed between the source and drain.

Details of connection in such a DC / DC power converter will be described. Note that portions similar to those of the sixth embodiment are omitted.
The source terminal of S2d is connected to the voltage terminal VL, the drain terminal is connected to the source terminal of S2u, and the drain terminal of S2u is connected to the source terminal of S3d. The drain terminal of S3d is connected to the source terminal of S3u, and the drain terminal of S3u is connected to the connection point between the reactor Lc and the capacitor Cs. The anode terminal of D1dA is connected to the voltage terminal Vcom, the cathode terminal is connected to the anode terminal of D1u, and the cathode terminal of D1u is connected to the voltage terminal VL. The anode terminal of D1dB is connected to the voltage terminal Vcom, the cathode terminal is connected to the anode terminal of D1uB, and the cathode terminal of D1uB is connected to the voltage terminal VL. One end of the LC serial body LC12 is connected to a connection point between S2d and S2u, and the other end is connected to a connection point between D1dA and D1uA. One end of the LC serial body LC13 is connected to a connection point between S3d and S3u, and the other end is connected to a connection point between D1dB and D1uB.

  The gate terminals of S2d, S2u, S3d, S3u, Spd, and Spu and the voltage terminals VL and Vcom are connected to the control circuit 2d. Gate signals GS2d, GS2u, GS3d, GS3u, GSpd, and GSpu based on the voltage of the source terminal of each MOSFET are input to the gate terminals of S2d, S2u, S3d, S3u, Spd, and Spu, and the control circuit 2d The voltages at the voltage terminals VL and Vcom are input.

As described above, the DC / DC power converter according to this embodiment converts the voltage V2 input between the voltage terminals VH and Vcom to the voltage V1 that is stepped down to 0.29 × V2 to 0.4 × V2. The control is different between the first case where the voltage is lowered to 0.29 × V2 to 0.33 × V2 and the second case where the voltage is lowered to 0.33 × V2 to 0.4 × V2. .
First, in the first case, that is, the voltage V2 input between the voltage terminals VH and Vcom is stepped down to a voltage V1 of 0.29 × V2 to 0.33 × V2 and output between the voltage terminals VL and Vcom. The operation to be performed will be described. An electric load is connected between the voltage terminals VL and Vcom, and energy is transferred through the path from the voltage terminals VH and Vcom to the voltage terminals VL and Vcom and consumed. Further, the capacitance values of the smoothing capacitors CL, CL2, CH, and the capacitor Cs are set to sufficiently large values as compared with the capacitance values of the capacitors Cr12 and Cr13 of the LC series bodies LC12 and LC13. The resonance period of the LC series body LC12 determined by Lr12 and Cr12 and the resonance period of the LC series body LC13 determined by Lr13 and Cr13 are almost the same.

FIG. 20 shows gate signals GS2d, GS2u, GS3d, and GS3u of the MOSFETs in the constant multiplier circuit 5d, gate signals GSpd and GSpu of the MOSFETs in the PWM circuit 6, and currents ILr1 flowing through the LC series bodies LC12 and LC13. , ILr2, the voltage of the high-voltage side terminal Vm of the second circuit 4d (shown as Vm), and the current ILc of the reactor Lc are shown. Each MOSFET is turned on when the gate signal is at a high voltage. As shown in FIG. 20, the gate signals GS2d, GS2u, GS3d, and GS3u for the constant multiplication circuit 5d are resonances determined by the capacitance values of the capacitors Cr12 and Cr13 of the LC series bodies LC12 and LC13 and the inductance values of the inductors Lr12 and Lr13. It is an on / off signal of one pulse per cycle with a duty ratio of about 50% and a cycle that is slightly larger than the cycle T. The gate signals GSpd and GSpu for the PWM circuit 6 are the same period synchronized with the gate signals GS2d, GS2u, GS3d and GS3u for the constant multiplier circuit 5d, and one pulse ON / OFF signal determined in accordance with the step-down rate. It is.
The capacitor Cs stores a voltage of about 3 × V1, and the smoothing capacitor CL2 stores a voltage of about V1. Further, by repeating the operation described below, the voltage V1 is accumulated in the capacitor Cr12 and the voltage of about 2 × V1 is accumulated in the capacitor Cr13 on average. The initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described later.

  In the period v1, the gate signal GS2d is a low voltage, the gate signal GS2u is a high voltage, the gate signal GS3d is a high voltage, the gate signal GS3u is a low voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S2u and S3d are turned on, energy is passed between the smoothing capacitor CL2 → S2u → inductor Lr12 → capacitor Cr12 → D1uA and the capacitor Cr13 → inductor Lr13 → S3d → smoothing capacitor CL2 → smoothing capacitor CL → D1dB. , Transition to capacitor Cr12 and smoothing capacitors CL, CL2. On the other hand, when Spd is turned off and Spu is turned on, the capacitor Cs is connected in series to the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 4 × V1. As a result, the energy stored in the reactor Lc is released, and the energy is transferred to the smoothing capacitor CL through the path of the reactor Lc → the capacitor Cs → Spu → the smoothing capacitor CL → the smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while decreasing in absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc (in the figure, the current is expressed as a negative current).

  In the period v2, the gate signal GS2d is a low voltage, the gate signal GS2u is a high voltage, the gate signal GS3d is a high voltage, the gate signal GS3u is a low voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. The energy transfer operation to the capacitor Cr12 and the smoothing capacitors CL and CL2 is continued from the period v1 while the S2u and S3d are kept on. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 3 × V1. As a result, energy is transferred to the capacitor Cs through the path of the smoothing capacitor CH → reactor Lc → capacitor Cs → Spd via the reactor Lc, and at the same time, energy is accumulated in the reactor Lc. The current ILc flowing through the reactor Lc flows while increasing the absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

  In the period v3, the gate signal GS2d is a high voltage, the gate signal GS2u is a low voltage, the gate signal GS3d is a low voltage, the gate signal GS3u is a high voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. While Spd remains on, the energy transfer operation to the capacitor Cs via the reactor Lc continues from the period v2. Further, when S2u is turned off and S2d is turned on, and S3u is turned on and S3d is turned off, the energy accumulated in the capacitor Cr12 and the capacitor Cs is changed to the path of the capacitor Cr12 → the inductor Lr12 → S2d → the smoothing capacitor CL → D1dA, Transition is made to the smoothing capacitor CL and the capacitor Cr13 through the path of the capacitor Cs → S3u → inductor Lr13 → capacitor Cr13 → D1uB → smoothing capacitor CL → Spd. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13.

By repeating this series of operations, the voltage is stepped down and output.
The constant multiplication circuit 5d has two first serial bodies of the first circuit 3d using the two second serial bodies (S2d, S2u) and (S3d, S3u) of the second circuit 4d as drive circuits. (D1dA, D1uA) and (D1dB, D1uB) are operated as a rectifier circuit, and energy transfer from the capacitor Cs to the capacitors Cr12, Cr13 and the smoothing capacitor CL2 and further to the smoothing capacitor CL is repeatedly performed. In addition, the PWM circuit 6 sets the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5d, to 3 × V1 in the period (v2 + v3), and 4 × V1 in the other periods, and the reactor Lc By connecting to, energy is transferred from the smoothing capacitor CH to the capacitor Cs and the smoothing capacitor CL via the reactor Lc.

By adjusting the length of the period (v2 + v3), the height of the output voltage V1, that is, the step-down rate can be controlled. The output voltage V1 is high when the period (v2 + v3) is long, and low when the period is short. It is necessary to provide a period of 1/2 of the resonance period T as an energy accumulation period in the capacitor Cr13, during which S2u, S3d, and Spd are in the on state. Therefore, if the period of the gate signals GS2d, GS2u, GS3d, GS3u, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the Spd on period (v2 + v3) is T It is adjusted in the range of / 2 to T. That is, the adjustable output voltage V1 is (0.29 × V2) ≦ V1 ≦ (0.33 × V2).
The control circuit 2d determines the length of the period (v2 + v3) in advance according to a desired step-down rate, and generates one-pulse gate signals GSpd and GSpu in one cycle. Further, in the control circuit 2d, each voltage of the voltage terminals VL and Vcom is input, and a period (v2 + v3) having a pulse width when the gate signals GSpd and GSpu are generated according to the voltage between the voltage terminals VL and Vcom. Adjust the length. That is, by adjusting the length of the period (v2 + v3) so as to suppress the fluctuation of the output voltage V1, which is the voltage between the voltage terminals VL and Vcom, it is possible to reliably obtain the output voltage V1 having a desired step-down rate. .

Next, an initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described. The capacitor Cs needs to store the voltage 3 × V1, and the smoothing capacitor CL2 needs to store the voltage V1.
In the initial charging operation, S2d, S2u and S3d, S3u in the constant multiplying circuit 5d and Spd, Spu in the PWM circuit 6 are turned on / off at a cycle T with the same duty ratio as that in the step-down operation shown in FIG. With this operation, the capacitor Cs can be charged with the voltage 3 × V1, and at the same time, the smoothing capacitor CL2 can be charged with the voltage V1. At this time, the voltage V1 is (0.29 × V2) ≦ V1 ≦ (0.33 × V2).

The specifications (characteristics) of the reactor Lc used in the DC / DC power converter operating in this way are the same as in the above embodiments, but the average current value Iave is small, and the inductance value L is on the side where the output voltage level is low. It becomes smaller. In addition, L × Iave 2 that is a guide for the size of the reactor Lc is also significantly reduced. In this way, the size of the reactor, which has conventionally been a large component, can be made smaller, and the DC / DC power converter can be reduced in size and weight.

  Next, in the second case, that is, the voltage V2 input between the voltage terminals VH and Vcom is stepped down to a voltage V1 of 0.33 × V2 to 0.4 × V2 to be reduced between the voltage terminals VL and Vcom. The output operation will be described. An electric load is connected between the voltage terminals VL and Vcom, and energy is transferred through the path from the voltage terminals VH and Vcom to the voltage terminals VL and Vcom and consumed. Further, the capacitance values of the smoothing capacitors CL, CL2, CH, and the capacitor Cs are set to sufficiently large values as compared with the capacitance values of the capacitors Cr12 and Cr13 of the LC series bodies LC12 and LC13. The resonance period of the LC series body LC12 determined by Lr12 and Cr12 and the resonance period of the LC series body LC13 determined by Lr13 and Cr13 are almost the same.

FIG. 21 shows the gate signals GS2d, GS2u, GS3d, GS3u of each MOSFET in the constant multiplier circuit 5d, the gate signals GSpd, GSpu of each MOSFET in the PWM circuit 6, and the current ILr1 flowing through the LC series bodies LC12, LC13. , ILr2, the voltage of the high-voltage side terminal Vm of the second circuit 4d (shown as Vm), and the current ILc of the reactor Lc are shown. Each MOSFET is turned on when the gate signal is at a high voltage. As shown in FIG. 21, the gate signals GS2d, GS2u, GS3d, and GS3u for the multiplier circuit 5d are resonances determined by the capacitance values of the capacitors Cr12 and Cr13 of the LC series bodies LC12 and LC13 and the inductance values of the inductors Lr12 and Lr13. It is an on / off signal of one pulse per cycle with a duty ratio of about 50% and a cycle that is slightly larger than the cycle T. The gate signals GSpd and GSpu for the PWM circuit 6 are the same period synchronized with the gate signals GS2d, GS2u, GS3d and GS3u for the constant multiplier circuit 5d, and one pulse ON / OFF signal determined in accordance with the step-down rate. It is.
The capacitor Cs stores a voltage of about 2 × V1, and the smoothing capacitor CL2 stores a voltage of about V1. Further, by repeating the operation described below, the voltage V1 is accumulated in the capacitor Cr12 and the voltage of about 2 × V1 is accumulated in the capacitor Cr13 on average. The initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described later.

  In the period vv1, the gate signal GS2d is a high voltage, the gate signal GS2u is a low voltage, the gate signal GS3d is a low voltage, the gate signal GS3u is a high voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. When S2d, S3u, and Spu are turned on, the energy is in the path of capacitor Cr12 → inductor Lr12 → S2d → smoothing capacitor CL → D1dA and capacitor Cs → S3u → inductor Lr13 → capacitor Cr13 → D1uB → Spu. Transition to smoothing capacitor CL and capacitor Cr13. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13. On the other hand, when Spd is turned off and Spu is turned on, the capacitor Cs is connected in series with the smoothing capacitor CL, and the voltage (Vm) of the high-voltage side terminal Vm becomes 3 × V1. As a result, the energy accumulated in the reactor Lc is released, and shifts to the smoothing capacitor CL and the capacitor Cs through the path of the reactor Lc → the capacitor Cs → Spu → smoothing capacitor CL → smoothing capacitor CH. The current ILc flowing through the reactor Lc flows while decreasing in absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc (in the figure, the current is expressed as a negative current).

  In the period vv2, the gate signal GS2d is a low voltage, the gate signal GS2u is a high voltage, the gate signal GS3d is a high voltage, the gate signal GS3u is a low voltage, the gate signal GSpu is a high voltage, and the gate signal GSpd is a low voltage. The energy transfer operation to the smoothing capacitor CL and the capacitor Cs by releasing the energy of the reactor Lc is continued from the period vv1, while the Spu is kept on. On the other hand, when S2u and S3d are turned on, the energy is supplied from the smoothing capacitor CL2 → S2u → inductor Lr12 → capacitor Cr12 → D1uA and the capacitor Cr13 → inductor Lr13 → S3d → smoothing capacitor CL2 → smoothing capacitor CL → D1dB. Then, the process proceeds to the capacitor Cr12 and the smoothing capacitors CL and CL2.

  In the period vv3, the gate signal GS2d is a low voltage, the gate signal GS2u is a high voltage, the gate signal GS3d is a high voltage, the gate signal GS3u is a low voltage, the gate signal GSpu is a low voltage, and the gate signal GSpd is a high voltage. S2u and S3d remain on, and the energy transfer to the capacitor Cr12 and the smoothing capacitors CL and CL2 continues from the period vv2. This operation continues for T / 2 time which is 1/2 of the resonance period T of the LC series bodies LC12 and LC13. On the other hand, when Spu is turned off and Spd is turned on, the voltage (Vm) of the high-voltage side terminal Vm becomes 2 × V1, and the energy passes through the reactor Lc to the smoothing capacitor CH → reactor Lc → capacitor Cs → Spd. In the path, energy is accumulated in the reactor Lc at the same time as the transition to the capacitor Cs. The current ILc flowing through the reactor Lc flows while increasing the absolute value with a slope determined by the inductance value of the reactor Lc and the voltage across the reactor Lc.

By repeating this series of operations, the voltage is stepped down and output.
The constant multiplication circuit 5d has two first serial bodies of the first circuit 3d using the two second serial bodies (S2d, S2u) and (S3d, S3u) of the second circuit 4d as drive circuits. (D1dA, D1uA) and (D1dB, D1uB) are operated as a rectifier circuit, and energy transfer from the capacitor Cs to the capacitors Cr12, Cr13 and the smoothing capacitor CL2 and further to the smoothing capacitor CL is repeatedly performed. The PWM circuit 6 is connected to the reactor Lc with the voltage (Vm) of the high-voltage side terminal Vm, which is the high-voltage side terminal of the constant multiplier circuit 5d, being 2 × V1 in the period vv3 and 3 × V1 in the other periods. By doing so, energy is transferred from the smoothing capacitor CH to the capacitor Cs and the smoothing capacitor CL via the reactor Lc.

By adjusting the length of the period vv3, the height of the output voltage V1, that is, the step-down rate can be controlled. The output voltage V1 is high when the period vv3 is long, and low when the period vv3 is short. It is necessary to provide a period of 1/2 of the resonance period T as an energy storage period in the capacitor Cr13, during which S2d, S3u, and Spu are in an on state. Therefore, if the period of the gate signals GS2d, GS2u, GS3d, GS3u, GSpd, and GSpu, that is, the driving period of each MOSFET and the resonance period T are substantially the same, the length of the period vv3 that is the Spd on period is T / 2. It is as follows. That is, the adjustable output voltage V1 is (0.33 × V2) ≦ V1 ≦ (0.4 × V2).
The control circuit 2d determines the length of the period vv3 in advance according to a desired step-down rate, and generates one-pulse gate signals GSpd and GSpu in one cycle. Further, in the control circuit 2d, the voltages of the voltage terminals VL and Vcom are input, and when the gate signals GSpd and GSpu are generated according to the voltage between the voltage terminals VL and Vcom, the length of the period vv3 which is the pulse width thereof is generated. Adjust the height. That is, the desired output voltage V1 can be reliably obtained by adjusting the length of the period vv3 so as to suppress the fluctuation of the output voltage V1, which is the voltage between the voltage terminals VL and Vcom.

  Next, an initial charging operation for the capacitor Cs and the smoothing capacitor CL2 will be described. The capacitor Cs needs to store the voltage 2 × V1, and the smoothing capacitor CL2 needs to store the voltage V1. In the initial charging operation, S2d, S2u and S3d, S3u in the constant multiplying circuit 5d, and Spd, Spu in the PWM circuit 6 are turned on / off at a cycle T with the same duty ratio as that in the step-down operation shown in FIG. By this operation, the voltage 2 × V1 can be charged to the capacitor Cs, and at the same time, the voltage V1 can be charged to the smoothing capacitor CL2. At this time, the voltage V1 is (0.33 × V2) ≦ V1 ≦ (0.4 × V2).

The specifications (characteristics) of the reactor Lc used for the DC / DC power converter operating in this way can greatly reduce L × Iave 2 which is a measure of the size of the reactor Lc, as in the first case, and the reactor. Therefore, the size and weight of the DC / DC power converter can be reduced.

  Further, in both the first case and the second case described above, as in the first embodiment, the voltage level connected to the reactor Lc is applied to Spd and Spu in the PWM circuit 6 for controlling the period. Voltage and the current flowing through Spd and Spu can be reduced in stages compared to the conventional one, and loss can be reduced. As the MOSFETs (Spd, Spu) in the PWM circuit 6, similarly to the MOSFETs in the constant multiplier circuit 5 d, elements with small ratings can be used, and each MOSFET can be driven at a high frequency with each stage. As a result, the inductance value L of the reactor Lc can be reduced, and the reactor Lc can be made smaller and lighter.

  Further, in the fixed-magnification circuit 5d, LC resonance is used for energy transfer, and the driving period of each MOSFET is made the same as or slightly larger than the resonance period T. For this reason, at the time of MOSFET switching, the current value flowing through the MOSFET is zero, and high-efficiency energy transfer with low loss becomes possible. Further, since energy is efficiently transferred using the resonance current, small elements with small ratings can be used for the capacitors Cr12 and Cr13 and the inductors Lr12 and Lr13.

In this embodiment, similarly to the first embodiment, the inductor Lr12 may be connected to the charge / discharge path of the capacitor Cr12, and the inductor Lr13 may be connected to the charge / discharge path of the capacitor Cr13. can get.
In addition, the inductors Lr12 and Lr13 may be omitted. In this case, in the constant multiplication circuit 5d, high-efficiency energy transfer using the resonance current is not achieved, but MOSFETs (Spd, Spu) in the PWM circuit 6 are not used. An element having a small rating can be used, and high-frequency driving is possible, and the effect of reducing the size and weight of the reactor Lc can be obtained in the same manner.

  Further, the voltage V2 inputted between the voltage terminals VH and Vcom is stepped down to 0.29 × V2 to 0.33 × V2 in the first case, and 0.33 × V2 to 0 in the second case. Although the voltage is stepped down to 4 × V2, the control circuit 2d selects and uses the control shown in the first or second case according to the step-down rate, so that 0.29 × V2 to 0.4 × The voltage can be stepped down to V2 and output between the voltage terminals VL and Vcom.

Embodiment 8 FIG.
Hereinafter, a DC / DC power converter according to an eighth embodiment of the present invention will be described.
In the sixth and seventh embodiments, the two series bodies that operate as rectifier circuits are configured by connecting a low-voltage side element and a high-voltage side element that are formed of diode elements in series. As in the fifth embodiment, a low-voltage side element and a high-voltage side element made of a MOSFET as a semiconductor switching element are connected in series. That is, in the DC / DC power conversion main circuit 1c shown in FIG. 12 of the sixth embodiment, the second circuit 4d shown in FIG. 19 of the seventh embodiment is used instead of the second circuit 4c. . Each voltage of the voltage terminals VL, VH, and Vcom is input to the control circuit 2c. The gate terminals of S1dA, S1uA, S1dB, S1uB, S1d, S1u, S2d, S2u, Spd, and Spu are connected to each MOSFET. Gate signals GS1dA, GS1uA, GS1dB, GS1uB, GS1d, GS1u, GS2d, GS2u, GSpd, and GSpu based on the voltage of the source terminal are input from the control circuit 2b.

In this embodiment, during the step-up operation, the control and operation described in the sixth embodiment are performed, and during the step-down operation, the control and operation described in the seventh embodiment are performed. As described above, the step-up / step-down operation is realized by switching between the step-up operation and the step-down operation.
Since the second circuit 4d in the step-up operation and the first circuit 3c in the step-down operation are used as rectifier circuits, each MOSFET is turned off and rectified by a parasitic diode between the source and drain. The operation is the same as in the sixth embodiment and the seventh embodiment. In the operation as the rectifier circuit, each MOSFET may be turned on in accordance with the conduction timing of the parasitic diode, and the loss becomes smaller.

  As described above, this embodiment has both DC / DC power conversion functions of the step-up function and the step-down function, and, similarly to the above-described embodiments, the MOSFET (Spd, Spu) enables high-frequency driving of each MOSFET using a small-rated element, and the size of the reactor Lc is made smaller in each stage to promote the downsizing and weight reduction of the DC / DC power converter and high efficiency. Energy transfer.

  In Embodiments 6 to 8 described above, each of the multiple multiplier circuits 5c and 5d includes the first series body, the second series body, and the LC series body, but has the same number of three or more. May be. When there are three or more N first series bodies, second series bodies, and LC series bodies, in the first circuit, N first series bodies are parallel between the voltage terminals VL and Vcom. In the second circuit, N second series bodies are connected in series to the high voltage side of the first circuit, and N−1 second series bodies on the low voltage side of the N second series bodies are connected. A smoothing capacitor is connected in parallel to each of the two serial bodies. Each LC series body is connected between an intermediate point of each first series body and an intermediate point of each second series body. As a result, the DC / DC power converter capable of handling a wide range of step-up rate and step-down rate can achieve the same effects as those of the sixth to eighth embodiments.

  In each of the above embodiments, a power MOSFET in which a parasitic diode is formed between the source and drain is used for each semiconductor switching element. However, other semiconductor switching elements in which diodes are connected in reverse parallel may be used. IGBTs connected in reverse parallel can be used effectively, and similar effects can be obtained.

1, 1a-1d DC / DC power conversion main circuit, 2, 2a-2d control circuit,
3, 3a-3d first circuit, 4, 4a-4d second circuit,
5, 5a to 5d fixed magnification circuit, 6 PWM circuit, CH high-voltage side smoothing capacitor,
CL low voltage side smoothing capacitor, CL2 smoothing capacitor, Cr12, Cr13 capacitor,
Cs PWM capacitor,
D1d, D1u, D1dA, D1uA, D1dB, D1uB, D2d, D2u, D3d, D3u Diode element,
(D1d, D1u), (D1dA, D1uA), (D1dB, D1uB) first series body,
(D2d, D2u), (D3d, D3u) Second series body,
GS1d, GS1u, GS1dA, GS1uA, GS1dB, GS1uB, GS2d, GS2u, GS3d, GS3u Gate signal (for constant multiplier),
GSpd, Gspu Gate signal (for PWM circuit), Lc reactor, Lr12, Lr13 inductor,
S1d, S1u, S1dA, S1uA, S1dB, S1uB, S2d, S2u, S3d, S3u, Spd, Spu MOSFETs as semiconductor switch elements,
(S1d, S1u), (S1dA, S1uA), (S1dB, S1uB) first series body,
(S2d, S2u), (S3d, S3u) Second series body, (VL, Vcom) Low voltage side I / O terminals,
(VH, Vcom) High-voltage side I / O terminals, Vcom common terminal (negative terminal),
Vm High voltage side terminal of the second circuit.

Claims (11)

  1. A low-voltage smoothing capacitor connected between the low-voltage input and output terminals;
    A high-voltage side smoothing capacitor connected between the high-voltage side input / output terminals and the low-voltage side input / output terminals and the negative-electrode side terminal in common;
    A first circuit formed by connecting a first series body of a low-voltage side element composed of a semiconductor switch element and a high-voltage side element between the low-voltage side input / output terminals, a low-voltage side element composed of a diode element, and a high-voltage side element; A second circuit formed by connecting the second series body in series with the high-voltage side of the first circuit, and between the intermediate point of the first series body and the intermediate point of the second series body. A constant multiplication circuit having a connected capacitor;
    A PWM circuit comprising a series body of a low-voltage side semiconductor switch element and a high-voltage side semiconductor switch element and connected between the low-voltage side input / output terminals;
    A PWM capacitor connected between an intermediate point of the PWM circuit and a high-voltage side terminal of the second circuit;
    A reactor connected between the high-voltage side terminal of the second circuit and the positive-side terminal of the high-voltage side input / output terminals;
    A DC / DC power converter characterized by performing a boosting operation by transferring energy from between the low-voltage input / output terminals to the high-voltage input / output terminals.
  2. A low-voltage smoothing capacitor connected between the low-voltage input and output terminals;
    A high-voltage side smoothing capacitor connected between the high-voltage side input / output terminals and the low-voltage side input / output terminals and the negative-electrode side terminal in common;
    A first circuit formed by connecting a first series body of a low-voltage side element composed of a diode element and a high-voltage side element between the low-voltage side input / output terminals; a low-voltage side element composed of a semiconductor switch element; A second circuit formed by connecting the second series body in series with the high-voltage side of the first circuit, and between the intermediate point of the first series body and the intermediate point of the second series body. A constant multiplication circuit having a connected capacitor;
    A PWM circuit comprising a series body of a low-voltage side semiconductor switch element and a high-voltage side semiconductor switch element and connected between the low-voltage side input / output terminals;
    A PWM capacitor connected between an intermediate point of the PWM circuit and a high-voltage side terminal of the second circuit;
    A reactor connected between the high-voltage side terminal of the second circuit and the positive-side terminal of the high-voltage side input / output terminals;
    A DC / DC power converter characterized by performing a step-down operation by transferring energy from between the high-voltage input / output terminals to the low-voltage input / output terminals.
  3. A low-voltage smoothing capacitor connected between the low-voltage input and output terminals;
    A high-voltage side smoothing capacitor connected between the high-voltage side input / output terminals and the low-voltage side input / output terminals and the negative-electrode side terminal in common;
    A first circuit formed by connecting a first series body of a low-voltage side element composed of a semiconductor switch element and a high-voltage side element between the low-voltage side input / output terminals, a low-voltage side element and a high-voltage side element composed of a semiconductor switch element And a second circuit formed by connecting the second series body in series to the high-voltage side of the first circuit, and between the midpoint of the first series body and the midpoint of the second series body A constant-magnification circuit having a capacitor connected to
    A PWM circuit comprising a series body of a low-voltage side semiconductor switch element and a high-voltage side semiconductor switch element and connected between the low-voltage side input / output terminals;
    A PWM capacitor connected between an intermediate point of the PWM circuit and a high-voltage side terminal of the second circuit;
    A reactor connected between the high-voltage side terminal of the second circuit and the positive-side terminal of the high-voltage side input / output terminals;
    A DC / DC power converter characterized in that energy is transferred between the low-voltage side input / output terminals and the high-voltage side input / output terminals to perform one or both of step-up and step-down operations.
  4. The fixed-multiplier circuit has the same number N of two or more of the first series body, the second series body, and the capacitor,
    In the first circuit, the N first series bodies are connected in parallel between the low-voltage side input / output terminals,
    In the second circuit, the N second series bodies are connected in series to the high-voltage side of the first circuit, and among the N second series bodies, N-1 pieces on the low-pressure side are connected. A smoothing capacitor is connected in parallel to each of the second series bodies,
    Each said capacitor | condenser is each connected between the intermediate point of each said 1st serial body, and the intermediate point of each said 2nd serial body, The any one of Claims 1-3 characterized by the above-mentioned. The DC / DC power conversion device described.
  5. And a control circuit for controlling the semiconductor switching elements in the PWM circuit and the constant multiplier circuit, wherein the control circuit operates the constant multiplier circuit and the PWM circuit at the same period of synchronization. The DC / DC power converter device according to any one of claims 1 to 4.
  6. The control circuit operates the semiconductor switch elements in the constant-magnification circuit with a gate signal of one pulse per cycle with a duty ratio of about 50%, and boosts / steps down the semiconductor switch elements in the PWM circuit. 6. The DC / DC power conversion apparatus according to claim 5, wherein the DC / DC power conversion apparatus is operated with one pulse of a gate signal in one cycle determined according to the magnification.
  7. The control circuit adjusts the pulse width of the gate signal to the semiconductor switch elements in the PWM circuit based on the voltage between the low-voltage input / output terminals or the voltage between the high-voltage input / output terminals. The DC / DC power converter according to claim 6, wherein
  8. The DC / DC power according to any one of claims 5 to 7, wherein an inductor is provided in a charge / discharge path of the capacitor in the fixed-multiplier circuit, and a charge / discharge current of the capacitor is LC-resonated. Conversion device.
  9. 9. The DC / DC according to claim 8, wherein the period in which the constant frequency circuit and the PWM circuit operate is the same as or slightly larger than a resonance period determined from a capacitance value of the capacitor and an inductance value of the inductor. Power conversion device.
  10. 10. The DC / DC power converter according to claim 1, wherein each of the semiconductor switching elements is a MOSFET having a parasitic diode between a source and a drain.
  11. 10. The DC / DC power converter according to claim 1, wherein each of the semiconductor switching elements is an IGBT in which diodes are connected in antiparallel.
JP2009094524A 2009-04-09 2009-04-09 DC / DC power converter Expired - Fee Related JP5222775B2 (en)

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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6192162A (en) * 1984-10-08 1986-05-10 Juichi Irie Dc/dc converter
JP2002291232A (en) * 2001-03-28 2002-10-04 Seiko Epson Corp Power supply circuit, display and electronic equipment
JP2004343894A (en) * 2003-05-15 2004-12-02 Seiko Epson Corp Control method of step-up circuit
JP2005012904A (en) * 2003-06-18 2005-01-13 Seiko Epson Corp Power supply and electronic apparatus using the same
JP2006262619A (en) * 2005-03-17 2006-09-28 Mitsubishi Electric Corp Switched-capacitor type dc/dc converter device
JP2008283847A (en) * 2007-04-12 2008-11-20 Mitsubishi Electric Corp Dc/dc power converter

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6192162A (en) * 1984-10-08 1986-05-10 Juichi Irie Dc/dc converter
JP2002291232A (en) * 2001-03-28 2002-10-04 Seiko Epson Corp Power supply circuit, display and electronic equipment
JP2004343894A (en) * 2003-05-15 2004-12-02 Seiko Epson Corp Control method of step-up circuit
JP2005012904A (en) * 2003-06-18 2005-01-13 Seiko Epson Corp Power supply and electronic apparatus using the same
JP2006262619A (en) * 2005-03-17 2006-09-28 Mitsubishi Electric Corp Switched-capacitor type dc/dc converter device
JP2008283847A (en) * 2007-04-12 2008-11-20 Mitsubishi Electric Corp Dc/dc power converter

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