JP2010245263A5 - - Google Patents
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- Publication number
- JP2010245263A5 JP2010245263A5 JP2009092014A JP2009092014A JP2010245263A5 JP 2010245263 A5 JP2010245263 A5 JP 2010245263A5 JP 2009092014 A JP2009092014 A JP 2009092014A JP 2009092014 A JP2009092014 A JP 2009092014A JP 2010245263 A5 JP2010245263 A5 JP 2010245263A5
- Authority
- JP
- Japan
- Prior art keywords
- layer
- semiconductor substrate
- barrier metal
- metal pattern
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
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Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009092014A JP5419525B2 (ja) | 2009-04-06 | 2009-04-06 | 半導体装置及びその製造方法 |
US12/752,736 US8598684B2 (en) | 2009-04-06 | 2010-04-01 | Semiconductor device, and method of manufacturing the same |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2009092014A JP5419525B2 (ja) | 2009-04-06 | 2009-04-06 | 半導体装置及びその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2010245263A JP2010245263A (ja) | 2010-10-28 |
JP2010245263A5 true JP2010245263A5 (zh) | 2012-04-05 |
JP5419525B2 JP5419525B2 (ja) | 2014-02-19 |
Family
ID=43097963
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2009092014A Active JP5419525B2 (ja) | 2009-04-06 | 2009-04-06 | 半導体装置及びその製造方法 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JP5419525B2 (zh) |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5601380B2 (ja) * | 2010-12-28 | 2014-10-08 | 富士通セミコンダクター株式会社 | 半導体装置の製造方法 |
KR101278442B1 (ko) | 2012-01-19 | 2013-07-01 | 한국과학기술원 | 관통 실리콘 비아를 이용한 수동 이퀄라이저를 구비하는 인터포저, 그 제조 방법, 인터포저를 포함하는 적층 칩 패키지, 및 그 제조 방법 |
JP2015153978A (ja) * | 2014-02-18 | 2015-08-24 | キヤノン株式会社 | 貫通配線の作製方法 |
KR101855607B1 (ko) * | 2014-03-12 | 2018-05-04 | 가부시키가이샤 트루칩 재팬 | 적층 반도체 집적 회로 장치 |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4131648B2 (ja) * | 2002-07-10 | 2008-08-13 | 株式会社東芝 | 半導体装置および半導体装置の製造方法 |
JP4327644B2 (ja) * | 2004-03-31 | 2009-09-09 | Necエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP2006278646A (ja) * | 2005-03-29 | 2006-10-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP5394617B2 (ja) * | 2006-06-16 | 2014-01-22 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法及び基板 |
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2009
- 2009-04-06 JP JP2009092014A patent/JP5419525B2/ja active Active
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