JP2010226919A - Power conversion apparatus, refrigeration air-conditioning system and solarlight power-generation system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an inexpensive power conversion apparatus having high efficiency, to provide a refrigeration air-conditioning system using the same, and to provide a solarlight power-generation system. <P>SOLUTION: An inverter circuit 2 (the power conversion apparatus) driving a motor 1 includes a MOS FET 5 having an SJ structure, and a reverse-current preventive diode 7 connected in series in the opposite direction to the MOS FET 5 and used to suppress a reverse current to the MOS FET 5. The inverter circuit 2 further includes at least one or more one-side arms composed of reflux diodes 8 connected in parallel with the series circuit of the MOS FET 5 and the reverse-current preventive diode 7. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

  The present invention relates to a power converter, a refrigeration air conditioning system and a solar power generation system using the power converter.

  As variable voltage / variable frequency inverters are put into practical use, various application fields of power converters have been developed. For example, a three-phase voltage source inverter or the like is used for a drive circuit used in an electric motor drive device or the like. The three-phase voltage source inverter includes a three-phase bridge circuit using a power semiconductor switching element such as a thyristor, transistor, IGBT, or MOS FET. In this circuit, the switching element for each phase can be realized by directly connecting the positive terminal and the negative terminal to the positive terminal and the negative terminal of the DC voltage source, respectively. In recent years, as the efficiency of devices has been improved, such standard circuits have been improved to further improve the efficiency.

  Conventionally, for example, an example in which a freewheeling diode is connected in antiparallel to a series connection circuit of a MOS FET with a parasitic diode and a high-speed diode to prevent occurrence of reverse recovery loss in the parasitic diode has been disclosed (for example, Patent Document 1). reference).

  In addition, for example, in a motor drive device using an inverter circuit in which a plurality of upper and lower arms having switch elements connected in series are connected in parallel to a DC power source and AC power is output from a series connection point of the switch elements, A PNP-type junction transistor is used as an element, the emitter of the junction transistor is connected to the positive side of the DC power supply, and the collector of the junction transistor is a Schottky barrier diode (hereinafter referred to as SiC-SBD) made of silicon carbide. An anode is connected, and the SiC-SBD cathode is connected to the emitter of the junction transistor has been proposed (see, for example, Patent Document 2).

  Also, for example, “a series circuit in which first and second main switching elements each having a main circuit switching terminal to be opened and closed, a control signal terminal, and a body diode are connected in series so that the body diodes are in anti-series. An external diode connected in parallel to the series circuit in the same conduction direction as the body diode of the first main switching element, and the first and second main switching elements at substantially the same timing. And a control means for providing a control signal for opening / closing control to the control signal terminal has been proposed (see, for example, Patent Document 3).

  Also, for example, “having a plurality of series circuits including MOS FETs that are upstream and downstream along the voltage application direction, and free-wheeling diodes connected in reverse parallel to each IGBT and MOS FET, A switching circuit in which an interconnection point between the IGBT and the MOS FET in the series circuit is connected to a load including an inductive component, and at least one other series in the series circuit by turning on / off the IGBT of at least one series circuit. And a control means for sequentially switching a plurality of phases of energization for turning on the MOS FET of the circuit ”has been proposed (see, for example, Patent Document 4).

JP-A-60-261372 (2nd page, FIG. 3) JP 2003-219687A (pages 3 to 5, FIGS. 1 to 2, FIGS. 5 to 6) JP 2008-289232 A (page 3 to page 4, FIG. 1) JP 2007-74858 A (page 3 to page 4, FIG. 1)

  In the case of Patent Document 1, a high-speed diode connected in series with a MOS FET causes power loss, which is accompanied by a decrease in inverter efficiency. In addition, the circuit was complicated due to an increase in the number of parts.

  In the case of Patent Document 2, a countermeasure against reverse bias of a PNP junction transistor is assumed. The upper switch element is composed of a PNP junction transistor, a diode connected in series to the PNP junction transistor, and an SiC-SBD connected in reverse parallel to the PNP junction transistor. Therefore, the recovery loss of the lower MOS FET cannot be reduced, and there is a limit to the higher efficiency.

  In the case of Patent Document 3, the current flowing through the body diode of the main MOS FET is cut off by the sub MOS FET. Since the control of the sub-MOS FET is controlled by the same signal as that of the main MOS FET, there is no increase in the number of control units, but the number of sub-MOS FET elements is increased.

  In the case of Patent Document 4, a high-function and expensive control device is required to control the reverse voltage application timing based on dv / dt variations of switching elements. Further, since reverse voltage is applied by the additional circuit, there is a problem that the inverter efficiency is remarkably lowered when the additional circuit fails.

  An object of the present invention is to provide an inexpensive and highly efficient power conversion device, and a refrigeration air conditioning system and a solar power generation system using the power conversion device.

  The power conversion device according to the present invention includes at least one one-side arm, and the one-side arm includes a switching element having a built-in parasitic diode, a backflow prevention diode connected in series with the switching element to prevent backflow to the switching element, and switching A free-wheeling diode connected in reverse parallel to a series circuit of an element and a backflow prevention diode is provided.

  According to the power conversion device of the present invention, the power conversion device includes at least one one-side arm, and the one-side arm includes a switching element having a built-in parasitic diode, and a backflow prevention diode that is connected in series with the switching element and suppresses backflow to the switching element. Since the free-wheeling diode connected in reverse parallel to the series circuit of the switching element and the backflow prevention diode is provided, the recovery loss of the MOS FET can be reduced and the system can be driven with high efficiency. As a result, heat countermeasures such as a heat sink can be reduced, and the system can be downsized.

It is a figure showing the structural example of arbitrary 1 arms of the inverter which concerns on this invention. It is a figure showing an example of the structure schematic of SJ structure MOS FET concerning Embodiment 1. FIG. It is the figure which showed an example of the relationship between the drain-source voltage regarding SJ structure MOS FET, and ON resistance. It is the figure which showed an example of the short circuit current at the time of applying the SJ structure MOS FET concerning Embodiment 1 to an inverter. It is a figure showing an example of the structure of the electric motor drive system centering on the power converter device which concerns on Embodiment 1. FIG. 3 is an example of a flow showing a PWM creation sequence according to the first embodiment. It is a figure showing an example of equivalent short circuit formation by the parasitic diode of MOS FET. FIG. 6 is a diagram (part 1) illustrating an example of a configuration of an electric motor drive system centering on a power converter according to a second embodiment. FIG. 6 is a diagram (part 2) illustrating an example of a configuration of an electric motor drive system centering on a power conversion device according to a second embodiment. It is a figure showing the upper arm logic state of the PWM inverter which concerns on Embodiment 1-2. It is a relationship diagram of the inverter rotation angle and voltage command vector of the PWM inverter which concerns on Embodiment 1-2. It is a figure showing an example (an example of two-phase modulation with an underscore) of the PWM switching pattern of the power converter device which concerns on Embodiment 2. FIG. It is a figure showing an example (an example of two-phase modulation with an overlay) of the PWM switching pattern of the power converter device which concerns on Embodiment 2. FIG. It is a figure showing an example of a structure of the electric motor drive system centering on the power converter device which concerns on Embodiment 3. FIG. It is a figure showing an example of the U-phase voltage command of the power converter device which concerns on Embodiment 3, and a slave side inverter U-phase electric potential (U2 location in FIG. 14). FIG. 10 is a diagram illustrating an example of a power conversion device according to a fourth embodiment. FIG. 10 is a diagram illustrating an example of a grid interconnection inverter device according to a fifth embodiment. It is a figure showing an example of the power converter device using the conventional MOS FET. It is a figure showing an example of equivalent short circuit formation by the parasitic diode of MOS FET.

  Hereinafter, an inverter drive device or a power conversion device (hereinafter collectively referred to as a power conversion device) according to an embodiment of the present invention will be described with reference to the drawings.

Embodiment 1 FIG.
Power devices such as IGBTs and MOS FETs have been used for various applications from consumer equipment to industrial equipment. Currently, device development using SiC (silicon carbide), GaN (gallium nitride) and the like has been performed in various forms. On the other hand, power MOS FETs having an SJ (Super Junction) structure have appeared, and an ultra-low on-resistance device has been realized.
FIG. 2 shows a structural schematic diagram of the SJ structure. The SJ structure has an advantage that the on-resistance and the withstand voltage can be increased by balancing the charge of the p layer 25 and the n layer 26.
FIG. 3 shows an example of the relationship between the drain-source voltage and the on-resistance. As can be seen from this figure, the conventional element has a problem that the on-resistance increases as the drain-source voltage increases, but the on-resistance can be kept low in the SJ structure.
However, the SJ structure MOS FET has a problem that the reverse recovery time is slow due to the parasitic diode built in the element. Therefore, when applying an SJ-structure MOS FET to an inverter, when the switching element of any one arm is turned off and the switching element of the opposite arm is turned on, an equivalent short circuit is established in the loop path with the main circuit side. Since the current flows (until the charge of the parasitic diode is completely discharged), there is a problem that the loss is deteriorated by this amount (see FIG. 4).

In view of this, the inventors have devised a method for preventing the occurrence of the short-circuit current by forming a single-side arm using a MOS FET, a backflow prevention diode for preventing backflow to the MOS FET, and a freewheeling diode.
FIG. 1 is a diagram showing a configuration example of an arbitrary one-side arm when an SJ structure MOS FET having a parasitic diode or the like is applied to an inverter.
First, the operation of the devised one-side arm will be described.
FIG. 1 includes a switching element 5a such as a MOS FET, a backflow prevention diode 7a, and a freewheeling diode 8a.
The backflow prevention diode 7a is assumed to be a high-speed type such as a Schottky barrier diode (SBD). Due to the characteristics of the circuit configuration described above, a high withstand voltage is not essential for the backflow prevention diode, and a low withstand voltage may be used.
If an inverter is configured by using at least one such one-side arm, when the switching element 5a in the one-side arm is switched from on to off, the directions of the parasitic diode 6a and the backflow prevention diode 7a of the switching element 5a are reversed. In addition, the short-circuit current path is blocked by the two effects that the speed of the backflow prevention diode 7a is sufficiently high compared to the parasitic diode 6a of the switching element 5a, so that the short-circuit current is sufficiently suppressed.
Further, since the inverter can be regarded as a kind of step-down chopper, a return path is necessary, and therefore a return diode 8a is prepared for this.
By adopting the configuration as described above, the efficiency of the system can be improved relatively easily with respect to the inverter circuit without impairing the merit of the switching element such as the SJ-structure MOS FET having the parasitic diode.
The above shows the case of the MOS FET having the SJ structure, but the present technique is effective for all the switching elements having the parasitic inductance.
In addition, it is possible to remove noise factors such as an increase in lead inductance by mounting the one-side arm having such a configuration in one module.

Next, an embodiment in which the devised one-side arm is applied to a power converter will be described.
FIG. 5 is a diagram illustrating an example of a configuration of an electric motor drive system centering on the power conversion device according to the first embodiment of the present invention. The system shown in FIG. 5 includes a DC voltage source 12, an inverter circuit 2, an electric motor 1, a current detection means 3 (3 a, 3 b) that detects the motor winding current flowing through the electric motor 1, a voltage detection means 10, and an inverter circuit PWM ( For example, a CPU (Central Processing Unit) 11 or the like for controlling the pulse width modulation (pulse width modulation) and driving the electric motor 1 is configured. The inverter circuit 2 is composed of one side arms 4a to 4f.

  The inverter circuit 2 of the present embodiment includes switching elements 5a to 5f, backflow prevention diodes 7a to 7f, and freewheeling diodes 8a to 8f. The switching elements 5a to 5f are assumed to use MOS FETs. The backflow prevention diodes 7a to 7f are connected in the opposite direction to the parasitic diodes 6a to 6f of the switching elements 5a to 5f in order to suppress backflow to the switching elements 5a to 5f.

  In the current detection method of the present embodiment, the both-end voltage obtained from the current detection means 3a, 3b is taken into the CPU 11, and converted into numerical data representing the voltage value by an A / D converter or the like built in the CPU 11. It is performed by converting into motor current data (information) (however, it is not limited to this method).

  Further, the voltage detection means 10 of the present embodiment is constituted by a voltage dividing circuit composed of a resistor / capacitor, an A / D converter, an amplifier, and the like. The bus voltage is converted into numerical data by the A / D converter or the like built in the CPU 11 as in the case of the current detection, and converted into DC bus voltage data (information) (same as above, in this case) Is not limited to this method).

  First, an electric motor drive operation method using PWM (Pulse Width Modulation) will be described. In the first embodiment, a case will be described in which the magnetic pole position sensor is not added, and the CPU 11 performs control for driving the electric motor 1 based on data (information) of the current flowing through the winding.

  In the system shown in FIG. 5, motor current data can be obtained by the current detection means 3a, 3b. Also, bus voltage data can be obtained via the voltage detection means 10. A calculation is performed based on these data to generate a PWM duty signal (hereinafter referred to as a PWM signal), the switching elements 5a to 5f in the one-side arm are operated to apply a voltage to the motor 1, and the driving operation of the motor 1 is performed. Take control.

FIG. 6 is a flowchart showing the operation of the CPU 11 when the PWM signal is generated, etc., and at the same time, a block diagram in which the function of the CPU is constituted by each functional means. As shown in FIG. 6, the function of the CPU 11 includes phase current calculation means 61 for calculating inverter output currents Iu to Iw for each phase from two phase currents Iu and Iw obtained by the current detection means 3a and 3b, and inverter output. The next voltage command vectors Vγ * and Vδ * are calculated from the excitation current Iγ and torque current Iδ for calculating the excitation current and torque current from the currents Iu to Iw, and from the excitation current Iγ, torque current Iδ and frequency command f *. Voltage command vector calculating means 63 for calculating the voltage, and voltage command vectors Vγ * and Vδ * from the voltage command vector calculating means 63 and voltage commands Vu * to Vw * for each phase from the bus voltage Vdc. Based on the calculation means 64 and the voltage commands Vu * to Vw * of each phase output from each phase voltage command calculation means 64, the PWM original signals Tup to Twn are created. The WM signal generating means 65 and the PWM generating means 66 for generating the PWM signals Up to Wn based on the PWM original signals Tup to Twn from the PWM signal generating means 65 are constituted.
Next, a process in which the CPU 11 generates a PWM switching signal to be output to the inverter circuit 2 based on the motor currents Iu, Iv, and Iw will be described using each functional unit of the CPU.

  In step S201, the phase current calculation unit 61 obtains the characteristics of the three-phase balanced inverter such as “the sum of the three-phase currents is 0” from the two-phase currents obtained based on the detection by the current detection units 3a and 3b. Using this, the amount of current flowing through each phase of UVW is calculated.

  Next, in step S202, the means 62 for obtaining the excitation current and the torque current performs coordinate conversion of each phase current value to calculate the excitation current component (γ-axis current) Iγ and the torque current component (δ-axis current) Iδ. Specifically, the excitation current Iγ and the torque current Iδ are calculated by multiplying the conversion matrix [C1] as shown in the following formula (1) and the motor currents Iu, Iv, and Iw. However, (theta) in (1) shows an inverter rotation angle, and the case where a rotation direction is clockwise.

When a sensor for detecting the rotor position such as a pulse encoder is used, the electrical angular frequency of the rotor and the rotational frequency of the inverter circuit substantially coincide with each other. Therefore, the inverter circuit has the same frequency as the electrical angular frequency of the rotor. A rotating coordinate system is generally referred to as a dq coordinate system.
On the other hand, when a sensor for detecting the rotor position such as a pulse encoder is not used, the CPU 11 cannot accurately capture the dq axis coordinates, and actually the inverter circuit rotates with a phase difference Δθ from the dq coordinate system. is doing. Assuming such a case, a coordinate system that rotates at the same frequency as the output voltage of the inverter circuit is generally referred to as a γδ coordinate system, and is handled separately from the rotating coordinate system. Since the first embodiment shows an example in which no sensor is used, γ and δ are used as subscripts following this convention.

  Next, in step S203, the γ-axis voltage / δ-axis voltage command calculation means 63 performs various vector controls including speed control from the excitation current Iγ, torque current Iδ, and frequency command f *. For example, the following equation (2) is used. Next, the next γ-axis voltage command Vγ * and δ-axis voltage command Vδ * are obtained.

  Next, in step S204, each phase voltage command calculation means 64 uses the following equation (3) which is the inverse matrix [C1] -1 of equation (1) to obtain each phase voltage command Vu *, Vv *, Vw *. Ask.

Next, in step S205, the PWM signal creating means 65 determines the ratio of each phase voltage command Vu *, Vv *, Vw * of the inverter circuit 2 to the bus voltage Vdc obtained from the voltage detecting means 10 (each phase voltage relative to Vdc). Based on the command ratio), the PWM original signals Tup to Twn indicating the ON time (or OFF time) of each one-side arm switching element are calculated.
In the above description, an example of calculating the ON time (or OFF time) of each single-side arm switching element has been shown in the calculation of the PWM original signals Tup to Twn. However, the conventional method such as space vector modulation may be used. good.

  The PWM original signal obtained by converting the switching time in one carrier cycle calculated in this way is transmitted as PWM signals Up to Wn by the PWM signal generating means 66, and based on this, the switching elements in the respective one side arms 4a to 4f are transmitted. 5a-5f operate | moves, the pulse voltage corresponding to operation | movement is applied, and the electric motor 1 is drive-operated. As an example, FIG. 7 shows the logic of the PWM signal of the switching element.

  On the other hand, the circuit configuration of the conventional MOS FET inverter is generally a circuit having one switching element 101a to 101f in each arm as shown in FIG. When the motor driving operation using PWM is performed with such a circuit configuration, the recovery loss of the parasitic diodes 102a to 102f associated with the switching elements 101a to 101f cannot be ignored.

  For example, paying attention to the U phase, consider a case where the U-phase upper switching element 101a is turned on when a load current flows through the parasitic diode 102d of the U-phase lower switching element 101d. In this case, since the parasitic diode can be regarded as a kind of capacitor, the main circuit voltage is changed until the amount of charge stored in the parasitic diode 102d is completely discharged, that is, until the parasitic diode 102d of the U-phase lower switching element 101d is turned off. A short circuit is formed (during this period, the diode portion can be equivalently regarded as a short circuit). FIG. 19 shows how the equivalent short circuit is formed at this time. As shown in this example, in this configuration, an equivalent short circuit is formed due to the presence of the parasitic diode at the time of switching, so that the recovery loss is large.

  On the other hand, according to the configuration of FIG. 5, when a load current flows through the free wheeling diode 8d in the U-phase lower arm 4d, no load current flows through the MOS FET parasitic diode of the switching element 5d. This is due to the effect that the conduction path is blocked (blocked) by the backflow prevention diode 7d. That is, reverse conduction through the parasitic diode cannot be performed when the MOS FET is turned off, and commutation is performed on the freewheeling diode 8d side. Therefore, the recovery current by the parasitic diode 6d can be reduced, and high-efficiency driving can be performed.

Further, when a low breakdown voltage type element is used for the backflow prevention diode 7d, an increase in the on-voltage can be suppressed to a low level, and a decrease in efficiency due to an increase in the number of elements can be suppressed to a minimum.
The case of the inverter using the SJ structure MOS FET has been described above. However, the present technique is effective for a three-phase inverter using all switching elements in which parasitic inductance exists.
Further, by mounting any one or all of the arms of this inverter in a single module, it is possible to eliminate noise factors such as an increase in lead inductance, which is advantageous in terms of mounting area.

Embodiment 2. FIG.
FIG. 8 is a diagram illustrating an example of a configuration of an electric motor drive system centering on the power conversion device according to the second embodiment of the present invention. In the motor drive system of FIG. 8, the configurations of the lower arms 4 d to 4 f in the inverter main circuit 2 are different from those in FIG. 5. 4d to 4f are constituted by high-speed switching elements 13a to 13c and free-wheeling diodes 8d to 8f. In addition, 13a to 13c are assumed to be composed of elements such as an inexpensive type IGBT, although the switching speed is relatively slow among a plurality of types of IGBTs. Thereby, an inexpensive inverter circuit can be configured. However, a MOS FET may be used in consideration of various conditions (carrier frequency, switching speed, degree of recovery loss, availability, etc.).

Here, in conjunction with the configuration as shown in FIG. 8, a method for improving the efficiency without increasing the number of elements has been devised by devising the PWM pattern. With the configuration as shown in FIG. 8, the recovery loss in the upper arm can be reduced, and further, the switching loss can be reduced in the lower arm by using the two-phase modulation of the under-straining method with a small number of switching times. Therefore, it is possible to increase the efficiency of the system. FIG. 12 shows an example of the gate signal pattern of each one-side arm at the time of two-phase modulation of the underlaying method.
By using such an apparatus / method, it is possible to further increase the efficiency of the system. Further, by suppressing the increase in the number of elements as much as possible, it is possible to reduce the cost and reduce the global environmental load.

The above has described an example of the underlaying method, but it can also be realized by using the upholstery method. In this case, the configuration is as shown in FIG.
In the motor drive system of FIG. 9, the configurations of the upper arms 4 a to 4 c in the inverter main circuit 2 are different from those in FIG. 5. The inside of 4a-4c is comprised by the switching elements 14a-14c and the free-wheeling diodes 8a-8c. Moreover, it is assumed that 14a-14c is comprised by elements, such as IGBT with slow switching speed, for example. However, a MOS FET may be used in consideration of various conditions (carrier frequency, switching speed, degree of recovery loss, availability, etc.).

In this case, the recovery loss in the lower arm can be reduced, and the switching loss can be reduced in the upper arm by using the two-phase modulation of the upper tension method with a small number of switching operations. It is possible to improve efficiency. FIG. 13 shows an example of the gate signal pattern of each one-side arm at the time of the two-phase modulation of the top-up type.
By using such an apparatus / method, it is possible to further increase the efficiency of the system. Further, by suppressing the increase in the number of elements as much as possible, it is possible to reduce the cost and reduce the global environmental load.
The above shows an example in which an SJ-structure MOS FET is used. However, this method is effective in a three-phase inverter using all switching elements in which parasitic inductance exists.
Also in this embodiment, it is possible to remove noise factors such as an increase in lead inductance by mounting any at least one arm or all arms of this inverter as one module, and in terms of mounting area, Become superior.

Embodiment 3 FIG.
FIG. 14 is a diagram illustrating an example of a configuration of an electric motor drive system centering on a power conversion device according to a third embodiment of the present invention. The system shown in FIG. 14 includes a DC voltage source 12, inverter circuits 2a (master side) and 2b (slave side), electric motor 1, current detection means 3 (3a, 3b) for detecting electric motor winding current flowing through the electric motor 1, The voltage detection means 10 is constituted by, for example, a CPU (Central Processing Unit) 11 for driving the electric motor 1 by PWM control of the inverter circuit. The master side inverter circuit 2a is constituted by each one side arm 4a to 4f. The slave-side inverter circuit 2b is composed of one-side arms 15a to 15f.

The master-side inverter circuit 2a of the present embodiment is a circuit having each one-side arm 4a to 4f. Each one-side arm includes switching elements 5a to 5f, backflow prevention diodes 7a to 7f, and freewheeling diodes 8a to 8f. The switching elements 5a to 5f are assumed to use MOS FETs. The backflow prevention diodes 7a to 7f are connected in the opposite direction to the parasitic diodes 6a to 6f of the switching elements 5a to 5f in order to suppress backflow to the switching elements 5a to 5f.
The slave-side inverter circuit 2b of the present embodiment is a circuit having each one-side arm 15a to 15f. Each one-side arm includes switching elements 13a to 13f and free-wheeling diodes 8a to 8f. Each of the one-side arms 15a to 15f is assumed to be composed of an element such as an inexpensive type IGBT, although the switching speed is relatively slow among a plurality of types of IGBTs. Thereby, an inexpensive inverter circuit can be configured. However, a MOS FET may be used in consideration of various conditions (carrier frequency, switching speed, degree of recovery loss, availability, etc.).

In the present embodiment, the PWM of the master-side inverter circuit outputs a PWM signal by the method shown in the first embodiment. The slave-side inverter outputs a PWM signal using two-phase modulation attached to the P-side potential or N-side potential according to the polarity of each phase output voltage command of the master-side inverter. As an example, FIG. 15 shows the U-phase output command voltage command and the command voltage of the slave inverter. For example, for the U phase, when the command voltage of the master-side inverter is positive, the upper arm is always turned off (attached to the N side). Further, when the command voltage of the master side inverter is negative, the upper arm is always turned on (applied to the P side). When the command voltage of the master-side inverter is 0, it may not be output, or may be attached to either the P side or the N side. As described above, by outputting the PWM signal by the two-phase modulation stuck to the P-side potential or the N-side potential according to the polarity of each phase output voltage command of the master-side inverter, the switching frequency of the slave-side inverter can be reduced. This reduces the number of parts and cost of this system.
Here, although the case where the SJ-structure MOS FET is used is shown, the present technique is effective in the cooperative operation of a plurality of inverters using all switching elements in which parasitic inductance exists.
Also, in this embodiment, noise factors such as an increase in lead inductance can be obtained by integrating and mounting on at least one or all arms of the master side inverter or at least one module including the slave side inverter. It can be removed, and is advantageous in terms of mounting area.

Embodiment 4 FIG.
FIG. 16 is a diagram illustrating an example of a power converter according to Embodiment 4 of the present invention. In the system shown in FIG. 16, the DC voltage source 12, the inverter circuit 2, the load device 16, the current detection means 3 for detecting the load current flowing through the load device 16, the voltage detection means 10, and the inverter circuit are PWM controlled to control the load device. For example, it is configured by the CPU 11 or the like. The inverter circuit 2 is configured by one-side arms 4a to 4d.

  The inverter circuit 2 of the present embodiment is a circuit having each one side arm 4a to 4d. Each one-side arm includes switching elements 5a to 5d, backflow prevention diodes 7a to 7d, and freewheeling diodes 8a to 8d. The switching elements 5a to 5d are assumed to use MOS FETs. The backflow prevention diodes 7a to 7d are connected in the opposite direction to the parasitic diodes 6a to 6d of the switching elements 5a to 5d in order to suppress backflow to the switching elements 5a to 5d.

Not only the three-phase equipment but also the single-phase bridge-structured inverter of the present embodiment has the same effect as that of the above-described embodiment for suppressing the recovery reduction of the MOS FET, and the system can be made highly efficient.
Further, as in the other embodiments, the limited phase of the arm is configured with an arm like this configuration, and the remaining arm is configured with one switching device, and depending on the type of the device, with one device configuration of a freewheeling diode. By combining the circuit configurations, cost optimization can be achieved while maintaining necessary efficiency.
The above shows an example in which an SJ-structure MOS FET is used. However, the present technique is effective in an inverter using all switching elements in which parasitic inductance exists.
Also in the present embodiment, it is possible to eliminate noise factors such as an increase in lead inductance by integrating at least one arm or all arms into one module, which is advantageous in terms of mounting area. Become.

Embodiment 5 FIG.
The inverter circuit of the above embodiment can be used not only in an air conditioning refrigeration system but also has other uses.
FIG. 17 is a diagram illustrating an example of a grid-connected photovoltaic power generation system according to Embodiment 5 of the present invention. The system shown in FIG. 17 converts a solar cell array 51 composed of a plurality of solar cell modules, and DC power generated by the solar cell array 51 into AC power, which is connected to a single-phase commercial power system 52 to generate power. And a grid-connected inverter device 53 that performs supply.

  The grid-connected inverter device 53 attenuates a high-frequency switching component included in a booster circuit 61 that boosts an input DC voltage, an inverter circuit 2 that converts a DC voltage into a high-frequency AC voltage, and an output voltage of the inverter circuit 2. The filter circuit 62, the interconnection relay 63 that connects and disconnects the output voltage of the filter circuit 62 to the commercial power system 52, the current detection means 3 a that detects the output current of the inverter circuit 2, and the output current of the filter circuit 62 The current detection means 3c to detect, and the arithmetic processing unit 64 which outputs the PWM signal for driving the inverter circuit 2 based on the information of the current detection means 3a, 3c and the like.

  The inverter circuit 2 of this embodiment is an inverter circuit having a single-phase bridge configuration, as in the fourth embodiment, and includes arms 4a to 4d. SJ-structure MOS FETs are used for the switching elements 5a to 5d in the arm, high-speed types such as SBD are used for the backflow prevention diodes 7a to 7d, and high-speed types having good reverse recovery characteristics are used for the free-wheeling diodes 8a to 8d. Was used.

In the present embodiment, since the inverter circuit 2 is configured as described above, the recovery current at the time of switching can be reduced, and high-efficiency driving is possible.
In the solar power generation system, an increase in power conversion efficiency in the inverter device leads to an increase in the amount of generated power, and the user can obtain a larger amount of generated power. Further, since loss during power conversion can be reduced, heat generation in the inverter device can be suppressed, and there are advantages such as downsizing of the heat dissipation device and improvement in reliability of components due to reduction in temperature rise.

As described above, the present invention is linked not only to an inverter device connected to an independent load such as an electric motor and a load device as in the first to fourth embodiments, but also to a commercial power system as in the fifth embodiment. It can be used for a grid-connected inverter device, and the same effect can be obtained.
In the present embodiment, a grid-connected photovoltaic power generation system linked to a single-phase commercial power system is shown. However, a grid-connected photovoltaic power generation system linked to a three-phase commercial power grid or a grid-connected grid The same effect can also be obtained in an independent solar power generation system that supplies power to an independent load without any problem.
Furthermore, in the present embodiment, a solar power generation system using a solar cell module as a power generation element is shown. However, the present invention is similarly applied to a power generation system using any power generation element that generates DC power, such as a fuel cell and a wind power generator. Needless to say, the same effect can be obtained.

  DESCRIPTION OF SYMBOLS 1 Electric motor, 2 Inverter circuit, 3, 3a-3c Current detection means 4, 4a-4f Configuration of each one side arm 5, 5a-5f Switching element (MOS FET) in arm 6, 6, 6a-6f Parasitic diode, 7 , 7a to 7f Backflow prevention diode, 8, 8a to 8f Reflux diode, 10 Voltage detection means, 11 CPU, 12 DC voltage source, 13a to 13f Switching element (IGBT and others), 14a to 14c Switching element (IGBT and others), 15a -15 f Each side arm of an inverter composed of IGBT, 16 load device, 21 gate, 22 source, 23 drain, 24 substrate (polarity n +), 25 p layer, 26 n layer, 51 solar cell array, 52 single phase commercial Power system, 53 grid-connected inverter device, 61 step-up chopper circuit, 62 Filter circuit, 63 consecutive relays, 64 processor, 101a to 101f switching elements, 102a-102f parasitic diode.

Claims (12)

Comprising at least one unilateral arm;
The one-side arm is antiparallel to a series circuit of a switching element having a built-in parasitic diode, a backflow prevention diode connected in series with the switching element to suppress backflow to the switching element, and the switching element and the backflow prevention diode. A power conversion device comprising a connected freewheeling diode. The switching element is a super junction structure MOSFET.
The power converter according to claim 1, wherein the backflow prevention diode is connected in series with the MOS FET in the reverse direction.   The power converter according to claim 1, wherein a low breakdown voltage element is used for the backflow prevention diode. Comprising at least one arm consisting of two one-sided arms connected in series;
One of the one side arms is connected in series so as to be connected to the MOS FET, the source and the anode side of the MOS FET, a backflow prevention diode for suppressing backflow to the MOS FET, the MOS FET and the backflow A freewheeling diode connected in antiparallel to a series circuit with a prevention diode;
2. The power conversion device according to claim 1, wherein the other arm includes an IGBT or a MOS FET and a free-wheeling diode connected in parallel to the IGBT or the MOS FET.   The power converter according to any one of claims 1 to 4, further comprising control means for performing PWM control on the one-side arm by underlaying two-phase modulation.   The power converter according to any one of claims 1 to 4, further comprising control means for performing PWM control on the one side arm by two-phase modulation with an extension. A first inverter and a second inverter connected to the first inverter via a load;
The first inverter is connected in series so as to be connected to the MOS FET, the source and the anode side of the MOS FET, a backflow prevention diode for suppressing backflow to the MOS FET, the MOS FET and the backflow At least one arm having a free-wheeling diode connected in reverse parallel to a series circuit with a prevention diode;
The second inverter includes at least one one-side arm including a switching element and a free-wheeling diode connected in parallel with the switching element. With control means,
8. The control means for sticking each phase voltage of the second inverter to the positive side or the negative side of the DC bus according to the voltage polarity of each phase voltage command of the first inverter. The power converter device described in 1.   The power conversion device according to claim 1, wherein at least one one-side arm is modularized.   One or more one-sided arms constituting at least one of the first inverter and the second inverter, or at least one inverter of the first inverter and the second inverter is modularized. The power conversion device according to claim 7 or 8.   A refrigeration and air conditioning system, wherein the power conversion device according to claim 1 is used as an inverter drive device for driving a load device such as an electric motor.   A solar power generation system using a solar cell as a DC power source for supplying power to the power conversion device while connecting the output of the power conversion device according to any one of claims 1 to 10 to a power supply system.

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