JP2010225716A - Wiring board, method of manufacturing the same, and semiconductor device - Google Patents

Wiring board, method of manufacturing the same, and semiconductor device Download PDF

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JP2010225716A
JP2010225716A JP2009069351A JP2009069351A JP2010225716A JP 2010225716 A JP2010225716 A JP 2010225716A JP 2009069351 A JP2009069351 A JP 2009069351A JP 2009069351 A JP2009069351 A JP 2009069351A JP 2010225716 A JP2010225716 A JP 2010225716A
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Prior art keywords
wiring board
electrode
protective film
wiring
solder
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Japanese (ja)
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Akira Warikashi
亮 割栢
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Toppan Inc
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Toppan Printing Co Ltd
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Priority to JP2009069351A priority Critical patent/JP2010225716A/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation

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  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a wiring board which forms a thin protective coating capable of preventing outflow of solder in order to shorten the distance between an electric component and the wiring board as much as possible, and to provide a method for mounting an electric component on the wiring board. <P>SOLUTION: In the wiring board 100 provided, in the uppermost layer, with a metal wiring pattern 11 having an electrode, an electrically insulating protective coating 2 is formed to cover the wiring pattern 11 including the electrode. The protective coating 2 is located at the highest part of the insulating substrate 100. Preferably, the thickness of the protective coating is smaller than the thickness of the metal wiring pattern 11 including the electrode. <P>COPYRIGHT: (C)2011,JPO&INPIT

Description

本発明は、配線基板に関するものである。配線基板としては、たとえば、BGA基板も含まれる。   The present invention relates to a wiring board. Examples of the wiring board include a BGA board.

配線基板上の電極と配線基板及びリード線などをはんだによって接続する際に、はんだが隣接する電極へと流出することを防ぐ目的としてソルダーレジストを配線基板の表面に積層することが行われている。   When connecting an electrode on a wiring board to the wiring board and a lead wire with solder, a solder resist is laminated on the surface of the wiring board for the purpose of preventing the solder from flowing out to an adjacent electrode. .

ところが昨今の半導体パッケージの開発においては高周波駆動、高機能かつ小型化を行うため、配線間隔を狭くしてより集積度を上げる試みが行われている。   However, in recent development of semiconductor packages, attempts have been made to increase the degree of integration by narrowing the wiring interval in order to achieve high-frequency driving, high functionality, and miniaturization.

そのため、このソルダーレジストの厚みにより半導体チップと配線基板、とりわけBGA基板との接続において、はんだ電極の高さをソルダーレジストの厚み分高くする必要がある。   Therefore, it is necessary to increase the height of the solder electrode by the thickness of the solder resist when connecting the semiconductor chip and the wiring substrate, particularly the BGA substrate, due to the thickness of the solder resist.

はんだ電極をソルダーレジストの厚み分高くしようとすると、はんだ電極の直径も大きくなってしまい配線間隔を狭くすることに逆行してしまったり、電極が接続できなくなってしまうなどの問題が発生する。   If an attempt is made to increase the solder electrode by the thickness of the solder resist, the diameter of the solder electrode also increases, causing problems such as reversing the narrowing of the wiring interval and making it impossible to connect the electrodes.

このことを克服するため、構造的にバンプそのものを高くする方法により、ソルダーレジストの高さを克服する方法が考えられているが、これらの方法では工程数が増えてしまうという欠点がある。   In order to overcome this problem, a method of overcoming the height of the solder resist by a method of structurally increasing the bump itself has been considered. However, these methods have a drawback that the number of steps increases.

特開平6−151587JP-A-6-151587 特開平8−196704JP-A-8-196704

本発明は上記の問題点を鑑みて、形成される保護皮膜がソルダーレジストと同等のはんだ流れ出し防止の機能を持ち、その厚みが従来のソルダーレジストよりも薄くなり、電極が基板上で最も高い位置に存在する配線基板を提供することで、配線基板と電気部品の接続距離を短くすることである。またこの配線基板を用いて電気部品を搭載する際に保護皮膜が接合を阻害しないようにする配線基板と、その製造方法において工程数を増やさない手段を提供することである。   In view of the above problems, the present invention has a protective film formed with a solder flow prevention function equivalent to that of a solder resist, the thickness of which is thinner than that of a conventional solder resist, and the electrode is the highest position on the substrate. By providing the wiring board which exists in a, the connection distance of a wiring board and an electrical component is shortened. Another object of the present invention is to provide a wiring board that prevents the protective film from obstructing bonding when an electrical component is mounted using the wiring board, and a means that does not increase the number of steps in the manufacturing method.

請求項1は、最上層に電極を有する金属製の配線パターンが設けられた配線基板において、前記電極を含めて前記配線パターンを覆う電気絶縁性の保護皮膜が形成され、前記絶縁基板の最も高い箇所に、前記保護皮膜が位置していることを特徴とした配線基板である。
言い換えると、本発明の請求項1にかかわる発明は、電気部品を接続する配線基板において電極を有しており、少なくとも、この電極を含む最上層に存在する金属層上に電気絶縁性を持った保護皮膜が形成されていること、金属層上に形成された保護皮膜は1種類のみで、他の種類の有機・無機、絶縁性、導電性を問わず保護皮膜が存在しないことを特徴とする配線基板である。
According to the first aspect of the present invention, in the wiring board provided with a metal wiring pattern having an electrode in the uppermost layer, an electrically insulating protective film covering the wiring pattern including the electrode is formed, and the highest of the insulating board The wiring board is characterized in that the protective film is located at a location.
In other words, the invention according to claim 1 of the present invention has an electrode in the wiring board to which the electric component is connected, and at least has an electric insulation on the metal layer existing in the uppermost layer including the electrode. A protective film is formed, and there is only one type of protective film formed on the metal layer, and there is no protective film regardless of other types of organic / inorganic, insulating or conductive. It is a wiring board.

すなわち、金属層上に形成された保護皮膜の最表面が、配線基板の構成物のなによりも厚み方向でもっとも外側にあることを特徴とした配線基板である。   That is, the wiring board is characterized in that the outermost surface of the protective film formed on the metal layer is the outermost in the thickness direction more than the constituents of the wiring board.

請求項2は、保護皮膜の厚さが、前記電極を含めた前記金属製の配線パターンの厚み未満であることを特徴とする請求項1に記載された配線基板である。
言い換えると、本発明の請求項3にかかわる発明は、形成された保護皮膜の厚さが配線基板の最上層に設けられた電極を構成する金属層の厚みよりも薄いことを特徴とした請求項2か3に記載された配線基板である。
According to a second aspect of the present invention, in the wiring board according to the first aspect, the thickness of the protective film is less than the thickness of the metal wiring pattern including the electrodes.
In other words, the invention according to claim 3 of the present invention is characterized in that the thickness of the protective film formed is thinner than the thickness of the metal layer constituting the electrode provided on the uppermost layer of the wiring board. It is a wiring board described in 2 or 3.

請求項3は、前記保護皮膜は、防錆皮膜であることを特徴とする請求項1または2に配線基板である。
言い換えると、本発明の請求項3にかかわる発明は、上記保護皮膜が電極や配線層の金属に対して防錆効果を発揮する保護膜を形成することを特徴とした請求項1または2に記載の配線基板である。
A third aspect of the present invention is the wiring board according to the first or second aspect, wherein the protective film is a rust preventive film.
In other words, the invention according to claim 3 of the present invention is characterized in that the protective film forms a protective film exhibiting a rust preventive effect on the metal of the electrode or the wiring layer. This is a wiring board.

請求項4は、配線基板の最上層にある電極を有する金属製の配線パターンを覆うように、電気絶縁性を持った保護皮膜を形成する工程と、上記配線基板を150℃以上で加熱する工程と、上記電極にはんだを搭載する工程とを含むことを特徴とした配線基板の製造方法である。
言い換えると、本発明の請求項4にかかわる発明は、配線基板の少なくとも最上層にある金属層に電気絶縁性を持った保護皮膜を形成する工程と、その後に上記配線基板を150℃で過熱してエージング処理を行う工程と、上記配線基板上にある電極部分にはんだを接合する工程を含む配線基板を製造する方法である。
According to a fourth aspect of the present invention, there is provided a step of forming a protective film having electrical insulation so as to cover a metal wiring pattern having an electrode on the uppermost layer of the wiring substrate, and a step of heating the wiring substrate at 150 ° C. or higher. And a step of mounting solder on the electrode.
In other words, the invention according to claim 4 of the present invention includes a step of forming a protective film having electrical insulation on at least the uppermost metal layer of the wiring board, and then heating the wiring board at 150 ° C. A method of manufacturing a wiring board including a step of performing an aging treatment and a step of joining solder to an electrode portion on the wiring board.

請求項5は、前記はんだが鉛を含まないことを特徴とした請求項4に記載の配線基板の製造方法である。
言い換えると、本発明の請求項5にかかわる発明は、配線基板の製造方法において、電極との接合に用いるはんだに鉛を含まない種類を使用することを特徴とした請求項4に記載の配線基板の製造方法である。
A fifth aspect of the present invention is the method for manufacturing a wiring board according to the fourth aspect, wherein the solder does not contain lead.
In other words, in the invention according to claim 5 of the present invention, in the method of manufacturing a wiring board, a solder that does not contain lead is used for solder used for joining with an electrode. It is a manufacturing method.

請求項6は、配線基板の最上層にある電極を有する金属製の配線パターンを覆うように、電気絶縁性を持った保護皮膜を形成する工程と、上記配線基板に熱を加える工程と、上記電極に導電性物質を押し付ける工程と、前記押し付けられた導電性物質に超音波を印加する工程とを含むことを特徴とした配線基板の製造方法である。
言い換えると、本発明の請求項6にかかわる発明は、配線基板の少なくとも最上層にある金属層に電気絶縁性を持った保護皮膜を形成する工程と、上記配線基板に熱を加えて予備過熱を行う工程と、上記配線基板の電極に、電気部品との通電を担う導電性物質を押し付けておく工程と、その導電性物質に超音波を印加し電極と導電性物質を溶着させることを特徴とした配線基板の製造方法である。
According to a sixth aspect of the present invention, there is provided a step of forming a protective film having electrical insulation so as to cover a metal wiring pattern having an electrode on the uppermost layer of the wiring substrate, a step of applying heat to the wiring substrate, A method for manufacturing a wiring board, comprising: a step of pressing a conductive material against an electrode; and a step of applying an ultrasonic wave to the pressed conductive material.
In other words, the invention according to claim 6 of the present invention includes a step of forming a protective coating having electrical insulation on at least the uppermost metal layer of the wiring board, and preheating by applying heat to the wiring board. And a step of pressing a conductive substance responsible for energization with an electrical component against the electrode of the wiring board, and applying an ultrasonic wave to the conductive substance to weld the electrode and the conductive substance. This is a method for manufacturing a printed wiring board.

請求項7は、請求項1から3に記載の配線基板、または請求項4から6に記載された方法で製造された配線基板に、半導体素子が搭載されることを特徴とする半導体装置である。
言い換えると、本発明の請求項7にかかわる発明は、請求項1から3に記載された配線基板、または請求項4から6に記載された製造方法で製造された配線基板に接続する電気部品が半導体素子であることを特徴とした配線基板である。
A seventh aspect of the present invention is a semiconductor device in which a semiconductor element is mounted on the wiring board according to the first to third aspects or the wiring board manufactured by the method according to the fourth to sixth aspects. .
In other words, in the invention according to claim 7 of the present invention, there is provided an electrical component connected to the wiring board described in claims 1 to 3 or the wiring board manufactured by the manufacturing method described in claims 4 to 6. A wiring board characterized by being a semiconductor element.

本発明によれば、配線基板上の最も高い位置には配線基板上の電極に形成された絶縁性保護膜が存在するため、電極上の保護皮膜だけを除去することで、配線基板と電気部品の間の距離を狭くすることができる。さらに本発明によれば、電極上のすべてに保護皮膜が形成されていても接続が可能であることから、露光現像といった工程が不必要で、工程短縮を図ることができる。   According to the present invention, since the insulating protective film formed on the electrode on the wiring board exists at the highest position on the wiring board, the wiring board and the electrical component can be removed by removing only the protective film on the electrode. The distance between can be reduced. Further, according to the present invention, since the connection is possible even if a protective film is formed on all the electrodes, a process such as exposure and development is unnecessary, and the process can be shortened.

本発明の実施の形態に係る配線基板の構成を説明する断面図である。It is sectional drawing explaining the structure of the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線基板を示す断面図である。It is sectional drawing which shows the wiring board which concerns on embodiment of this invention. 本発明の実施の形態に係る配線基板を示す断面図である。It is sectional drawing which shows the wiring board which concerns on embodiment of this invention.

図1に示すように、本発明の実施の形態に係る配線基板100は、絶縁基材層(絶縁基板または配線基板)3上の主面に金属層1を有し、金属層1には保護皮膜2が形成されている。なお、図1ではビアや対面の配線等は省略してある。また、電極を有する配線パターン11は金属層1の一部である。
保護皮膜2はこの配線基板100上の金属層1上に形成することが望ましい。図1は金属層1上のみ保護皮膜2を形成した例であるが、皮膜は金属層1に限らずに絶縁基材層3上に形成されていてもよい。しかし少なくとも金属層1には保護皮膜2が形成されている必要があり、金属層1の上に形成された保護皮膜2が、配線基板100上で最も高い位置に存在する必要がある。これにより配線基板100の電極11と電気部品4の電極間距離は保護皮膜2のみに依存することになり、保護皮膜2を薄くする手段を講じることで、電極間距離をより狭くすることが可能である。
As shown in FIG. 1, a wiring board 100 according to an embodiment of the present invention has a metal layer 1 on the main surface on an insulating base material layer (insulating board or wiring board) 3, and the metal layer 1 is protected. A film 2 is formed. In FIG. 1, vias, facing wiring, and the like are omitted. The wiring pattern 11 having electrodes is part of the metal layer 1.
The protective film 2 is preferably formed on the metal layer 1 on the wiring substrate 100. FIG. 1 shows an example in which the protective film 2 is formed only on the metal layer 1, but the film may be formed not only on the metal layer 1 but also on the insulating base material layer 3. However, at least the metal layer 1 needs to have a protective film 2 formed thereon, and the protective film 2 formed on the metal layer 1 needs to be present at the highest position on the wiring substrate 100. As a result, the distance between the electrodes 11 of the wiring board 100 and the electrical component 4 depends only on the protective film 2, and the distance between the electrodes can be made narrower by providing a means for thinning the protective film 2. It is.

配線基板100は、絶縁基材層3と金属層1とをそれぞれ一層以上積層して構成される。絶縁基材層3を一層とし、金属層1を一層として、これらを互いに積層し、最上面の金属層1に保護皮膜2を積層したものである。   The wiring substrate 100 is configured by laminating one or more insulating base material layers 3 and metal layers 1. The insulating base layer 3 is a single layer, the metal layer 1 is a single layer, and these layers are laminated together, and the protective film 2 is laminated on the uppermost metal layer 1.

図2(a)及び図2(b)に示すように、配線基板100は絶縁基材層3のそれぞれ両面に金属層1を形成したものであり、多層構成のものを表している。図2(a)及び図2(b)では、絶縁基材層3の両面に金属層1と保護皮膜2が形成されているが、絶縁基材層3の片面だけに形成できるため本発明はこれに限定されるわけではない。絶縁基材層3と金属層1とをそれぞれ複数層として、これら絶縁基材層3と金属層1とを交互に積層して構成されるビルドアップ配線基板に適用することができる。   As shown in FIGS. 2A and 2B, the wiring substrate 100 is formed by forming the metal layers 1 on both surfaces of the insulating base material layer 3, and has a multilayer structure. 2 (a) and 2 (b), the metal layer 1 and the protective film 2 are formed on both surfaces of the insulating base material layer 3, but the present invention can be formed only on one surface of the insulating base material layer 3. However, the present invention is not limited to this. The insulating base material layer 3 and the metal layer 1 can be used as a plurality of layers, respectively, and the insulating base material layer 3 and the metal layer 1 can be applied to a build-up wiring board configured by alternately laminating them.

金属層1は、銅箔からなる層、銅めっき層及び金属ペーストからなる層等が使用できるが本発明はこれらに限定されるわけではない。銅以外では、アルミ、銀等の配線に用いることができる金属材料を使用することができる。金属箔又は金属めっき層を金属層1として使用する場合には、絶縁基材層3上にこれら銅箔又は銅めっき層を形成した後、エッチングして金属層1を形成することができる。また、金属ペーストを金属層1として使用する場合には、この金属ペーストを所望のパターンに印刷することができる。金属層1の配線パターンを同時に形成することにより、金属層1が形成される。   The metal layer 1 may be a layer made of copper foil, a copper plating layer, a layer made of metal paste, or the like, but the present invention is not limited to these. Other than copper, a metal material that can be used for wiring such as aluminum and silver can be used. When a metal foil or a metal plating layer is used as the metal layer 1, the metal layer 1 can be formed by etching after forming the copper foil or copper plating layer on the insulating base layer 3. Moreover, when using a metal paste as the metal layer 1, this metal paste can be printed in a desired pattern. By simultaneously forming the wiring pattern of the metal layer 1, the metal layer 1 is formed.

保護皮膜2は電気絶縁性の物質であれば特に制限はなく、回路基板そのものを外部から保護するためにガラス皮膜や塩化ビニル系の材料を基板上に薄く形成することで、金属層1を保護することができるが、本発明ではこれらの材料に限定されるわけではない。さらには、保護皮膜2は、金属層1の酸化を防止することを目的とした防錆剤を使用することができ、特に金属層1が銅である場合、銅上にのみ形成するベンゾトリアゾール系、イミダゾール系、ホウ素系などから選択することができるが、これらに限定されるわけではない。
すなわち、基板表面に、金属層1が酸化しない様に薄いガラス膜を塗布したり、防錆皮膜薬液処理により形成することなとで、これを保護皮膜2とすることができる。電気部品を実装する際はこの保護皮膜2を超音波や熱を使って除去することで配線基板の電極が露出し接続が可能になる。
The protective film 2 is not particularly limited as long as it is an electrically insulating substance, and the metal layer 1 is protected by forming a thin glass film or vinyl chloride material on the substrate in order to protect the circuit board itself from the outside. However, the present invention is not limited to these materials. Furthermore, the protective film 2 can use a rust preventive agent for the purpose of preventing the oxidation of the metal layer 1, and in particular, when the metal layer 1 is copper, a benzotriazole type formed only on copper. , Imidazole, boron and the like, but is not limited thereto.
That is, the protective film 2 can be formed by applying a thin glass film on the surface of the substrate so as not to oxidize the metal layer 1 or forming it by a rust preventive film chemical treatment. When mounting the electrical components, the protective coating 2 is removed using ultrasonic waves or heat, so that the electrodes of the wiring board are exposed and can be connected.

さらに、保護皮膜2の厚さを金属層1の厚みよりも薄くすることで、金属層1以外に付着した保護皮膜2が存在しても、その厚さは金属層1以下であるために電気部品4との接合を阻害する要因にはならないため、この厚さは重要である。   Furthermore, by making the thickness of the protective coating 2 thinner than the thickness of the metal layer 1, even if there is a protective coating 2 attached in addition to the metal layer 1, the thickness is less than or equal to the metal layer 1. This thickness is important because it does not interfere with the joining with the component 4.

絶縁基材層3は、ポリイミド樹脂やガラス/エポキシ樹脂等の有機系絶縁基材のほか、酸化アルミニウム質焼結体や窒化アルミニウム質焼結体等のセラミック系絶縁基材を使用することができるが本発明ではこれらに限定されるわけではない。   The insulating base material layer 3 can use an organic insulating base material such as polyimide resin or glass / epoxy resin, or a ceramic insulating base material such as an aluminum oxide sintered body or an aluminum nitride based sintered body. However, the present invention is not limited to these.

図3を例に本発明の実施の形態を示す。図3(a)は保護皮膜2が金属層1上に形成された配線基板100上の配線パターン11に、はんだ電極41がついた電気部品4を乗せる。このとき、金属層1が銅である場合に使用する保護皮膜2は銅表面のみに保護皮膜をつくる防錆剤を使用するのが適している。これらの保護皮膜は非常に薄く、またはんだとの接合時に保護皮膜を容易に除去することが可能であることがその理由である。   An embodiment of the present invention is shown by taking FIG. 3 as an example. In FIG. 3A, the electric component 4 with the solder electrode 41 is placed on the wiring pattern 11 on the wiring substrate 100 on which the protective film 2 is formed on the metal layer 1. At this time, when the metal layer 1 is copper, it is suitable to use a rust preventive agent that forms a protective film only on the copper surface. The reason is that these protective coatings are very thin or can be easily removed at the time of joining with the solder.

配線基板100上の電気部品4を搭載する際に、その接続にはんだを用いれば、そのはんだを溶融させる熱を加えることで保護皮膜2が除去でき、配線基板100と電子部品4を接続することができる。   When mounting the electrical component 4 on the wiring board 100, if solder is used for the connection, the protective coating 2 can be removed by applying heat that melts the solder, and the wiring board 100 and the electronic component 4 are connected. Can do.

さらに保護皮膜2が、銅皮膜の防錆を目的とすることを特徴とする薬液を使用する場合は、配線基板100と電気部品4とをはんだを用いて接続する前に保護皮膜の耐熱温度を超える150℃以上で加熱しておくことで、保護皮膜2が変質し金属層1が酸化する。これによりはんだの濡れ性を低下させ流れ出しを抑制することができる。しかし、はんだを必要としている部分はフラックスにより酸化膜が除去されその接続性に問題は発生しない。   Further, when a chemical solution characterized in that the protective coating 2 is intended to prevent rust of the copper coating is used, the heat resistance temperature of the protective coating is set before connecting the wiring board 100 and the electrical component 4 with solder. By heating at 150 ° C. or higher, the protective film 2 is altered and the metal layer 1 is oxidized. Thereby, the wettability of a solder can be reduced and flow-out can be suppressed. However, the oxide film is removed by the flux in the portion requiring the solder, and there is no problem in the connectivity.

さらに、配線基板100と電気基板4を接合するのに使用するはんだが鉛を含まない場合は、そのはんだの濡れ性が鉛を含むはんだに比べて悪いため、流れ出しを抑制の効果が大きくなる。   Furthermore, when the solder used to join the wiring substrate 100 and the electric substrate 4 does not contain lead, the wettability of the solder is worse than that of the solder containing lead, so that the effect of suppressing the flow out is increased.

図3(b)は、電気部品4の電極に突起電極42(たとえば金バンプ)を用いて配線基板100と接合するような、主に半導体素子の場合である。このときに使用する皮膜は、先の防錆剤だけでなく基板全体を保護する皮膜まで使用することができる。この場合、防錆皮膜とは皮膜の形成方法が異なるためにごく薄い保護皮膜を形成することは困難であるが、塗布方法、たとえばスプレー塗布や蒸着法によってこの問題は解決が可能である。また手法はこれに限定されるものではない。   FIG. 3B mainly shows the case of a semiconductor element in which the electrode of the electrical component 4 is joined to the wiring substrate 100 using a protruding electrode 42 (for example, a gold bump). The film used at this time can be used not only for the rust preventive agent but also for the film for protecting the entire substrate. In this case, it is difficult to form a very thin protective film because the method of forming the film is different from the anticorrosive film, but this problem can be solved by an application method such as spray coating or vapor deposition. Further, the method is not limited to this.

配線基板100と電気部品4との接合に突起電極42を使用した場合の接続方法は、まず予備加熱した配線基板100の上に電気部品4を所定の場所に固定し、一定の力で突起電極42を電極11に押し付け、突起電極42に超音波を印加する、ことで突起電極42が振動し予備加熱との作用ともあいまって配線基板100と電極11の間に熱を発生する。発生した熱により保護皮膜2が変質し、また振動により皮膜を削り、同時にその熱で突起電極42と金属配線11が溶融して配線基板100と電気部品4が接続される。この接続方法は公知の超音波溶着の原理と同じである。   When the protruding electrode 42 is used for joining the wiring board 100 and the electric component 4, the electric component 4 is first fixed at a predetermined position on the preheated wiring board 100, and the protruding electrode is fixed with a certain force. 42 is pressed against the electrode 11 and an ultrasonic wave is applied to the protruding electrode 42, so that the protruding electrode 42 vibrates and generates heat between the wiring substrate 100 and the electrode 11 together with the action of preheating. The protective coating 2 is altered by the generated heat, and the coating is shaved by vibration. At the same time, the protruding electrode 42 and the metal wiring 11 are melted by the heat, and the wiring substrate 100 and the electrical component 4 are connected. This connection method is the same as the principle of known ultrasonic welding.

上記の接合に使用される電気部品は、抵抗、コンデンサ、インダクタ、などが挙げられるがこれに限られることはなく、ダイオードやトランジスタ、半導体チップの等の半導体素子を接合することも可能である。   Examples of the electrical components used for the above-mentioned joining include resistors, capacitors, inductors, and the like, but are not limited thereto, and semiconductor elements such as diodes, transistors, and semiconductor chips can be joined.

上記のいずれの実施形態においても既存のソルダーレジストのように、電極部分に開口を作る必要がないため、保護皮膜2を形成するだけで露光、現像が必要なく工程短縮が可能である。また、既存の設備を使用することが可能である。
(実施例1)
In any of the above-described embodiments, unlike the existing solder resist, it is not necessary to make an opening in the electrode portion. Therefore, the process can be shortened by forming the protective film 2 without requiring exposure and development. It is also possible to use existing equipment.
Example 1

ポリイミド樹脂を絶縁基材層3として両面に銅箔を積層した銅張り積層板を使用して、脱脂、酸洗、洗浄、乾燥の各工程の後、その片面に、四国化成(株)製、商品名「タフエースF2(LX)PK」で表示されるプリフラックス剤を常温で1分間浸漬し洗浄の後、100℃で1分間過熱し配線基板を乾燥させた。
このとき、この基板にはソルダーレジストは形成されていない。
Using a copper-clad laminate in which copper foil is laminated on both sides as an insulating base layer 3 with polyimide resin, after each step of degreasing, pickling, washing and drying, on one side, made by Shikoku Kasei Co., Ltd. The preflux agent indicated by the trade name “Tuff Ace F2 (LX) PK” was immersed for 1 minute at room temperature, washed, and then heated at 100 ° C. for 1 minute to dry the wiring board.
At this time, no solder resist is formed on the substrate.

次に、この保護皮膜2を形成した配線基板を175℃で30分間乾燥させ、防錆皮膜を酸化させた。   Next, the wiring board on which the protective film 2 was formed was dried at 175 ° C. for 30 minutes to oxidize the anticorrosive film.

乾燥させた配線基板に印刷法を用いて鉛フリーはんだを電極の面積と等しくなるように印刷し、その上に電極部分が鉛フリーはんだであるチップコンデンサを搭載し、最大温度240℃になるように過熱してチップコンデンサと配線基板を接続した。   Print the lead-free solder on the dried wiring board using the printing method so that it is equal to the area of the electrode, and mount the chip capacitor with the electrode part made of lead-free solder on it, so that the maximum temperature is 240 ° C. The chip capacitor was connected to the wiring board by overheating.

接合後の外観は、電極より先の配線パターンへの流れ出しが1mmでチップコンデンサ電極上部から配線基板電極の端部まで滑らかな弓状のフィレットを形成していた。また導通テストにより配線基板100とチップコンデンサが通電していることを確認し、この発明が有効であることを確認した。
(実施例2)
The appearance after bonding was that the flow out to the wiring pattern ahead of the electrode was 1 mm, and a smooth arcuate fillet was formed from the top of the chip capacitor electrode to the end of the wiring board electrode. Further, it was confirmed that the wiring board 100 and the chip capacitor were energized by a continuity test, and it was confirmed that the present invention was effective.
(Example 2)

実施例1と同じ基板を準備し、墨東化成工業(株)製、商品名「シラグシタールーA6200」で表示される常温ガラスコーティング剤をエアースプレーにて塗布し、24時間乾燥させ基板表面にガラス薄膜を形成し、このガラス皮膜の厚さは触針計で測定し、その厚さは金属層未満であることを確認した。
このとき、この基板にはソルダーレジストは形成されていない。
Prepare the same substrate as in Example 1, apply a room temperature glass coating agent indicated by the brand name “Shiragusitaru A6200” manufactured by Bokuto Kasei Kogyo Co., Ltd. with air spray, and dry for 24 hours to form a glass thin film on the substrate surface. The thickness of this glass film was measured with a stylus meter, and it was confirmed that the thickness was less than the metal layer.
At this time, no solder resist is formed on the substrate.

次に、この基板上に半導体素子を搭載し配線基板と半導体素子を金バンプで接続する。バンプの径は25umであり、加熱温度は220℃、1バンプあたりの超音波出力130mW 加重50g 打ち付け時間は5mSecとした。   Next, a semiconductor element is mounted on the substrate, and the wiring board and the semiconductor element are connected by gold bumps. The bump diameter was 25 μm, the heating temperature was 220 ° C., the ultrasonic output per bump was 130 mW, the weight was 50 g, and the firing time was 5 mSec.

接続後に配線基板と半導体素子の導通試験を実施し、導通されていることを確認し、この発明が有効であることを確認した。   After the connection, a continuity test between the wiring board and the semiconductor element was performed to confirm that the continuity was established, and it was confirmed that the present invention was effective.

1:金属層
11:配線パターン、電極
2:保護皮膜
3:絶縁基材層
4:電気部品
41:はんだ電極
42:金属電極
100: 配線基板
1: Metal layer 11: Wiring pattern, electrode 2: Protective film 3: Insulating base material layer 4: Electrical component 41: Solder electrode 42: Metal electrode 100: Wiring board

Claims (7)

最上層に電極を有する金属製の配線パターンが設けられた配線基板において、
前記電極を含めて前記配線パターンを覆う電気絶縁性の保護皮膜が形成され、
前記絶縁基板の最も高い箇所に、前記保護皮膜が位置している、
ことを特徴とした配線基板。
In a wiring board provided with a metal wiring pattern having electrodes on the top layer,
An electrically insulating protective film covering the wiring pattern including the electrode is formed,
The protective film is located at the highest portion of the insulating substrate,
A wiring board characterized by that.
保護皮膜の厚さが、前記電極を含めた前記金属製の配線パターンの厚み未満であることを特徴とする請求項1に記載された配線基板。   The wiring board according to claim 1, wherein a thickness of the protective film is less than a thickness of the metal wiring pattern including the electrodes. 前記保護皮膜は、防錆皮膜であることを特徴とする請求項1または2に記載の配線基板。   The wiring board according to claim 1, wherein the protective film is a rust-proof film. 配線基板の最上層にある電極を有する金属製の配線パターンを覆うように、電気絶縁性を持った保護皮膜を形成する工程と、
上記配線基板を150℃以上で加熱する工程と、
上記電極にはんだを搭載する工程と、
を含むことを特徴とした配線基板の製造方法。
Forming a protective coating with electrical insulation so as to cover a metal wiring pattern having an electrode on the uppermost layer of the wiring board;
Heating the wiring board at 150 ° C. or higher;
A step of mounting solder on the electrode;
The manufacturing method of the wiring board characterized by including.
前記はんだが鉛を含まないことを特徴とした請求項4に記載の配線基板の製造方法。   The method for manufacturing a wiring board according to claim 4, wherein the solder does not contain lead. 配線基板の最上層にある電極を有する金属製の配線パターンを覆うように、電気絶縁性を持った保護皮膜を形成する工程と、
上記配線基板に熱を加える工程と、
上記電極に導電性物質を押し付ける工程と、
前記押し付けられた導電性物質に超音波を印加する工程と、
を含むことを特徴とした配線基板の製造方法。
Forming a protective coating with electrical insulation so as to cover a metal wiring pattern having an electrode on the uppermost layer of the wiring board;
Applying heat to the wiring board;
Pressing the conductive material against the electrode;
Applying ultrasonic waves to the pressed conductive material;
The manufacturing method of the wiring board characterized by including.
請求項1から3に記載の配線基板、または請求項4から6に記載された方法で製造された配線基板に、半導体素子が搭載されることを特徴とする半導体装置。   A semiconductor device, wherein a semiconductor element is mounted on the wiring board according to claim 1 or the wiring board manufactured by the method according to claims 4 to 6.
JP2009069351A 2009-03-23 2009-03-23 Wiring board, method of manufacturing the same, and semiconductor device Pending JP2010225716A (en)

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