JP2010192928A - Semiconductor device, and method of manufacturing the same - Google Patents

Semiconductor device, and method of manufacturing the same Download PDF

Info

Publication number
JP2010192928A
JP2010192928A JP2010101251A JP2010101251A JP2010192928A JP 2010192928 A JP2010192928 A JP 2010192928A JP 2010101251 A JP2010101251 A JP 2010101251A JP 2010101251 A JP2010101251 A JP 2010101251A JP 2010192928 A JP2010192928 A JP 2010192928A
Authority
JP
Japan
Prior art keywords
wire
semiconductor device
pin
electrode
portion
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2010101251A
Other languages
Japanese (ja)
Inventor
Yoshitaka Aiba
Yasunori Fujimoto
Tetsuya Fujisawa
Kazuyuki Imamura
Junichi Kasai
Takashi Nomoto
Mitsutaka Sato
Masaaki Seki
Noriaki Shiba
和之 今村
光孝 佐藤
隆司 埜本
喜孝 愛場
典章 柴
純一 河西
康則 藤本
哲也 藤沢
正明 関
Original Assignee
Fujitsu Semiconductor Ltd
富士通セミコンダクター株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to JP22868099 priority Critical
Application filed by Fujitsu Semiconductor Ltd, 富士通セミコンダクター株式会社 filed Critical Fujitsu Semiconductor Ltd
Priority to JP2010101251A priority patent/JP2010192928A/en
Publication of JP2010192928A publication Critical patent/JP2010192928A/en
Application status is Pending legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/03Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02Bonding areas ; Manufacturing methods related thereto
    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0652Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next and on each other, i.e. mixed assemblies
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes
    • H01L25/10Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/023Redistribution layers [RDL] for bonding areas
    • H01L2224/0233Structure of the redistribution layers
    • H01L2224/02333Structure of the redistribution layers being a bump
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/033Manufacturing methods by local deposition of the material of the bonding area
    • H01L2224/0333Manufacturing methods by local deposition of the material of the bonding area in solid form
    • H01L2224/03334Manufacturing methods by local deposition of the material of the bonding area in solid form using a preform
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/0391Forming a passivation layer after forming the bonding area
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05005Structure
    • H01L2224/05007Structure comprising a core and a coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/0501Shape
    • H01L2224/05016Shape in side view
    • H01L2224/05017Shape in side view comprising protrusions or indentations
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001Internal layers
    • H01L2224/05099Material
    • H01L2224/051Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05144Gold [Au] as principal constituent
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0555Shape
    • H01L2224/05556Shape in side view
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05568Disposition the whole external layer protruding from the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05569Disposition the external layer being disposed on a redistribution layer on the semiconductor or solid-state body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • H01L2224/05572Disposition the external layer being disposed in a recess of the surface the external layer extending out of an opening
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/113Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134Stud bumping, i.e. using a wire-bonding apparatus
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1182Applying permanent coating, e.g. in-situ coating
    • H01L2224/11822Applying permanent coating, e.g. in-situ coating by dipping, e.g. in a solder bath
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/11Manufacturing methods
    • H01L2224/118Post-treatment of the bump connector
    • H01L2224/1183Reworking, e.g. shaping
    • H01L2224/1184Reworking, e.g. shaping involving a mechanical process, e.g. planarising the bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1301Shape
    • H01L2224/13016Shape in side view
    • H01L2224/13017Shape in side view being non uniform along the bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13022Disposition the bump connector being at least partially embedded in the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/1302Disposition
    • H01L2224/13023Disposition the whole bump connector protruding from the surface
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16104Disposition relative to the bonding area, e.g. bond pad
    • H01L2224/16105Disposition relative to the bonding area, e.g. bond pad the bump connector connecting bonding areas being not aligned with respect to each other
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/741Apparatus for manufacturing means for bonding, e.g. connectors
    • H01L2224/742Apparatus for manufacturing bump connectors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/74Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies and for methods related thereto
    • H01L2224/78Apparatus for connecting with wire connectors
    • H01L2224/7825Means for applying energy, e.g. heating means
    • H01L2224/783Means for applying energy, e.g. heating means by means of pressure
    • H01L2224/78301Capillary
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/812Applying energy for connecting
    • H01L2224/81201Compression bonding
    • H01L2224/81203Thermocompression bonding, e.g. diffusion bonding, pressure joining, thermocompression welding or solid-state welding
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93Batch processes
    • H01L2224/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/96Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06513Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06517Bump or bump-like direct electrical connections from device to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/0652Bump or bump-like direct electrical connections from substrate to substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06555Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
    • H01L2225/06558Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking the devices having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/04All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers
    • H01L2225/065All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503Stacked arrangements of devices
    • H01L2225/06572Auxiliary carrier between devices, the carrier having an electrical connection structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1017All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support
    • H01L2225/1023All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement the lowermost container comprising a device support the support being an insulating substrate
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2225/00Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00
    • H01L2225/10All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers
    • H01L2225/1005All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/1011All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L51/00 the devices having separate containers the devices being of a type provided for in group H01L27/00 the containers being in a stacked arrangement
    • H01L2225/1047Details of electrical connections between containers
    • H01L2225/1058Bump or bump-like electrical connections, e.g. balls, pillars, posts
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H01L23/3128Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157Partial encapsulation or coating
    • H01L23/3192Multilayer coating
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00013Fully indexed content
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01006Carbon [C]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01029Copper [Cu]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/102Material of the semiconductor or solid state bodies
    • H01L2924/1025Semiconducting materials
    • H01L2924/10251Elemental semiconductors, i.e. Group IV
    • H01L2924/10253Silicon [Si]
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress

Abstract

PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which has a plurality of pin wires at narrow pitches, the plurality of pin wires being nearly constant in height.
SOLUTION: The method of manufacturing the semiconductor device includes a step of performing half-cutting a metal wire, having a first end, at a desired position, a step of bonding the first end of the metal wire to an electrode portion 83 of a semiconductor element 85 or the semiconductor device, and a step of cutting the metal wire at the desired position by drawing the metal wire away from the electrode portion to form a pin wire 84, the pin wire having a cut second end 80c.
COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明はピンワイヤを有する半導体装置の製造方法に関する。 The present invention relates to a method of manufacturing a semiconductor device having a pin wire.

従来から半導体チップを樹脂で封止してなる半導体パッケージは知られている。 The semiconductor package obtained by encapsulating a semiconductor chip with resin conventionally known. 半導体パッケージはますます小型化されてきており、最近では半導体チップの大きさとほぼ同じ大きさの半導体パッケージが出現している。 The semiconductor package has been increasingly miniaturized, almost the semiconductor package having the same size as the size of the semiconductor chip is recently have emerged. このような半導体パッケージは例えばCSP(チップサイズパッケージ)と呼ばれている。 Such semiconductor packages is called for example CSP (chip size package).

CSPの製造方法の一つとして、ウエハに集積回路や電極パッド等を形成し、ウエハの電極パッドに接続される柱状電極をウエハに形成し、ウエハの表面及び柱状電極を樹脂で封止し、封止の後でウエハをダイシングして個々の半導体チップを含む半導体パッケージに分離する方法がある(例えば、特開平9−64049号公報)。 As one method of manufacturing the CSP, wafer to form an integrated circuit and the electrode pads, the columnar electrodes connected to electrode pads of the wafer is formed on the wafer, sealing the surface and the columnar electrode of the wafer with a resin, by dicing the wafer after sealing there is a method of separating a semiconductor package containing individual semiconductor chips (e.g., JP-a-9-64049).

樹脂層は柱状電極の高さとほぼ同じ厚さになるように形成され、柱状電極の先端が樹脂層の表面に露出する。 Resin layer is formed to be approximately the same thickness as the height of the columnar electrodes, the tip of the columnar electrodes is exposed on the surface of the resin layer. 柱状電極に接続される外部端子(電極パッド)が樹脂層の表面に形成され、この外部端子にははんだバンプを取り付けることができる。 External terminal connected to the columnar electrode (electrode pad) is formed on the surface of the resin layer, this external terminal can be attached to the solder bumps. また、導体パターンからなる再配線導体部分をウエハの表面に形成し、柱状電極の位置をウエハに形成された電極パッドの位置とは異なるように配置することができるようにする。 Moreover, the re-wiring conductor portion made of a conductor pattern formed on the surface of the wafer, so that can be arranged differently from the position of the electrode pad position formed on the wafer of the columnar electrodes.

また、特開平9−260428号公報(特許文献1)は金属ワイヤを用いて半導体チップを実装基板に実装することを開示している。 Further, JP-A-9-260428 (Patent Document 1) discloses that a semiconductor chip is mounted on a mounting substrate by using a metal wire. 金属ワイヤの一端は半導体チップの電極パッドにボンディングされ、金属ワイヤの他端ははんだにより実装基板に固定される。 One end of the metal wire is bonded to the electrode pads of the semiconductor chip, the other end of the metal wire is fixed to the mounting board by solder. この構成によれば、半導体チップと実装基板との熱膨張の差により発生した応力を金属ワイヤのしなりにより吸収することができる。 According to this structure, the stress generated by the difference in thermal expansion between the semiconductor chip and the mounting substrate can be absorbed by bending of the metal wire.

特開平9−260428号公報 JP-9-260428 discloses

半導体装置を回路基板に搭載して使用する場合、半導体装置の外部端子(又ははんだバンプ)が回路基板の電極パッドに接続され、半導体装置の半導体チップと回路基板とが半導体装置の封止樹脂を間に挟んで対向する。 When used by mounting a semiconductor device on a circuit board, an external terminal of the semiconductor device (or solder bumps) is connected to the electrode pads of the circuit board, the sealing resin of the semiconductor chip and the circuit board and the semiconductor device of the semiconductor device facing each other between. 使用においては、半導体装置の半導体チップの熱膨張量と実装基板の熱膨張量とが異なっているので、半導体装置の外部端子や柱状電極等に熱応力が発生し、外部端子や柱状電極は繰り返しの熱応力によって疲労する。 In use, since the amount of thermal expansion between the mounting substrate thermal expansion of the semiconductor chip of the semiconductor device are different, thermal stress is generated in the external terminal and the column electrodes of the semiconductor device, the external terminal and the columnar electrode is repeatedly fatigued by the heat stress.

この熱応力は、半導体装置の半導体チップの熱膨張量と回路基板の熱膨張量との差に比例し、封止樹脂層の厚さに反比例する。 This thermal stress is proportional to the difference between the thermal expansion amount of the circuit thermal expansion of the substrate of the semiconductor chip of the semiconductor device, it is inversely proportional to the thickness of the sealing resin layer. 従って、応力緩和を図るためには、封止樹脂層の厚さを厚くした方がよいことが分かった。 Therefore, in order to stress relaxation has been found that it is better to increase the thickness of the sealing resin layer. しかし、封止樹脂層の厚さを厚くするためには、柱状電極の長さを長くすることが必要である。 However, in order to increase the thickness of the sealing resin layer, it is necessary to increase the length of the columnar electrodes. 柱状電極は通常はメッキにより形成されるが、メッキにより形成された柱状電極の長さを長くすることは限られてしまう。 Although the columnar electrode usually formed by plating, increasing the length of the columnar electrodes formed by plating it is limited.

そこで、柱状電極をワイヤ(ボンディングワイヤ)によって形成すると、柱状電極の長さを長くすることができ、よって封止樹脂層の厚さを厚くすることができる。 Therefore, the columnar electrode be formed by wires (bonding wires), it is possible to increase the length of the columnar electrodes, thus it is possible to increase the thickness of the sealing resin layer. しかし、ワイヤボンダーで処理されるワイヤを柱状電極として用いる場合、ワイヤは柱状電極としては細すぎ、強度が不足することがある。 However, when using a wire that is processed by the wire bonder as columnar electrodes, wire too thin as the cylindrical electrodes, the strength is insufficient. 従って、十分な長さ及び強度をもつワイヤで形成された柱状電極を形成することが望まれている。 Therefore, it is desired to form a columnar electrode formed by a wire having a sufficient length and strength.

さらに、ワイヤは十分に長い柱状電極を提供できるとともにフレキシビリティを備えており、ワイヤからなる柱状電極に熱応力がかかっても柱状電極は破壊されることはない。 Further, the wire has a flexibility with can provide a sufficiently long columnar electrodes, never columnar electrodes are destroyed even if thermal stress is afflicted with columnar electrodes made of wire. しかし、半導体装置の封止樹脂層が硬いと、封止樹脂で拘束されたワイヤからなる柱状電極と回路基板に固定された外部端子との間の接合部に大きな応力がかかる。 However, when the encapsulating resin layer of the semiconductor device is hard, large stress at the junction between the external terminal fixed to the columnar electrode and the circuit board made of wire that is constrained by the sealing resin is applied. 従って、半導体装置の封止樹脂はできるだけ軟らかい樹脂からなるのが好ましい。 Accordingly, the sealing resin of the semiconductor device preferably comprises a possible soft resin.

また、柱状電極の先端を研削したりして調整するときに、ウエハ全体に圧力がかかり、ウエハを損傷してしまうという問題があった。 Further, when adjusting with or grinding the tip of the columnar electrodes, pressure is applied to the entire wafer, there is a problem that damage the wafer. また、樹脂封止の際に、樹脂の流れが柱状電極に望ましくない変形を生じさせることがあった。 At the time of resin sealing, the resin flow was sometimes causing undesirable deformation of the columnar electrode.
他方、近年、半導体装置は、軽く且つ小さいだけでなく高速で作動し、高い機能を備えることを要求されている。 On the other hand, in recent years, semiconductor device operates at a high speed not only lighter and smaller, are required to be provided with high functionality. 半導体チップをインターポーザやマザーボード等の装置に搭載する場合、上記要求を満足するものとして、はんだボールを使用したフリッチチップタイプの搭載方法がある。 When mounting a semiconductor chip on device, such as an interposer or motherboard, as satisfying the above requirements, there is a full rich chip type mounting method using solder balls. しかし、この方法では、半導体チップの電極パッド間が狭ピッチであるため、接続に使用されるはんだボールは、ボール径が小さく、バラツキも少ない特別の仕様となり、非常に高価となる。 In this method, however, between the electrode pads of the semiconductor chip is a narrow pitch, solder balls used for connecting the ball diameter is small, the variation is small becomes a special specification, is very expensive. 回路面の封止のために使用されるアンダーフィルも、半導体チップとマザーボードの間の狭い隙間を埋めるにあたってボイド等が発生しないことが特性として要求されるため、半導体チップやマザーボードの仕様毎に流れ性や密着性などを改善した特別仕様となる場合が多い。 Even underfill used for sealing the circuit surface, since the voids or the like is required as is characteristic not occur when filling the narrow gap between the semiconductor chip and the mother board, the flow for each specification of the semiconductor chip and the motherboard If it made a special specification which has improved such as sex and adhesion often. 従って、フリップチップタイプの半導体装置は、コストが高くなる。 Accordingly, the semiconductor device of the flip chip type, the cost is high.

また、導電粒子を内在した接着剤による接合方法や、スタッドバンプを用いた接合方法などがあるが、これらの方法では、半導体チップの反り、ボイド、端子のレベリング精度などにより密着性がバラツクため、信頼性が低く、これらのバラツキ管理のためのコストがアップすることが懸念されている。 Moreover, and bonding method using an adhesive agent inherent conductive particles, there are such bonding method using a stud bump, in these methods, the semiconductor chip warpage, voids, and the adhesion leveling accuracy of terminals for fluctuates, unreliable, that costs for these variations management up are concerned.
フリッチチップタイプの搭載方法においてはんだボールを使用する代わりに、金属ワイヤを使用することが考えられる。 Instead of using the solder balls in the mounting process of full rich chip type, it is conceivable to use a metal wire. 金属ワイヤの使用は、自動ワイヤボンダーを使用した従来のワイヤボンディングにおいて発展している。 The use of metal wire, has evolved in the conventional wire bonding with automatic wire bonder. しかし、従来のワイヤボンディングでは、金属ワイヤの先端部を半導体チップの先端に接合し、金属ワイヤの所望の部分をマザーボードの電極に接合した後、キャピラリを動かして金属ワイヤを引っ張ることにより金属ワイヤを切断する。 However, in the conventional wire bonding, joining the leading end of the metal wire to the tip of the semiconductor chip, after joining the desired portion of the metal wire to the electrode of the motherboard, the metal wire by pulling the metal wire by moving the capillary to cut. この場合、金属ワイヤは引きちぎられるので、金属ワイヤの切断部は一様な形状にならず、引きちぎられた金属ワイヤの長さも一様にならないという問題があった。 In this case, since the metal wire is torn off, the cutting portion of the metal wire is not a uniform shape, there is a problem that the length of the metal wires torn not uniform.

本発明の目的は熱応力に対して優れた耐久性のあるピンワイヤを有する半導体装置の製造方法を提供することである。 An object of the present invention is to provide a method of manufacturing a semiconductor device having a pin wire with superior durability against thermal stress.

本発明の特徴による半導体装置の製造方法は、第1端部を有する金属ワイヤに所望の位置でハーフカット処理を行う工程と、該金属ワイヤの第1端部を半導体素子又は半導体装置の電極部にボンディングする工程と、該金属ワイヤを該電極部に対して引っ張ることにより該金属ワイヤを該所望の位置で切断してピンワイヤを形成する工程とを備え、該ピンワイヤは切断された第2端部を有することを特徴とする。 The method of manufacturing a semiconductor device according to the features of the present invention, the electrode portions of the desired and performing half-cutting processing with a position, a semiconductor device or a semiconductor device a first end of the metal wire to a metal wire having a first end portion comprising a step of bonding, and a step of by pulling the metal wire against the electrode portion to form a pin wire by cutting the metal wires at the position of said desired in, the pin wire and the second cut ends characterized in that it has a.

この構成において、金属ワイヤに所望の位置でハーフカット処理を行い、金属ワイヤの第1端部を半導体素子の電極部にボンディングした後で、金属ワイヤを電極部に対して引っ張ると、金属ワイヤはハーフカットしておいた前記所望の位置で確実に且つきれいに切断される。 In this configuration, performs half-cutting processing at a desired position in the metal wire, after bonding the first end of the metal wire to the electrode of the semiconductor element, pulling the metal wire to the electrode portion, the metal wire the had been half-cut is reliably and cleanly cut at a desired position. 金属ワイヤの切断部は一様な形状になり、金属ワイヤの長さも一様になる。 Cutting portion of the metal wire becomes uniform shape, also becomes uniform length of metal wire. 従って、狭いピッチの複数のピンワイヤを有する半導体素子においては、複数のピンワイヤの高さがほぼ一定になり、半導体素子をマザーボード等の他の装置と接合するの適したものとなる。 Accordingly, in the semiconductor device having a plurality of pin wire of a small pitch, the height of the plurality of pin wire becomes substantially constant, and be suitable for bonding the semiconductor element and other devices such as a motherboard.

以上説明したように、本発明によれば、金属ワイヤの切断部は一様な形状になり、金属ワイヤの長さも一様になる。 As described above, according to the present invention, the cutting portion of the metal wire becomes uniform shape, also becomes uniform length of metal wire. 従って、狭いピッチの複数のピンワイヤを有する半導体素子においては、複数のピンワイヤの高さがほぼ一定になり、半導体素子をマザーボード等の他の装置と接合するの適したものとなる。 Accordingly, in the semiconductor device having a plurality of pin wire of a small pitch, the height of the plurality of pin wire becomes substantially constant, and be suitable for bonding the semiconductor element and other devices such as a motherboard.

本発明の第1実施例による半導体装置を示す部分断面斜視図である。 Is a partial cross-sectional perspective view showing a semiconductor device according to a first embodiment of the present invention. はんだボール付着前の図1の半導体装置を示す断面図である。 It is a sectional view showing a semiconductor device of FIG. 1 before the solder balls attached. 図1の半導体装置の変形例を示す図である。 It is a diagram showing a modified example of the semiconductor device in FIG. 図1の半導体装置を回路基板に取り付けた例を示す図である。 The semiconductor device of FIG. 1 is a diagram showing an example in which the circuit board. 樹脂層の厚さと外部端子における応力との関係を示す図である。 Is a diagram showing the relationship between the stress in the thickness and the external terminals of the resin layer. ウエハに集積回路を形成し、はんだボールを付着し、そして個々の半導体装置に分離する工程を含む半導体装置の製造方法の例を示す図である。 Wafer to form an integrated circuit, depositing a solder ball, and is a diagram showing an example of a method of manufacturing a semiconductor device including a step of separating the individual semiconductor devices. 外部端子に膨大部を形成する工程を含む半導体装置の製造方法の例を示す図である。 Is a diagram illustrating an example of a method of manufacturing a semiconductor device including a step of forming a large part to the external terminal. 膨大部分を有する柱状電極の形成方法の例を示す図である。 Is a diagram illustrating an example of a method of forming columnar electrodes having a large portion. 図8の方法で形成された柱状電極を示す図である。 It is a diagram showing a columnar electrode formed by the method of FIG. 膨大部分を有する柱状電極の形成方法の他の例を示す図である。 It is a diagram showing another example of a method of forming columnar electrodes having a large portion. 柱状電極の形成方法の他の例を示す図である。 It is a diagram showing another example of a method of forming columnar electrodes. 柱状電極の形成方法の他の例を示す図である。 It is a diagram showing another example of a method of forming columnar electrodes. 柱状電極の形成方法の他の例を示す図である。 It is a diagram showing another example of a method of forming columnar electrodes. 本発明の第2実施例による半導体装置を示す部分断面図である。 It is a partial sectional view showing a semiconductor device according to a second embodiment of the present invention. 図14の半導体装置の変形例を示す図である。 It is a diagram showing a modified example of the semiconductor device in FIG 14. 図14の半導体装置の変形例を示す図である。 It is a diagram showing a modified example of the semiconductor device in FIG 14. 図14の半導体装置の変形例の柱状電極の形成方法を示す図である。 It is a diagram showing a method of forming columnar electrodes of a modification of the semiconductor device in FIG 14. 図14の半導体装置の変形例を示す図である。 It is a diagram showing a modified example of the semiconductor device in FIG 14. 図18の半導体装置の変形例を示す図である。 It is a diagram showing a modified example of the semiconductor device in FIG 18. 本発明の第3実施例による半導体装置を示す部分断面図である。 It is a partial sectional view showing a semiconductor device according to a third embodiment of the present invention. 図20の半導体装置の変形例を示す図である。 It is a diagram showing a modified example of the semiconductor device in FIG 20. 図14から図20の半導体装置の柱状電極の露出方法を示す図である。 Figures 14 is a diagram showing a method of exposing the columnar electrodes of the semiconductor device in FIG 20. 図22の柱状電極の露出方法の一例を示す図である。 Is a diagram illustrating an example of a method of exposing the columnar electrodes of Figure 22. 図22の柱状電極の露出方法の一例を示す図である。 Is a diagram illustrating an example of a method of exposing the columnar electrodes of Figure 22. 図24の柱状電極の露出方法の変形例を示す図である。 It is a diagram showing a modified example of the exposure method of the columnar electrodes of Figure 24. 図24の柱状電極の露出方法の変形例を示す図である。 It is a diagram showing a modified example of the exposure method of the columnar electrodes of Figure 24. 本発明の第4実施例によるピンワイヤを有する半導体装置の製造方法を示す図である。 It is a diagram showing a manufacturing method of a semiconductor device having a pin wire according to a fourth embodiment of the present invention. 図27のハーフカット処理された金属ワイヤを示す拡大図である。 Is an enlarged view showing the half-cut treated metal wire of Figure 27. 図27及び図28の切断された金属ワイヤ(ピンワイヤ)を示す拡大側面図である。 It is an enlarged side view showing a cut metal wire 27 and 28 (pin wire). ピンワイヤを有する半導体装置を示す略図である。 It is a schematic diagram showing a semiconductor device having a pin wire. 種々のピンワイヤを示す図である。 Is a diagram showing various pin wire. ピンワイヤを有する半導体装置の一例を示す図である。 Is a diagram illustrating an example of a semiconductor device having a pin wire. 再配線電極及びピンワイヤを有する半導体装置の他の例を示す図である。 It is a diagram showing another example of a semiconductor device having a re-wiring electrodes and pin wire. 図33の半導体装置を形成する工程を示す詳細図である。 It is a detail view showing the step of forming a semiconductor device of FIG. 33. ピンワイヤの変形例を示す図である。 It is a diagram showing a modification of the pin wire. ピンワイヤを有する半導体装置の他の例を示す図である。 It is a diagram showing another example of a semiconductor device having a pin wire. ピンワイヤを有する半導体装置の他の例を示す図である。 It is a diagram showing another example of a semiconductor device having a pin wire. ピンワイヤの先端に導体材料を付着させた半導体装置の例を示す図であり、(A)は半導体素子に設けられたピンワイヤを槽の導電材料に漬けることによって導電材料を付着させることを示し、(B)は半導体素子に設けられたピンワイヤを形成板の凹部の導電材料に漬けることによって導電材料を付着させることを示し、(C)はピンワイヤ及び導電材料を有する半導体素子をインターポーザ又はマザーボードに搭載するところを示す図である。 Is a diagram showing an example of a semiconductor device obtained by attaching the conductive material at the tip of the pin wire, (A) shows the depositing a conductive material by dipping the pin wire provided on the semiconductor element to the conductive material of the vessel, ( B) indicates that adhering a conductive material by soaking the conductive material of the recess of the forming plate the pin wire provided in the semiconductor device, (C) is for mounting a semiconductor device having a pin wire and a conductive material on an interposer or motherboard it is a diagram showing a place. 熱圧着によるピンワイヤの接合の例を示す図である。 Is a diagram illustrating an example of a joining pin wire by thermal compression bonding. ピンワイヤの直径を変えることによるインピーダンスマッチングの例を示す図である。 Is a diagram illustrating an example of the impedance matching by varying the diameter of the pin wire. ピンワイヤの先端の膨大部の太さを変えることによるインピーダンスマッチングの例を示す図である。 Is a diagram illustrating an example of the impedance matching by varying the thickness of the enlarged portion of the distal end of the pin wire. メッキ部によりピンワイヤを接合した半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device formed by joining pin wire by plating unit. ピンワイヤを有する半導体装置の一例を示す図である。 Is a diagram illustrating an example of a semiconductor device having a pin wire. 樹脂封止の他の例を示す図である。 It is a diagram showing another example of the resin sealing. 半導体装置の一例を示す平面図である。 Is a plan view showing an example of a semiconductor device. 図45の平面的に配置された複数の半導体素子を含む半導体装置の例を示す図である。 It is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements which are planarly disposed in FIG. 45. 立体的に配置された複数の半導体素子を含む半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements are arranged three-dimensionally. 立体的に配置された複数の半導体素子を含む半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements are arranged three-dimensionally. スタックとして立体的に配置された複数の半導体装置を含む半導体装置の例を示す図である。 It is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor devices that are arranged three-dimensionally as a stack. スタックとして立体的に配置された複数の半導体装置を含む半導体装置の例を示す図である。 It is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor devices that are arranged three-dimensionally as a stack. ピンワイヤを有する半導体装置の製造方法の一例を示す図である。 Is a diagram illustrating an example of a manufacturing method of a semiconductor device having a pin wire. 図51の半導体装置に樹脂封止工程を示す図である。 Is a diagram showing the resin sealing step in the semiconductor device in FIG 51. 図52の半導体装置のダイシング工程を示す図である。 It is a diagram illustrating a dicing process of the semiconductor device in FIG 52. ピンワイヤを印刷により形成された導電材料に接合する例を示す図である。 Is a diagram illustrating an example of joining pin wire to the conductive material formed by printing. 複数の半導体素子を含む半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements. 複数の半導体素子を含む半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements. 複数の半導体素子を含む半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements. 複数の半導体素子を含む半導体装置の例を示す図である。 Is a diagram illustrating an example of a semiconductor device including a plurality of semiconductor elements.

以下本発明の実施例について図面を参照して説明する。 It will be described with reference to the accompanying drawings embodiments of the present invention follows.
図1は本発明の第1実施例による半導体装置10を示す部分断面斜視図である。 Figure 1 is a partial cross-sectional perspective view showing a semiconductor device 10 according to a first embodiment of the present invention. 図2ははんだボール付着前の図1の半導体装置を示す断面図である。 Figure 2 is a sectional view showing a semiconductor device of FIG. 1 before the solder balls attached.
図1及び図2において、半導体装置10は、複数の電極パッド12を有する半導体素子14と、複数の電極パッド12に接続され且つ半導体素子14に対して垂直に延びる複数の柱状電極16と、半導体素子14及び柱状電極16を覆う樹脂層18と、柱状電極16に電気的に接続されるように樹脂層18の表面に配置された外部端子20とを備える。 1 and 2, the semiconductor device 10 includes a semiconductor element 14 having a plurality of electrode pads 12, a plurality of columnar electrodes 16 extending perpendicular to the plurality of connected to the electrode pads 12 and the semiconductor element 14, the semiconductor It includes a resin layer 18 covering the element 14 and the columnar electrode 16, and an external terminal 20 disposed on the surface of the resin layer 18 to be electrically connected to the columnar electrode 16.

半導体素子14はシリコンチップからなり、集積回路(図示せず)とこの集積回路に適切に接続された電極パッド12を含む。 The semiconductor device 14 consists of a silicon chip includes an integrated circuit (not shown) the electrode pads 12 which are suitably connected to the integrated circuit of Toko. 外部端子20は樹脂層18の表面に配置され、柱状電極16の先端に接続、固定されている電極パッドである。 External terminal 20 is disposed on the surface of the resin layer 18, connected to the tip of the columnar electrodes 16, an electrode pad that is fixed. さらに、はんだボール20aが外部端子20に接続、固定されている。 Furthermore, solder balls 20a are connected to the external terminals 20 are fixed.
樹脂層18は、半導体素子14の表面に形成された柔軟性を有する第1の樹脂層18aと、第1の樹脂層18aよりも半導体素子14から遠い側にあり第1の樹脂層18aよりも高い弾性をもつ第2の樹脂層18bとからなる。 The resin layer 18, a first resin layer 18a having flexibility which is formed on the surface of the semiconductor element 14, than the first resin layer 18a located farther from the semiconductor element 14 than the first resin layer 18a and a second resin layer 18b having a high elasticity. 第1の樹脂層18aはシリコン系樹脂や低弾性エポキシ系樹脂等からなるヤング率が数〜数100kg/mm 2の低弾性樹脂であり、第2の樹脂層18bは高弾性エポキシ系樹脂等からなるヤング率が1000〜2000kg/mm 2の高弾性樹脂である。 The first resin layer 18a is a low-elasticity resin having a Young's modulus of several to several 100 kg / mm 2 made of a silicone resin or a low elasticity epoxy resin, the second resin layer 18b is a highly elastic epoxy resin comprising a Young's modulus of high elasticity resin 1000~2000kg / mm 2.

柱状電極16は、半導体素子14の電極パッド12から延び、軸線方向に沿ってほぼ一定の断面積を有するワイヤ部分16aと、外部端子20aから延び且つワイヤ部分16aよりも大きい断面積を有する膨大部分16bとを有する。 Columnar electrodes 16, large portions having extending from the electrode pads 12 of the semiconductor element 14, a wire portion 16a having a substantially constant cross-sectional area along the axial direction, the cross-sectional area greater than and wire portion 16a extends from the external terminal 20a and a 16b. 従って、柱状電極16は、基本的にワイヤによって作られ、長さ及びフレキシビリティを備えるとともに、柱状電極16と外部端子20との接合領域が膨大部分16bを設けることによって強化されている。 Therefore, the columnar electrode 16 is made essentially by wire, provided with a length and flexibility, bonding area of ​​the columnar electrode 16 and the external terminals 20 is enhanced by providing a large portion 16b. 例えば、柱状電極16は金のワイヤで形成され、柱状電極16のワイヤ部分16aの直径は30〜50μmであり、膨大部分16bの直径はワイヤ部分16aの直径の2〜3倍である。 For example, the columnar electrode 16 is formed of gold wire, the diameter of the wire portion 16a of the columnar electrode 16 is 30 to 50 [mu] m, the diameter of the large portions 16b are 2-3 times the diameter of the wire portion 16a. 外部端子20の直径は膨大部分16bの直径値〜バンプピッチ×0.5であった。 The diameter of the external terminals 20 had a diameter value-bump pitch × 0.5 a huge portion 16b.

図3は図1の半導体装置10の変形例を示す図である。 Figure 3 is a diagram showing a modification of the semiconductor device 10 of FIG. 1. 図1の例と同様に、半導体装置10は、複数の電極パッド12を有する半導体素子14と、複数の電極パッド12に接続された複数の柱状電極16と、半導体素子14及び柱状電極16を覆う樹脂層18と、柱状電極16に電気的に接続されるように樹脂層18の表面に配置された外部端子20とを備える。 As in the example of FIG. 1, the semiconductor device 10 covers the semiconductor device 14 having a plurality of electrode pads 12, a plurality of columnar electrodes 16 connected to the plurality of electrode pads 12, the semiconductor device 14 and the columnar electrode 16 It includes a resin layer 18, and an external terminal 20 disposed on the surface of the resin layer 18 to be electrically connected to the columnar electrode 16.

柱状電極16は、半導体素子14の電極パッド12から延び、軸線方向に沿ってほぼ一定の断面積を有するワイヤ部分16aと、外部端子20から延び且つワイヤ部分16aよりも大きい断面積を有する膨大部分16bとを有する。 Columnar electrodes 16, large portions having extending from the electrode pads 12 of the semiconductor element 14, a wire portion 16a having a substantially constant cross-sectional area along the axial direction, the cross-sectional area greater than and wire portion 16a extends from the external terminal 20 and a 16b. 従って、柱状電極16は、基本的にワイヤによって作られ、長さ及びフレキシビリティを備えるとともに、柱状電極16と外部端子20との接合領域が膨大部分16bを設けることによって強化されている。 Therefore, the columnar electrode 16 is made essentially by wire, provided with a length and flexibility, bonding area of ​​the columnar electrode 16 and the external terminals 20 is enhanced by providing a large portion 16b.

この実施例においては、樹脂層18は、半導体素子14の表面に形成された柔軟性を有する第1の樹脂層18aと、第1の樹脂層18aよりも半導体素子14から遠い側にあり第1の樹脂層18aよりも高い弾性をもつ第2の樹脂層18bと、第1の樹脂層18aと第2の樹脂層18bとの間にあってこれらの2つの樹脂層の接着を補助する第3の樹脂層18cとからなる。 In this embodiment, the resin layer 18 is first located in the first resin layer 18a having flexibility which is formed on the surface of the semiconductor element 14, the semiconductor element 14 than the first resin layer 18a on the far side third resin to assist the second resin layer 18b having a higher elasticity than the resin layer 18a, the adhesion of these two resin layers there between the first resin layer 18a and the second resin layer 18b of the consisting of a layer 18c. この例の作用は基本的に図1及び図2の例の作用と同様である。 The operation of this example is the same as the operation example of the essentially FIGS.

図4は図1の半導体装置を回路基板に取り付けた例を示す図である。 Figure 4 is a diagram showing an example in which the circuit board of the semiconductor device of FIG. 回路基板22は半導体装置10の外部端子20及びはんだボール20aと同じ配列の電極パッド24を有し、半導体装置10は外部端子20(はんだボール20a)を電極パッド24に接合させることにより回路基板22に搭載される。 Circuit board 22 has electrode pads 24 of the same sequence as the external terminals 20 and the solder balls 20a of the semiconductor device 10, the semiconductor device 10 includes the external terminal 20 the circuit board by joining the (solder balls 20a) to the electrode pads 24 22 It is mounted to. 従って、半導体素子14と回路基板22とは樹脂層18を介して対向する。 Accordingly, the semiconductor element 14 and the circuit board 22 opposed to each other via the resin layer 18.

使用時には、半導体素子14及び回路基板22は発熱素子の作動によって膨張収縮する。 In use, the semiconductor device 14 and the circuit board 22 expands and contracts by the operation of the heating elements. 半導体素子14の熱膨張係数と回路基板22の熱膨張係数との差に従って半導体素子14の変形量と回路基板22の変形量との間には差が生じ、柱状電極16及び外部端子20(及びその他の部材)に熱応力が発生する。 The difference between the deformation amount of deformation of the circuit board 22 of the semiconductor element 14 occurs according to the difference of thermal expansion coefficient between the circuit board 22 of the semiconductor element 14, columnar electrodes 16 and the external terminals 20 (and other members) thermal stress is generated in. 半導体装置10の外部端子20や柱状電極16は繰り返しの熱応力によって疲労する。 External terminals 20 and the columnar electrodes 16 of the semiconductor device 10 is the fatigue by the thermal stress of repeated.

しかし、本発明によれば、柱状電極16を基本的にワイヤ部分16aによって構成することによって、長さやフレキシビリティを備え、同時に、膨大部分16bを設けることによって少くとも外部電極20との接合部において十分な強度がある柱状電極16とすることができる。 However, according to the present invention, by constructing the basic wire portion 16a of the columnar electrode 16, with the length and flexibility, at the same time, at least by providing a vast portion 16b at the junction between the external electrode 20 it can be a columnar electrode 16 with sufficient strength. よって、柱状電極16の長さを長く且つ封止樹脂層18の厚さを厚くすることができ、熱疲労に対して優れた耐久性のある半導体装置10を得ることができる。 Therefore, it is possible to be able to increase the thickness of the long and the sealing resin layer 18 the length of the columnar electrode 16 to obtain the semiconductor device 10 with a superior durability against thermal fatigue.

図5は樹脂層18の厚さと外部端子20における応力(バンプ応力)との関係を示す図である。 Figure 5 is a diagram showing the relationship between the stress (bump stress) in thickness and the external terminal 20 of the resin layer 18. 樹脂層18の厚さが厚いほど、外部端子20における応力(バンプ応力)は小さくなる。 The thicker the thickness of the resin layer 18, the stress in the external terminal 20 (bump stress) is reduced. 四角マーク及び菱形マークで示される例は樹脂層18が一層のみであり、その樹脂層の弾性率をAとする。 Example shown in square marks and rhombic mark resin layer 18 is only one layer, the elastic modulus of the resin layer and the A.
四角マークで示される例では、外部端子20が0.8mmピッチで配置され、樹脂層18の厚さが100μmのときにバンプ応力が4.3kg/mm 2であった。 In the example shown in square marks, the external terminals 20 are arranged in a 0.8mm pitch, bump stress when the thickness of the resin layer 18 is 100μm was 4.3 kg / mm 2. 菱形マークで示される例では、外部端子20が0.5mmピッチで配置され、樹脂層18の厚さが150μmのときにバンプ応力が4.3kg/mm 2となる。 In the example shown in diamond mark, the external terminals 20 are arranged in a 0.5mm pitch, bump stress when the thickness of the resin layer 18 is 150μm is 4.3 kg / mm 2.

三角マークで示された例では、第1の樹脂層18aの弾性率を(1/6)Aとし、第2の樹脂層18bの弾性率をAとした。 In the example shown by a triangle mark, the elastic modulus of the first resin layer 18a and (1/6) A, the elastic modulus of the second resin layer 18b was A. Xマークで示された例では、第1の樹脂層18aの弾性率は(1/6)Aとし、第2の樹脂層18bの弾性率は5Aとした。 In the example shown by X mark, the elastic modulus of the first resin layer 18a is set to (1/6) A, the elastic modulus of the second resin layer 18b was 5A. いずれの場合にも、第1の樹脂層18aの厚さは50μm、第2の樹脂層18bの厚さは100μmであった。 In either case, the thickness of the first resin layer 18a is 50 [mu] m, the thickness of the second resin layer 18b was 100 [mu] m. 今後、端子の微細化がすすんでも、バンプの接合応力は十分に信頼性のあるものを得ることができる。 In the future, also the miniaturization of the terminal is willing, bonding stress of the bumps can be obtained which sufficiently reliable. 低弾性の第1の樹脂層18aはヤング率が数〜数100kg/mm 2のシリコン樹脂または低弾性のエポキシ樹脂とすることができ、高弾性の第2の樹脂層18bはヤング率が1000〜2000kg/mm 2の高弾性のエポキシ樹脂とすることができる。 The first resin layer 18a of low elasticity can be Young's modulus of a number of to several 100 kg / mm 2 silicon resin or a low elasticity epoxy resin, the second resin layer 18b of high elastic Young's modulus 1000 it can be a high elasticity of the epoxy resin of 2000 kg / mm 2.

図6は図1から図3の半導体装置10を製造するための方法の例を示す図である。 6 is a diagram showing an example of a method for manufacturing the semiconductor device 10 of FIGS. 図6(A)はシリコンウエハ30に集積回路や電極パッド12や柱状電極16を形成する工程を示す。 FIG 6 (A) shows a step of forming an integrated circuit and the electrode pads 12 and the columnar electrode 16 to the silicon wafer 30. 図6(B)はシリコンウエハ30に樹脂層18やはんだボール20aを形成した工程を示す。 FIG 6 (B) shows the steps of forming the resin layer 18 and the solder balls 20a in the silicon wafer 30. 図6(C)ははんだボール20aを形成したシリコンウエハ30を個別の半導体装置10にダイシングする工程を示す図である。 FIG 6 (C) is a diagram illustrating a process of dicing the silicon wafer 30 formed with solder balls 20a into individual semiconductor device 10. 図6(D)は分離された半導体装置10を示す図である。 FIG 6 (D) are diagrams showing a semiconductor device 10 which is separated. 図6(A)〜図6(D)から分かるように、本発明による半導体装置10は、シリコンウエハ30の段階で封止用の樹脂層18を形成し、その後で1つの半導体チップを含むチップサイズパッケージ(CSP)として個別の半導体装置10を形成されたものである。 As it can be seen from FIG. 6 (A) ~ FIG 6 (D), chip semiconductor device 10 according to the present invention, to form a resin layer 18 for sealing in the stage of the silicon wafer 30, including thereafter one semiconductor chip and it is formed of individual semiconductor device 10 as size package (CSP). 従って、封止用の樹脂層18はスピンコートによって塗布されることができるものである。 Therefore, the resin layer 18 for sealing are those which can be applied by spin-coating.

図7は、樹脂層を形成し、それから外部端子に膨大部を形成する工程を含む半導体装置の製造方法の例を示す図である。 7, to form a resin layer, then a diagram showing an example of a method of manufacturing a semiconductor device including a step of forming a large part to the external terminal. 図7(A)において、ウエハ30に集積回路及び電極パッド12を形成し、図7(B)において、電極パッド12に接続された柱状電極16を形成する。 In FIG. 7 (A), to form an integrated circuit and the electrode pads 12 on the wafer 30, in FIG. 7 (B), the formed columnar electrode 16 connected to the electrode pads 12. 柱状電極16は図1から図3に示されるようにワイヤ部分16aと膨大部分16bとを含む。 Columnar electrode 16 includes a large portion 16b and the wire part 16a as shown in FIGS. 1-3. 図7(C)において、第1の樹脂層18aを形成し、図7(D)において、第2の樹脂層18bを形成する。 In FIG. 7 (C), the first resin layer 18a is formed, in FIG. 7 (D), the forming the second resin layer 18b. 図7(E)において、第2の樹脂層18bを研磨加工し、第2の樹脂層18bから突出する柱状電極16の先端部分を切断する。 In FIG. 7 (E), the second resin layer 18b is polished to cut the tip portions of the columnar electrodes 16 protruding from the second resin layer 18b. このとき、柱状電極16の膨大部分16bの先端のみを切断する。 At this time, cutting only the tip of the massive portion 16b of the columnar electrode 16. それから、図7(E)において、柱状電極16の膨大部分16bの先端に外部端子20を形成する。 Then, in FIG. 7 (E), to form the external terminal 20 to the tip of the massive portion 16b of the columnar electrode 16. それから、図6(B)に示されるようにはんだボール20aを形成し、図6(C)に示されるようにしてウエハ30を個々の半導体装置10に切断する。 Then, to form a solder ball 20a as shown in FIG. 6 (B), as shown in FIG. 6 (C) cutting the wafer 30 into individual semiconductor devices 10.

図8は膨大部分を有する柱状電極の形成方法の例を示す図である。 Figure 8 is a diagram showing an example of a method of forming columnar electrodes having a large portion. この例では、柱状電極16をワイヤボンダーを用いてボンディングワイヤ36によって形成する。 In this example, the columnar electrode 16 is formed by a bonding wire 36 using the wire bonder. ワイヤボンダーは市販のものを利用することができる。 Wire bonder can be used commercially. 図8(A)において、ワイヤボンダーのキャピラリ32をウエハ30の電極パッド12に向かって下降させる。 In FIG. 8 (A), the lowering towards the capillary 32 of the wire bonder to the electrode pads 12 of the wafer 30. キャピラリ32の先端にはワイヤ材料の小塊34が形成されている。 The tip end of the capillary 32 nodules 34 are formed of a wire material. 図8(B)において、キャピラリ32をウエハ30に向かってさらに下降させ、キャピラリ32の先端のワイヤ材料の小塊34をウエハ30に接触させる。 In FIG. 8 (B), the is further lowered toward the capillary 32 to the wafer 30, contacting the nodules 34 of the wire material of the tip of the capillary 32 to the wafer 30.

図8(C)において、キャピラリ32をウエハ30から引き上げ、ボンディングワイヤ36を形成する。 In FIG. 8 (C), the pulling up the capillary 32 from the wafer 30, to form a bonding wire 36. 通常のワイヤボンディングにおいては、キャピラリ32がさらに別の電極パッドへ下降され、そこに接触せしめられる。 In a typical wire bonding capillary 32 is further lowered to another electrode pad, it is contacted thereto. 本発明においては、キャピラリ32はウエハ30に対してほぼ垂直にほぼ一定の断面積でまっすぐ引き上げられる。 In the present invention, the capillary 32 is straight up at a substantially constant cross-sectional area substantially perpendicular to the wafer 30. 例えば金のワイヤであれば、直径30〜50μmで、高さ500μm程度まで引き上げることができる。 For example, if the gold wire may be pulled up at a diameter of 30 to 50 [mu] m, to a height 500μm approximately.

それから、図8(D)において、電気スパーク発生装置38でボンディングワイヤ36に電気スパークを印加すると、ボンディングワイヤ36の一部が小塊状に丸くなる。 Rounded Then, in FIG. 8 (D), the voltage is applied to the electrolyte spark bonding wires 36 in the electric spark generator 38, a portion of the bonding wire 36 is a small lump. このとき、電気スパークのエネルギーは、ボンディングワイヤ36が切断されない程度となるように設定する。 At this time, electric spark energy is set to be the extent to which the bonding wire 36 is not disconnected. それから、図8(E)において、ボンディングワイヤ36の先端部の小塊が適当な大きさ(例えば、ボンディングワイヤ36の直径の2〜3倍)になるまで、さらに電気スパークを続けて印加し、最後に、ボンディングワイヤ36が切断される程度のエネルギーで電気スパークを印加する。 Then, in FIG. 8 (E), nodules suitable size of the tip of the bonding wire 36 (e.g., 2 to 3 times the diameter of the bonding wire 36) until, by applying further continuing the electric spark, Finally, apply electrical spark energy to the extent that the bonding wire 36 is cut. こうして、図8(F)において、ボンディングワイヤ36は切断され、キャピラリ32を次のポイントへ移動させる。 Thus, in FIG. 8 (F), the bonding wire 36 is cut, moving the capillary 32 to the next point.

図9はこうして形成された、ワイヤ部分16aと膨大部分16bとを有する柱状部分16を示す。 Figure 9 is thus formed shows a columnar portion 16 having a wire portion 16a and the large portions 16b. なお、膨大部分16bに接続される外部端子20の大きさは膨大部分16bの大きさ〜パンプピッチ×0.5程度にする。 The size of the external terminals 20 connected to the large portion 16b is approximately the size-bump pitch × 0.5 a huge portion 16b.
図10は膨大部分を有する柱状電極の形成方法の他の例を示す図である。 Figure 10 is a diagram showing another example of a method of forming columnar electrodes having a large portion. この例でも、柱状電極16をワイヤボンダーを用いてボンディングワイヤによって形成する。 In this example, the columnar electrode 16 using a wire bonder is formed by a bonding wire. 図8の例と同様に、図9において、ワイヤボンダーのキャピラリ32をウエハ30の電極パッド12から上方へ持ち上げ、ボンディングワイヤ36を形成する。 As in the example of FIG. 8, 9, lifting the capillary 32 of the wire bonder from the electrode pad 12 of the wafer 30 upward to form a bonding wire 36. それから、電気スパーク発生装置38でボンディングワイヤ36に電気スパークを印加する。 Then, applying an electric spark to the bonding wires 36 in the electric spark generator 38. このとき、電気スパークのエネルギーは、ボンディングワイヤ36の一部が小塊状に丸くなり、かつ、ボンディングワイヤ36が丸くなった小塊において切断される程度となるように設定する。 At this time, electric spark energy, part of the bonding wire 36 is rounded into small lumps and, set such that the degree to be cut in the nodules bonding wire 36 is rounded. こうして、ワイヤ部分16aと膨大部分16bとを有する柱状部分16が形成される。 Thus, the columnar portion 16 and a wire portion 16a and the large portions 16b are formed.

図11は、柱状電極16の形成方法の他の例を示す図である。 Figure 11 is a diagram showing another example of a method of forming the columnar electrodes 16. この例では、ワイヤボンダーによってボンディングワイヤ36を形成し、ボンディングワイヤ36の表面にメッキ層40を形成する。 In this example, to form a bonding wire 36 by a wire bonder, to form a plating layer 40 on the surface of the bonding wire 36. 例えば、ボンディングワイヤ36は銅であり、50〜100μmmの直径を有する。 For example, the bonding wire 36 is copper, has a diameter of 50~100Myumm. メッキ層40ははんだのメッキ層であり、その直径はボンディングワイヤ36の直径1.5〜2倍とする。 Plating layer 40 is plated layer of solder, its diameter is 1.5 to 2 times the diameter of the bonding wire 36. 膨大部分16bに接続される外部端子20の大きさは膨大部分16bの大きさ〜パンプピッチ×0.5程度にする。 The magnitude of the external terminals 20 connected to the large portion 16b is approximately the size-bump pitch × 0.5 a huge portion 16b.

この例では、ボンディングワイヤ36は、半導体素子14の電極パッド12から延びるワイヤ部分16aとなり、メッキ層40は、外部端子20から延び且つワイヤ部分16aよりも大きい断面積を有する膨大部分16bとなる。 In this example, the bonding wire 36, a wire portion 16a, and the plating layer 40 extending from the electrode pads 12 of the semiconductor device 14 becomes enormous portion 16b having a larger cross-sectional area than and wire portion 16a extends from the external terminal 20. この例では、柱状電極16の形成は樹脂層18の形成前に実施され、その後で柱状電極16は樹脂層18によって覆われる。 In this example, formation of the columnar electrode 16 is carried out before the formation of the resin layer 18, the columnar electrode 16 then is covered by the resin layer 18.

図12は、柱状電極16の形成方法の他の例を示す図である。 Figure 12 is a diagram showing another example of a method of forming the columnar electrodes 16. 図11の例と同様に、この例でも、ワイヤボンダーによってボンディングワイヤ36を形成し、ボンディングワイヤ36の表面にメッキ層40を形成する。 As in the example of FIG. 11, in this example, to form a bonding wire 36 by a wire bonder, to form a plating layer 40 on the surface of the bonding wire 36. ボンディングワイヤ36は、半導体素子14の電極パッド12から延びるワイヤ部分16aとなり、メッキ層40は、外部端子20から延び且つワイヤ部分16aよりも大きい断面積を有する膨大部分16bとなる。 Bonding wires 36, the wire portion 16a, and the plating layer 40 extending from the electrode pads 12 of the semiconductor device 14 becomes enormous portion 16b having a larger cross-sectional area than and wire portion 16a extends from the external terminal 20. この例では、ボンディングワイヤ36の形成は第1の樹脂層18aの形成前に実施され、その後でボンディングワイヤ36は第1の樹脂層18aによって覆われる。 In this example, formation of the bonding wire 36 is carried out before the formation of the first resin layer 18a, a bonding wire 36 then is covered with the first resin layer 18a. メッキ層40は第1の樹脂層18aによって覆われていないボンディングワイヤ36の部分に被覆され、その後で第2の樹脂層18bによって覆われる。 Plated layer 40 is coated on a portion of the bonding wire 36 that is not covered by the first resin layer 18a, it is then covered by the second resin layer 18b.

図13は、柱状電極16の形成方法の他の例を示す図である。 Figure 13 is a diagram showing another example of a method of forming the columnar electrodes 16. 図11の例と同様に、この例でも、ワイヤボンダーによってボンディングワイヤ36を形成し、ボンディングワイヤ36の表面にメッキ層40を形成する。 As in the example of FIG. 11, in this example, to form a bonding wire 36 by a wire bonder, to form a plating layer 40 on the surface of the bonding wire 36. ボンディングワイヤ36は、半導体素子14の電極パッド12から延びるワイヤ部分16aとなり、メッキ層40は、外部端子20から延び且つワイヤ部分16aよりも大きい断面積を有する膨大部分16bとなる。 Bonding wires 36, the wire portion 16a, and the plating layer 40 extending from the electrode pads 12 of the semiconductor device 14 becomes enormous portion 16b having a larger cross-sectional area than and wire portion 16a extends from the external terminal 20. この例では、樹脂層18は第1〜第3の樹脂層18a、18b、18cを含む。 In this example, the resin layer 18 includes first to third resin layers 18a, 18b, a 18c. ボンディングワイヤ36の形成は第1の樹脂層18aの形成前に実施され、その後でボンディングワイヤ36は第1及び第3の樹脂層18a、18cによって覆われる。 Formation of the bonding wire 36 is carried out before the formation of the first resin layer 18a, a bonding wire 36 then is covered by the first and third resin layers 18a, 18c. メッキ層40は第1及び第3の樹脂層18a、18cによって覆われていないボンディングワイヤ36の部分に被覆され、その後で第2の樹脂層18bによって覆われる。 Plated layer 40 is coated on a portion of the bonding wire 36 that is not covered by the first and third resin layers 18a, 18c, it is then covered by the second resin layer 18b.

図14は、本発明の第2実施例による半導体装置を示す部分断面図である。 Figure 14 is a partial sectional view showing a semiconductor device according to a second embodiment of the present invention. 半導体装置10は、複数の電極パッド12を有する半導体素子14と、複数の電極パッド12に接続された複数の柱状電極16と、半導体素子14及び柱状電極16を覆う樹脂層18と、柱状電極16に電気的に接続されるように樹脂層18の表面に配置された外部端子としてのはんだボール20aと、半導体素子14の電極パッド12と柱状電極16との間に設けられる再配線導体部分50とを備える。 The semiconductor device 10 includes a semiconductor element 14 having a plurality of electrode pads 12, a plurality of columnar electrodes 16 connected to the plurality of electrode pads 12, a resin layer 18 covering the semiconductor element 14 and the columnar electrode 16, columnar electrodes 16 and the solder balls 20a as external terminals arranged on the surface of the resin layer 18 so as to be electrically connected to a rewiring conductor portions 50 provided between the electrode pads 12 and the columnar electrode 16 of the semiconductor element 14 equipped with a.

絶縁層52が半導体素子14の表面に形成され、電極パッド12は絶縁層52の開口部から露出している。 Insulating layer 52 is formed on the surface of the semiconductor element 14, the electrode pad 12 is exposed from the opening of the insulating layer 52. 再配線導体部分50は電極パッド12と一対一で対応する電極パッド部分を含む。 Rewiring conductor portion 50 includes an electrode pad portions corresponding one-to-one with the electrode pad 12. 再配線導体部分50の電極パッド部分は半導体素子14の電極パッド12と電気的に接続され、柱状電極16はその電極パッド部分に固定、接続される。 Electrode pad portion of the re-wiring conductor portion 50 is the electrode pad 12 electrically connected to the semiconductor element 14, the columnar electrode 16 is fixed to the electrode pad portion are connected. 電極パッド12は半導体素子14上の制限された位置に形成されるのに対して、再配線導体部分50の電極パッド部分は所望のパターンで形成されることができる。 Whereas the electrode pads 12 are formed on the restricted position of the semiconductor element 14, the electrode pad portion of the re-wiring conductor portion 50 can be formed in a desired pattern. 従って、再配線導体部分50の電極パッド部分は比較的に一様に配置される。 Accordingly, the electrode pad portion of the re-wiring conductor portion 50 are uniformly arranged relatively. 従って、樹脂層18にかかる力を特定の柱状電極16と外部端子としてのはんだボール20aの接合部に分散することができる。 Therefore, it is possible to disperse the force applied to the resin layer 18 at the junction of the solder balls 20a as a specific columnar electrodes 16 and the external terminal.

この実施例でははんだボール20aが外部端子として示されているが、前の実施例と同様に樹脂層18の表面に電極パッドを形成し、その電極パッドを外部端子20とすることができることは言うまでもない。 While this embodiment is illustrated solder balls 20a is an external terminal, the previous embodiment and forms an electrode pad on the surface of the resin layer 18 in the same manner, it can be the electrode pad and the external terminal 20 is needless to say There.
樹脂層18はスピンコートされた比較的に軟らかい樹脂からなる。 The resin layer 18 is made of relatively soft resin is spin-coated. 逆に言えば、樹脂層18はスピンコートが可能なほどに軟らかいシリコン樹脂又は低弾性のエポキシ樹脂からなる。 Conversely, the resin layer 18 is made of soft silicon resin or a low elasticity epoxy resin enough capable of spin coating. そして、柱状電極16は主としてボンディングワイヤで形成されている。 Then, the columnar electrode 16 is formed mainly bonding wire.

従来の柱状電極はメッキの堆積層として形成されており、大きな厚さにすることが難しいばかりでなく、かなり硬いものであった。 Conventional columnar electrodes are formed as a deposited layer of the plating, it is not only difficult to a large thickness, it was quite stiff. そして、従来の封止樹脂層は高弾性の硬いエポキシ樹脂で構成されていた。 Then, the conventional sealing resin layer was composed of a hard epoxy resin having high elasticity. そのため、硬い柱状電極が硬い封止樹脂層に埋め込まれ、封止樹脂の表面に対向する回路基板が熱ストレスによって封止樹脂に対して動くとき、外部端子が力を受け、その力が柱状電極に伝達されるが、柱状電極は動きにくいために外部端子と柱状電極との接合部が損傷しやすかった。 Therefore, hard columnar electrode is embedded in a hard encapsulating resin layer, when the circuit substrate facing the surface of the sealing resin is moved relative to the sealing resin by thermal stress, subjected to a force external terminals, the force is columnar electrode is transmitted to the junction between the external terminal and the column electrode is likely to damage to columnar electrode hard to move.

本発明においては、ボンディングワイヤで形成されている柱状電極16自身がフレキシビリティがあり、且つ柱状電極16を取り囲んでいる封止樹脂層18も軟らかくてフレキシビリティがあるので、封止樹脂層18の表面に対向する回路基板が熱ストレスによって封止樹脂層18に対して動くとき、はんだボール20aが力を受け、その力が柱状電極16に伝達されるが、柱状電極16ははんだボール20aの動きに追従して柔軟に動き、はんだボール20aと柱状電極16との接合部が損傷しにくい。 In the present invention, the columnar electrodes 16 themselves are formed of bonding wires may flexibility, and since the sealing resin layer 18 surrounding the columnar electrodes 16 is also soft is flexibility, the encapsulating resin layer 18 when the circuit board facing the surface to be moved relative to the sealing resin layer 18 by thermal stress, but the solder balls 20a receives a force, the force is transmitted to the columnar electrode 16, the columnar electrode 16 is the movement of the solder balls 20a motion flexibly following the junction between the solder balls 20a and the columnar electrode 16 is not easily damaged.

図15は図14の半導体装置の変形例を示す図である。 Figure 15 is a diagram showing a modified example of the semiconductor device in FIG 14. この例では、ボンディングワイヤで形成されている柱状電極16が全体的に膨大化されている。 In this example, the columnar electrodes 16 are formed of a bonding wire is generally thickened. この例は、ボンディングワイヤが細すぎる場合に、太い柱状電極16を得るのに有効である。 In this example, when the bonding wire is too thin, it is effective to obtain a thick columnar electrode 16.
図16は図14の半導体装置の変形例を示す図である。 Figure 16 is a diagram showing a modified example of the semiconductor device in FIG 14. この例では、柱状電極16を構成するボンディングワイヤの端部が、再配線導体部分50に接合され、それから途中で曲がって再び再配線導体部分50に接合され、それから樹脂層18の表面に向かって延びている。 In this example, the ends of the bonding wires that comprise columnar electrode 16 is joined to the re-wiring conductor portion 50 is joined to the re-wiring conductor portion 50 again and then bent in the middle, then toward the surface of the resin layer 18 It extends. この例は、よりフレキシビリティのある柱状電極16を得るのに有効であり、また、再配線導体部分50が断線している場合でも柱状電極16がその断線を補償することができることがある。 This example is effective to obtain a columnar electrode 16 a more flexibility, also the columnar electrode 16 even if the re-wiring conductor portion 50 is broken is to be able to compensate for the disconnection.

図17(A)は図14の半導体装置の変形例を示す図である。 Figure 17 (A) is a diagram showing a modified example of the semiconductor device in FIG 14. この例では、複数のボンディングワイヤを1つの柱状電極16の形体に接合してなる。 In this example, formed by joining a plurality of bonding wires to form a single column electrode 16. この例は、柱状電極16の強度を増大するとともに、フレキシビリティのある柱状電極16を得るのに有効である。 This example serves to increase the strength of the columnar electrode 16, it is effective to obtain a columnar electrode 16 with flexibility. 図17(B)から図17(D)は図17(A)の柱状電極16の製造工程を示する。 View the manufacturing process of the columnar electrodes 16 of FIG. 17 from FIG. 17 (B) (D) is 17 (A). 図17(B)において、2つのボンディングワイヤ36a、36bが1つの柱状電極16のために形成され、図17(C)において、2つのボンディングワイヤ36a、36bの先端に電気トーチ38aが適用され、よって、図17(D)において、2つのボンディングワイヤ36a、36bの先端が接合される。 In FIG. 17 (B), 2 two bonding wires 36a, 36b are formed for one of the columnar electrodes 16, in FIG. 17 (C), 2 two bonding wires 36a, electric torch 38a is applied to the tip of 36b, Therefore, in FIG. 17 (D), 2 single bonding wire 36a, the tip of 36b are joined. また、電気トーチ38aの上下動作制御により、多数の柱状電極16の高さを平均化することもできる。 Further, the vertical movement control of the electric torch 38a, the height of the large number of columnar electrodes 16 may be averaged.

図18は図14の半導体装置の変形例を示す図である。 Figure 18 is a diagram showing a modified example of the semiconductor device in FIG 14. この例では、樹脂層18内に柱状電極16とほぼ平行に配置されたダミー電極54をさらに含む。 In this example, further comprises a dummy electrode 54 disposed substantially parallel to the cylindrical electrode 16 in the resin layer 18. 柱状電極16及びダミー電極54は再配線導体部分50に接合される。 Columnar electrodes 16 and the dummy electrode 54 is joined to the re-wiring conductor portion 50. 柱状電極16の先端がはんだボール20aに接合されるのに対して、ダミー電極54の先端ははんだボール20aに接合されない。 Whereas the tip of the columnar electrode 16 is joined to the ball 20a solder, the tip of the dummy electrodes 54 are not bonded to the solder balls 20a. 従って、ダミー電極54は電気的には働かないが、樹脂層18を形成する際に、樹脂の流れに起因する力が柱状電極16に集中的にかかるのを防止する。 Accordingly, the dummy electrode 54 is not work in electrical, when forming the resin layer 18, the force caused by the flow of resin is prevented from such intensive columnar electrode 16.

図19は図18の半導体装置の変形例を示す図である。 Figure 19 is a diagram showing a modified example of the semiconductor device in FIG 18. この例では、樹脂層18内に柱状電極16とほぼ平行に配置されたダミー電極54aをさらに含む。 In this example, further comprises a dummy electrode 54a which is substantially parallel to the columnar electrode 16 in the resin layer 18. このダミー電極54aは例えばシリコン樹脂や低弾性の樹脂等の樹脂で作られている。 The dummy electrode 54a is made of resin such as for example silicone resin or the low elastic resin. ダミー電極54aは、樹脂層18を形成する際に、樹脂の流れに起因する力が柱状電極16に集中的にかかるのを防止し、さらに、樹脂の流れを均等化して樹脂層18の表面が平坦になるのを助ける。 The dummy electrode 54a, when forming the resin layer 18, to prevent the force caused by the flow of resin that according to intensive columnar electrode 16, furthermore, by equalizing the flow of the resin surface of the resin layer 18 It helps to become flat.

図20は本発明の第3実施例による半導体装置を示す部分断面図である。 Figure 20 is a partial sectional view showing a semiconductor device according to a third embodiment of the present invention. 半導体装置10は、複数の電極パッド12を有する半導体素子14と、複数の電極パッド12に接続された複数の柱状電極16と、半導体素子14及び柱状電極16を覆う樹脂層18と、柱状電極16と接続して樹脂層18の表面に設けられる再配線導体部分60と、樹脂層18及び再配線導体部分60の一部を覆う絶縁層62と、再配線導体部分60の絶縁層62から露出された部分に電気的に接続される外部端子としてのはんだボール20aとを備えている。 The semiconductor device 10 includes a semiconductor element 14 having a plurality of electrode pads 12, a plurality of columnar electrodes 16 connected to the plurality of electrode pads 12, a resin layer 18 covering the semiconductor element 14 and the columnar electrode 16, columnar electrodes 16 connected with the redistribution conductor portions 60 provided on the surface of the resin layer 18, an insulating layer 62 covering a part of the resin layer 18 and the redistribution conductor portions 60 are exposed from the insulating layer 62 of the re-wiring conductor portion 60 and and a solder ball 20a as external terminals electrically connected to the portion. この場合にも、はんだボール20aが外部端子として示されているが、前の実施例と同様に樹脂層18の表面に形成された電極パッドを形成し、その電極パッドを外部端子20とすることができることは言うまでもない。 In this case, the solder ball 20a is shown as an external terminal, the previous examples and to form an electrode pad formed on the surface of the resin layer 18 similarly to the electrode pads and the external terminals 20 that it is needless to say that it is.

つまり、この半導体装置10では、半導体素子14の電極パッド12上に柱状電極16が形成され、半導体素子14及び柱状電極16が樹脂層18によって封止された後、再配線導体部分60のパターニングを行い、その後で絶縁層62が形成される。 That is, in the semiconductor device 10, the columnar electrode 16 is formed on the electrode pads 12 of the semiconductor device 14, after the semiconductor element 14 and the columnar electrode 16 is sealed by the resin layer 18, the patterning of the rewiring conductor portions 60 performed, the insulating layer 62 is formed thereafter. 外部端子としてのはんだボール20aは再配線導体部分60と接続されることになる。 Solder balls 20a as external terminals to be connected with the re-wiring conductor portion 60. 再配線導体部分60は樹脂層18に覆われていないのでフレキシビリティがあり、再配線導体部分60と外部端子としてのはんだボール20aとの接合部にかかる応力を分散することができる。 Rewiring conductor portion 60 has flexibility because it is not covered with the resin layer 18, the stress applied to the joint between the solder balls 20a as rewiring conductor portions 60 and the external terminal can be dispersed.

図21(A)は図20の半導体装置の変形例を示す図である。 Figure 21 (A) is a diagram showing a modified example of the semiconductor device in FIG 20. 半導体装置10は、複数の電極パッド12を有する半導体素子14と、半導体素子14の一部を覆う絶縁層64と、絶縁層64から露出された電極パッド12と接続して絶縁層64の表面に設けられる再配線導体部分60と、絶縁層64及び再配線導体部分60の一部を覆う絶縁層62と、再配線導体部分60の絶縁層62から露出された部分に電気的に接続される外部端子としてのはんだボール20aとを備えている。 The semiconductor device 10 includes a semiconductor element 14 having a plurality of electrode pads 12, and the insulating layer 64 covering a part of the semiconductor element 14, connected to the electrode pads 12 exposed from the insulating layer 64 on the surface of the insulating layer 64 a rewiring conductor portions 60 provided, an insulating layer 62 covering a part of the insulating layer 64 and the redistribution conductor portions 60, the outside to be electrically connected to the exposed portions of insulating layer 62 of the re-wiring conductor portion 60 and a solder ball 20a as a terminal. 柱状電極16は、電極パッド12と再配線導体部分60との接合部材66である。 Columnar electrode 16 is a joint member 66 of the re-wiring conductor portion 60 and the electrode pads 12.

つまり、この半導体装置10では、半導体素子14上に絶縁層64が形成され、絶縁層64の電極パッド12上の部分は開口される。 That is, in the semiconductor device 10, the insulating layer 64 is formed on the semiconductor element 14, portion on the electrode pads 12 of the insulating layer 64 is opened. それから、絶縁層64の上に再配線導体部分60のパターニングを行い、その後で絶縁層62が形成される。 Then, patterning is performed for re-wiring conductor portion 60 on the insulating layer 64, insulating layer 62 is formed thereafter. 外部端子としてのはんだボール20aは再配線導体部分60と接続されることになる。 Solder balls 20a as external terminals to be connected with the re-wiring conductor portion 60. 再配線導体部分60は樹脂層18に覆われていないのでフレキシビリティがあり、再配線導体部分60と外部端子としてのはんだボール20aとの接合部にかかる応力を分散することができる。 Rewiring conductor portion 60 has flexibility because it is not covered with the resin layer 18, the stress applied to the joint between the solder balls 20a as rewiring conductor portions 60 and the external terminal can be dispersed.

図21(B)は電極パッド12と再配線導体部分60との合金層66の形成の例を示す図である。 Figure 21 (B) is a diagram showing an example of formation of an alloy layer 66 of the re-wiring conductor portion 60 and the electrode pads 12. 合金層66はアルミニウムと金の共晶合金からなる。 Alloy layer 66 is made of aluminum and gold eutectic alloy. 表層がアルミニウムの電極パッド12に銅に金メッキした再配線導体部分60を、ボンディングツール68で超音波熱圧着するとアルミニウムと金の共晶合金ができ、合金層66なる。 Rewiring conductor portions 60 surface layer which plated with gold copper electrode pads 12 of aluminum, the ultrasonic thermocompression bonding tool 68 can of aluminum and gold eutectic alloy, comprising an alloy layer 66.

図21(C)、(D)は電極パッド12と再配線導体部分60との接合部材66の形成の例を示す図である。 FIG. 21 (C), the diagram showing an example of the formation of the bonding member 66 (D) and re-wiring conductor portion 60 and the electrode pads 12. 図21(C)は半導体装置10の断面図、図21(D)は絶縁層64の略平面図である。 Figure 21 (C) is a sectional view of the semiconductor device 10, FIG. 21 (D) is a schematic plan view of an insulating layer 64. 絶縁層64の電極パッド12上の部分は開口され、その開口部には電極パッド12上にメッキ66aがなされている。 Portion on the electrode pads 12 of the insulating layer 64 is opened, the plating 66a have been made on the electrode pad 12 in the opening. このメッキ66aが接合部材66となる。 The plating 66a is bonded member 66. メッキを堆積させるために、電極パッド12上の部分がメッキ浴槽に晒されるように絶縁材をデザインしている。 To deposit the plating portion on the electrode pad 12 is designed insulating material to be exposed to the plating bath.

図22は図14から図20の半導体装置の柱状電極の露出方法を示す図である。 Figure 22 is a diagram showing a method of exposing the columnar electrodes of the semiconductor device of FIG. 20 from FIG. 14. 複数の電極パッド12を有する半導体素子14と、複数の電極パッド12に接続された複数の柱状電極16と、半導体素子14及び柱状電極16を覆う樹脂層18とを備えた半導体装置10においては、樹脂層18をコーティングした直後の状態において、樹脂層18の表面と柱状電極16の先端との関係は、次の2つがある。 A semiconductor element 14 having a plurality of electrode pads 12, a plurality of columnar electrodes 16 connected to the plurality of electrode pads 12, the semiconductor device 10 that includes a resin layer 18 covering the semiconductor element 14 and the columnar electrode 16, in the state immediately after coating the resin layer 18, the relationship between the tip surface and the columnar electrode 16 of the resin layer 18 is next There are two. (a)柱状電極16の先端が樹脂層18の表面よりも突出している(図7)。 (A) the tip of the columnar electrode 16 is protruded from the surface of the resin layer 18 (FIG. 7). (b)柱状電極16の先端が樹脂層18の表面とほぼ同じになる。 (B) the tip of the columnar electrodes 16 is substantially the same as the surface of the resin layer 18. これから説明する例は(b)の場合についてのものである。 Examples to be described are for the case of (b).

図22(A)は樹脂層18をコーティングした直後の状態を示し、柱状電極16の先端が樹脂層18の表面とほぼ同じになる。 Figure 22 (A) shows a state immediately after coating the resin layer 18, the tip of the columnar electrodes 16 is substantially the same as the surface of the resin layer 18. この場合、柱状電極16の先端は樹脂層18の材料の膜が付着しているので、図22(B)に示すように、柱状電極16の先端を外部電極20と電気的に接続するためには、柱状電極16の先端の樹脂層18の材料の膜を除去しなければならない。 In this case, since the distal end of the columnar electrode 16 is deposited film of the material of the resin layer 18, as shown in FIG. 22 (B), to connect the distal end of the columnar electrode 16 and the electrically the external electrodes 20 We shall remove the film of the material of the tip of the resin layer 18 of the columnar electrode 16. この場合、樹脂層18の表面全体を除去する必要はなく、樹脂層18の表面のうちで柱状電極16の先端が位置する部分のみを除去すればよい。 In this case, it is not necessary to remove the entire surface of the resin layer 18 may be only removed portions the tip of the columnar electrodes 16 are positioned within the surface of the resin layer 18.

図23は図22の柱状電極の露出方法の一例を示す図である。 Figure 23 is a diagram showing an example of a method of exposing the columnar electrodes of Figure 22. 樹脂層18をコーティングしたウエハ30を持ってきて、ドリルやヤスリ等の工具70を使用して、樹脂層18の表面を、全ての柱状電極16の位置を順番になぞる。 Bring wafer 30 coated with a resin layer 18, using the tool 70 of the drill or rasp like, the surface of the resin layer 18, tracing the location of all of the columnar electrodes 16 in order. すると、柱状電極16の先端の樹脂層18の材料の膜が露出され、柱状電極16の先端が露出される。 Then, the film of the material of the tip of the resin layer 18 of the columnar electrode 16 is exposed, the tip of the columnar electrodes 16 are exposed. 従って、その後で、柱状電極16の先端に外部電極である電極パッド20を形成したり、はんだボール20aを形成したりすることができる。 Accordingly, then, or to form an electrode pad 20 is an external electrode to the tip of the columnar electrodes 16, or can form the solder balls 20a. この方法によれば、樹脂層18の表面全体をグラインダ等で研削する場合と比べて、ウエハ30に大きな力がかからないため、ウエハ30が損傷しない。 According to this method, the entire surface of the resin layer 18 as compared with the case of grinding by a grinder or the like, since a large force to the wafer 30 is not applied, the wafer 30 is not damaged.

図24は図22の柱状電極の露出方法の一例を示す図である。 Figure 24 is a diagram showing an example of a method of exposing the columnar electrodes of Figure 22. 図24(A)は平面図、図24(B)は側面図である。 Figure 24 (A) is a plan view, FIG. 24 (B) is a side view. この例では、紙ヤスリや金属等の無端状の帯部材72が使用される。 In this example, an endless belt member 72 of the sandpaper or a metal or the like is used. 帯部材72は図24(B)の矢印に沿って回転する。 Belt member 72 is rotated along the arrow in FIG. 24 (B). この例では、帯部材72は2つのローラ73に巻きかけられている。 In this example, the band member 72 is wound around two rollers 73. 金属の帯部材72がリール巻き取り式またはリール一連式になっているようにすることもできる。 Belt member 72 of the metal can also be so has the reel Retractable or reel series expressions. 帯部材72の上方走行部分はウエハ30の上面に接触するように配置され、帯部材72の下方走行部分はウエハの下面の下方に配置される。 Upper running portion of the belt member 72 is arranged to be in contact with the upper surface of the wafer 30, the lower running portion of the belt member 72 is disposed below the lower surface of the wafer. こうすることによって、樹脂層18の表面の柱状電極16のある部分のみを除去し、柱状電極16の先端が露出されるようにする。 By doing so, only to remove portions of the columnar electrodes 16 of the surface of the resin layer 18, so that the tip of the columnar electrodes 16 are exposed. 従って、この場合にも、樹脂層18の表面全体をグラインダ等で研削する場合と比べて、ウエハ30に大きな力がかからないため、ウエハ30が損傷しない。 Therefore, also in this case, the entire surface of the resin layer 18 as compared with the case of grinding by a grinder or the like, since a large force to the wafer 30 is not applied, the wafer 30 is not damaged.

図25は図24の柱状電極の露出方法の変形例を示す図である。 Figure 25 is a diagram showing a modification of the method of exposing the columnar electrodes of Figure 24. この例では、帯部材72が使用され、さらに、帯部材72を加熱可能なヒータ74が設けられる。 In this example, the band member 72 is used, further, a heater 74 capable of heating is provided a belt member 72. 帯部材72を温めることによって、樹脂層18の表面の除去を助ける。 By warming the belt member 72, aid in the removal of the surface of the resin layer 18.
図26は図24の柱状電極の露出方法の変形例を示す図である。 Figure 26 is a diagram showing a modification of the method of exposing the columnar electrodes of Figure 24. この例では、金の電極パッド12に対して、柱状電極16は金の部分16x及びはんだの部分16yを含む構成になっている。 In this example, with respect to the gold electrode pad 12, the columnar electrode 16 has a configuration including portions 16x and the solder portion 16y of gold. 銅の帯部材72及びヒータ74が使用される。 Belt member 72 and the heater 74 of copper is used.

銅の帯部材72を加熱しながら回転させると、樹脂層18の表面が除去され、且つ銅の帯部材72と柱状電極16のはんだの部分16yとが反応して、柱状電極16のはんだの部分16yが銅の帯部材72に吸着され、よって柱状電極16の先端が露出される。 Rotation while heating the belt member 72 of copper, is removed the surface of the resin layer 18, and a solder portion 16y of the belt member 72 and the columnar electrode 16 of the copper reacts, the solder portions of the columnar electrodes 16 16y is adsorbed by the belt member 72 of copper, thus leading end of the columnar electrode 16 is exposed. この場合、銅の帯部材72を粗くしたり、フラックスを塗布しておくと、はんだの部分16yをより吸着しやすくなる。 In this case, or to roughen the belt member 72 of copper and keep applying flux becomes easier to adsorb the solder portion 16y. また、柱状電極16にフラックスを塗った後、柱状電極16の先端に沿って銅の帯部材72を回転させ、さらにその上部よりはんだ融点より高い熱を加えることにより、銅の帯部材72に柱状電極16のはんだの部分16yを吸着させながら、電極上面を露出させることができる。 Further, after the coated flux in the columnar electrode 16, along the tip of the columnar electrodes 16 to rotate the belt member 72 of copper, further by applying heat above the solder melting point than the upper portion thereof, the columnar the band member 72 of copper while adsorbing the solder portion 16y of the electrode 16, it is possible to expose the electrode upper surface. また、柱状電極16のはんだの部分16yの次の部分を銅にすると、はんだの部分16yには一方において銅の吸着があり且つ他方において銅の吸着があるので、吸着にかかる応力が均等化される。 Further, when the next portion of the solder portion 16y of the columnar electrode 16 to the copper, since the solder portion 16y is adsorption of copper in and the other has the adsorption of copper on the one hand, the equalization stress on the adsorption that.

図27を参照して本発明の第4実施例によるピンワイヤを有する半導体装置の製造する方法について説明する。 Referring to FIG. 27 describes a method of manufacturing a semiconductor device having a pin wire according to a fourth embodiment of the present invention. ピンワイヤは前の実施例の柱状電極16と同様にボンディングワイヤで作られ、柱状電極16と同様に使用されることができる。 Pin wire is made of similarly bonding wire and the columnar electrode 16 of the previous embodiment, it can be used similarly to the columnar electrode 16. しかし、この実施例のピンワイヤは前の実施例の柱状電極16よりも種々の応用に使用されることができる。 However, the pin wire in this embodiment may be used in a variety of applications than the columnar electrode 16 of the previous embodiment.

図27(A)において、金属ワイヤ80をキャピラリ81に通す。 In FIG. 27 (A), through a metal wire 80 to the capillary 81. キャピラリ81は従来的な自動ワイヤボンダーのキャピラリである。 Capillary 81 is a capillary of conventional automatic wire bonder. 金属ワイヤ80はワイヤボンディングで使用される金属、例えば金のワイヤである。 Metal wires 80 are metals used in wire bonding, such as gold wire. キャピラリ81の下側に位置する金属ワイヤ80の下端部分はボール形状の膨大部80aとなっている。 The lower end portion of the metallic wire 80 located below the capillary 81 has a enlarged portion 80a of the ball-shaped. 膨大部80aは従来的なワイヤボンディングで形成されるのと同様にして例えば加熱や放電等で形成される。 Ampulla 80a are formed by in the same manner as are formed by conventional wire bonding for example heating or discharge.

図27(B)において、キャピラリ81を矢印に示されるように金属ワイヤ80に対して動かし、キャピラリ81の下端部と金属ワイヤ80の膨大部80aとの間に適切な間隔をあけさせ、金属ワイヤ80の所定の長さ部分を露出させる。 In FIG. 27 (B), move the metal wire 80 as shown a capillary 81 in an arrow, let appropriate intervals between the enlarged portion 80a of the lower portion and the metal wires 80 of the capillary 81, a metal wire exposing a predetermined length of the 80.
図27(C)において、ハーフカット用工具82は金属ワイヤ80及びキャピラリ81と関連して作動するように配置されている。 In FIG. 27 (C), the half-cutting tool 82 is arranged to operate in conjunction with the metal wires 80 and the capillary 81. 工具82を作動させ、金属ワイヤ80の所望の位置にハーフカット処理を行い、金属ワイヤ80に物理的な傷をつける。 The tool 82 is operated, perform the half-cut process in a desired position of the metal wires 80, put a physical wound to the metal wire 80. 実施例においては、工具82は金属ワイヤ80の両側に配置され、互いに近づき且つ離れるように作動される一対のブレードからなる。 In the embodiment, the tool 82 is disposed on both sides of the metal wire 80, a pair of blades that are actuated away and approach each other.

図28は、ハーフカット処理を行った金属ワイヤ80を示す。 Figure 28 shows a metal wire 80 subjected to half-cut process. 金属ワイヤ80にはハーフカット処理を行った位置にウエッジ状の窪み80bが形成される。 The metal wire 80 is wedge-shaped recesses 80b in a position subjected to the half-cut process are formed. 工具82の位置は金属ワイヤ80から所望の長さのピンワイヤが得られるように設定される。 Position of the tool 82 is set so that pin wire of desired length from a metal wire 80 is obtained. なお、ハーフカット処理を行う工具82は従来的な自動ワイヤボンダーにはなく、本発明を実施するために従来的な自動ワイヤボンダーに付加されたものである。 Incidentally, the tool 82 for performing half-cutting processing is not in the conventional automatic wire bonder, in which added to the conventional automatic wire bonder for carrying out the present invention.

図27(D)において、キャピラリ81を矢印に示されるように元の位置へ動かし、キャピラリ81の下端部を金属ワイヤ80の膨大部80aへ近づける。 In FIG. 27 (D), moves to the original position as shown the capillary 81 in the arrow, closer to the lower end of the capillary 81 to the enlarged portion 80a of the metallic wire 80. この状態は、従来的なワイヤボンディングのスタート位置に相当する。 This state corresponds to the start position of the conventional wire bonding. さらに、キャピラリ81及び金属ワイヤ80を所望の電子装置の電極部83へ向かって下降させ、キャピラリ81の下端部によって金属ワイヤ80の膨大部80aを電極部83に対して圧着させ、金属ワイヤ80の膨大部80aを電極部83に接合させる。 Furthermore, the capillary 81 and the metal wire 80 is lowered toward the electrode portion 83 of the desired electronic device, the enlarged portion 80a of the metal wire 80 is crimped to the electrode portion 83 by the lower end of the capillary 81, the metal wire 80 joining the enlarged portion 80a to the electrode portion 83. 熱圧着時に、従来のワイヤボンディングのように熱又は高周波振動を与えることができる。 At the time of thermocompression bonding, it is possible to provide heat or high frequency vibration as the conventional wire bonding.

図27(E)において、金属ワイヤ80の膨大部80aが電極部83に接合されたら、矢印で示されるようにキャピラリ81を上昇させる。 In FIG. 27 (E), the enlarged portion 80a of the metal wire 80 if it is bonded to the electrode portion 83 increases the capillary 81 as indicated by arrows. 金属ワイヤ80の膨大部80aは電極部83に接合されているので、金属ワイヤ80は動かず、キャピラリ81のみが上昇する。 Since the enlarged portion 80a of the metal wire 80 is bonded to the electrode portion 83, the metal wire 80 does not move, only the capillary 81 is raised.
図27(F)において、キャピラリ81がある距離上昇したら、キャピラリ81に設けられたクランパによってキャピラリ81をクランプし、キャピラリ81をさらに上昇させる。 In FIG. 27 (F), After the distance increases is capillary 81, the capillary 81 is clamped by the clamper provided in the capillary 81, further increases the capillary 81. すると、金属ワイヤ80は引っ張られ、ハーフカット処理を行った窪み80bの位置で確実に切断される。 Then, the metal wire 80 is pulled, is reliably cut at the position of the recess 80b was half-cut process. こうして、切断された金属ワイヤ80は端部80cを有するピンワイヤ84になる。 Thus, the cut metal wire 80 will pin wire 84 having an end portion 80c.

図29(A)はこのようにして形成されたピンワイヤ84を示している。 Figure 29 (A) shows the pin wire 84 formed in this way. 図29(B)はピンワイヤ84の一部を拡大して示す。 Figure 29 (B) is an enlarged view of a portion of the pin wire 84. 本発明では、ピンワイヤ84は金属ワイヤ80の窪み80bの位置で確実に切断され、得られたピンワイヤ84の長さのバラツキが少ない。 In the present invention, the pin wire 84 is reliably cut at the position of the recess 80b of the metal wire 80, the variation of the length of the resulting pin wire 84 is small. また、ハーフカット処理の影響で、ピンワイヤ84の先端がほぼ一定な、安定した突起形状となっている。 Further, the influence of the half-cut process, the tip of the pin wire 84 is substantially constant, and has a stable projection shape.

金属ワイヤ80にハーフカット処理が行われていない金属ワイヤ80の切断の場合には、切断位置が正確に特定されず、金属ワイヤ80の切断部分の形状が一定でなく、ピンワイヤの長さのバラツキが大きくなる。 In the case of cutting the metal wire 80 to the metal wire 80 the half-cutting operation is not performed, the cutting position is not accurately identified, not constant the shape of the cut portion of the metal wire 80, the variation of the length of the pin wire It increases. 本発明では、機械的なハーフカット処理を施した後で金属ワイヤ80を切断しているので、金属ワイヤ80はハーフカット処理の位置で確実に切断され、長さのバラツキも低減される。 In the present invention, since the cut metal wires 80 after subjected to mechanical half-cut processing, metal wire 80 is reliably cut at a position of the half-cut process is also reduced variation in length. また、ハーフカット処理の影響で、ピンワイヤ84の先端がほぼ一定な、中心部が小さく突起した突起形状となっている。 Further, the influence of the half-cut process, the tip of the pin wire 84 is substantially constant, the center portion has a smaller projection to projections shape. 先端がフラットな場合と比べ、導電材料との密着面積が広くなり、信頼性の向上が見込める。 Than when the tip is flat, it widens the adhesion area between the conductive material, expected improvement in reliability.

図30はピンワイヤ84を有する半導体素子を示す略図である。 Figure 30 is a schematic diagram showing a semiconductor device having a pin wire 84. 半導体素子85は半導体チップ又は半導体ウエハからなり、IC回路が形成されている。 The semiconductor device 85 consists of a semiconductor chip or a semiconductor wafer, IC circuits are formed. 半導体素子85の表面にはIC回路と接続された電極パッドが形成されている。 Electrode pads are formed which are connected to the IC circuit on the surface of the semiconductor element 85. 電極部83は半導体素子85の電極パッドである。 Electrode portion 83 is an electrode pad of the semiconductor element 85. ピンワイヤ84は円柱状のピン部80dを有し、ピン部80dの先端側の直径Φaとピン部80dの根元側の直径Φbとはほぼ等しい。 Pin wire 84 has a cylindrical pin portion 80d, substantially equal to the root side of the diameter Φb diameter Φa the pin portion 80d of the front end side of the pin portion 80d. ピンワイヤ84の膨大部80aはピン部80dの直径Φa、Φbよりも大きく、ピン部80dの長さtはピン部80dの直径Φa、Φbよりも大きい。 Pin wire vast portion 80a of 84 the pin portion 80d of the diameter .PHI.a, greater than .PHI.b, pin length t of 80d and the diameter of the pin portion 80d .PHI.a, greater than .PHI.b.

図31は種々のピンワイヤの例を示す図である。 Figure 31 is a diagram showing an example of a variety of pin wire. ピンワイヤ84Aはピン部80dの直径Φa、Φbが30μmの例である。 Pin wire 84A is the diameter of the pin portion 80d .PHI.a, .PHI.b are examples of 30 [mu] m. ピンワイヤ84Bはピン部80dの直径Φa、Φbが50μmの例である。 Pin wire 84B is the diameter of the pin portion 80d .PHI.a, .PHI.b are examples of 50 [mu] m. ピンワイヤ84Cはピン部80dの直径Φa、Φbが70μmの例である。 Pin wire 84C is the diameter of the pin portion 80d .PHI.a, .PHI.b are examples of 70 [mu] m. このように、金属ワイヤ80を選択することによって、所望の大きさ及び長さ、及び材質のピンワイヤ84Bを得ることができる。 Thus, by selecting the metal wire 80, it is possible to obtain desired size and length, and the material of the pin wire 84B.

ピンワイヤ84(84A、84B、84C)を得るための金属ワイヤ80の材質、ワイヤ径(ピン径)、ピン長さ、膨大部80aのサイズには実質的に制限がなく、さらに、フリップチップ用はんだボールやスタッドバンプを使用する場合と比べ、ピンワイヤ84(84A、84B、84C)を非常に低コストで形成することができる。 Pin wire 84 (84A, 84B, 84C) made of metal wires 80 for obtaining a wire diameter (pin diameter), the pin length, no substantial limit to the size of the enlarged portion 80a, further, the solder for flip chip compared with the case of using a ball or stud bumps can be formed with the pin wire 84 (84A, 84B, 84C) a very low cost. また、ピン部80dの長さを自由に変えることができることから、フィラー径との関係でフリップチップタイプでは使うことが困難とされていたトランスファーモールドによる一括封止も可能になる。 Further, since it is possible to vary the length of the pin portion 80d freely, collectively sealing also it allows by transfer molding has been difficult to use a flip-chip type in relation to the filler size.

図32(A)は図27から図30を参照して説明したピンワイヤ84を有する半導体素子85を示す図である。 Figure 32 (A) is a diagram showing a semiconductor device 85 having a pin wire 84 described with reference to FIG. 30 from FIG. 27. 図30では1つのピンワイヤ84のみが示されているが、図32(A)に示されるように、半導体素子85は通常多数の電極部(電極パッド)83を有し、ピンワイヤ84は各電極部83に接合される。 Although only Figure 30 In one pin wire 84 is shown, as shown in FIG. 32 (A), the semiconductor device 85 has the normal number of the electrode portion (electrode pad) 83, the pin wire 84 is the electrode sections It is joined to the 83. 多数のピンワイヤ84は全てほぼ一様な長さを有する。 Numerous pin wire 84 has a substantially uniform length all. ピンワイヤ84は半導体素子85の表面に対して垂直に、非常に狭いピッチで配置されることができる。 Pin wire 84 is perpendicular to the surface of the semiconductor element 85 can be arranged at very narrow pitches. ピンワイヤ84は外部端子となる。 Pin wire 84 serves as an external terminal.

図32(B)は図32(A)の半導体素子85に樹脂86で樹脂封止を行い、半導体パッケージとした例を示す。 Figure 32 (B) performs a resin sealing with resin 86 in the semiconductor device 85 of FIG. 32 (A), showing an example in which the semiconductor package. ピンワイヤ84は樹脂86の表面から突出して外部端子となる。 Pin wire 84 serves as an external terminal protrudes from the surface of the resin 86.
図33(A)は再配線技術により形成された再配線電極83Aにピンワイヤ84を接合した半導体素子85を示す図である。 Figure 33 (A) is a diagram showing a semiconductor device 85 formed by joining pin wire 84 to the re-wiring electrode 83A formed by the re-wiring technology. この場合にも、多数のピンワイヤ84は全てほぼ一様な長さを有し、外部端子となる。 In this case, a number of pin wire 84 has a substantially uniform length all, the external terminal.

図33(B)は図33(A)の半導体素子85に樹脂86で樹脂封止を行い、半導体パッケージとした例を示す。 Figure 33 (B) performs a resin sealing with resin 86 in the semiconductor device 85 of FIG. 33 (A), showing an example in which the semiconductor package. ピンワイヤ84は樹脂86の表面から突出して外部端子となる。 Pin wire 84 serves as an external terminal protrudes from the surface of the resin 86.
図34(A)から図34(C)は再配線電極83Aにピンワイヤ84を接合した半導体素子85の詳細を示す図である。 Figure 34 (A) 34 from (C) is a diagram showing details of the semiconductor device 85 formed by joining pin wire 84 to the re-wiring electrode 83A. 図34(A)において、半導体素子85はIC回路に直接に接続された電極パッド88Aを有し、絶縁層87が半導体素子85を覆って形成される。 In FIG. 34 (A), the semiconductor device 85 has electrode pads 88A, which are directly connected to the IC circuit, the insulating layer 87 is formed to cover the semiconductor element 85. 柱状電極88B及び導電膜88Cが絶縁層87を通って電極パッド88Aに接続され、再配線電極83Aは適切な配置パターンで導電膜88Cに接続される。 Columnar electrode 88B and the conductive film 88C is connected to the electrode pads 88A through the insulating layer 87, the rewiring electrode 83A is connected to the conductive film 88C in an appropriate arrangement pattern. 各再配線電極83Aは各電極パッド88Aに接続されているが、再配線電極83Aの位置は電極パッド88Aの位置とは異なっている。 Each rewiring electrodes 83A are connected to the respective electrode pads 88A, the position of the re-wiring electrode 83A is different from the position of the electrode pad 88A.

図34(B)において、ピンワイヤ84が再配線電極83Aに接合される。 In FIG. 34 (B), the pin wire 84 is joined to the re-wiring electrode 83A. 図34(C)において、半導体素子85は樹脂86で樹脂封止され、半導体パッケージとなる。 In FIG. 34 (C), the semiconductor element 85 is sealed with a resin in the resin 86, the semiconductor package.
ワイヤボンディング技術を使用したピンワイヤ84の形成は再配線電極(電極部)83Aを含む回路面に与えるダメージが少ないため、ピンワイヤ84は、半導体素子85の電極パッドだけでなく、再配線技術により形成された電極83Aに接合されるのに適している。 Formation of pin wire 84 using wire bonding technology for less damage to the circuit surface, including a re-wiring electrode (electrode section) 83A, pin wire 84 is not only the electrode pads of the semiconductor element 85, it is formed by rewiring technique It is suitable to be bonded to the electrode 83A. このため、ピンワイヤ84を有する複数の半導体素子を積み重ねた半導体装置を得ることもできる。 Therefore, it is possible to obtain a semiconductor device having stacked a plurality of semiconductor elements having a pin wire 84. さらに、ピン部80dの長さtがピン部80dの直径Φa及びΦbを超えない条件において、ピン部80dの長さtとピン部80dの直径ΦaやΦbは自由に長さや大きさを選択することができる。 Further, in the condition where the length t of the pin portion 80d does not exceed the diameter Φa and Φb of the pin portion 80d, the diameter Φa and Φb of the pin portion 80d length t and the pin portion 80d selects a free length and size be able to. 上記の特徴から、ダメージレス接合やチップスタック化、フレキシブルボンディング、低コストであるトランスファーモールド一括封止などが可能となり、軽量、小型だけでなく高速動作可能で複数の高い機能を備えた半導体装置を低コストで得ることができる。 From the above characteristics, damage-free bonding and chip stacked, flexible bonding enables such transfer mold collectively sealing a low-cost, light weight, a semiconductor device having a plurality of high functionality and high speed operation can not size only it can be obtained at low cost.

図35(A)及び図35(B)はピンワイヤ84の変形例を示す図である。 Figure 35 (A) and FIG. 35 (B) is a diagram showing a modification of the pin wire 84. 図35(A)はピンワイヤ84が屈曲した形状の例を示す。 Figure 35 (A) shows an example of a shape of the pin wire 84 is bent. 図35(B)はピンワイヤ84が斜めに接合された例を示す。 Figure 35 (B) shows an example in which the pin wire 84 is bonded to diagonally. このような変形ピンワイヤ84は半導体素子85側から荷重をかけることによって得られる。 Such modifications pin wire 84 is obtained by applying a load from the semiconductor device 85 side. このような変形ピンワイヤ84は応力吸収しやすくなる利点がある。 Such modifications pin wire 84 has the advantage of easily stress absorbing.

図36はピンワイヤ84を有する半導体装置の他の例を示す図である。 Figure 36 is a diagram showing another example of a semiconductor device having a pin wire 84. この例では、図32(A)に示される半導体素子85がそれに接合されたピンワイヤ84によってインターポーザ89に搭載されている。 In this example, it is mounted on the interposer 89 by pin wire 84 to the semiconductor element 85 is bonded to that shown in FIG. 32 (A). ピンワイヤ84は垂直に曲げられ、インターポーザ89の対応する電極(図示せず)との接触面積を増加させるようになっている。 Pin wire 84 is bent vertically, so as to increase the contact area between the corresponding electrodes (not shown) of the interposer 89. さらに、ピンワイヤ84はインターポーザ89の対応する電極との間に導電材料90が配置され、電気的な接続をより確実にしている。 Furthermore, the pin wire 84 is a conductive material 90 is disposed between the corresponding electrodes of the interposer 89, and the electrical connection more reliable. なお、ピンワイヤ84は垂直に曲げるのは、半導体素子85をインターポーザ89に対して横方向に動かすことによって達成される。 Incidentally, the pin wire 84 is bent vertically is accomplished by moving laterally the semiconductor element 85 with respect to the interposer 89.

図37はピンワイヤ84を有する半導体装置の他の例を示す図である。 Figure 37 is a diagram showing another example of a semiconductor device having a pin wire 84. この例では、図33(B)に示される半導体素子85がそれに接合されたピンワイヤ84によってマザーボード91に搭載されている。 In this example, are mounted on the mother board 91 by the pin wire 84 to the semiconductor element 85 is bonded to that shown in FIG. 33 (B). ピンワイヤ84は垂直に曲げられ、マザーボード91の対応する電極(図示せず)との接触面積を増加させるようになっている。 Pin wire 84 is bent vertically, so as to increase the contact area between the corresponding electrodes (not shown) of the motherboard 91. さらに、ピンワイヤ84はマザーボード91の対応する電極との間に導電材料90が配置され、電気的な接続をより確実にしている。 Furthermore, the pin wire 84 is a conductive material 90 is disposed between the corresponding electrodes of the motherboard 91, and the electrical connection more reliable.

図38(A)及び図38(C)はピンワイヤの先端に導電材料を付着させ、インターポーザ又はマザーボードに接着し、熱を加えることによって接合した半導体装置の例を示す図である。 Figure 38 (A) and FIG. 38 (C) is deposited a conductive material at the tip of the pin wire, and bonded to the interposer or motherboard is a diagram showing an example of a semiconductor device bonded by the application of heat. 図38(A)においては、半導体素子85に設けられたピンワイヤ84を槽90Aの導電材料90に漬けることによって導電材料90を付着させる。 In FIG. 38 (A) is to deposit a conductive material 90 by dipping the pin wire 84 provided on the semiconductor element 85 to the conductive material 90 in the tank 90A. 図38(B)においては、半導体素子85に設けられたピンワイヤ84を形成板90Bの凹部90Cの導電材料90に漬けることによって導電材料90を付着させる。 In FIG. 38 (B) is to deposit a conductive material 90 by dipping the pin wire 84 provided on the semiconductor element 85 in the forming plate 90B recess 90C of the conductive material 90 of the. 図38(C)は、ピンワイヤ84及び導電材料90を有する半導体素子85をインターポーザ89又はマザーボード91に搭載するところを示す。 Figure 38 (C) shows the place for mounting a semiconductor element 85 having a pin wire 84 and the conductive material 90 on the interposer 89 or motherboard 91. 図38(B)の方法では導電性材料の濡れ量の管理が容易であるという利点がある。 There is an advantage that the method of FIG. 38 (B) is easily managed wetting amount of the conductive material.

図39は熱圧着によるピンワイヤの接合の例を示す図である。 Figure 39 is a diagram showing an example of a joining pin wire by thermal compression bonding. 半導体素子85に設けられたピンワイヤ84をヒータ92上に置かれたインターポーザ89又はマザーボード91に搭載する。 The pin wire 84 provided on the semiconductor element 85 is mounted on the interposer 89 or motherboard 91 is placed on the heater 92. 半導体素子85には図に矢印で示される力を付加しながら、熱をかけて、ピンワイヤ84をインターポーザ89又はマザーボード91の対応する電極(図示せず)に接合させる。 While the semiconductor device 85 adds the force indicated by the arrow in the figure, by applying heat, bonding the pin wire 84 to the corresponding electrode of the interposer 89 or motherboard 91 (not shown). 熱圧着による金属結合の場合には接合部の密着性は非常に高い。 In the case of metal bonding by thermocompression bonding adhesion junction is very high.

図54は印刷によるピンワイヤの接合の例を示す。 Figure 54 shows an example of a joining pin wire by printing. 図54(A)において、印刷マスク90Cを用いて導電材料90をインターポーザ89又はマザーボード91の対応する電極に印刷する。 In FIG. 54 (A), a conductive material 90 is printed on the corresponding electrodes of the interposer 89 or motherboard 91 using a printing mask 90C. 図54(B)において、半導体素子85に設けられたピンワイヤ84を導電材料に接合する。 In FIG. 54 (B), joining pin wire 84 provided on the semiconductor element 85 to the conductive material.
図40(A)及び図40(B)はピンワイヤ84の直径を変えることによるインピーダンスマッチングの例を示す図である。 Figure 40 (A) and FIG. 40 (B) is a diagram showing an example of impedance matching by varying the diameter of the pin wire 84. インターポーザ89はランド89A及びランド89Aからピンワイヤ84に接続される電極まで延びる配線89Bを有する。 Interposer 89 has a wiring 89B extending to the electrode connected from the land 89A and the land 89A on the pin wire 84. インターポーザ89側の設計により、配線89Bの長さが変わることがある。 The interposer 89 side of the design, it is the length of the wiring 89B is changed. 図40(A)に示される配線89Bの長さは、図40(B)に示される配線89Bの長さよりも長い。 The length of the wire 89B shown in FIG. 40 (A) is longer than the length of the wiring 89B shown in FIG. 40 (B). このような場合には、図40(A)に示されるピンワイヤ84の直径を太くし、図40(B)に示されるピンワイヤ84の直径を補足することにより、インピーダンスマッチングを達成することができる。 In such a case, thicker the diameter of the pin wire 84 shown in FIG. 40 (A), by supplementing the diameter of the pin wire 84 shown in FIG. 40 (B), it is possible to achieve impedance matching.

図41(A)及び図41(B)はピンワイヤ84の直径を変えることによるインピーダンスマッチングの例を示す図である。 Figure 41 (A) and FIG. 41 (B) is a diagram showing an example of impedance matching by varying the diameter of the pin wire 84. この例では、図40(A)に示される長い配線89Bの場合にはピンワイヤ84の膨大部80aの太さを太くし、図40(B)に示される短い配線89Bの場合にはピンワイヤ84の膨大部80aの太さを小さくする。 In this example, thicker the thickness of the enlarged portion 80a of the pin wire 84 in the case of a long wire 89B shown in FIG. 40 (A), in the case of short wiring 89B shown in FIG. 40 (B) is a pin wire 84 to reduce the thickness of the enlarged portion 80a.

このように、数MHz帯の高速半導体デバイスにおいて問題となっている各配線間の信号遅れを低減するために、配線が長い場合には、ワイヤ径を太くしたり、膨大部を大きくしたりして相対的な抵抗値を下げ、各配線間のインピーダンスの値を調整し、信号遅れを少なくする。 Thus, in order to reduce signal delay between the wirings has become a problem in high-speed semiconductor devices of several MHz band, if the wiring is long, or thicker wire diameter, and or increasing the ampulla lowering the relative resistance value each, to adjust the value of the impedance between the wires, to reduce the signal delay.
図42(A)から図42(E)はメッキ部によりピンワイヤを接合した半導体装置の例を示す図である。 Figure 42 Figure 42 from (A) (E) is a diagram showing an example of a semiconductor device formed by joining pin wire by plating unit. 図42(A)において、凹部93Aを形成したリードフレーム93を準備し、図42(B)において、凹部93Aの表面にメッキしてメッキ部93Bを形成する。 In FIG. 42 (A), to prepare a lead frame 93 to form a recess 93A, in FIG. 42 (B), and plating the surface of the concave portion 93A to form the plated portion 93B. 図42(C)において、半導体素子85のピンワイヤ84の先端をメッキ部93Bに接合する。 In FIG. 42 (C), joining the leading end of the pin wire 84 of the semiconductor element 85 to the plating unit 93B. 熱圧着により、ピンワイヤ84の先端はメッキ部93Bに簡単に接合する。 By thermocompression bonding, the tip of the pin wire 84 is simply bonded to the plating section 93B. 図42(D)において、半導体素子85を樹脂94により樹脂封止する。 In FIG. 42 (D), the semiconductor device 85 sealed with resin by the resin 94. 樹脂94は半導体素子85とリードフレーム93との間の空間を埋める。 Resin 94 fills the space between the semiconductor element 85 and the lead frame 93. それから、図42(E)において、リードフレーム93を化学的なエッチングにより溶かし、メッキ部93Bを露出させる。 Then, in FIG. 42 (E), dissolved by chemical etching the lead frame 93, exposing the plated portion 93B. メッキ部93Bはピンワイヤ84の先端に付着している。 Plating part 93B is attached to the tip of the pin wire 84. このようにして、メッキ部93Bはピンワイヤ84とともに外部端子となる。 In this way, the plated portion 93B is an external terminal with the pin wire 84. この技術はフェイスアップタイプのBCC(Bump Chip Carrier )パッケージと比較して、小型化、ファインピッチ化、高速化を実現できる。 This technology as compared to the face-up type of BCC (Bump Chip Carrier) package, compact, fine pitch, a high speed can be realized.

図43はピンワイヤを有する半導体装置の一例を示す図である。 Figure 43 is a diagram showing an example of a semiconductor device having a pin wire. 図43(A)は、図38、図39又は図54に示されるように半導体素子85が導電材料90を付着させたピンワイヤ84によりインターポーザ89に搭載された例を示す。 Figure 43 (A) is 38, an example which is mounted on the interposer 89 by pin wire 84 to the semiconductor element 85 is adhered a conductive material 90 as shown in FIG. 39 or FIG. 54. 図43(B)は図43(A)に示される半導体装置にトランスファーモールドする例を示す。 Figure 43 (B) shows an example of transfer molding the semiconductor device shown in FIG. 43 (A). 樹脂94を金型95に流し込む。 Pouring the resin 94 in the mold 95. ピンワイヤ84が高い密度で配置されている場合でも、トランスファーモールドを行うことができる。 Even if the pin wire 84 is arranged at a high density, it is possible to perform transfer molding. 図43(C)においては、金型95を除去し、インターポーザ89の反対面側に金属ボール96を接合して、半導体パッケージを完成する。 In FIG. 43 (C), to remove the mold 95, by joining a metal ball 96 on the opposite side of the interposer 89, to complete the semiconductor package.

図44は樹脂封止の他の例を示す図である。 Figure 44 is a diagram showing another example of the resin sealing. 図43(B)のトランスファーモールドの代わりに、図44に示されるようにポッティングにより樹脂封止を行うこともできる。 Instead of transfer molding in FIG. 43 (B), it may be sealed with resin by potting as shown in Figure 44.
図45は半導体装置の一例を示す平面図である。 Figure 45 is a plan view showing an example of a semiconductor device. 図46は図45の平面的に配置された複数の半導体素子を含む半導体装置の例を示す図である。 Figure 46 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements which are planarly disposed in FIG. 45. 図45(A)及び図46(A)において、それぞれにピンワイヤ84を有する複数の半導体素子85が金属板97に平面的に配置される。 Figure 45 In (A) and FIG. 46 (A), a plurality of semiconductor elements 85 with the pin wire 84 to each of which is planarly disposed in the metal plate 97. ピンワイヤ84には導電材料90を付着させてある。 The pin wire 84 are adhered to the conductive material 90. 複数の半導体素子85は接着剤98によって金属板97に固定される。 A plurality of semiconductor elements 85 are fixed to the metal plate 97 by an adhesive 98. 図46(B)において、複数の半導体素子85はピンワイヤ84によりインターポーザ89に搭載される。 In FIG. 46 (B), a plurality of semiconductor elements 85 are mounted on the interposer 89 by the pin wire 84. 図46(C)において、半導体素子85を樹脂94により樹脂封止し、インターポーザ89の反対面側に金属ボール96を接合して、半導体パッケージを完成する。 In FIG. 46 (C), the semiconductor element 85 by the resin 94 is sealed with resin, and joining the metal balls 96 on the opposite side of the interposer 89, to complete the semiconductor package. 図45(B)は金属ボール96の配置を示している。 Figure 45 (B) shows the arrangement of the metal balls 96.

図47は立体的に配置された複数の半導体素子85を含む半導体装置の例を示す図である。 Figure 47 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements 85 which are arranged three-dimensionally. この例では、半導体素子85Aの回路面側と半導体素子85Bの背面側は接着材により固定、接着され、これらの半導体素子85A、85Bはそれぞれにピンワイヤ84を有する。 In this example, fixed by the rear side adhesive of the circuit surface side and the semiconductor device 85B of the semiconductor device 85A, glued, these semiconductor elements 85A, 85B has a pin wire 84, respectively. 半導体素子85A、85Bはピンワイヤ84によりインターポーザ89に搭載される。 Semiconductor elements 85A, 85B are mounted on the interposer 89 by the pin wire 84. 半導体素子85A、85Bを樹脂94により樹脂封止し、インターポーザ89の反対面側に金属ボール96を接合して、半導体パッケージを完成する。 Semiconductor element 85A, the through resin 94 sealed with resin 85B, by joining a metal ball 96 on the opposite side of the interposer 89, to complete the semiconductor package.

図48は立体的に配置された複数の半導体素子を含む半導体装置の例を示す図である。 Figure 48 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements are arranged three-dimensionally. この例では、半導体素子85Aはピンワイヤ84及び例えば図34(C)に示される再配線電極83Aを有し、それぞれにピンワイヤ84を有する半導体素子85Bと半導体素子85Cとは背中合わせで互いに固定される。 In this example, the semiconductor device 85A includes a rewiring electrode 83A shown in pin wire 84 and, for example, FIG. 34 (C), the semiconductor element 85B and the semiconductor device 85C having a pin wire 84 respectively are secured together back to back. 半導体素子85Bのピンワイヤ84は半導体素子85Aの再配線電極83Aに接合される。 Pin wire 84 of the semiconductor device 85B is joined to the re-wiring electrode 83A of the semiconductor device 85A. 一方、半導体素子85A、85Bはピンワイヤ84によりインターポーザ89に搭載される。 On the other hand, the semiconductor device 85A, 85B is mounted on the interposer 89 by the pin wire 84. 半導体素子85A、85Bを樹脂94により樹脂封止し、インターポーザ89の反対面側に金属ボール96を接合して、半導体パッケージを完成する。 Semiconductor element 85A, the through resin 94 sealed with resin 85B, by joining a metal ball 96 on the opposite side of the interposer 89, to complete the semiconductor package.

図49はスタックとして立体的に配置された複数の半導体装置を含む半導体装置の例を示す図である。 Figure 49 is a diagram showing an example of a semiconductor device including a plurality of semiconductor devices that are arranged three-dimensionally as a stack. 参照数字100は半導体素子85と、インターポーザ89と、半導体素子85とインターポーザ89とを樹脂封止する樹脂94とからなる半導体装置(半導体パッケージ)を示す。 Reference numeral 100 denotes a semiconductor element 85, an interposer 89, the semiconductor element 85 and the interposer 89 semiconductor device consisting of 94. resins the resin sealing (semiconductor package). 半導体素子85とインターポーザ89とは、図示しない適切な導体により接続される。 The semiconductor element 85 and the interposer 89 are connected by suitable conductors, not shown.

図49においては、3つの半導体装置(半導体パッケージ)100がスタックとして立体的に配置されている。 In Figure 49, three semiconductor device (semiconductor package) 100 are arranged three-dimensionally as a stack. 各インターポーザ89は樹脂94から横方向に延びだし、インターポーザ89の延びだした部分は電極部83Bを有し、その電極部83Bにはピンワイヤ84が接合されている。 Each interposer 89 out extends laterally from the resin 94, extends out portions of the interposer 89 has an electrode portion 83B, the pin wire 84 to the electrode portion 83B is joined. ピンワイヤ84の電極部83Bへの接合は上記したのと同様にして行われる。 Bonding to the electrode portion 83B of the pin wire 84 is carried out in the same manner as that described above. 上下関係で隣接する2つの半導体装置(半導体パッケージ)100はピンワイヤ84によって接続されている。 Two upper and lower semiconductor devices (semiconductor packages) adjacent in relation 100 is connected by a pin wire 84. このように、パッケージとパッケージを積み重ねる際の接続端子としてピンワイヤを適用すると、従来技術よりも伝送経路の短縮が図れるため高速伝送に非常に有利となる。 Thus, application of the pin wire as connection terminals when stacking packages and package, is very advantageous in high-speed transmission for over the prior art can be shortened transmission path.

図50はスタックとして形成された立体的に配置された複数の半導体素子を含む半導体装置の例を示す図である。 Figure 50 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements are arranged three-dimensionally formed as a stack. 図50においては、3つの半導体装置(半導体パッケージ)100がスタックとして立体的に配置されている。 In Figure 50, three semiconductor device (semiconductor package) 100 are arranged three-dimensionally as a stack. 図50では各半導体装置(半導体パッケージ)100の半導体素子85とインターポーザ89とがピンワイヤ84によって接合され、そして、インターポーザ89の延びだした部分にもピンワイヤ84が接合されている。 In FIG. 50 the semiconductor device a semiconductor device 85 (semiconductor package) 100 and the interposer 89 are joined by pin wire 84, and, pin wire 84 is bonded to extend out portions of the interposer 89. このようにして、ピンワイヤ84は各半導体装置(半導体パッケージ)100内に配置されるばかりでなく、隣接する2つの半導体装置(半導体パッケージ)100を接続する。 In this way, the pin wire 84 is not only arranged in each semiconductor device (semiconductor package) 100, connecting the two adjacent semiconductor devices (semiconductor packages) 100.

以上に説明した半導体素子53及び半導体装置及び半導体パッケージにおいて、ピンワイヤ84の長さ及び直径は所望に応じて変えることができる。 In the semiconductor device 53 and a semiconductor device and a semiconductor package described above, the length and diameter of the pin wire 84 can be varied as desired. また、ピンワイヤ84のの接合は、半導体素子毎でも、ウエハレベルでも、パッケージとなった後でも作製できることは当然ながら可能である。 The joining of the pin wire 84, even each semiconductor device, a wafer level, it can be produced even after a package is of course possible.
図51から図53はピンワイヤを有する半導体装置の製造方法の一例を示す図である。 FIGS. 51 53 is a diagram showing an example of a manufacturing method of a semiconductor device having a pin wire. 図51(A)においては、半導体ウエハ101を準備し、集積回路及び電極パッドの形成や、必要に応じて再配線電極を形成する。 In FIG. 51 (A), to prepare a semiconductor wafer 101, forming and the integrated circuit and the electrode pads, forming a rewiring electrode if necessary. 図51(B)においては、ピンワイヤ84を半導体ウエハ101の電極部(電極パッド又は再配線電極)83に接合する。 In FIG. 51 (B), joining pin wire 84 to the electrode portion (electrode pads or rewiring electrode) 83 of the semiconductor wafer 101. 図51(C)においては、半導体ウエハ101のピンワイヤ84とは反対側の表面に接着性テープ102を貼りつける。 In FIG. 51 (C), pasted adhesive tape 102 on the surface opposite to the pin wire 84 of the semiconductor wafer 101.

図52において、半導体ウエハ101及び接着性テープ102を厚さ調整用の一対のローラ103の間を走行させながら、半導体ウエハ101のピンワイヤ84側の表面に樹脂104がコーティングされたPETのシート105を貼りつける。 In Figure 52, while running between the pair of rollers 103 for thickness adjusting the semiconductor wafer 101 and the adhesive tape 102, the PET sheet 105 of the resin 104 is coated on the surface of the pin wire 84 side of the semiconductor wafer 101 Paste. 低弾性樹脂のワニスが槽106に入っている。 Low-elasticity resin varnish is in the tank 106. PETのシート105は槽106を通りながら半導体ウエハ101のピンワイヤ84側の表面に沿って走行する。 PET sheet 105 travels along the surface of the pin wire 84 side of the semiconductor wafer 101 while passing through the bath 106. 低弾性樹脂のワニスは半導体ウエハ101とPETのシート105との間にピンワイヤ84の先端を突出させる程度に充填される。 Low-elasticity resin varnish is filled to such an extent that the tip thereof protrudes pin wire 84 between the semiconductor wafer 101 and the sheet 105 of PET. 乾燥した低弾性樹脂のワニスはモールド樹脂104となる。 Varnish dried low elastic resin becomes molding resin 104.

図53において、PETのシート105を適当な時期に除去し、ダンシングして半導体ウエハ101を個々の半導体チップに分割する。 In Figure 53, the sheet 105 of PET was removed at an appropriate time, to divide the semiconductor wafer 101 by Dancing into individual semiconductor chips. 分割された半導体チップはすでに樹脂封止された半導体パッケージとなっている。 Divided semiconductor chips already a resin sealed semiconductor package. 最終的に個々の半導体チップは接着性テープ102から除去される。 Finally individual semiconductor chips are removed from the adhesive tape 102. この方法によれば、シートタイプの接着剤を貼り合わせる技術を応用してできるため、作業工程数の低減と、設備的にも大幅なコストダウンができる。 According to this method, since it by applying a technique of bonding the sheet-type adhesive, a reduction in the number of working processes, in equipment specifically be significant cost down.

図55は複数の半導体素子を含む半導体装置の例を示す図である。 Figure 55 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements. この例では、2つの半導体素子85A、85Bが1つのインターポーザ89に搭載される。 In this example, two semiconductor elements 85A, 85B are mounted on a single interposer 89. インターポーザ89は再配線電極89Cを有する。 Interposer 89 has a rewiring electrode 89C. 再配線電極89Cは半導体素子85A、85Bの電極パッドに対応して形成された第1の電極部分と、第1の電極部分に接続され且つ位置を変えて配置された第2の電極部分とを有する。 Rewiring electrode 89C is a semiconductor element 85A, a first electrode portion formed corresponding to the electrode pads of 85B, and a second electrode portion disposed with different connected to and positioned in the first electrode portion a. 半導体素子85A、85Bの電極パッドは再配線電極89Cの第1の電極部分に接続され、ピンワイヤ84は再配線電極89Cの第2の電極部分に接合されている。 Semiconductor element 85A, the electrode pad 85B is connected to the first electrode portion of the rewiring electrode 89C, the pin wire 84 is bonded to the second electrode portion of the rewiring electrode 89C. こうして形成された半導体装置は樹脂94により樹脂封止され、ピンワイヤ84は樹脂94から突出している。 The semiconductor device thus formed is resin sealed by resin 94, the pin wire 84 protrudes from the resin 94.

図56は複数の半導体素子を含む半導体装置の例を示す図である。 Figure 56 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements. この例では、2つの半導体素子85A、85Bが1つのインターポーザ89に搭載される。 In this example, two semiconductor elements 85A, 85B are mounted on a single interposer 89. インターポーザ89は再配線電極89Cを有する。 Interposer 89 has a rewiring electrode 89C. 再配線電極89Cは半導体素子85A、85Bの電極パッドに対応して形成された第1の電極部分と、第1の電極部分に接続され且つ位置を変えて配置された第2の電極部分とを有する。 Rewiring electrode 89C is a semiconductor element 85A, a first electrode portion formed corresponding to the electrode pads of 85B, and a second electrode portion disposed with different connected to and positioned in the first electrode portion a. ピンワイヤ84は半導体素子85A、85Bの電極パッドに接合され、ピンワイヤ84の先端は再配線電極89Cの第1の電極部分に接続される。 Pin wire 84 is a semiconductor element 85A, are bonded to the electrode pads of the 85B, the tip of the pin wire 84 is connected to the first electrode portion of the rewiring electrode 89C. 金属ボール96が再配線電極89Cの第2の電極部分に接合されている。 Metal ball 96 is joined to the second electrode portion of the rewiring electrode 89C. こうして形成された半導体装置は樹脂94により樹脂封止され、金属ボール96が外部天使となる。 The semiconductor device thus formed is resin sealed by resin 94, the metal ball 96 is external angels.

図57は複数の半導体素子を含む半導体装置の例を示す図である。 Figure 57 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements. この例では、2つの半導体素子85A、85Bが1つのインターポーザ89に搭載される。 In this example, two semiconductor elements 85A, 85B are mounted on a single interposer 89. 半導体素子85Aは再配線電極83Aを有する。 The semiconductor device 85A includes a rewiring electrodes 83A. 一群のピンワイヤ84は半導体素子85Bの電極パッドに接合され、これらのピンワイヤ84の先端が半導体素子85Aの一群の再配線電極89Cに接続される。 Group of pin wire 84 is bonded to the electrode pads of the semiconductor element 85B, the distal end of the pin wire 84 is connected to a group of rewiring electrodes 89C of the semiconductor device 85A. 他の一群のピンワイヤ84は半導体素子85Aの一群の再配線電極89Cに接合される。 Other group of pin wire 84 is bonded to a group of rewiring electrodes 89C of the semiconductor device 85A. こうして形成された半導体装置は樹脂94により樹脂封止され、一群のピンワイヤ84は樹脂94から突出している。 The semiconductor device thus formed is resin sealed by resin 94, a group of pin wire 84 protrudes from the resin 94.

図58は複数の半導体素子を含む半導体装置の例を示す図である。 Figure 58 is a diagram showing an example of a semiconductor device including a plurality of semiconductor elements. この例では、3つの半導体素子85A、85Bが1つのインターポーザ89に搭載される。 In this example, three semiconductor elements 85A, 85B are mounted on a single interposer 89. 半導体素子85Aは再配線電極83Aを有し、半導体素子85Cも再配線電極83Aを有する。 The semiconductor device 85A includes a rewiring electrodes 83A, also has a re-wiring electrode 83A semiconductor device 85C. 一群のピンワイヤ84は半導体素子85Bの電極パッドに接合され、これらのピンワイヤ84の先端が半導体素子85Cの一群の再配線電極83Aに接続される。 Group of pin wire 84 is bonded to the electrode pads of the semiconductor element 85B, the distal end of the pin wire 84 is connected to a group of rewiring electrodes 83A of the semiconductor device 85C. 他の一群のピンワイヤ84は半導体素子85Cの一群の再配線電極83Aに接合され、これらのピンワイヤ84の先端が半導体素子85Aの一群の再配線電極83Aに接続される。 Other group of pin wire 84 is bonded to a group of rewiring electrodes 83A of the semiconductor device 85C, the tip of the pin wire 84 is connected to a group of rewiring electrodes 83A of the semiconductor device 85A. 他の一群のピンワイヤ84は半導体素子85Aの一群の再配線電極83Aに接合される。 Other group of pin wire 84 is bonded to a group of rewiring electrodes 83A of the semiconductor device 85A. こうして形成された半導体装置は樹脂94により樹脂封止され、一群のピンワイヤ84は樹脂94から突出している。 The semiconductor device thus formed is resin sealed by resin 94, a group of pin wire 84 protrudes from the resin 94.

本発明によれば、金属ワイヤはハーフカットしておいた前記所望の位置で確実に且つきれいに切断され、金属ワイヤの切断部は一様な形状になり、金属ワイヤの長さも一様になる。 According to the present invention, the metal wire is reliably and cleanly cut at the desired position that has been half-cut, the cutting portion of the metal wire becomes uniform shape, also becomes uniform length of metal wire. 従って、狭いピッチの複数のピンワイヤを有する半導体素子においては、複数のピンワイヤの高さがほぼ一定になり、半導体素子をマザーボード等の他の装置と接合するの適したものとなる。 Accordingly, in the semiconductor device having a plurality of pin wire of a small pitch, the height of the plurality of pin wire becomes substantially constant, and be suitable for bonding the semiconductor element and other devices such as a motherboard.

10 半導体装置 12 電極パッド 14 半導体素子 16 柱状電極 16a ワイヤ部分 16b 膨大部分 18 樹脂層 20 外部端子 20a はんだボール 22 回路基板 24 電極パッド 30 ウエハ 32 キャピラリ 34 小塊 36 ボンディングワイヤ 50 再配線導体部分 80 金属ワイヤ 81 キャピラリ 82 ハーフカット用工具 83 電極部 84 ピンワイヤ 85 半導体素子 10 semiconductor device 12 electrode pad 14 semiconductor element 16 columnar electrodes 16a wire portion 16b vast portion 18 resin layer 20 external terminals 20a solder balls 22 circuit board 24 electrode pads 30 wafer 32 capillary 34 nodules 36 bonding wire 50 rewiring conductor portions 80 metal wire 81 capillary 82 half-cutting tool 83 electrode 84 pin wire 85 semiconductor element

Claims (5)

  1. 第1端部を有する金属ワイヤに所望の位置でハーフカット処理を行う工程と、 And performing half-cutting processing at a desired position in the metal wire having a first end,
    該金属ワイヤの第1端部を半導体素子又は半導体装置の電極部にボンディングする工程と、 A step of bonding the first end portion of the metal wire to the electrode portion of the semiconductor device or apparatus,
    該金属ワイヤを該電極部に対して引っ張ることにより該金属ワイヤを該所望の位置で切断してピンワイヤを形成する工程とを備え、該ピンワイヤは切断された第2端部を有することを特徴とする半導体装置の製造方法。 And forming a pin wire by cutting the metal wires at the position of said desired by pulling the metal wire against the electrode portion, and wherein the said pin wire is having a second cut ends the method of manufacturing a semiconductor device to be.
  2. 該ピンワイヤは円柱状のピン部を有し、該ピンワイヤの該一端部は該ピン部の直径よりも大きい膨大形状を有し、該ピンワイヤのピン部の長さは該ピンワイヤのピン部の直径よりも大きいことを特徴とする請求項1に記載の半導体装置の製造方法。 The pin wire has a cylindrical pin portion, said one end of said pin wire having a larger enormous shape than the diameter of the pin portion, the length of the pin portion of the pin wire than the diameter of the pin portion of the pin wire the method of manufacturing a semiconductor device according to claim 1, characterized in that also large.
  3. 該ピンワイヤの該第2端部が突出するように該半導体素子をモールド材料でモールドする工程を備え、該ピンワイヤのモールド材料から突出する第2端部が外部端子となることを特徴とする請求項1に記載の半導体装置の製造方法。 Claims, characterized in that the second end said second end of said pin wire comprises a step of molding the semiconductor element with a mold material so as to protrude, protruding from the molding material of the pin wire is external terminal the method of manufacturing a semiconductor device according to 1.
  4. 該ピンワイヤの第2端部を該半導体素子とは別の装置の電極部に接続する工程を備えることを特徴とする請求項3に記載の半導体装置の製造方法。 The method of manufacturing a semiconductor device according to a second end of the pin wire to claim 3, characterized in that it comprises the step of connecting the electrode portion of another apparatus with the semiconductor device.
  5. 該ピンワイヤの該第2端部に導電材料を付着させる工程を備え、該導電材料を付着させた該ピンワイヤの該第2端部が外部端子となることを特徴とする請求項1に記載の半導体装置の製造方法。 The semiconductor according to claim 1, characterized in that comprising the step of depositing a conductive material on said second end of said pin wire, the second end of the pin wire adhered with conductive material as an external terminal manufacturing method of the device.
JP2010101251A 1999-08-12 2010-04-26 Semiconductor device, and method of manufacturing the same Pending JP2010192928A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP22868099 1999-08-12
JP2010101251A JP2010192928A (en) 1999-08-12 2010-04-26 Semiconductor device, and method of manufacturing the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010101251A JP2010192928A (en) 1999-08-12 2010-04-26 Semiconductor device, and method of manufacturing the same

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2000119616 Division 2000-04-20

Publications (1)

Publication Number Publication Date
JP2010192928A true JP2010192928A (en) 2010-09-02

Family

ID=42578299

Family Applications (2)

Application Number Title Priority Date Filing Date
JP2010101251A Pending JP2010192928A (en) 1999-08-12 2010-04-26 Semiconductor device, and method of manufacturing the same
JP2010101202A Expired - Fee Related JP5333337B2 (en) 1999-08-12 2010-04-26 A method of manufacturing a semiconductor device

Family Applications After (1)

Application Number Title Priority Date Filing Date
JP2010101202A Expired - Fee Related JP5333337B2 (en) 1999-08-12 2010-04-26 A method of manufacturing a semiconductor device

Country Status (1)

Country Link
JP (2) JP2010192928A (en)

Cited By (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2015508240A (en) * 2012-02-24 2015-03-16 インヴェンサス・コーポレイション Method for package-on-package assembly having a wire bond to the sealing surface
JP5686912B1 (en) * 2014-02-20 2015-03-18 株式会社新川 Bump forming method, a manufacturing method of the bump forming apparatus and a semiconductor device
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5908218B2 (en) * 2011-05-10 2016-04-26 エスアイアイ・セミコンダクタ株式会社 The method for manufacturing an optical sensor and an optical sensor

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5087278A (en) * 1973-12-05 1975-07-14
JPH02503616A (en) * 1987-05-21 1990-10-25
JPH0394438A (en) * 1989-09-06 1991-04-19 Shinko Electric Ind Co Ltd Semiconductor chip module
JPH09260428A (en) * 1996-03-19 1997-10-03 Toshiba Corp Semiconductor device an mounting method thereof
JPH10135221A (en) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd Bump-forming method
JPH10303244A (en) * 1997-04-25 1998-11-13 Sony Corp Bump structure and its manufacture

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917707A (en) * 1993-11-16 1999-06-29 Formfactor, Inc. Flexible contact structure with an electrically conductive shell
JPH0855856A (en) * 1994-08-11 1996-02-27 Shinko Electric Ind Co Ltd Semiconductor device and its manufacture
JP3362545B2 (en) * 1995-03-09 2003-01-07 ソニー株式会社 A method of manufacturing a semiconductor device
JP3313547B2 (en) * 1995-08-30 2002-08-12 沖電気工業株式会社 Method of manufacturing a chip size package
JPH09172036A (en) * 1995-12-19 1997-06-30 Toshiba Corp Manufacturing method for semiconductor package device
JP2825083B2 (en) * 1996-08-20 1998-11-18 日本電気株式会社 Mounting structure of the semiconductor element
JP3152180B2 (en) * 1997-10-03 2001-04-03 日本電気株式会社 Semiconductor device and manufacturing method thereof
JP3618212B2 (en) * 1998-01-08 2005-02-09 松下電器産業株式会社 Semiconductor device and manufacturing method thereof
JPH11220069A (en) * 1998-02-02 1999-08-10 Seiko Epson Corp Semiconductor device and its manufacture, circuit board, and/or electronic equipment

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5087278A (en) * 1973-12-05 1975-07-14
JPH02503616A (en) * 1987-05-21 1990-10-25
JPH0394438A (en) * 1989-09-06 1991-04-19 Shinko Electric Ind Co Ltd Semiconductor chip module
JPH09260428A (en) * 1996-03-19 1997-10-03 Toshiba Corp Semiconductor device an mounting method thereof
JPH10135221A (en) * 1996-10-29 1998-05-22 Taiyo Yuden Co Ltd Bump-forming method
JPH10303244A (en) * 1997-04-25 1998-11-13 Sony Corp Bump structure and its manufacture

Cited By (43)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9570416B2 (en) 2004-11-03 2017-02-14 Tessera, Inc. Stacked packaging improvements
US9984901B2 (en) 2005-12-23 2018-05-29 Tessera, Inc. Method for making a microelectronic assembly having conductive elements
US10128216B2 (en) 2010-07-19 2018-11-13 Tessera, Inc. Stackable molded microelectronic packages
US9553076B2 (en) 2010-07-19 2017-01-24 Tessera, Inc. Stackable molded microelectronic packages with area array unit connectors
US9570382B2 (en) 2010-07-19 2017-02-14 Tessera, Inc. Stackable molded microelectronic packages
US9691731B2 (en) 2011-05-03 2017-06-27 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US10062661B2 (en) 2011-05-03 2018-08-28 Tessera, Inc. Package-on-package assembly with wire bonds to encapsulation surface
US9761558B2 (en) 2011-10-17 2017-09-12 Invensas Corporation Package-on-package assembly with wire bond vias
US9842745B2 (en) 2012-02-17 2017-12-12 Invensas Corporation Heat spreading substrate with embedded interconnects
US9691679B2 (en) 2012-02-24 2017-06-27 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
US9349706B2 (en) 2012-02-24 2016-05-24 Invensas Corporation Method for package-on-package assembly with wire bonds to encapsulation surface
JP2015508240A (en) * 2012-02-24 2015-03-16 インヴェンサス・コーポレイション Method for package-on-package assembly having a wire bond to the sealing surface
US9953914B2 (en) 2012-05-22 2018-04-24 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US10170412B2 (en) 2012-05-22 2019-01-01 Invensas Corporation Substrate-less stackable package with wire-bond interconnect
US9917073B2 (en) 2012-07-31 2018-03-13 Invensas Corporation Reconstituted wafer-level package dram with conductive interconnects formed in encapsulant at periphery of the package
US9391008B2 (en) 2012-07-31 2016-07-12 Invensas Corporation Reconstituted wafer-level package DRAM
US9502390B2 (en) 2012-08-03 2016-11-22 Invensas Corporation BVA interposer
US9615456B2 (en) 2012-12-20 2017-04-04 Invensas Corporation Microelectronic assembly for microelectronic packaging with bond elements to encapsulation surface
US9601454B2 (en) 2013-02-01 2017-03-21 Invensas Corporation Method of forming a component having wire bonds and a stiffening layer
US9685365B2 (en) 2013-08-08 2017-06-20 Invensas Corporation Method of forming a wire bond having a free end
US10008477B2 (en) 2013-09-16 2018-06-26 Invensas Corporation Microelectronic element with bond elements to encapsulation surface
US10026717B2 (en) 2013-11-22 2018-07-17 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9728527B2 (en) 2013-11-22 2017-08-08 Invensas Corporation Multiple bond via arrays of different wire heights on a same substrate
US9852969B2 (en) 2013-11-22 2017-12-26 Invensas Corporation Die stacks with one or more bond via arrays of wire bond wires and with one or more arrays of bump interconnects
US9837330B2 (en) 2014-01-17 2017-12-05 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
US9583411B2 (en) 2014-01-17 2017-02-28 Invensas Corporation Fine pitch BVA using reconstituted wafer with area array accessible for testing
CN106233443B (en) * 2014-02-20 2018-11-20 株式会社新川 Bump forming method, a method for manufacturing a bump forming apparatus and a semiconductor device
CN106233443A (en) * 2014-02-20 2016-12-14 株式会社新川 Bump forming method, bump forming apparatus, and semiconductor device manufacturing method
WO2015125316A1 (en) * 2014-02-20 2015-08-27 株式会社新川 Bump forming method, bump forming apparatus, and semiconductor device manufacturing method
JP5686912B1 (en) * 2014-02-20 2015-03-18 株式会社新川 Bump forming method, a manufacturing method of the bump forming apparatus and a semiconductor device
US9412714B2 (en) 2014-05-30 2016-08-09 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9947641B2 (en) 2014-05-30 2018-04-17 Invensas Corporation Wire bond support structure and microelectronic package including wire bonds therefrom
US9735084B2 (en) 2014-12-11 2017-08-15 Invensas Corporation Bond via array for thermal conductivity
US10008469B2 (en) 2015-04-30 2018-06-26 Invensas Corporation Wafer-level packaging using wire bond wires in place of a redistribution layer
US9761554B2 (en) 2015-05-07 2017-09-12 Invensas Corporation Ball bonding metal wire bond wires to metal pads
US10115678B2 (en) 2015-10-12 2018-10-30 Invensas Corporation Wire bond wires for interference shielding
US9812402B2 (en) 2015-10-12 2017-11-07 Invensas Corporation Wire bond wires for interference shielding
US10181457B2 (en) 2015-10-26 2019-01-15 Invensas Corporation Microelectronic package for wafer-level chip scale packaging with fan-out
US9911718B2 (en) 2015-11-17 2018-03-06 Invensas Corporation ‘RDL-First’ packaged microelectronic device for a package-on-package device
US10043779B2 (en) 2015-11-17 2018-08-07 Invensas Corporation Packaged microelectronic device for a package-on-package device
US9659848B1 (en) 2015-11-18 2017-05-23 Invensas Corporation Stiffened wires for offset BVA
US9984992B2 (en) 2015-12-30 2018-05-29 Invensas Corporation Embedded wire bond wires for vertical integration with separate surface mount and wire bond mounting surfaces
US9935075B2 (en) 2016-07-29 2018-04-03 Invensas Corporation Wire bonding method and apparatus for electromagnetic interference shielding

Also Published As

Publication number Publication date
JP2010161430A (en) 2010-07-22
JP5333337B2 (en) 2013-11-06

Similar Documents

Publication Publication Date Title
KR100493063B1 (en) BGA package with stacked semiconductor chips and manufacturing method thereof
JP3526788B2 (en) A method of manufacturing a semiconductor device
JP3611948B2 (en) Semiconductor device and manufacturing method thereof
US7902648B2 (en) Interposer configured to reduce the profiles of semiconductor device assemblies, packages including the same, and methods
JP3142723B2 (en) Semiconductor device and manufacturing method thereof
JP3996315B2 (en) Semiconductor device and manufacturing method thereof
US6977439B2 (en) Semiconductor chip stack structure
US8357999B2 (en) Assembly having stacked die mounted on substrate
US6844619B2 (en) Compact semiconductor device capable of mounting a plurality of semiconductor chips with high density and method of manufacturing the same
EP2852974B1 (en) Method of making a substrate-less stackable package with wire-bond interconnect
JP5043743B2 (en) A method of manufacturing a semiconductor device
US7422978B2 (en) Methods of manufacturing interposers with flexible solder pad elements
US5838061A (en) Semiconductor package including a semiconductor chip adhesively bonded thereto
KR100938970B1 (en) Semiconductor device and manufacturing method thereof
US6555917B1 (en) Semiconductor package having stacked semiconductor chips and method of making the same
US7138706B2 (en) Semiconductor device and method for manufacturing the same
US6593220B1 (en) Elastomer plating mask sealed wafer level package method
US9502390B2 (en) BVA interposer
JP3233535B2 (en) Semiconductor device and manufacturing method thereof
JP3994262B2 (en) Semiconductor device and manufacturing method thereof, the circuit board and electronic equipment
US8618659B2 (en) Package-on-package assembly with wire bonds to encapsulation surface
JP4343296B2 (en) A method of manufacturing a semiconductor device
JP3548082B2 (en) Semiconductor device and manufacturing method thereof
US6611063B1 (en) Resin-encapsulated semiconductor device
KR100868419B1 (en) Semiconductor device and manufacturing method thereof

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20121107

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20121113

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20130312