JP2010183405A - Solid-state imaging device and signal processing method thereof - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging device and the like comprising an ADC circuit for each column capable of reducing power consumption and improving actual operational precision by using a clock to be used for a counter with a clock of low frequency by using the counter having bits less than bits of an output digital signal. <P>SOLUTION: Comparators 14-17 level-compare a signal from a pixel 1 in a column direction amplified by a non-inverted amplifier comprised of an operational amplifier 12 or the like with comparative reference voltages V1-V4. A data processing/selecting circuit 18 detects from a relationship of logic values of four output signals from the comparators 14-17 which one of four signal ranges, obtained by equally dividing a saturation signal voltage of the pixel with the comparative reference voltages V1-V4, the signal from the pixel 1 belongs to, and indicates the detected signal range as high-order two bits of the output digital signal and outputs an enable signal. An n-bit counter 19 outputs low-order (n) bits of the digital signal by counting clock during an enable period. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device and a signal processing method thereof, and in particular, solid-state imaging such as a CMOS (Complementary Metal-Oxide Semiconductor) type imaging device (hereinafter referred to as a CMOS sensor) having an ADC circuit for each column that outputs a digital image signal. The present invention relates to an element and a signal processing method thereof.

  Conventionally, a CMOS sensor sometimes outputs pixel signals separately for each pixel, takes out signals in the vertical direction, and performs processing by a CDS circuit (correlated double sampling circuit) at a time in units of horizontal lines. This CDS circuit is prepared for each vertical signal (each column), takes a difference with respect to an analog signal as a pixel output, and an analog / digital converter (hereinafter referred to as an ADC circuit) at the time of final signal reading with respect to the difference. ) Is often used to convert to a digital signal.

  First, an ADC circuit in a conventional CMOS sensor will be described.

  FIG. 8 shows a configuration diagram of an example of the CMOS sensor. In the figure, a plurality of pixels 1 are arranged in a two-dimensional matrix, and any one of the pixels is selected using a vertical selection circuit 2 and a horizontal selection circuit 3. The signal output from the selected pixel to the CDS circuit 4 for each horizontal line is subjected to correlated double sampling (CDS) processing on the same horizontal line signal simultaneously in the CDS circuit 4 provided for each column. The signal subjected to CDS processing by the CDS circuit 4 is finally output for each pixel through an amplifier (AMP) 5.

  FIG. 9 shows an equivalent circuit diagram of an example of one pixel 1. As shown in the figure, one pixel 1 is composed of a photodiode PD1 and three MOS transistors Tr11, Tr12, Tr13. In the readout from the pixel 1, the input signal ROWS1 to the gate of the MOS transistor Tr13 is set to a high (HIGH) voltage to turn it on, and the voltage generated at the photodiode PD1 is set to the source follower and the MOS transistor of the MOS transistor Tr12. The output voltage Vsout is output to the terminal Sout through each Tr13. This output voltage Vsout is input as a signal to the CDS circuit 4 of FIG.

  Next, a high voltage reset signal PDRST1 is applied to the gate of the MOS transistor Tr11 to turn on the MOS transistor Tr11, whereby the power supply voltage Vdd is applied to the cathode of the photodiode PD1 via the drain and source of the MOS transistor Tr11. This is applied to reset the photodiode PD1. Subsequently, as described above, the MOS transistor Tr13 is turned on to be in the selected state, and the reset voltage Vrout is output to the terminal Sout through the source follower of the MOS transistor Tr12 and the MOS transistor Tr13.

  Here, the output voltage Vsout after the light is converted into a voltage is expressed by the following equation.

Vsout = Vpd1-Vth12-Von13 (1)
Vpd1: Optical signal voltage converted by PD1
Vth12: threshold voltage Vth of the MOS transistor Tr12
Von13: ON voltage of the MOS transistor Tr13 The output voltage Vrout after the reset of the photodiode PD1 is expressed by the following equation.

Vrout = Vdd−Vth11−Vth12−Von13 (2)
Vdd: power supply voltage
Vth11: threshold voltage Vth of the MOS transistor Tr11
Vth12: threshold voltage Vth of the MOS transistor Tr12
Von13: On-voltage of MOS transistor Tr13 Here, when the CMOS sensor is a multi-pixel of HD (High Definition) class, it is necessary to convert the output voltage from the pixel at high speed in the configuration in which one ADC circuit is provided. When the number of bits of the output digital signal is large, it is difficult to convert at high speed. For example, when 60 sheets of 1920 pixels in the horizontal direction and 1080 pixels in the vertical direction are read out per second, the conversion speed of 124.4 MHz is required at the minimum in the configuration in which one ADC circuit is provided.

  Therefore, a method of reducing the conversion speed by increasing the number of ADC circuits can be considered. In that case, it can be realized by arranging an ADC circuit for each column. Therefore, conventionally, an ADC circuit for each column is generally added after the CDS circuit 4 (see, for example, Patent Document 1). In some cases, the ADC circuit includes a CDS function for each column (see, for example, Non-Patent Document 1 and Patent Document 2). However, in this case, the circuit configuration becomes complicated.

  However, even when an ADC circuit is arranged for each column, it is usually sufficient to convert the input signal in several μs to several tens of μs, so that it is markedly higher than the high-speed conversion of about 10 ns when one ADC circuit is provided. Although the speed is slow, there is a limit to the time for AD conversion. If a general high-speed ADC circuit is used, this conversion time is sufficient. However, it is difficult to arrange such a high-speed ADC circuit for each column in terms of area, especially when the pixel pitch is narrow, and more ADC circuits are required for the number of columns. Since it is necessary, the power consumption becomes very large and cannot be realized.

  Therefore, an ADC circuit for each column that obtains a digital value by converting a pixel signal into a pulse width modulation (PWM) wave and counting the time is known, as shown in FIG. The ADC circuit for each column having this configuration has a simple circuit configuration, and is highly likely to be used in a place where the pixel pitch is narrow in terms of layout, and power consumption can be reduced.

  FIG. 10 shows a basic configuration diagram of an example of an ADC circuit for each column. As shown in FIG. 10, the ADC circuit for each column has a comparator 7 connected to the vertical signal line 6, an output terminal of the comparator 7 connected to the enable terminal EN, and a clock CLK input to the clock terminal is enabled. And an n-bit counter 8 that counts only when

  The operation of the ADC circuit for each column will be described with reference to the timing chart shown in FIG. A voltage a obtained by converting light is output to the vertical signal line 6 from the MOS transistor Tr13 of the pixel 1 having the configuration shown in FIG. The comparator 7 receives the voltage a shown in FIG. 11A output to the vertical signal line 6 at the negative input terminal and the comparison voltage b of the ramp waveform shown at b in FIG. 11A at the positive input terminal. Is inputted, the input voltages a and b are compared in magnitude, and a signal corresponding to the comparison result is output.

  As shown in FIG. 11B, the output signal of the comparator 7 is high level when the voltage a from the pixel 1 is lower than the comparison voltage b, and low level when the voltage a is higher than the comparison voltage b. , Pulse width modulated (PWM) waveform. The pulse width of the output signal of the comparator 7 changes depending on the level of the voltage a from the pixel 1 because the comparison voltage b has a fixed period. The PWM waveform signal output from the comparator 7 is supplied to the enable terminal EN of the n-bit counter 8.

  The n-bit counter 8 is enabled during the period when the output signal of the comparator 7 is at a high level. During the enable state, the n-bit counter 8 counts the clock CLK shown in FIG. 11C, and is schematically shown in FIG. The n-bit digital signal shown is output. The counter value when the input enable signal of the n-bit counter 8 changes from the high level to the low level is a digital output obtained by AD converting the voltage a from the pixel 1. This is the basic operation of the ADC circuit for each column.

  In addition, a solid-state imaging device including an ADC circuit for each column for the purpose of reducing power consumption with a small number of clocks is also known (see, for example, Patent Document 3). The ADC circuit for each column in the solid-state imaging device described in Patent Document 3 compares the pixel signal with a large stepped staircase by a comparator and corresponds to the number of steps of the staircase when the comparison output is inverted. Is stored in the first latch circuit, and then the second count value corresponding to the number of steps of the step wave when the pixel signal is compared with the step wave of the small step by the comparator and the comparison output is inverted. Is held in the second latch circuit. The ADC circuit for each column outputs a digital signal having the first and second count values held in the first and second latch circuits as upper and lower bits, respectively.

JP 2005-347932 A JP 2006-128752 A JP 2002-232291 A

Kazuya Yonemoto, “Basics and Applications of CCD / CMOS Image Sensors”, CQ Publishing Co., Ltd., p. 201-203

  However, the solid-state imaging device having the ADC circuit for each column shown in FIG. 10 has the following problems.

  (1) In an ADC circuit for each column of a conventional solid-state imaging device, ADC time for PWM of a signal from a pixel, counting the number of clocks corresponding to the pulse width of the PWM signal, and converting it into a digital signal is solid-state imaging. It is necessary to finish within a certain period for all the number of pixels on the same line of the element. For this reason, as the number of pixels of the solid-state imaging device increases, it is necessary to shorten the ADC time per pixel in the ADC circuit. Therefore, it is necessary to increase the clock frequency counted by the n-bit counter 8. However, it may be difficult to increase the clock frequency due to chip area, power consumption, and accuracy issues. There is a possibility that the clock frequency is limited to around 200 MHz, which becomes a problem when high-speed reading is performed by increasing the frame rate in the future.

  (2) In the conventional solid-state imaging device, when increasing the number of bits of the digital signal output from the ADC circuit for each column, it is necessary to double the clock frequency of the n-bit counter 8 to increase one bit. However, it may be difficult to increase the clock frequency for the same reason as described above, and it may be difficult to increase the number of bits of the digital signal.

  Further, in the conventional solid-state imaging device described in Patent Document 3, a large step staircase (first comparison reference voltage corresponding to a ramp waveform) that is compared with a pixel signal by a comparator in order to obtain upper bits of a digital signal, In order to obtain the low-order bits of the digital signal, it is necessary to create a total of two types of step-wise comparison reference voltages, a small stepped wave (second comparison reference voltage corresponding to the ramp waveform) compared with the pixel signal by the comparator. . In this conventional solid-state imaging device, the accuracy of the ADC is determined by correctly creating the above-described two types of comparison reference voltage steps, and in particular, the second comparison reference voltage for the lower bits needs to be accurately produced. Further, the variation for each column is determined by the capacity ratio for holding the comparison reference voltage.

  The present invention has been made in view of the above points, and a signal obtained by comparing a pixel signal with one type of comparison reference signal by a comparator is used with a counter having a bit number smaller than the bit number of the output digital signal. A solid-state imaging device having an ADC circuit for each column and a signal processing method thereof capable of using a low-frequency clock as a clock for the counter by counting, thereby reducing power consumption and improving the accuracy of actual operation The purpose is to provide.

In order to achieve the above object, the solid-state imaging device of the first invention is arranged in the column direction among a plurality of pixels of the solid-state imaging device in which a plurality of pixels each provided with photoelectric conversion means are regularly arranged. Amplifying means for amplifying a signal from the pixel, a ramp waveform generating means for generating a ramp waveform obtained by adding a signal having a constant slope to the pixel signal level output from the amplifying means, and a saturation signal level of the pixel signal in the ramp waveform Output from a plurality of level comparison means for dividing the range into k signal ranges, a plurality of comparison reference signals having different levels from each other, a plurality of level comparison means for separately comparing the ramp waveforms, and a plurality of level comparison means M bits of a value indicating which signal range of the plurality of signal ranges the signal level of the pixel signal output from the amplification means in the ramp waveform belongs to based on the plurality of comparison results However, it outputs the 2 ^M = k), among the plurality of comparison reference signal, and a data processing and selecting means for selecting one of the comparison reference signal defining a belonging and signal range, among the plurality of level comparison means, Counter means for counting a clock and outputting an N-bit count value during a pulse width period of a pulse output from one level comparison means for comparing one selected comparison reference signal with a ramp waveform; A digital signal having M bits as upper bits and an N-bit count value at the end of counting by the counter means as lower bits is output as an AD conversion signal of signals from pixels arranged in the column direction.

In order to achieve the above object, the solid-state imaging device according to the second invention is arranged in the column direction among a plurality of pixels of the solid-state imaging device in which a plurality of pixels each having a photoelectric conversion means are regularly arranged. Amplifying means for amplifying a signal from the pixel, a ramp waveform generating means for generating a ramp waveform obtained by adding a signal having a constant slope to a signal from the pixel output from the amplifying means, and a pixel signal in the ramp waveform In order to divide the saturation signal level range into k signal ranges, a plurality of comparison reference signals having different levels are switched and sequentially output, and a ramp waveform generating unit generates a signal having a constant slope. After the first level comparison is performed between the pixel signal output from the amplifying unit before addition and the plurality of comparison reference signals output from the comparison reference signal generating unit, signals obtained by adding a constant slope are obtained. Level comparison means for performing a second level comparison between the ramp waveform and one comparison reference signal selected and output from the comparison reference signal generation means, and a plurality of comparison results obtained by the first level comparison of the level comparison means. Based on the logical value, M bits of a value indicating to which signal range the signal level from the pixel output from the amplifying means before adding the signal having a constant slope belongs to the signal range (however, 2 ^M = k), and one of the plurality of comparison reference signals to select one comparison reference signal that defines the signal range to which the signal belongs, and to perform the second level comparison by the level comparison means. A selection unit; and a counter unit that counts a clock and outputs an N-bit count value during a pulse width period of a pulse output by the second level comparison by the level comparison unit. A digital signal having M bits as upper bits and an N-bit count value at the end of counting by the counter means as lower bits is output as an AD conversion signal of signals from pixels arranged in the column direction. .

  Here, the ramp waveform generating means includes a capacitor connected between the output terminal of the amplifying means and the signal input terminal of the level comparing means, a constant current source, and a signal input terminal of the constant current source and the level comparing means. A first switch connected between the second switch, a second switch connected in parallel to the capacitor, and only the second switch of the first and second switches is turned on to discharge the capacitor charge. And control means for turning on only the first switch and supplying a constant current from the constant current source to the capacitor through the first switch for a predetermined period of time.

In order to achieve the above object, a signal processing method for a solid-state imaging device according to a fourth aspect of the present invention includes a plurality of pixels of a solid-state imaging device in which a plurality of pixels each provided with photoelectric conversion means are regularly arranged. An amplification step for amplifying signals from pixels arranged in the column direction, a ramp waveform generation step for generating a ramp waveform by adding a signal having a constant slope to the signals from the pixels amplified in the amplification step, Level comparison step and level comparison step for separately comparing a plurality of comparison reference signals having different levels with each other and a ramp waveform for dividing the saturation signal level range of the pixel signal into k signal ranges. The signal level from the pixel amplified in the amplification step in the ramp waveform based on the plurality of comparison results obtained by the signal range of the plurality of signal ranges M-bit value indicating belongs (although, 2 ^M = k) outputs the among the plurality of comparison reference signal, and a data processing and selecting step of selecting one of the comparison reference signal defining a belonging and the signal range A counter step for counting the clock and outputting an N-bit count value for a period of a pulse width of a pulse which is a result of level comparison between the selected comparison reference signal and the ramp waveform, A digital signal having a bit and an N-bit count value at the end of counting by the counter step as a lower bit is output as an AD conversion signal of a signal from pixels arranged in the column direction.

In order to achieve the above object, a signal processing method for a solid-state imaging device according to a fifth aspect of the present invention includes a plurality of pixels of a solid-state imaging device in which a plurality of pixels each having a photoelectric conversion means are regularly arranged. An amplification step for amplifying signals from pixels arranged in the column direction, a ramp waveform generation step for generating a ramp waveform by adding a signal having a constant slope to the signals from the pixels amplified in the amplification step, A comparison reference signal generation step for switching a plurality of comparison reference signals having different levels and sequentially outputting them in order to divide the saturation signal level range of the pixel signal into k signal ranges and a ramp waveform generation step. After performing a first level comparison between the signal from the pixel amplified in the amplification step before adding the slope signal and a plurality of comparison reference signals, the signal having a constant slope is added. A level comparison step for performing a second level comparison between the obtained ramp waveform and one comparison reference signal selected from the plurality of comparison reference signals, and logical values of the plurality of comparison results obtained by the first level comparison. On the basis of this, M bits of a value indicating to which signal range the signal level from the pixel amplified in the amplification step before adding the signal with a constant slope belongs (where 2 ^M = k) and a data processing / selection step of selecting one comparison reference signal defining a signal range to which the signal belongs, from among a plurality of comparison reference signals, and performing a second level comparison in the level comparison step And a counter step for counting the clock and outputting an N-bit count value during the pulse width period of the pulse output by the second level comparison by the level comparison step. The digital signal having the M bit as the upper bit and the N-bit count value at the end of counting by the counter step as the lower bit is output as an AD conversion signal of the signal from the pixels arranged in the column direction. To do.

  According to the present invention, when a digital signal having a predetermined number of bits obtained by AD-converting a signal from each pixel arranged in the column direction is used, a predetermined number of bits is obtained using a counter having a number of bits smaller than the predetermined number of bits. Therefore, the frequency of the clock counted by the counter can be lowered as compared with the conventional case, thereby reducing the power consumption and improving the accuracy of the actual operation.

It is a block diagram of the principal part of 1st Embodiment of the solid-state image sensor of this invention. It is a figure which shows the timing chart etc. for operation | movement description of FIG. It is a figure which shows the structure and table | surface of the principal part of 2nd Embodiment of the solid-state image sensor of this invention. It is a detailed circuit diagram of Example 1 of the solid-state image sensor of the present invention. 5 is a timing chart for explaining the operation of FIG. 4. It is a detailed circuit diagram of Example 2 of the solid-state image sensor of the present invention. 7 is a timing chart for explaining the operation of FIG. 6. It is a block diagram of an example of the conventional CMOS sensor. It is an equivalent circuit diagram of an example of a conventional pixel. It is a basic composition figure of an example of the conventional ADC circuit for every column. 11 is a timing chart for explaining the operation of FIG. 10.

  Next, embodiments of the present invention will be described in detail with reference to the drawings.

(First embodiment)
FIG. 1 is a configuration diagram of a main part of a first embodiment of a solid-state imaging device according to the present invention. In FIG. 1, the solid-state imaging device 10 according to the present embodiment includes a plurality of pixels arranged in a vertical direction such as the pixel 1 among a plurality of pixels arranged in a two-dimensional matrix as in FIG. An operational amplifier 12 in which a single vertical signal line 11 connected in common is connected to a non-inverting input terminal, a constant current source 13, four comparators 14 to 17, and output signals of the comparators 14 to 17 are input. The data processing / selection circuit 18 for latching and decoding these four input signals and selecting one of the four input signals based on the decoding result, and an n-bit counter 19 Each column has an ADC circuit.

  Further, the operational amplifier 12 is configured such that a circuit composed of a resistor R1 and a resistor R2 is feedback-connected between the output terminal and the inverting input terminal, thereby forming a non-inverting amplifier. A reference voltage Vref is applied to one end of the resistor R1. The output terminal of the operational amplifier 12 is commonly connected to the negative input terminals of the comparators 14 to 17 via the capacitor C1 and the switch S2 in parallel. One end of the constant current source 13 is connected to the power supply terminal of the power supply voltage VDD, and the other end is commonly connected to the negative side input terminals of the comparators 14 to 17 via the switch S1. The comparators 14, 15, 16, and 17 are applied with different reference voltages V1, V2, V3, and V4, respectively, at their positive input terminals. The n-bit counter 19 counts the clock signal CLK while a high level enable signal is input from the data processing / selection circuit 18 to the enable terminal EN.

  In the solid-state imaging device 10 of the present embodiment, the circuit shown in FIG. 1 is provided for the number of pixels arranged in the horizontal direction on the same line.

  Next, the operation of the solid-state imaging device 10 of the present embodiment shown in FIG. 1 will be described. A signal of a level corresponding to the intensity of incident light is read from one pixel 1 selected by a vertical selection circuit and a horizontal selection circuit (not shown), and a non-inverting amplifier including an operational amplifier 12 and resistors R1 and R2, for example, Non-inverted amplification is about 4 times. Thus, if the saturation signal level of the signal read from the pixel 1 is 200 mV, the output signal level of the non-inverting amplifier is 800 mV at the time of saturation. Here, when the output signal of the operational amplifier 12 constituting the non-inverting amplifier is Vop, this signal Vop is expressed by the following equation.

Vop = Vi * (R1 + R2) / R1- (R2 / R1) * Vref (3)
In Equation (3), Vi is an output signal from the pixel, R1 and R2 are resistance values of the resistors R1 and R2, and Vref is a reference voltage applied to one end of the resistor R1. A ramp waveform generated by the output signal Vop of the operational amplifier 12, the constant current I1 from the constant current source 13, the capacitor C1, and the switches S1 and S2 is input to the negative input terminal. Specifically, when the time when the output signal Vop of the operational amplifier 12 is determined by amplifying the signal from the pixel is t1, first, the switch S2 is turned on at the time t1 to discharge the capacitor C1. Thereby, the charge Q1 of the capacitor C1 is expressed by the following equation.

Q1 = C1 × 0 = 0 (4)
However, in Formula (4), C1 shows the capacitance value of the capacitor C1 (hereinafter, C1 in the formula shows the capacitance value of the capacitor C1).

  Next, at time t2, the switch S2 is turned off, and at the same time, the switch S1 is turned on so that the current I1 flows from the constant current source 13 into the capacitor C1. Then, the voltage Vp represented by the following expression is applied to the positive side input terminals of the comparators 14 to 17.

Vp = Vop + I1 × T / C1 (5)
However, in the formula (5), T represents a charging time. Equation (5) indicates that the voltage Vp has a ramp waveform whose level increases with time. A thick solid line Vp shown in FIG. 2B indicates this ramp waveform.

  The charging time T is the time from time t2 to time t3 when the switch S1 is turned off. At the timing of this time t3, Vp becomes the highest voltage of the ramp waveform as shown by a thick solid line in FIG. That is, in the solid-state imaging device 10 of the present embodiment, the voltage Vp obtained by adding the ramp waveform of I1 × T / C1 to the signal Vop from the pixel 1 is applied to the negative input terminals of the comparators 14 to 17. Therefore, unlike the prior art, the ramp waveform changes depending on the level of the signal Vi from the pixel 1.

  The comparators 14, 15, 16, and 17 have different DC comparison reference voltages indicated by V1, V2, V3, and V4 in FIG. 2B applied to the positive input terminal, respectively. The ramp waveform voltage Vp supplied to the side input terminal is compared in magnitude and the signals shown in FIGS. 2C, 2D, 2E, and 2F are output. Here, the comparison reference voltages V1, V2, V3, and V4 are voltages assigned as shown in FIG. 2B by dividing the saturation signal voltage from the pixel into four equal parts.

  As a result, the voltage Vp at the time t2 (in this case, since the ramp waveform component is still 0, it may be considered that only the pixel signal voltage Vop) is compared with the comparison reference voltages V1 and V2 shown in FIG. Signal range between (1), signal range between comparison reference voltages V2 and V3 (2), signal range between comparison reference voltages V3 and V4 (3), comparison reference voltage V4 and saturation signal level The upper 2 bits of the digital signal obtained by AD-converting the pixel signal can be determined according to which of the signal range (4) between the pixel signal and the pixel signal. As a result, the output signal periods of the comparators 14 to 17 are within ¼ of all the ramp waveforms, and can be compared in a short time.

  Here, the signals indicated by the solid lines in FIGS. 2C, 2D, 2E, and 2F indicate that the voltage Vp of the ramp waveform indicated by the thick solid line in FIG. 17 shows output signal waveforms of comparators 14, 15, 16, and 17 when applied to 17 negative input terminals.

  As described above, the DC voltage of the ramp waveform voltage Vp varies depending on the signal from the pixel 1. For example, in the case of a ramp waveform having an inclined portion indicated by I in FIG. Changes as indicated by a dotted line in FIG. Similarly, when the voltage Vp is a ramp waveform having an inclined portion indicated by II in FIG. 2B, the output signal of the comparator 15 has a waveform indicated by a dotted line in FIG. In the case of a ramp waveform having an inclined portion indicated by III, the output signal of the comparator 17 becomes a waveform indicated by a dotted line in FIG. As described above, the logical values of the output signals of the comparators 14, 15, 16, and 17 change according to the signal from the pixel 1 as shown in the table of FIG.

  The data processing / selection circuit 18 receives the output signals of the comparators 14, 15, 16, and 17 as input signals, and according to the logical values at the time t2 as shown in the table of FIG. The upper 2 bits are output, and one signal to be output to the n-bit counter 19 is selected from the signals input from the four comparators 14 to 17. Here, the output at the time t2 of the comparators 14, 15, 16, and 17 when the voltage Vp having the ramp waveform indicated by the thick solid line in FIG. 2B is applied to the negative input terminals of the comparators 14 to 17. The logical values of the signals are “1”, “1”, “1”, and “0” as shown in FIGS. 2C, 2D, 2E, and 2F. The selection circuit 18 outputs “10” as the upper 2 bits X1 and X2 of the output digital signal according to the table shown in FIG.

  Note that the data processing / selection circuit 18 determines that the ramp waveform voltage Vp is a ramp waveform when the pixel signal level having the slope portion indicated by I in FIG. Since only the output signal of the comparator 14 is at the high level, “00” is output as the upper 2 bits X1 and X2 of the output digital signal according to the table shown in FIG. Similarly, when the voltage Vp of the ramp waveform is a ramp waveform when the pixel signal level having the slope portion indicated by II in FIG. 2B is relatively small, the pixel signal level having the slope portion indicated by III is large. In the case of the ramp waveform, “01”, “1” as the upper 2 bits X1 and X2 of the output digital signal according to the table shown in FIG. 2A based on the logical value of the output signal of the comparators 14 to 17 at the time t2. 11 "is output. As described above, the data processing / selection circuit 18 outputs the upper 2 bits X1 and X2 of the output digital signal corresponding to the pixel signal level.

  Further, the data processing / selection circuit 18 compares one level higher than the comparison reference voltage of the comparator that outputs a low level signal at time t2 among the four input signals supplied from the comparators 14-17. A comparison is made with the reference voltage, and a signal output from a comparator that outputs a high level signal at time t2 is selected and supplied to the enable terminal EN of the n-bit counter 19. Accordingly, when the voltage Vp having the ramp waveform indicated by the thick solid line in FIG. 2B is applied to the negative side input terminals of the comparators 14 to 17, the data processing / selection circuit 18 performs the processing shown in FIGS. Since the signal indicated by the solid line in F) is supplied from the comparators 14 to 17, the signal supplied from the comparator 16 is selected and supplied to the enable terminal EN of the n-bit counter 19.

  The n-bit counter 19 counts the clock CLK schematically shown in FIG. 2G during the period when the high-level signal selected by the data processing / selection circuit 18 is supplied to the enable terminal EN. The n-bit counter value schematically shown in FIG. Of the n-bit counter value, the pixel value is converted from the counter value when the n-bit counter 19 is not enabled from the enabled state (when the input enable signal changes from high level to low level). Output as the lower n bits of the output digital signal.

  Thus, according to the ADC circuit for each column of the solid-state imaging device 10 of the present embodiment, the signal voltage Vp applied to the negative side input terminals of the comparators 14 to 17 is the right side of the equation (5) at the time t2. The ramp waveform component due to the constant current of the second term is 0, and only the pixel signal voltage Vop output from the non-inverting amplifier. Therefore, in the present embodiment, the signal voltage Vp (that is, the pixel signal voltage Vop) at the time t2 is the pixel saturation signal voltage determined by the comparison reference voltages V1 to V4 (V1> V2> V3> V4). The signal range of the four signal ranges (1) to (4) shown in FIG. 2B divided into four equal parts is detected from the relationship of the logical values of the four output signals of the comparators 14 to 17, The detected signal range is shown as the upper 2 bits of the digital signal obtained by AD converting the pixel signal. Since the signal levels indicated by the signal ranges (1) to (4) are (1) <(2) <(3) <(4), the upper 2 bits are set in the table shown in FIG. To be determined. Here, this table shows the signal ranges (1), (2), (3), and (4) in order from the top.

  In this embodiment, the n-bit counter 19 counts the period of the pulse width of the output signal of the comparator in order to further detect the level position of the pixel signal level in the detection signal range. The measured value is output as the lower n bits of the digital signal obtained by AD converting the pixel signal.

  Therefore, according to the present embodiment, the comparator can actually be compared with ¼ of the normal time, so that the ¼ period is counted by the n-bit counter 19 so as to correspond to one horizontal scanning period of the signal output. By setting the clock frequency, it is possible to count at a clock frequency that is 1/4 lower than usual. Note that the n-bit counter 19 may be an (n-2) -bit counter, and an n-bit digital signal may be output as a whole, including the upper 2 bits from the data processing / selection circuit 18. Further, according to the present embodiment, the step signal is not required, and the reference signal can be composed of one type of reference voltage.

(Second Embodiment)
Next, a second embodiment of the present invention will be described. FIG. 3A shows a configuration diagram of a main part of a second embodiment of the solid-state imaging device according to the present invention. 3, the same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 3A, the solid-state imaging device 20 of the present embodiment includes a comparison reference voltage generator 21, an n-bit counter 23, and a data processing / selection circuit 24, and there are four in FIG. An ADC circuit for each column having a configuration in which only one comparator 22 is used as a comparator is provided. In the solid-state imaging device 20 of the present embodiment, the circuit shown in FIG. 3A is provided for the number of pixels arranged in the horizontal direction on the same line.

  The comparison reference voltage generator 21 generates a comparison reference voltage that is a quaternary step wave. The four values of the comparison reference voltage correspond to the values of the comparison reference voltages V1, V2, V3, and V4 shown in FIG. The data processing / selection circuit 24 compares one of the four comparison reference voltages from the comparison reference voltage generator 21 based on the value obtained by latching the output signal of the comparator 22 by the data processing / selection circuit 24. A reference voltage is selected, and the n-bit counter 23 is enabled by a pulse obtained by comparing the selected comparison reference voltage and the ramp waveform.

  The operation of this embodiment will be described. In the present embodiment, before the n-bit counter 23 is counted at the time when the signal from the pixel is determined, that is, before the ramp waveform is generated, the comparison reference voltage from the comparison reference voltage generator 21 is, for example, V1, The output is changed for each predetermined period in the order of V2, V3, and V4 and supplied to the positive input terminal of the comparator 22. The data processing / selection circuit 24 includes comparison reference voltages V1, V2, V3, and V4 that are switched and input by the comparator 22, and a signal from a non-inverted amplified pixel that is supplied to the negative side input terminal before the ramp waveform is generated. Each time the comparison result is obtained, the comparison result is latched. Subsequently, the data processing / selection circuit 24 decodes the latched four comparison results in accordance with the table shown in FIG. 3B, selects one comparison reference voltage from the four comparison reference voltages V1 to V4, The upper two bits corresponding to the selected comparison reference voltage are output, and the comparison reference voltage selected from the comparison reference voltage generator 21 is generated in a fixed manner during the subsequent ramp waveform generation period described later.

  The table shown in FIG. 3B corresponds to the table shown in FIG. 2A. In the comparator 22, the comparison result with the comparison reference voltage V1 is “1”, and the comparison reference voltages V2 to V4 are When all the comparison results are “0”, that is, when the signal level from the pixel is between V1 and V2, the comparison reference voltage is selected as V1. Similarly, FIG. 3B shows the comparison reference voltage when the signal from the pixel is between V2 and V3 based on the comparison result between the comparison reference voltages V1 to V4 from the comparator 22 and the signal from the pixel. Is selected as V2, and when the signal from the pixel is between V3 and V4, the comparison reference voltage is selected as V3. When the signal from the pixel is between V4 and the saturation level, the comparison reference voltage is V4. Indicates that you want to choose.

  Further, the data processing / selection circuit 24 outputs the upper 2 bits of the digital signal obtained by performing AD conversion of the pixel signal according to the table shown in FIG. 3B corresponding to the selected comparison reference voltage. For example, when the comparison reference voltage V1 is selected, the range in which the signal level from the pixel shows the smallest signal level in the range obtained by equally dividing the saturation level range into four (the range (1) shown in FIG. 2B). Therefore, the value of the upper 2 bits is set to “00”.

  Thereafter, similarly to the solid-state imaging device 10 in FIG. 1, a ramp waveform is generated by the constant current source 13, the switches S1 and S2, and the capacitor C1, and the n-bit counter 23 is configured based on the ramp waveform and the comparison reference voltage determined in advance. An enable signal is generated by the comparator 22. The n-bit counter 23 outputs the lower n bits excluding the upper 2 bits of the AD conversion digital signal of the pixel signal from the n-bit counter 23 by counting the clock CLK while the enable signal is at a high level. The lower n bits are determined by the counter value when the n-bit counter 23 stops the counter when the enable signal changes from the high level to the low level.

  Since the present embodiment can also be compared with 1/4 of the normal time, the frequency of the clock counted by the n-bit counter 23 is set so that this 1/4 period corresponds to one horizontal scanning period of the signal output. Thus, it is possible to count at a clock frequency that is 1/4 lower than usual.

  Next, Example 1 corresponding to the first embodiment of the present invention will be described.

  FIG. 4 shows a circuit diagram of a main part of the first embodiment of the solid-state imaging device according to the present invention. 4, the same components as those in FIG. 1 are denoted by the same reference numerals. In FIG. 4, the solid-state imaging device 30 of this embodiment includes a column-by-column ADC circuit including four comparators 14 to 17. A plurality of pixels arranged in the vertical direction, such as the pixels 1a and 1b, are connected to the vertical signal line 11, and each drain and source are connected to the ends of the vertical signal line 11, respectively. The switch is composed of a channel MOS transistor TR41 and an N-channel MOS transistor TR42, and is connected to the gate of a P-channel MOS transistor TR46 constituting a part of the operational amplifier.

  A constant current source composed of N-channel MOS transistors TR43 and TR44 is connected to a terminal opposite to the vertical signal line 11 of the switch. This constant current source applies a low level voltage to TR41 via the terminal SW1B and a high level voltage to TR42 via the terminal SW1 when reading signals from the pixels 1a, 1b, etc. Is turned on and used as a load of an output source follower circuit such as the pixels 1a and 1b.

  P channel MOS transistors TR45, TR46, and TR47, N channel MOS transistors TR48, TR49, TR50, and TR51, P channel MOS transistors TR52, TR53, TR54, and TR55, and resistors R1 and R2 are shown in FIG. A non-inverting amplifier including the operational amplifier 12 and the resistors R1 and R2 is configured.

  The P-channel MOS transistors TR60 and TR61 constitute the constant current source 13 shown in FIG. 1, and the constant current source is an N-channel MOS transistor TR58 in which the drains and the sources are connected to each other. And a first switch (corresponding to the switch S1 in FIG. 1) including the P-channel MOS transistor TR59. The first switch is commonly connected to the negative side input terminals of the four comparators 14 to 17, while the N-channel MOS transistor TR 56 and the P-channel MOS transistor TR 57 each having the drain and the source connected to each other. Are connected to a common connection point between the transistors TR51 and TR53 and the resistor R2 through a second switch (corresponding to the switch S2 in FIG. 1) and a capacitor C1 in parallel.

  The output terminals of the comparators 14 to 17 are separately connected to the D input terminals of the corresponding D-type flip-flops 31 to 34, and are connected in common to the data selector (D / S) 36. . Each output terminal of the D flip-flops 31 to 34 is connected to the decoder 35. The decoder 35 outputs a select signal to the data selector 36. The D-type flip-flops 31 to 34, the decoder 35, and the data selector 36 constitute the data processing / selection circuit 18 of FIG. 1, and an enable signal is sent from the data selector 36 to an n-bit counter (not shown). Is output.

  Next, the operation of the solid-state imaging device 30 of the first embodiment will be described with reference to the timing chart of FIG. First, at the reset output of the pixels 1a, 1b, etc., the input signal of the terminal SW1 is high for a certain period as shown in FIG. 5H, and the input signal of the terminal SW1B is low for a certain period as shown in FIG. The transistors TR41 and TR42 are turned on, and the constant current source including the transistors TR43 and TR44 is used as a load of the output source follower circuit such as the pixels 1a and 1b.

  After that, at the time t11 after the lapse of a predetermined period, the output of the optical signal from the pixels 1a, 1b, etc. to the vertical signal line 11 is started, and at the same time, as shown in FIGS. While the signal is at a high level and the input signal at the terminal SW1B is at a low level, the input signal at the terminal SW2 is at a high level for a certain period as shown in FIG. 5 (J), and at the terminal SW2B as shown in FIG. The input signal is kept at a low level for a certain period, and the second switch including the transistors TR56 and TR57 is turned on to discharge the capacitor C1.

  In addition, the optical signal from the pixels 1a, 1b and the like input via the vertical signal line 11 is non-inverted and amplified by, for example, about four times by the above-described non-inverted amplifier. Therefore, this non-inverting amplifier amplifies to about 800 mV when the saturation signal level is about 200 mV. This is for improving accuracy of the comparators 14 to 17 and improving S / N. The output signal (amplified optical signal) of this non-inverting amplifier is indicated by Vs in FIG. 5B and is applied to the negative input terminals of the comparators 14 to 17 through the second switch in the on state. . The comparators 14 to 17 respectively compare the comparison reference voltages V1 to V4 having different levels shown in FIG. 5C applied to the respective positive side input terminals with the above-described signal Vs, and compare the levels shown in FIG. The signals O1 to O4 shown in (D) to (G) are output.

  The D-type flip-flops 31 to 34 latch the signals O1 to O4 independently of each other, and then output them to the decoder 35. The decoder 35 outputs the higher-order 2-bit signals X1 and X2 according to the table shown in FIG. 4 based on the relationship between the logical values immediately after the time t11 of the signals supplied from the four D-type flip-flops 31 to 34. To do. In the case of the signals O1 to O4 shown in FIGS. 5D to 5G, the decoder 35 outputs “0” (low level) for the signal X1 and “1” (high level) for the signal X2 according to the above table. . The data selector 36 selects the signal O2 based on the signals X1 and X2.

  Next, at time t13, the input signal to the terminal SW2 shown in FIG. 5 (J) is set to the low level and the input signal to the terminal SW2B shown in FIG. 5 (K) is set to the high level. At the same time as the OFF state, the input signal at the terminal SW3 shown in FIG. 11L is set to the high level and the input signal at the terminal SW3B shown in FIG. The first switch consisting of TR59 is turned on. As a result, the current from the constant current source composed of the transistors TR60 and TR61 is applied to the capacitor C1 through the first switch to charge it.

  As a result, during the period from time t13 to time t15, the terminal voltage of the capacitor C1 rises with time, and the signal applied to the negative input terminal of the comparator has a ramp waveform in the amplified signal Vs from the pixel. The added voltage Vg shown in FIG.

  In this embodiment, a comparator (FIG. 5) that uses a comparison reference voltage (V3 in the example of FIG. 5) that is lower than the comparison reference voltage (V2 in the example of FIG. 5) of the comparator that outputs a high level signal at time t11. When the high level signal is not output in 16) in the example of 4, the output signal of the comparator (15 in the example of FIG. 4) from which the high level signal is output (in the example of FIG. 5). O2) is output from the data selector 36 as described above.

  The signal O2 output from the data selector 36 is ANDed with the input signal of the terminal SW3 shown in FIG. 5 (L) in an AND circuit not shown in FIG. Supplied as The n-bit counter is enabled while the enable signal is input and counts the clock.

  Thus, according to the present embodiment, the count number of the n-bit counter can be reduced, and the upper 2 bits can be created using the decode values X1 and X2. Thereby, according to the solid-state imaging device 30 of the present embodiment, the count time can be shortened if the clock frequency is the same as the conventional one, and if the number of bits of the counter is, for example, (n-2) bits, It is possible to reduce the clock frequency to be lower than before.

  Next, Example 2 corresponding to the second embodiment of the present invention will be described.

  FIG. 6 shows a circuit diagram of a main part of a solid-state imaging device according to a second embodiment of the present invention. In FIG. 6, the same components as those in FIG. 3A are denoted by the same reference numerals. The solid-state imaging device 40 of the present embodiment shown in FIG. 6 shows a detailed circuit of a portion excluding the n-bit counter 23 and the data processing / selection circuit 24 in the basic configuration of the column ADC circuit shown in FIG. . The data processing / selection circuit 24 can be composed of one D-type flip-flop, a decoder, and a data selector, as in FIG.

  The n-bit counter is a commonly used n-bit synchronous counter, and counts up the clock during a period in which an enable signal (in this case, enabled at a high level) is input. In order to perform the CDS operation, the comparator output period based on the reset signal voltage is counted down, and the comparator output period based on the optical signal voltage is counted up, and subtraction may be performed.

  A plurality of pixels arranged in the vertical direction, such as the pixels 1a and 1b, are connected to the vertical signal line 11, and each drain and source are connected to the ends of the vertical signal line 11, respectively. The switch is composed of a channel MOS transistor TR3 and an N channel MOS transistor TR4, and is connected to the gate of a P channel MOS transistor TR6 that constitutes a part of the operational amplifier.

  A constant current source composed of N-channel MOS transistors TR1 and TR2 is connected to a terminal opposite to the vertical signal line 11 of the switch. This constant current source applies a low level voltage to TR3 via a terminal SW1B and a high level voltage to TR4 via a terminal SW1 when reading signals from the pixels 1a, 1b, etc. Is turned on and used as a load of an output source follower circuit such as the pixels 1a and 1b.

  P channel MOS transistors TR5, TR6, and TR7, N channel MOS transistors TR8, TR9, TR10, and TR11, P channel MOS transistors TR12, TR13, TR14, and TR15, and resistors R1 and R2 are shown in FIG. A non-inverting amplifier including the operational amplifier 12 and the resistors R1 and R2 is configured.

  The P-channel MOS transistors TR20 and TR21 constitute the constant current source 13 shown in FIG. 3, and the constant current source is an N-channel MOS transistor TR18 in which the drains and the sources are connected to each other. And a first switch (corresponding to the switch S1 in FIG. 3) composed of the P-channel MOS transistor TR19. The first switch is connected to the gate of the P-channel MOS transistor TR23 (a negative input terminal of the comparator) constituting a part of the comparator, while the N-channel is connected to each other's drain and source. A second switch (corresponding to the switch S2 in FIG. 3) composed of the MOS transistor TR16 and the P-channel MOS transistor TR17 and a capacitor C1 are connected in parallel to a common connection point between the transistors TR11 and TR13 and the resistor R2. Yes.

  The P-channel MOS transistors TR22, TR23, and TR24, the N-channel MOS transistors TR25, TR26, TR27, and TR28, and the P-channel MOS transistors TR29, TR30, TR31, and TR32 are comparators corresponding to the comparator 22 in FIG. Is configured.

  A third switch composed of an N channel MOS transistor TR33 and a P channel MOS transistor TR34, a fourth switch composed of an N channel MOS transistor TR35 and a P channel MOS transistor TR36, an N channel MOS transistor TR37 and a P channel The fifth switch composed of the MOS transistor TR38 and the sixth switch composed of the N-channel MOS transistor TR39 and the P-channel MOS transistor TR40 constitute the comparison reference voltage generation circuit 21 of FIG. In the third switch to the sixth switch, the comparison reference voltages V1 to V4 having different levels are input to one terminal, respectively, and the other terminal is the transistor TR24 that is the positive input terminal of the comparator 22 in common. Connected to the gate.

  Next, the operation of the solid-state imaging device 40 of the second embodiment will be described with reference to the timing chart of FIG. The operation in the period in which the reset output signal is input from the pixels 1a, 1b and the like illustrated in FIG. 7A via the vertical signal line 11 is the same as that of the first embodiment illustrated in FIG.

  Subsequently, at time t21, output of an optical signal from the pixels 1a, 1b, etc. to the vertical signal line 11 is started, and at the same time, as shown in FIGS. 7H and 7I, the input signal at the terminal SW1 is at a high level. The input signal at the terminal SW1B is at a low level, while the input signal at the terminal SW2 is at a high level for a certain period as shown in FIG. 7J, and the input signal at the terminal SW2B is constant as shown in FIG. During the period, the second switch including the transistors TR16 and TR17 is turned on to discharge the capacitor C1.

  In addition, the optical signal from the pixels 1a, 1b and the like input via the vertical signal line 11 is non-inverted and amplified by, for example, about four times by the above-described non-inverted amplifier. The output signal (amplified optical signal) of the non-inverting amplifier is indicated by Vs in FIG. 7B and is applied to the gate of the transistor TR23 which is the negative side input terminal of the comparator 22.

  On the other hand, the comparison reference voltage generator 21 outputs the comparison reference voltage V1 by turning on the transistors TR33 and TR34 by the signals of the terminals S1 and S1B shown in FIGS. Subsequently, during the period from time t22 to t23, the transistors TR35 and TR36 are turned on by the signals of the terminals S2 and S2B shown in FIGS. 7Q and 7R, and the comparison reference voltage V2 is output. Similarly, in the comparison reference voltage generator 21, the transistors TR37 and TR38 are turned on by the signals of the terminals S3 and S3B shown in FIGS. 7S and 7T during the period from time t23 to t24, and the comparison reference voltage V3. Subsequently, the transistors TR39 and TR40 are turned on by the signals of the terminals S4 and S4B shown in FIGS. 7 (U) and 7 (V) during the period from time t24 to t25, and the comparison reference voltage V4 is output. That is, as shown in FIG. 7C, the comparison reference voltage generator 21 switches and outputs the comparison reference voltages V1 to V4 at regular intervals and applies them to the gate of the transistor TR24 which is the positive side input terminal of the comparator 22. To do.

  The comparator 22 compares the signal Vs from the pixel with the comparison reference voltages V1 to V4 that are sequentially input, and outputs the comparison result. FIG. 7D shows the output signal COUT (1) of the comparator 22 when the signal (optical signal) Vs from the pixel is between the comparison reference voltages V1 and V2. Similarly, FIG. 7E shows the output signal COUT (2) of the comparator 22 when the signal (optical signal) Vs from the pixel is between the comparison reference voltages V2 and V3, and FIG. The output signal COUT (3) of the comparator 22 when it is between the comparison reference voltages V3 and V4, (G) shows the output of the comparator 22 when Vs is between the comparison reference voltage V4 and the saturation signal level. Signal COUT (4) is shown.

  The relationship between the values of the output signals COUT (1) to COUT (4) of the comparator 22 and the comparison reference voltages V1 to V4 is as shown in the table of FIG. Then, the comparison reference voltage to be input to the comparator 22 is also determined. Here, taking as an example the case where the signal Vs from the pixel is in the signal range (2) shown in FIG. 2B between the comparison reference voltages V2 and V3, the comparison reference voltage applied to the comparator 22 is V2. FIG. 7E shows that the comparison reference voltage generator 21 outputs only the comparison reference voltage V2 after time t25.

  After that, at time t26, the input signal at the terminal SW2 shown in FIG. 7 (J) is set to the low level and the input signal at the terminal SW2B shown in FIG. 7 (K) is set to the high level. At the same time as the state, during the period up to time t27, the input signal at the terminal SW3 shown in (L) in the figure is set to the high level, and the input signal at the terminal SW3B shown in (M) is set at the low level. The first switch consisting of is turned on. As a result, the constant current Ic from the constant current source composed of the transistors TR20 and TR21 is applied to the capacitor C1 through the first switch to charge it.

  As a result, during the period from time t26 to time t27, the terminal voltage of the capacitor C1 increases with time. The terminal voltage Vg of the capacitor C1 when the constant current Ic is supplied at this time is expressed by the following equation.

Vg = Vs + Icxt / C1 (6)
In the equation (6), t represents a constant current injection time, and C1 represents a capacitance value of the capacitor C1. As can be seen from the equation (6), a ramp waveform in which the voltage Vg rises linearly with the injection time t is obtained. That is, the signal applied to the negative side input terminal of the comparator 22 is the voltage Vg shown in FIG. 7N obtained by adding the ramp waveform to the amplified signal Vs from the pixel.

  The comparator 22 compares the voltage Vg with the comparison reference voltage V2, and outputs the signal COUT (2) shown in FIG. 7E as an enable signal to the n-bit counter.

  In the above embodiments and examples, the signal range is divided into four, and the upper 2 bits based on the comparison result in which the signal range of the signal range belongs to which the signal from the pixel belongs is compared. However, in the present invention, the number of divisions of the signal range and the number of upper bits are not limited to this.

1, 1a, 1b Pixel 2 Vertical selection circuit 3 Horizontal selection circuit 4 CDS circuit 5 Amplifier (AMP)
10, 20, 30, 40 Solid-state imaging device 11 Vertical signal line 12 Operational amplifier 13 Constant current source 14-17, 22 Comparator 18 Data processing / selection circuit 19, 23 n-bit counter 21 Comparison reference voltage generator 31-34 D-type flip-flop 35 Decoder 36 Data selector (D / S)
C1 Capacitor R1, R2 Resistance V1-V4 Comparison reference voltage S1, S2 Switch

Claims (6)

Amplifying means for amplifying signals from the pixels arranged in the column direction among the plurality of pixels of the solid-state imaging device in which a plurality of pixels each having photoelectric conversion means are regularly arranged;
A ramp waveform generating means for generating a ramp waveform obtained by adding a signal having a constant slope to the pixel signal level output from the amplifying means;
A plurality of comparison reference signals having different levels for dividing the saturation signal level range of the pixel signal in the ramp waveform into k signal ranges and a plurality of levels for separately comparing the levels of the ramp waveform. A comparison means;
Based on a plurality of comparison results output from the plurality of level comparison units, to which signal range of the plurality of signal ranges a signal level of the pixel signal output from the amplification unit in the ramp waveform belongs Data processing / selecting means for outputting M bits (2 ^M = k) having a value indicating, and selecting one comparison reference signal defining the signal range to which the signal belongs, among the plurality of comparison reference signals ,
Among the plurality of level comparison means, the clock is counted for a period of the pulse width of a pulse output from one level comparison means for comparing the selected one comparison reference signal with the ramp waveform, and N bits are obtained. Counter means for outputting a count value, from the pixels arranged in the column direction, digital signals having the M bits as upper bits and the N bit count value at the end of counting by the counter means as lower bits A solid-state image pickup device that outputs the signal as an AD conversion signal. The ramp waveform generating means includes
A capacitor connected between the output terminal of the amplification means and the signal input terminal of the level comparison means;
A constant current source;
A first switch connected between the constant current source and a signal input terminal of the level comparison means;
A second switch connected in parallel to the capacitor;
After only the second switch of the first and second switches is turned on to discharge the charge of the capacitor, only the first switch is turned on and a constant current from the constant current source is supplied for a predetermined period of time. The solid-state imaging device according to claim 1, further comprising: a control unit that supplies the capacitor through the switch of 1 and charges the capacitor. Amplifying means for amplifying signals from the pixels arranged in the column direction among the plurality of pixels of the solid-state imaging device in which a plurality of pixels each having photoelectric conversion means are regularly arranged;
A ramp waveform generating means for generating a ramp waveform obtained by adding a signal having a constant slope to a signal from the pixel output from the amplifying means;
Comparison reference signal generating means for switching and sequentially outputting a plurality of comparison reference signals having different levels for dividing the saturation signal level range of the pixel signal in the ramp waveform into k signal ranges;
A first level comparison between the pixel signal output from the amplifying means before adding the constant slope signal by the ramp waveform generating means and the plurality of comparison reference signals output from the comparison reference signal generating means Level comparison means for performing a second level comparison between the ramp waveform obtained by adding the constant slope signals and one comparison reference signal selected and output from the comparison reference signal generation means,
The level of the signal from the pixel output from the amplifying means before adding the constant slope signal based on a plurality of comparison result logical values obtained by the first level comparison of the level comparing means Outputs M bits (2 ^M = k) having a value indicating which signal range of the plurality of signal ranges belongs to, and the signal range to which the comparison reference signal belongs belongs to A data processing / selection unit that selects one comparison reference signal to be determined, and causes the second level comparison to be performed by the level comparison unit;
Counter means for counting a clock and outputting an N-bit count value during a period of a pulse width of a pulse output by the second level comparison by the level comparison means, wherein the M bit is an upper bit, A solid-state imaging device, characterized in that a digital signal having the N-bit count value at the end of counting by the counter means as a lower bit is output as an AD conversion signal of a signal from the pixels arranged in a column direction. The ramp waveform generating means includes
A capacitor connected between the output terminal of the amplification means and the signal input terminal of the level comparison means;
A constant current source;
A first switch connected between the constant current source and a signal input terminal of the level comparison means;
A second switch connected in parallel to the capacitor;
Only the second switch of the first and second switches is turned on to discharge the charge of the capacitor, and then only the first switch is turned on to supply a constant current from the constant current source for a predetermined period of time. The solid-state imaging device according to claim 3, further comprising a control unit that supplies the capacitor through the switch of 1 and charges the capacitor. An amplification step for amplifying signals from the pixels arranged in the column direction among the plurality of pixels of the solid-state imaging device in which a plurality of pixels each having photoelectric conversion means are regularly arranged;
A ramp waveform generating step for generating a ramp waveform obtained by adding a signal having a constant slope to the signal from the pixel amplified in the amplification step;
A level comparison step for separately comparing a plurality of comparison reference signals having different levels and the ramp waveform separately to divide the saturated signal level range of the pixel signal in the ramp waveform into k signal ranges. When,
Based on a plurality of comparison results obtained by the level comparison step, to which signal range of the plurality of signal ranges a level of a signal from the pixel amplified in the amplification step in the ramp waveform belongs A data processing / selection step of outputting M bits (2 ^M = k) of the indicated value and selecting one comparison reference signal defining the signal range to which the signal belongs, among the plurality of comparison reference signals;
A counter step of counting a clock and outputting an N-bit count value for a period of a pulse width of a pulse that is a result of level comparison between the selected one comparison reference signal and the ramp waveform; Is a high-order bit, and a digital signal having the N-bit count value at the end of counting by the counter step as a low-order bit is output as an AD conversion signal of a signal from the pixels arranged in the column direction. A signal processing method for a solid-state imaging device. An amplification step for amplifying signals from the pixels arranged in the column direction among the plurality of pixels of the solid-state imaging device in which a plurality of pixels each having photoelectric conversion means are regularly arranged;
A ramp waveform generating step for generating a ramp waveform obtained by adding a signal having a constant slope to the signal from the pixel amplified in the amplification step;
A comparison reference signal generation step of switching and sequentially outputting a plurality of comparison reference signals having different levels for dividing the saturation signal level range of the pixel signal in the ramp waveform into k signal ranges;
After performing a first level comparison between the signal from the pixel amplified in the amplification step and the plurality of comparison reference signals before adding the constant slope signal in the ramp waveform generation step, the constant slope A level comparison step of performing a second level comparison between the ramp waveform obtained by adding the signals and a comparison reference signal selected from the plurality of comparison reference signals;
Based on the logical values of the plurality of comparison results obtained by the first level comparison, the level of the signal from the pixel amplified in the amplification step before adding the signal having the constant slope is the plurality of signals. M bits (2 ^M = k) having a value indicating which signal range of the range are output, and one comparison reference for defining the signal range to which the plurality of comparison reference signals belong A data processing / selection step of selecting a signal and causing the second level comparison to be performed in the level comparison step;
A counter step of counting a clock and outputting an N-bit count value for a period of a pulse width of a pulse output by the second level comparison by the level comparison step, wherein the M bit is an upper bit, A signal processing of a solid-state imaging device, characterized in that a digital signal having the N-bit count value at the end of counting by a counter step as a lower bit is output as an AD conversion signal of signals from the pixels arranged in a column direction Method.

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