JP2010181823A - Reference voltage generating circuit and display panel driving device using the same - Google Patents

Reference voltage generating circuit and display panel driving device using the same Download PDF

Info

Publication number
JP2010181823A
JP2010181823A JP2009027621A JP2009027621A JP2010181823A JP 2010181823 A JP2010181823 A JP 2010181823A JP 2009027621 A JP2009027621 A JP 2009027621A JP 2009027621 A JP2009027621 A JP 2009027621A JP 2010181823 A JP2010181823 A JP 2010181823A
Authority
JP
Japan
Prior art keywords
reference voltage
connected
terminal
ladder
voltage terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2009027621A
Other languages
Japanese (ja)
Inventor
Narakazu Shimomura
奈良和 下村
Original Assignee
Sharp Corp
シャープ株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp, シャープ株式会社 filed Critical Sharp Corp
Priority to JP2009027621A priority Critical patent/JP2010181823A/en
Publication of JP2010181823A publication Critical patent/JP2010181823A/en
Application status is Pending legal-status Critical

Links

Images

Abstract

A reference voltage generation circuit having a high withstand value in a latch-up withstand test and a display panel driving device using the same are provided by preventing changes in the ladder resistance value and disconnection of the ladder resistance in the latch-up withstand test. A reference voltage generation circuit that generates a reference voltage used for the operation of another circuit and outputs the reference voltage to the other circuit, and includes a plurality of ladder resistors for generating the reference voltage, The voltage applied to the ladder resistor is connected to a plurality of reference voltage terminals, and the reference voltage terminal includes a first reference voltage terminal connected to the external power supply and a second reference voltage terminal not connected to the external power supply. In the ladder resistor, the width of the ladder resistor connected to the second reference voltage terminal is wider than the width of the ladder resistor connected to the first reference voltage terminal.
[Selection] Figure 1

Description

  The present invention relates to a reference voltage generation circuit used in a D / A converter or the like, and more particularly to a reference voltage generation circuit used in a driver LSI for driving a display panel.

  A D / A converter using a reference voltage generating circuit formed by a ladder resistor has been often used conventionally, and various devices for improving the conversion accuracy have been invented. For example, Patent Document 1 discloses a technique in which ladder resistors are meandered and arranged so that the resistance values are all equal including the turn-around point of the resistor array and the reference voltage can be divided with high accuracy.

  FIG. 4 is a configuration diagram of a D / A converter 40 using a reference voltage generation circuit formed by a ladder resistor. Here, for ease of explanation, a 3-bit D / A converter is illustrated.

  In the D / A converter 40 shown in FIG. 4, ladder resistors R1 to R7 are connected in series between a V7 terminal that supplies a high voltage side reference voltage and a V0 terminal that supplies a low voltage side reference voltage, and R1 and the GND potential are connected. Between these, a ladder resistor R0 is connected in series. The ladder resistors R0 to R7 are connected to MOS transistors Q0 to Q7 that perform a switching operation. One ends of the MOS transistors Q0 to Q7 are connected in common and connected to the non-inverting input terminal of the operational amplifier U1. The operational amplifier U1 operates as a unity gain amplifier. Although not shown in FIG. 4, the gate electrodes of the MOS transistors Q0 to Q7 are connected to a digital input signal through a decoder. In order to protect the D / A converter 40 against inflow of static electricity from the outside, diodes DP0, DN0, DP7, DN7 are connected to the V0 terminal and the V7 terminal.

  The D / A converter 40 using the ladder resistor performs the following operation. In the D / A converter 40, the decoder selects the MOS transistor Qi (i = 0 to 7) according to the digital input signal, and turns on the selected MOS transistor Qi. Here, if the voltages applied to the V0 terminal and the V7 terminal are V0 and V7, the voltage V = {(R0 + R1 + R2 +... + Ri) / ( R1 + R2 +... + R7)} * (V7−V0) is input. The operational amplifier U1 operates as a unity gain amplifier, and the output voltage Vref becomes the same voltage as the non-inverting input terminal voltage.

  In the display panel driver LSI, a D / A converter is generally used to adjust the density of the display panel. The display panel drive driver LSI converts the input digital signal indicating the gray scale of the display panel into an analog signal that allows the display panel to control the gray scale, and outputs the converted analog signal to the display panel. For example, an 8-bit display panel driving driver LSI can display 256 gray levels, and a 10-bit display panel driving driver LSI can display 1024 gray levels. The relationship between the digital signal (input signal) indicating grayscale and the analog signal voltage to be output is called “gamma characteristic”. The driver LSI for driving the display panel uses the gamma characteristic according to the characteristics of the display panel. Adjust.

  In a general D / A converter, as shown in FIG. 4, there are two terminals for supplying a reference voltage from the outside. Therefore, the analog signal voltage output from the D / A converter is determined by the resistance value ratio of the ladder resistor. However, in the display panel driving driver LSI, a voltage is applied to a predetermined ladder resistor from the outside in order to adjust the gamma characteristic in detail.

  FIG. 5 is a configuration diagram of the D / A converter 50 used in the display panel driver LSI. As shown in FIG. 5, the D / A converter 50 includes a V5 terminal that provides an intermediate reference voltage between a V7 terminal that provides a high-voltage side reference voltage and a V0 terminal that provides a low-voltage side reference voltage. If the voltage applied to the V5 terminal is V5, the voltage at the non-inverting input terminal of the operational amplifier U1 is V = {(R0 + R1 + R2 + ... + Ri) / (R1 + R2 + ... + R5) when 0 ≦ i ≦ 5. } * (V5−V0). When i = 6, V = {R6 / (R6 + R7)} * (V7−V5). When i = 7, V = V7.

  As described above, the D / A converter 50 applies the intermediate reference voltage (V5 in FIG. 5) other than the high-voltage side reference voltage V7 and the low-voltage side reference voltage V0 from the outside to thereby output the output voltage Vref. It becomes possible to adjust. As a result, the display panel drive driver LSI having the D / A converter 50 as shown in FIG. 5 has a more detailed gamma than the display panel drive driver LSI having the D / A converter 40 as shown in FIG. The characteristics can be adjusted. In the example shown in FIG. 5, one intermediate reference voltage is added to the 3-bit D / A converter. However, the more the number of intermediate reference voltages added, the more detailed adjustment of the gamma characteristic is. It becomes possible.

  Recent display panel drive driver LSIs often have more than 8 to 10 bits of gradation, and the number of intermediate reference voltage terminals also ranges from 8 to 20. A display panel driving driver LSI that uses a D / A converter having a plurality of intermediate reference voltage terminals is an external display panel driving driver for a plurality of display panels having different characteristics. By applying to the LSI, different gamma characteristics desired by a plurality of display panels can be obtained.

  The ladder resistor of the D / A converter is often formed of a polysilicon resistor, and the width of the polysilicon resistor is often laid out with a narrow width of about 1 to 10 μm in order to prevent an increase in layout occupation area. In addition, since the current value consumed by the ladder resistor is preferably small, the width of the polysilicon resistor is desirably narrow in order to increase the ladder resistance value.

JP-A-4-273401 (published on September 29, 1992)

  However, if a ladder resistor is laid out with a narrow polysilicon resistor width, there may be inconveniences in a latch-up resistance test, which is one of LSI quality confirmation tests.

  One of the latch-up withstand test methods is a pulse current injection method, which is defined as EIAJ ED-4701 / 300 in the Japan Electronics and Information Technology Industries Association Standard (JEITA). The pulse current injection method is to determine whether or not the LSI is in a latch-up state by injecting a pulse current from the outside to the terminal of the LSI with a power supply voltage applied to the LSI. Since the larger the pulse current that is injected, the more likely the LSI will be in a latch-up state, whether the LSI is likely to latch-up with the magnitude of the pulse current value required to reach the latch-up state (ie, the latch-up tolerance). Is shown.

  In general, a value of 100 mA is often used as an example of a reference value of a pulse current for determining the strength of latch-up tolerance. In other words, whether or not the LSI is in a latch-up state when a 100 mA pulse current is injected indicates the latch-up tolerance of the LSI.

  In the display panel driver LSI, the reference voltage terminal used in the D / A converter may also be the terminal to be evaluated in the latch-up resistance test. Since the reference voltage terminal is a terminal connected to an external power supply, it is not normally an evaluated terminal for a latch-up resistance test. However, a display panel driving driver LSI having a wide range of compatible display panel specifications and versatility may have a reference voltage terminal that is not connected to an external power supply. Such a reference voltage terminal that is not connected to the external power source is a terminal to be evaluated in the latch-up resistance test.

  Here, FIG. 6 shows an example of a configuration diagram of the D / A converter 60 of the display panel driver LSI including a reference voltage terminal that is not connected to an external power supply. The D / A converter 60 includes a V6 terminal that is a reference voltage terminal that is not connected to an external power supply in addition to the configuration of the D / A converter 50 shown in FIG. The V6 terminal is connected between the V7 terminal and the V5 terminal, that is, connected to the ladder resistors R6 and R7. Further, the diodes DP6 and DN6 are connected to the V6 terminal similarly to the V0, V5, and V7 terminals.

  The reason why the display panel driving driver LSI is provided with a reference voltage terminal that is not connected to an external power source is to reduce the manufacturing cost of the display panel and to share parts. This is because, by using the same display panel driving driver LSI for a plurality of types of display panels, the display panel driving driver LSI can be expected to reduce the cost due to the mass production effect, and consequently the manufacturing cost of the display panel can be reduced.

  As described above, the reference voltage terminal not connected to the external power source includes an intermediate reference voltage terminal. These become terminals to be evaluated in the latch-up withstand test, and the following problems may occur in the latch-up test.

  An example of a failure in the latch-up withstand test for the intermediate reference voltage terminal will be described with reference to FIG.

  FIG. 7 shows the V0 terminal, the V5 terminal, and the V7 terminal that are connected to the external power supply, and the V6 terminal that is not connected to the external power supply. Since the voltages V0, V5, and V7 are applied from the outside to the V0 terminal, the V5 terminal, and the V7 terminal, respectively, they are not evaluated terminals for the latch-up resistance test. On the other hand, the V6 terminal is a terminal to be evaluated because no voltage is applied from the outside.

  Here, consider a case where a negative pulse current injection test based on the GND potential is performed on the V6 terminal. The current value I6 drawn from the V6 terminal is applied to a current IR7 flowing through the ladder resistor R7 of the D / A converter 60, a current IR6 flowing through the ladder resistor R6, and an ESD (Electrostatic Discharge) protection diode DN6 provided at the V6 terminal. This is the sum of the flowing current IDN6.

  A terminal voltage when the current value I6 is extracted from the V6 terminal is V6. When the value of the terminal voltage V6 becomes −0.6 V or less, the ESD protection diode DN6 provided at the V6 terminal is in a forward bias state, so that a current flows. On the other hand, since the ESD protection diode DP6 never enters the forward bias state, no current flows through the DP6. Therefore, the current value drawn from the V6 terminal is I6 = IR7 + IR6 + IDN6.

  However, the terminal voltage of the V6 terminal does not suddenly become −0.6 V or less during the pulse current injection test. Therefore, the ESD protection diode DN6 does not enter the forward bias state in the transient state. Therefore, since no current flows through the ESD protection diode DN6 in the transient state, the current value drawn from the V6 terminal is I6 = IR7 + IR6. Furthermore, the currents IR7 and IR6 of the ladder resistance are IR7 = (V7−V6) / R7 and IR6 = (V6−V5) / R6.

  Since the terminal voltage of the reference voltage terminal V6 becomes 0V in the transient state of the pulse current injection test, if V6 = 0 is substituted, the current values IR7 and IR6 of the ladder resistance are IR7 = V7 / R7 and IR6 = −V5 / R6. It becomes. As described above, in the transient state of the pulse current injection test, the current IR7 (= V7 / R7) flowing from the reference voltage terminal serving as the terminal to be evaluated to the ladder resistor R7 and the current IR6 flowing to the ladder resistor R6 (= −V5 / R6). The sum of currents is drawn.

  In the display panel drive driver LSI, values of V7 = 10 to 18V, V5 = 9 to 17V, and R7 = R6 = 100 to 1000Ω are used. Therefore, the current flowing through the ladder resistor is IR7 = 10 to 180 mA, IR6 = -9 to -170 mA.

  FIG. 8 shows the relationship between the applied current and the width of the polysilicon resistor when a current is applied to the polysilicon resistor and the resistance value changes by 10%. FIG. 8 shows measured values in a composite film of a polysilicon film having a thickness of 200 nm and a refractory metal silicide film having a thickness of 50 nm. When calculated based on this drawing, the resistance of the polysilicon resistor used for the ladder resistor changes when a current of about 35 mA per unit width flows, and breaks when a current of about 70 mA per unit width flows.

  As described above, since the ladder resistor is formed of a polysilicon resistor having a width of about 1 to 10 μm, when a current of about 35 to 350 mA flows, the resistance value of the ladder resistor changes and a current of about 70 to 700 mA is generated. When it flows, the ladder resistance breaks. The D / A converter does not operate with a desired function only by changing the resistance value of the ladder resistor. In other words, when the reference voltage applied from the outside is high and the ladder resistance value is low, a large current flows through the ladder resistance, so that the ladder resistance value changes by performing a pulse current injection test and operates with the desired function. No longer. As a result, there is a problem that the result of the latch-up withstand test becomes a low withstand value.

  In the present invention, in view of the above points, a reference voltage generation circuit having a high withstand value of the latch-up withstand test and a reference voltage generation circuit using the same are used by preventing changes in the ladder resistance value and disconnection of the ladder resistance in the latch-up withstand test. An object is to provide a display panel driving device.

  In order to solve the above problems, a reference voltage generation circuit according to the present invention is a reference voltage generation circuit that generates a reference voltage used for the operation of another circuit and outputs the reference voltage to the other circuit. The ladder resistor is connected to a plurality of reference voltage terminals for applying a voltage to the ladder resistor, and the reference voltage terminal is connected to an external power source. The ladder resistor includes a reference voltage terminal and a second reference voltage terminal that is not connected to an external power source. The width of the ladder resistor connected to the second reference voltage terminal is equal to the first reference voltage terminal. It is characterized by being wider than the width of the ladder resistor connected.

  In order to solve the above problems, a display panel driving device according to the present invention is a display panel driving device that performs display by driving a display panel, and includes the reference voltage generation circuit described above or below. It is characterized by.

  According to the above configuration, in the reference voltage generation circuit according to the present invention, among the plurality of ladder resistors for generating the reference voltage, the second reference voltage terminal that is the target of the latch-up resistance test and is not connected to the external power supply The width of the ladder resistor connected to is wider than the width of the ladder resistor connected to the first reference voltage terminal connected to the external power supply. Therefore, it is possible to prevent a change in the ladder resistance value and disconnection of the ladder resistance during the latch-up resistance test, and a reference voltage generation circuit having a high resistance value in the latch-up resistance test can be formed. In addition, since only the width of the ladder resistor connected to the second reference voltage terminal is widened, generation of a reference voltage having a high withstand value in the latch-up withstand test as described above is achieved while minimizing an increase in layout occupation area. A circuit can be formed.

  Further, according to the above configuration, in the display panel driving device according to the present invention, the reference voltage generating circuit having a high withstand value in the latch-up withstand test can be provided while minimizing the increase in layout occupation area as described above. Therefore, it is possible to ensure high reliability of the operation while maintaining the small size of the apparatus.

  As described above, the present invention prevents the change in the ladder resistance value and the disconnection of the ladder resistance in the latch-up withstand test, so that the reference voltage generation circuit having a high withstand value in the latch-up withstand test and the display panel drive using the same There exists an effect that an apparatus can be provided.

  In the reference voltage generation circuit according to the present invention, the width of the ladder resistor connected to the second reference voltage terminal preferably satisfies the following expression (1).

W> ((Vs + 0.6) / (Rp * Ic)) (1)
W: width of a ladder resistor connected to a second reference voltage terminal not connected to the external power supply Vs: voltage Rp applied to a first reference voltage terminal connected to the external power supply: second reference not connected to the external power supply Resistance value Ic of ladder resistor connected to voltage terminal: Applied current value per unit width causing resistance value change According to the above configuration, the reference voltage generating circuit according to the present invention is connected to the second reference voltage terminal. The width W of the ladder resistor satisfies W> ((Vs + 0.6) / (Rp * Ic)). Therefore, it is possible to determine the optimum ladder resistance width that can prevent the change in the ladder resistance value and the disconnection of the ladder resistance during the latch-up resistance test. Therefore, there is an effect that it is possible to form a reference voltage generation circuit having a high withstand value of the latch-up withstand test as described above while suppressing an increase in layout occupation area to a minimum.

  The reference voltage generation circuit according to the present invention is preferably used together with the D / A converter circuit as the other circuit.

  According to the above configuration, since the reference voltage generation circuit according to the present invention is used together with the D / A converter circuit as the other circuit, high reliability can be ensured in the operation of the D / A converter circuit. There is an effect.

  As described above, the reference voltage generation circuit according to the present invention is a reference voltage generation circuit that generates a reference voltage used for the operation of another circuit and outputs the reference voltage to the other circuit, and generates the reference voltage. The ladder resistor is connected to a plurality of reference voltage terminals for applying a voltage to the ladder resistor, and the reference voltage terminal is connected to an external power source. The ladder resistor is connected to the second reference voltage terminal, and the width of the ladder resistor connected to the second reference voltage terminal is connected to the first reference voltage terminal. It is characterized by being wider than the width of the ladder resistor.

  Accordingly, it is possible to provide a reference voltage generation circuit having a high withstand value in a latch-up withstand test and a display panel driving device using the same by preventing a change in ladder resistance value in the latch-up withstand test and disconnection of the ladder resistance. There is an effect that can be.

FIG. 3, showing an embodiment of the present invention, is a diagram illustrating a layout example of polysilicon resistors. It is a figure which shows the example of a layout of a polysilicon resistance. It is a figure which shows the layout example of the ladder resistance by a conventional method. It is a block diagram of the D / A converter using ladder resistance. It is a block diagram of a D / A converter of a display panel driver LSI. It is a block diagram of a D / A converter of a display panel driver LSI including a reference voltage terminal that is not connected to an external power supply. It is a figure which shows the example of the malfunction in a latchup tolerance test. It is a figure which shows the relationship between the applied current when the resistance value of a polysilicon resistance changes 10%, and the width | variety of a polysilicon resistance.

  An embodiment of the present invention will be described below with reference to FIGS. 1 to 3, 6 and 8.

  The reference voltage generation circuit according to the present embodiment is basically the same as the conventional configuration shown in FIG. 6 except for the configuration of the feature point of the present invention, which will be described later. To do. The display panel driving driver LSI (display panel driving device) according to the present embodiment includes a D / A converter, and the display panel displays a grayscale gradation of the input digital signal indicating the grayscale of the display panel. This is a so-called source driver that converts an analog signal that can be controlled and outputs the converted analog signal to the display panel to drive the display panel to perform display. Since the configuration and the like are the same as those in general, the description thereof is omitted here.

  As shown in FIG. 2, the layout of the polysilicon resistor used for the ladder resistor is composed of a polysilicon layer 11, connection holes 12, and connection wirings 13 for connecting the polysilicon layer 11 to other elements or terminals. Is done. When the width of the polysilicon layer 11 is W (um) and the distance between the connection holes 12 is L (um), the resistance value R (Ω) of the polysilicon resistor is the sheet resistance ρs (Ω / sq of the polysilicon layer 11). ) Can be calculated as R = ρs * (L / W). The ladder resistor is configured by connecting a plurality of polysilicon resistors laid out as shown in FIG. 2 in series.

  FIG. 3 shows an example of the layout when the ladder resistance of the D / A converter 60 shown in FIG. 6 is implemented by the conventional method. The polysilicon resistor shown in FIG. 3 performs connection to the reference voltage terminals V7 and V5 connected to the external power supply, the connection wiring 14 and connection wiring 16 connected to the external power supply, and the reference voltage terminal V6 not connected to the external power supply. Connection wiring 15 is provided. The polysilicon resistors R7, R6, and R5 in FIG. 7 correspond to the polysilicon resistors 17, 18, and 19 in FIG.

  In the conventional method, the width W of the polysilicon resistor is laid out with the same dimension. Further, in order to prevent an increase in layout occupation area, the width of the polysilicon resistor is a narrow width of about 1 to 10 μm. Therefore, as described above, when the reference voltage applied from the outside is high and the ladder resistance value is low, the ladder resistance value is changed by performing the pulse current injection test, or the ladder resistance is disconnected. As a result, it does not operate with a desired function.

  An example of the layout when the ladder resistance of the D / A converter 60 shown in FIG. 6 is implemented by the method using the present invention is shown in FIG. The polysilicon resistors shown in FIG. 1 are connected to reference voltage terminals (first reference voltage terminals) V7 and V5 connected to an external power supply, connection wiring 1 and connection wiring 3, and a reference voltage not connected to an external power supply. A connection wiring 2 for connecting to a terminal (second reference voltage terminal) V6 is provided. The polysilicon resistors R7, R6, and R5 in FIG. 6 correspond to the polysilicon resistors 4, 5, and 6 in FIG.

  In the embodiment of the present invention, Wa (um), which is the width of the polysilicon layer of the polysilicon resistors R7 and R6 (polysilicon resistors 4 and 5 in FIG. 1) connected to the reference voltage terminal not connected to the external power source, Wb (um) is wider (wider) than Wc (um), which is the width of the polysilicon layer of polysilicon resistor R5 (polysilicon resistor 6 in FIG. 1) connected to a reference voltage terminal connected to an external power supply. is doing. The distances La (um) and Lb (um) between the connection holes of the polysilicon resistors R7 and R6 (polysilicon resistors 4 and 5 in FIG. 1) are increased according to the ratio of the expanded polysilicon resistor width. The polysilicon resistance value is maintained at the same value as the conventional method.

  As the widths of Wa and Wb, predetermined widths are used in which the ladder resistance value does not change and the ladder resistance is not disconnected by performing a pulse current injection test. The width can be determined from the voltage applied to the reference voltage terminal connected to the external power supply and the value of the polysilicon resistance.

Assuming that the voltage applied to the reference voltage terminal connected to the external power supply is Vs (V), and the value of the polysilicon resistance is Rp (Ω), the maximum value Ip (A) of the current value flowing through the ladder resistor during the pulse current injection test is Since this is the current value when the voltage of the terminal to be measured is −0.6 V, Ip = (Vs + 0.6) / Rp This is the state immediately before the ESD protection diode provided at the reference voltage terminal becomes forward biased, and all the current drawn during the pulse current injection test is supplied via the ladder resistor. Ip is set to Ip <35 × 10 −3 (A / um) * W (um) in order to make it less than the current value at which the resistance value of the polysilicon resistor starts to change (35 mA per unit width). Therefore, from (Vs + 0.6) / Rp <35 × 10 −3 * W, the width W (um) of the polysilicon resistor that does not cause a problem during the pulse current injection test is W> ((Vs + 0.6) / (Rp * 35 × 10 −3 ))

That is, in the embodiment using the present invention, the width Wa (um) of the polysilicon layer of the polysilicon resistors R7 and R6 (polysilicon resistors 4 and 5 in FIG. 1) connected to the reference voltage terminal not connected to the external power source. ), Wb (um) may be made thicker than the width Wc (um) of the polysilicon layer of the polysilicon resistor R5 (polysilicon resistor 6 in FIG. 1) connected to the reference voltage terminal connected to the external power source, The widths Wa and Wb may be larger than the value obtained by ((Vs + 0.6) / (Rp * 35 × 10 −3 )).

  The polysilicon resistor used in the example of the present invention is formed of a composite film of a polysilicon film having a thickness of 200 nm and a refractory metal silicide film having a thickness of 50 nm. The current value at which the composite film causes a change in resistance value is 35 mA per unit width as shown in FIG. This current value depends on the thicknesses of the polysilicon film and the refractory metal silicide film. When the film thickness is large, the current value is larger than 35 mA, and when the film thickness is small, the current value is smaller than 35 mA. Therefore, when the film thickness is changed, the current value Ic (A) per unit width causing the resistance value change is measured, so that the necessary width W (um) of the polysilicon resistance is W> ((Vs + 0 .6) / (Rp * Ic)).

  The present invention is not limited to the above-described embodiments, and various modifications can be made within the scope shown in the claims. That is, embodiments obtained by combining technical means appropriately modified within the scope of the claims are also included in the technical scope of the present invention.

  The present invention can be applied to a reference voltage generation circuit used in a D / A converter or the like, and more particularly to a reference voltage generation circuit used in a driver LSI for driving a display panel.

1 Connection wiring with reference voltage terminal V7 connected to external power supply 2 Connection wiring with reference voltage terminal V6 not connected to external power supply 3 Connection wiring with reference voltage terminal V5 connected to external power supply 4 Not connected to external power supply Polysilicon resistor R7 connected to the reference voltage terminal
5 Polysilicon resistor R6 connected to a reference voltage terminal not connected to an external power source
6 Polysilicon resistor R5 connected to a reference voltage terminal connected to an external power supply
DESCRIPTION OF SYMBOLS 11 Polysilicon layer 12 Connection hole 13 Connection wiring 14 Connection wiring with reference voltage terminal V7 connected to external power supply 15 Connection wiring with reference voltage terminal V6 not connected to external power supply 16 Reference voltage terminal V5 connected to external power supply Connection wiring 17 with polysilicon resistor R7 connected to a reference voltage terminal not connected to an external power source
18 Polysilicon resistor R6 connected to a reference voltage terminal not connected to an external power source
19 Polysilicon resistor R5 connected to a reference voltage terminal connected to an external power supply

Claims (4)

  1. A reference voltage generation circuit that generates a reference voltage used for operation of another circuit and outputs the reference voltage to the other circuit,
    A plurality of ladder resistors for generating the reference voltage;
    The ladder resistor is connected to a plurality of reference voltage terminals that apply a voltage to the ladder resistor.
    The reference voltage terminal includes a first reference voltage terminal connected to an external power source and a second reference voltage terminal not connected to the external power source,
    The ladder resistor is characterized in that the width of the ladder resistor connected to the second reference voltage terminal is wider than the width of the ladder resistor connected to the first reference voltage terminal. circuit.
  2. The reference voltage generation circuit according to claim 1, wherein the width of the ladder resistor connected to the second reference voltage terminal satisfies the following expression (1).
    W> ((Vs + 0.6) / (Rp * Ic)) (1)
    W: width of a ladder resistor connected to a second reference voltage terminal not connected to the external power supply Vs: voltage Rp applied to a first reference voltage terminal connected to the external power supply: second reference not connected to the external power supply Resistance value Ic of ladder resistor connected to voltage terminal: Applied current value per unit width causing resistance value change
  3.   3. The reference voltage generation circuit according to claim 1, wherein the reference voltage generation circuit is used together with a D / A converter circuit as the other circuit.
  4. A display panel driving device that performs display by driving a display panel,
    A display panel driving device comprising the reference voltage generation circuit according to claim 1.
JP2009027621A 2009-02-09 2009-02-09 Reference voltage generating circuit and display panel driving device using the same Pending JP2010181823A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2009027621A JP2010181823A (en) 2009-02-09 2009-02-09 Reference voltage generating circuit and display panel driving device using the same

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2009027621A JP2010181823A (en) 2009-02-09 2009-02-09 Reference voltage generating circuit and display panel driving device using the same

Publications (1)

Publication Number Publication Date
JP2010181823A true JP2010181823A (en) 2010-08-19

Family

ID=42763418

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2009027621A Pending JP2010181823A (en) 2009-02-09 2009-02-09 Reference voltage generating circuit and display panel driving device using the same

Country Status (1)

Country Link
JP (1) JP2010181823A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120193995A1 (en) * 2011-01-31 2012-08-02 Sony Corporation Voltage generation circuit, resonance circuit, communication apparatus, communication system, wireless charging system, power supply apparatus, and electronic apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20120193995A1 (en) * 2011-01-31 2012-08-02 Sony Corporation Voltage generation circuit, resonance circuit, communication apparatus, communication system, wireless charging system, power supply apparatus, and electronic apparatus

Similar Documents

Publication Publication Date Title
US8674745B2 (en) Level conversion circuit and semiconductor integrated circuit device employing the level conversion circuit
EP0765035B1 (en) Output circuit
KR100888806B1 (en) Semiconductor integrated circuit device
US6946865B2 (en) Semiconductor integrated circuit apparatus
US6184744B1 (en) Internal power supply voltage generation circuit that can suppress reduction in internal power supply voltage in neighborhood of lower limit region of external power supply voltage
US7683553B2 (en) LED current control circuits and methods
TWI554030B (en) High side switch circuit, interface circuit and electronic device
CN105528981B (en) Display device and power control
US6671816B1 (en) System and method for independent power sequencing of integrated circuits
US8643425B2 (en) Level shifter circuit
CN100517978C (en) D/a converter
US8063623B2 (en) Analog compensation circuit
US7631279B2 (en) Semiconductor integrated device and apparatus for designing the same
US7320482B2 (en) Semiconductor integrated circuit device
JP4620571B2 (en) Battery voltage monitoring device
US8405442B2 (en) Level shifters and integrated circuits thereof
US7038502B2 (en) LVDS driver circuit and driver circuit
KR100635167B1 (en) Temperature compensated bias source circuit
US20080062597A1 (en) Circuit for electrostatic discharge (ESD) protection
KR100610007B1 (en) programmable impedance Control circuit in semiconductor device and impedance range shifting method therefor
US7755580B2 (en) Automated adaptation of the supply voltage of a light-emitting display according to the desired luminance
US20080218139A1 (en) Voltage regulator circuit and control method therefor
EP1387491A2 (en) Level shifter and flat panel display
US7495872B2 (en) Semiconductor unit
JP5057828B2 (en) Display device