JP2010171574A - Semiconductor relay - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent an insulation deterioration of a gate oxide film in an output MOSFET. <P>SOLUTION: In a semiconductor relay, a clamp circuit having two resistors R1 and R2, and a diode D1 connected in parallel to the resistor R2 is connected between each gate and source of output MOSFETs 16a and 16b. When an output voltage of a photo diode array 13 is equal to or less than a designed value, e.g. 20 V, a voltage drop in the resistor R2 becomes approximately equal to a forward direction voltage of the diode D1, so that the output voltage of the photo diode array 13 is applied to the gates of the output MOSFETs 16a and 16b as it is. Alternatively, when the output voltage of the photo diode array 13 becomes equal to or more than 20 V, the voltage drop in the resistor R2 is fixed to the forward direction voltage of the diode, so that the voltage of 20 V is applied. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor relay that opens and closes a load current based on an electromotive force obtained by photoelectrically converting an input signal.

  2. Description of the Related Art A semiconductor relay that includes a light emitting element that emits light based on an input signal and a light receiving element that receives an optical signal from the light emitting element to generate an electromotive force, and turns on and off an output MOSFET by the electromotive force is known. (For example, refer to Patent Document 1).

  FIG. 7 is a diagram showing a configuration of a conventional semiconductor relay. The semiconductor relay 7 in FIG. 7 includes a light emitting element 72 such as an LED that generates an optical signal in response to input signals from the input terminals 71a and 71b, and a photodiode array 73 that receives the optical signal and generates an electromotive force. The charging / discharging circuit 74 that charges and discharges the generated electromotive force, and two output MOSFETs 76a and 76b that conduct and cut off in response to the voltage from the charging / discharging circuit 74.

  When a SiC-MOSFET made of silicon carbide (SiC) is used for the output MOSFETs 76a and 76b, the threshold voltage for conducting the drain-source connection between the SiC-MOSFET is as high as 3 V or more.

  On the other hand, the electromotive force of the photodiode array 73 has a temperature gradient of approximately −120 mV / ° C. For example, if the operating temperature range of the semiconductor relay 7 is −40 to 85 ° C., and the gate maximum rated voltage of the output MOSFETs 76a and 76b is 20V, the operating temperature range is less than the maximum rated voltage within the operating temperature range. It is necessary to set the gate applied voltage to 20 V at the lower limit of −40 ° C. Then, as shown in the following formula (1), the gate applied voltage at room temperature (20 ° C.) is lowered.

  20V- {120mV · (25 + 40)} = 12.2V (1)

  However, when the gate application voltage is 12.2 V, the output MOSFETs 76a and 76b having a high threshold voltage may not be sufficiently conducted.

  In order to avoid these problems, it is desirable to increase the amount of light emitted from the light emitting element 72 or increase the number of cells in the photodiode array 73, but it is desirable to increase the electromotive force. Therefore, it is necessary to prevent the gate oxide film from being deteriorated or destroyed.

JP-A-8-204533

  The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a semiconductor relay that can prevent insulation deterioration of the gate oxide film of the output MOSFET even when the electromotive force of the photodiode array increases. And

  The present invention relates to a light emitting element that generates an optical signal in response to an input signal, a photodiode array that receives the optical signal and generates a voltage, and a charge / discharge circuit that charges and discharges the voltage generated by the photodiode array. And a clamp circuit for limiting a voltage generated by the photodiode array between the charge / discharge circuit and the output MOSFET in a semiconductor relay including an output MOSFET having a gate and a source connected to the charge / discharge circuit. The clamp circuit includes two resistors connected in series between the gate and the source of the output MOSFET, and voltage clamp means connected in parallel to one or both of the two resistors. It is characterized by comprising.

  With this configuration, even when the electromotive force of the photodiode array increases, the gate application voltage of the output MOSFET can be maintained at a level necessary and sufficient for conduction, so that the gate oxide film can be prevented from being deteriorated in insulation. It becomes possible.

  In the semiconductor relay according to the present invention, the clamp means includes a diode connected in parallel to one of the two resistors. That is, the clamp circuit includes two resistors connected in series between the gate and the source of the output MOSFET, and a diode connected in parallel to one of the two resistors. Including those characterized by this.

  With this configuration, when the electromotive force of the photodiode array becomes large, the output voltage is clamped by the diode conducting, and the gate applied voltage of the output MOSFET can be maintained at a level sufficient for conduction, It becomes possible to prevent insulation deterioration of the gate oxide film.

  In the semiconductor relay according to the present invention, the clamp circuit includes two resistors connected in series between the gate and the source of the output MOSFET, and a gate at a connection point of the two resistors. And an N-channel FET having a drain connected to the gate of the output MOSFET through a resistor and a source connected to the source of the output MOSFET. .

  With this configuration, when the electromotive force of the photodiode array increases, the output voltage is clamped by the N-channel FET conducting, and the gate applied voltage of the output MOSFET can be maintained at a level sufficient for conduction. Therefore, it is possible to prevent the gate oxide film from being deteriorated in insulation.

  In the semiconductor relay according to the present invention, the clamp circuit includes two resistors connected in series between the gate and the source of the output MOSFET, and a gate at a connection point of the two resistors. And a P-channel FET having a source connected to the gate of the output MOSFET and a drain connected to the source of the output MOSFET via a resistor. .

  With this configuration, when the electromotive force of the photodiode array increases, the output voltage is clamped by the conduction of the P-channel FET, and the gate application voltage of the output MOSFET can be maintained at a level sufficient for conduction. Therefore, it is possible to prevent the gate oxide film from being deteriorated in insulation.

  Further, the present invention is the above-described semiconductor relay, wherein the clamp circuit has a base between two resistors connected in series between the gate and the source of the output MOSFET and a connection point of the two resistors. And an NPN bipolar transistor having a collector connected to the gate of the output MOSFET via a resistor and an emitter connected to the source of the output MOSFET. .

  With this configuration, when the electromotive force of the photodiode array increases, the output voltage is clamped by the NPN bipolar transistor conducting, and the gate applied voltage of the output MOSFET can be maintained at a level sufficient for conduction. Therefore, it is possible to prevent the gate oxide film from being deteriorated in insulation.

  Further, the present invention is the above-described semiconductor relay, wherein the clamp circuit has a base between two resistors connected in series between the gate and the source of the output MOSFET and a connection point of the two resistors. And a PNP bipolar transistor having an emitter connected to the gate of the output MOSFET and a collector connected to the source of the output MOSFET via a resistor. .

  With this configuration, when the electromotive force of the photodiode array increases, the output voltage is clamped by the conduction of the PNP bipolar transistor, and the gate application voltage of the output MOSFET can be maintained at a level sufficient for conduction. Therefore, it is possible to prevent the gate oxide film from being deteriorated in insulation.

  Furthermore, the present invention includes the above-described semiconductor relay, wherein the clamp circuit includes a Zener diode connected between the gate and the source of the output MOSFET.

  With this configuration, when the electromotive force of the photodiode array increases, the output voltage is clamped by the Zener voltage of the Zener diode, and the gate application voltage of the output MOSFET can be maintained at a level sufficient for conduction. Therefore, it is possible to prevent the gate oxide film from being deteriorated in insulation.

  ADVANTAGE OF THE INVENTION According to this invention, even if the electromotive force of a photodiode array becomes large, the semiconductor relay which can prevent the insulation deterioration of the gate oxide film of output MOSFET can be provided.

The figure which shows schematic structure of the semiconductor relay which concerns on Embodiment 1 of this invention. The figure which shows schematic structure of the semiconductor relay which concerns on Embodiment 2 of this invention. The figure which shows schematic structure of the semiconductor relay which concerns on Embodiment 3 of this invention. The figure which shows schematic structure of a modification in the semiconductor relay which concerns on Embodiment 3 of this invention. The figure which shows schematic structure of the semiconductor relay which concerns on Embodiment 4 of this invention. The figure which shows schematic structure of a modification in the semiconductor relay which concerns on Embodiment 4 of this invention. The figure which shows schematic structure of the conventional semiconductor relay

  Hereinafter, a semiconductor relay according to an embodiment of the present invention will be described with reference to the drawings.

(Embodiment 1)
FIG. 1 is a diagram showing a schematic configuration of a semiconductor relay according to Embodiment 1 of the present invention. As shown in the figure, the semiconductor relay 1 of the present embodiment includes a light emitting element 12 such as an LED having a first input terminal 11a and a second input terminal 11b, and a photodiode cell insulated from the light emitting element 12. Are connected in series, generate an electromotive force in response to light emission of the light emitting element 12 and output a voltage, a charge / discharge circuit 14 that charges and discharges the output voltage of the photodiode array 13, and a photodiode. A clamp circuit 15 that limits the output voltage of the array 13 to a predetermined voltage, and two silicon carbide (SiC) materials that are turned on and off between the drain and the source by applying an output voltage of a predetermined voltage to the gate. The output MOSFETs 16a and 16b are included.

  The two output MOSFETs 16a and 16b have their gates connected to the anode terminal of the photodiode array 13 via the clamp circuit 15 and their sources connected to each other in reverse series, and then the photo MOSFET via the clamp circuit 15. It is connected to the cathode terminal of the diode array 13. The drain of the output MOSFET 16a is connected to the first output terminal 17a, and the drain of the output MOSFET 16b is connected to the second output terminal 17b.

  The clamp circuit 15 includes resistors R1 and R2 connected in series between the gates and sources of the two output MOSFETs 16a and 16b, and a diode D1 connected in parallel to the resistor R2. The resistance values of the resistors R1 and R2 are, for example, 19.3 MΩ for R1 and 0.7 MΩ for R2.

  Next, the operation of the thus configured semiconductor relay according to the first embodiment of the present invention will be described.

  The light emitting element 12 emits light when an input signal is input from the first and second input terminals 11a and 11b, and generates an optical signal. The photodiode array 13 receives an optical signal from the light emitting element 12, generates an electromotive force at both ends, and outputs a voltage.

  The charge / discharge circuit 14 charges and discharges the output voltage of the photodiode array 13 and applies it to the gates of the output MOSFETs 16 a and 16 b via the clamp circuit 15. When the output voltage of the photodiode array 13 applied to the gates of the output MOSFETs 16a and 16b becomes higher than the threshold voltage Vth, the drain and source of the output MOSFETs 16a and 16b are turned on. The two output terminals 17a and 16b are electrically connected, and the relay is closed.

  On the other hand, when the input signal is turned off at the first and second input terminals 11a and 11b, the output voltage from the charge / discharge circuit 14 disappears, the drain-source between the output MOSFETs 16a and 16b is turned off, and the first And the second output terminals 17a and 16b are disconnected, and the relay is opened.

  Next, the operation of the clamp circuit 15 will be described.

  If the output voltage of the photodiode array 13 is, for example, 20 V or less, the clamp circuit 15 has a voltage drop across the resistor R2 that is substantially equal to the forward voltage Vf (about 0.7 V) of the diode D1. The output voltage of the photodiode array 13 is directly applied to the gates of the MOSFETs 16a and 16b.

  On the other hand, when the output voltage of the photodiode array 13 becomes 20 V or higher, the voltage drop across the resistor R2 is fixed at the forward voltage Vf of the diode D1. Therefore, for example, even if the electromotive force of the photodiode array 13 increases due to an increase in the amount of light emitted from the light emitting element 12 and the output voltage increases, the current does not increase but the output voltage does not increase.

  As a result, if the insulation degradation of the gate oxide films of the output MOSFETs 16a and 16b does not occur below the gate applied voltage of 20V, the insulation degradation can be effectively prevented.

  Actually, the forward voltage Vf of the diode D1 also has a temperature gradient of −1 to 2 mV / ° C., but the influence on the voltage applied to the gates of the output MOSFETs 16a and 16b is expressed by the following equation (2). It is a small value as calculated by

  −1 to 2 × (19.3 + 0.7) /0.7≈−30 mV / ° C. (2)

  This value is greatly improved compared to −120 mV / ° C. when the clamp circuit 15 is not provided. For example, even when the gate application voltage is set to 20 V at the lower limit of the operating temperature range of −40 ° C., the room temperature ( The decrease in the gate applied voltage at 20 ° C. can be reduced, and the output MOSFETs 76a and 76b having a high threshold voltage can be sufficiently conducted.

  As described above, according to the semiconductor relay according to the first embodiment of the present invention, the light emitting element that generates the optical signal in response to the input signal, and the electromotive force is generated by receiving the optical signal. Semiconductor relay comprising a photodiode array, a charge / discharge circuit for charging / discharging a voltage of an electromotive force generated in the photodiode array, and two output MOSFETs whose gates and sources are connected to the photodiode array via the charge / discharge circuit 2, a clamp circuit composed of two resistors connected in series and a diode connected in parallel to one of the resistors is connected between the gates and sources of the two output MOSFETs.

  As a result, even when the output voltage of the photodiode array reaches a design value of, for example, 20 V or more, the voltage drop in one of the resistors is fixed by the forward voltage Vf of the diode. The gate voltage is not applied, and the gate oxide film can be prevented from being deteriorated in insulation.

(Embodiment 2)
FIG. 2 is a diagram showing a schematic configuration of the semiconductor relay according to the second embodiment of the present invention. As shown in the figure, the semiconductor relay 2 of the present embodiment is configured to have a clamp circuit 25 in place of the clamp circuit 15 in the semiconductor relay 1 according to the first embodiment shown in FIG. In addition, about the same component as FIG. 1, the same code | symbol is attached | subjected and description is simplified or abbreviate | omitted.

  The clamp circuit 25 includes a Zener diode ZD1 whose Zener voltage is 20V, for example.

  Next, the operation of the thus configured semiconductor relay according to the second embodiment of the present invention will be described. Since the relay operation is the same as that of the first embodiment, the description is omitted, and only the operation of the clamp circuit 25 is described.

  In the clamp circuit 25, if the output voltage of the photodiode array 13 is 20 V or less of the design value, for example, no Zener current flows through the Zener diode ZD1, so that the output voltage of the photodiode array 13 remains as it is as the output MOSFETs 16a and 16b. Applied to the gate.

  On the other hand, when the output voltage of the photodiode array 13 becomes 20 V or more, a Zener current flows through the Zener diode ZD1, and a voltage of 20 V limited by the Zener voltage is applied to the gates of the output MOSFETs 16a and 16b.

  As a result, if the insulation degradation of the gate oxide films of the output MOSFETs 16a and 16b does not occur below the gate applied voltage of 20V, the insulation degradation can be effectively prevented.

  Actually, the Zener voltage of the Zener diode ZD1 also has a temperature gradient, but this value is approximately −30 mV / ° C., which is much larger than −120 mV / ° C. when the clamp circuit 25 is not provided. For example, even if the gate application voltage is set to 20 V at the lower limit of the operating temperature range of −40 ° C., the reduction of the gate application voltage at room temperature (20 ° C.) can be reduced, and the output voltage is high. It becomes possible to sufficiently conduct the MOSFETs 76a and 76b.

  As described above, according to the semiconductor relay according to the second embodiment of the present invention, a light emitting element that generates an optical signal in response to an input signal, and an electromotive force is generated by receiving the optical signal. Semiconductor relay comprising a photodiode array, a charge / discharge circuit for charging / discharging a voltage of an electromotive force generated in the photodiode array, and two output MOSFETs whose gates and sources are connected to the photodiode array via the charge / discharge circuit 2, a clamp circuit composed of a Zener diode having a Zener voltage of 20 V, for example, is connected between the gates and sources of the two output MOSFETs.

  As a result, even when the output voltage of the photodiode array exceeds a design value of, for example, 20V, the Zener voltage of the Zener diode is limited to 20V. Therefore, a gate voltage of 20V or more may be applied to the two output MOSFETs. Insulation deterioration of the gate oxide film can be prevented.

(Embodiment 3)
FIG. 3 is a diagram showing a schematic configuration of a semiconductor relay according to the third embodiment of the present invention. As shown in the figure, the semiconductor relay 3 of the present embodiment is configured to have a clamp circuit 35 instead of the clamp circuit 15 in the semiconductor relay 1 according to the first embodiment shown in FIG. The same components as those in FIG. 1 are denoted by the same reference numerals, and the description thereof is simplified or omitted.

  The clamp circuit 35 has resistors R3 and R4 connected in series between the gates and sources of the two output MOSFETs 16a and 16b, and a gate connected to the connection point of the resistors R3 and R4. The gates of the output MOSFETs 16a and 16b The N-channel FET (Q1) is connected to the drain via a resistor R5, and the source is connected to each source of the output MOSFETs 16a and 16b. The resistance values of the resistors R3 to R5 are, for example, values that are sufficiently smaller than the sum 20MΩ of R3 is 19 MΩ, R4 is 1 MΩ, and R5 is the sum of the resistance values of the resistors R3 and R4.

  Next, the operation of the thus configured semiconductor relay according to the third embodiment of the present invention will be described. Since the relay operation is the same as that of the first embodiment, the description is omitted, and only the operation of the clamp circuit 35 is described.

  If the output voltage of the photodiode array 13 is 20 V or less of the design value, the clamp circuit 35 is configured such that the voltage divided by the resistors R3 and R4 applied to the gate of the N-channel FET (Q1) is the N-channel FET. The threshold value of about 1V for turning on (Q1) is not exceeded. Therefore, the N-channel FET (Q1) remains off, and the output voltage of the photodiode array 13 of 20 V or less is applied as it is to the gates of the output MOSFETs 16a and 16b.

  On the other hand, when the output voltage of the photodiode array 13 exceeds 20V, the voltage divided by the resistors R3 and R4 exceeds the threshold value of approximately 1V, and the N-channel FET (Q1) is turned on and the drain-source connection is turned on. Is conducted. Therefore, for example, when the light emission amount of the light emitting element 12 increases, even if the output voltage of the photodiode array 13 increases, the current does not increase and the output voltage does not increase.

  As a result, if the insulation deterioration of the gate oxide films of the output MOSFETs 16a and 16b does not occur at 20 V or less, the insulation deterioration can be effectively prevented.

  Actually, the threshold voltage of the N-channel FET (Q1) also has a temperature gradient, but this value is approximately −2 mV / ° C. and affects the voltage applied to the gates of the output MOSFETs 16a and 16b. The influence is as small as about −20 mV / ° C. For example, even when the gate applied voltage is set to 20 V at the lower limit of the operating temperature range of −40 ° C., the decrease in the gate applied voltage at room temperature (20 ° C.) can be reduced. It becomes possible to sufficiently conduct the output MOSFETs 76a and 76b having a high voltage.

  FIG. 4 is a diagram showing a schematic configuration of a modified example in the semiconductor relay according to the third embodiment of the present invention. As shown in the figure, the semiconductor relay 4 according to the modified example has a clamp circuit 45 instead of the clamp circuit 35 in the semiconductor relay 3 according to the present embodiment shown in FIG.

  The clamp circuit 45 has resistors R6 and R7 connected in series between the gates and sources of the two output MOSFETs 16a and 16b, and a gate connected to the connection point of the resistors R6 and R7, and each gate of the output MOSFETs 16a and 16b. And a P-channel FET (Q2) having a drain connected to each source of the output MOSFETs 16a and 16b via a resistor R8. The resistance values of the resistors R6 to R8 are, for example, values that are sufficiently smaller than the sum 20MΩ of the resistance values of R6 and R7, for example, R6 is 19MΩ, R7 is 1MΩ.

  The operation of the clamp circuit 45 will be described in the modification of the semiconductor relay according to the third embodiment of the present invention configured as described above.

  If the output voltage of the photodiode array 13 is 20 V or less of the design value, the clamp circuit 45 is configured such that the voltage divided by the resistors R6 and R7 applied to the gate of the P-channel FET (Q2) is P-channel FET. The threshold value of about −1V for turning on (Q2) is not exceeded. Therefore, the P-channel FET (Q2) remains off, and the output voltage of the photodiode array 13 of 20 V or less is applied as it is between the gates and sources of the output MOSFETs 16a and 16b.

  On the other hand, when the output voltage of the photodiode array 13 becomes 20V or more, the voltage divided by the resistors R6 and R7 exceeds the threshold value of about -1V, and the P-channel FET (Q2) is turned on, and the drain / source Conduction between. Therefore, for example, even if the output voltage of the photodiode array 13 increases due to an increase in the light emission amount of the light emitting element 12, the output voltage does not increase only by increasing the current.

  As a result, if the insulation deterioration of the gate oxide films of the output MOSFETs 16a and 16b does not occur at 20 V or less, the insulation deterioration can be effectively prevented.

  Actually, the threshold voltage of the P-channel FET (Q2) also has a temperature gradient, but this value is approximately −2 mV / ° C. and affects the voltage applied to the gates of the output MOSFETs 16a and 16b. The influence is as small as about −20 mV / ° C. For example, even when the gate applied voltage is set to 20 V at the lower limit of the operating temperature range of −40 ° C., the decrease in the gate applied voltage at room temperature (20 ° C.) can be reduced. It becomes possible to sufficiently conduct the output MOSFETs 76a and 76b having a high voltage.

  As described above, according to such a semiconductor relay according to the third embodiment of the present invention, a light emitting element that generates an optical signal in response to an input signal, and an electromotive force is generated by receiving the optical signal. Semiconductor relay comprising a photodiode array, a charge / discharge circuit for charging / discharging a voltage of an electromotive force generated in the photodiode array, and two output MOSFETs whose gates and sources are connected to the photodiode array via the charge / discharge circuit , Two resistors connected in series between the gates and sources of the two output MOSFETs, and a gate connected to the connection point of both resistors, and a drain connected to each gate of the two output MOSFETs via the resistors. A clamp circuit composed of N-channel FETs connected to each other and connected to each source of the output MOSFET is connected.

  In addition, the clamp circuit has two resistors connected in series between the gate and source of the two output MOSFETs, and a gate connected to the connection point of both resistors, and a source is connected to each gate of the two output MOSFETs. It may be composed of a P-channel FET connected and having a drain connected to each source via a resistor.

  As a result, even when the output voltage of the photodiode array exceeds a design value of, for example, 20 V, the voltage divided by the two resistors is approximately 1 V and the threshold values of the N-channel FET and the P-channel FET, respectively. Since the drain-source connection is made to exceed approximately -1 V, the gate voltage of 20 V or more is not applied to the two output MOSFETs, and the insulation deterioration of the gate oxide film can be prevented.

(Embodiment 4)
FIG. 5 is a diagram showing a schematic configuration of a semiconductor relay according to the fifth embodiment of the present invention. As shown in the figure, the semiconductor relay 4 of the present embodiment has a configuration having a clamp circuit 55 in place of the clamp circuit 15 in the semiconductor relay 1 according to the first embodiment shown in FIG. In addition, about the same component as FIG. 1, the same code | symbol is attached | subjected and description is simplified or abbreviate | omitted.

  The clamp circuit 55 has resistors R9 and R10 connected in series between the gates and sources of the two output MOSFETs 16a and 16b, and a base connected to a connection point between the resistors R9 and R10, and each gate of the output MOSFETs 16a and 16b. And an NPN bipolar transistor Q3 having a collector connected through a resistor R11 and an emitter connected to each source of the output MOSFETs 16a and 16b. Note that the resistance values of the resistors R9 to R11 are, for example, values that are sufficiently smaller than the sum of 31 MΩ of R9 is 30 MΩ, R10 is 1 MΩ, and R11 is the sum of the resistance values of the resistors R9 and R10.

  Next, the operation of the thus configured semiconductor relay according to the fourth embodiment of the present invention will be described. Since the relay operation is the same as that of the first embodiment, the description is omitted, and only the operation of the clamp circuit 55 is described.

  If the output voltage of the photodiode array 13 is, for example, 20 V or less, the clamp circuit 55 is configured such that the voltage divided by the resistors R9 and R10 applied to the base of the NPN bipolar transistor Q3 is the NPN bipolar transistor Q3. The base-emitter voltage Vbe for turning on does not exceed about 0.7V. Therefore, the NPN bipolar transistor Q3 remains off, and the output voltage of the photodiode array 13 of 20 V or less is applied as it is between the gates and sources of the output MOSFETs 16a and 16b.

  On the other hand, when the output voltage of the photodiode array 13 becomes 20 V or more, the voltage divided by the resistors R9 and R10 exceeds approximately 0.7 V of Vbe, and the NPN bipolar transistor Q3 is turned on so that the collector-emitter is conductive. To do. Therefore, for example, when the light emission amount of the light emitting element 12 increases, even if the output voltage of the photodiode array 13 increases, the current does not increase and the output voltage does not increase.

  As a result, if the insulation deterioration of the gate oxide films of the output MOSFETs 16a and 16b does not occur at 20 V or less, the insulation deterioration can be effectively prevented.

  Actually, the base-emitter voltage Vbe of the NPN bipolar transistor Q3 also has a temperature gradient, but this value is approximately −2 mV / ° C., which has an effect on the voltage applied to the gates of the output MOSFETs 16a and 16b. Is as low as about −20 mV / ° C. For example, even when the gate applied voltage is set to 20 V at the lower limit of the operating temperature range of −40 ° C., the decrease in the gate applied voltage at room temperature (20 ° C.) can be reduced, and the threshold voltage High output MOSFETs 76a and 76b can be sufficiently conducted.

  FIG. 6 is a diagram showing a schematic configuration of a modified example in the semiconductor relay according to the fourth embodiment of the present invention. As shown in the figure, the semiconductor relay 6 of this modification has a configuration having a clamp circuit 65 in place of the clamp circuit 55 in the semiconductor relay 5 according to the present embodiment shown in FIG.

  The clamp circuit 65 has resistors R12 and R13 connected in series between the gates and sources of the two output MOSFETs 16a and 16b, and a base connected to a connection point between the resistors R12 and R13, and each gate of the output MOSFETs 16a and 16b. And a PNP bipolar transistor Q4 having a collector connected to each source of the output MOSFETs 16a and 16b via a resistor R14.

  The operation of the clamp circuit 65 will be described in the modification of the semiconductor relay according to the fourth embodiment of the present invention configured as described above.

  If the output voltage of the photodiode array 13 is 20 V or less, which is a design value, for example, the clamp circuit 65 determines that the voltage divided by the resistors R12 and R13 applied to the base of the PNP bipolar transistor Q4 causes the PNP bipolar transistor Q4 to The base-emitter voltage Vbe for turning on does not exceed approximately −0.7V. Therefore, the PNP bipolar transistor Q4 remains off, and the output voltage of the photodiode array 13 of 20 V or less is applied as it is between the gates and sources of the output MOSFETs 16a and 16b.

  On the other hand, when the output voltage of the photodiode array 13 exceeds 20V, the voltage divided by the resistors R6 and R7 exceeds approximately −0.7V of Vbe, the PNP bipolar transistor Q4 is turned on, and the collector-emitter is connected. Conduct. Therefore, for example, when the light emission amount of the light emitting element 12 increases, even if the output voltage of the photodiode array 13 increases, the current does not increase and the output voltage does not increase.

  As a result, if the insulation deterioration of the gate oxide films of the output MOSFETs 16a and 16b does not occur at 20 V or less, the insulation deterioration can be effectively prevented.

  Actually, the base-emitter voltage Vbe of the PNP bipolar transistor Q4 also has a temperature gradient, but this value is approximately −2 mV / ° C., which has an effect on the voltage applied to the gates of the output MOSFETs 16a and 16b. Is as low as about −20 mV / ° C. For example, even when the gate applied voltage is set to 20 V at the lower limit of the operating temperature range of −40 ° C., the decrease in the gate applied voltage at room temperature (20 ° C.) can be reduced, and the threshold voltage High output MOSFETs 76a and 76b can be sufficiently conducted.

  As described above, according to the semiconductor relay according to the fourth embodiment of the present invention, a light emitting element that generates an optical signal in response to an input signal, and an electromotive force is generated by receiving the optical signal. Semiconductor relay comprising a photodiode array, a charge / discharge circuit for charging / discharging a voltage of an electromotive force generated in the photodiode array, and two output MOSFETs whose gates and sources are connected to the photodiode array via the charge / discharge circuit , Two resistors connected in series between the gate and source of the two output MOSFETs, a base is connected to the connection point of both resistors, and a collector is connected to each gate of the output MOSFET via a resistor. A clamp circuit composed of an NPN bipolar transistor having an emitter connected to each source of the output MOSFET is connected.

  The clamp circuit has two resistors connected in series between the gate and source of the two output MOSFETs, and a base connected to the connection point of both resistors, and an emitter connected to each gate of the two output MOSFETs. The PNP bipolar transistor may have a collector connected to each source via a resistor.

  As a result, even if the output voltage of the photodiode array exceeds a design value of, for example, 20V, the voltage divided by the two resistors is approximately 0.7V of the base-emitter voltage Vbe of the NPN bipolar transistor and the PNP bipolar transistor. In addition, since the collector-emitter is conducted exceeding approximately −0.7 V, the gate voltage of 20 V or more is not applied to the two output MOSFETs, and the insulation deterioration of the gate oxide film can be prevented.

1-6 Semiconductor relay 12 Light emitting element 13 Photodiode array 14 Charge / discharge circuit 15, 25, 35, 45, 55, 65 Clamp circuit 16a, 16b Output MOSFET
D1 Diode R1-R14 Resistor Q1 N-channel FET
Q2 P-channel FET
Q3 NPN bipolar transistor Q4 PNP bipolar transistor ZD1 Zener diode

Claims (7)

A light emitting element that generates an optical signal in response to an input signal, a photodiode array that receives the optical signal and generates a voltage, a charge / discharge circuit that charges and discharges the voltage generated by the photodiode array, and the charge / discharge circuit In a semiconductor relay comprising an output MOSFET having a gate and a source connected to a discharge circuit,
A clamp circuit for limiting a voltage generated by the photodiode array between the charge / discharge circuit and the output MOSFET;
The clamp circuit is
Two resistors connected in series between the gate and the source of the output MOSFET;
A semiconductor relay comprising clamp means connected in parallel to one or both of the two resistors to control the voltage. The semiconductor relay according to claim 1,
The clamping means includes
A semiconductor relay which is a diode connected in parallel to one of the two resistors. The semiconductor relay according to claim 1,
The clamping means includes
An N-channel FET having a gate connected to a connection point of the two resistors, a drain connected to the gate of the output MOSFET via a resistor, and a source connected to the source of the output MOSFET;
A semiconductor relay comprising: The semiconductor relay according to claim 1,
The clamping means includes
A gate is connected to the connection point of the two resistors, a source is connected to the gate of the output MOSFET, and a P-channel FET is connected to the source of the output MOSFET via a resistor. Semiconductor relay. The semiconductor relay according to claim 1,
The clamping means includes
A base is connected to the connection point of the two resistors, a collector is connected to the gate of the output MOSFET via a resistor, and an NPN bipolar transistor is connected to the source of the output MOSFET. Semiconductor relay. The semiconductor relay according to claim 1,
The clamping means includes
A base is connected to the connection point of the two resistors, an emitter is connected to the gate of the output MOSFET, and a PNP bipolar transistor is connected to the source of the output MOSFET via a resistor. Semiconductor relay. A light emitting element that generates an optical signal in response to an input signal, a photodiode array that receives the optical signal and generates a voltage, a charge / discharge circuit that charges and discharges the voltage generated by the photodiode array, and the charge / discharge circuit In a semiconductor relay comprising an output MOSFET having a gate and a source connected to a discharge circuit,
A clamp circuit for limiting a voltage generated by the photodiode array between the charge / discharge circuit and the output MOSFET;
The clamp circuit is
A semiconductor relay comprising a Zener diode connected between the gate and the source of the output MOSFET.

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