JP2010171433A - 半導体装置およびその製造方法 - Google Patents
半導体装置およびその製造方法 Download PDFInfo
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- JP2010171433A JP2010171433A JP2010020255A JP2010020255A JP2010171433A JP 2010171433 A JP2010171433 A JP 2010171433A JP 2010020255 A JP2010020255 A JP 2010020255A JP 2010020255 A JP2010020255 A JP 2010020255A JP 2010171433 A JP2010171433 A JP 2010171433A
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Abstract
【解決手段】パワーMOSFETのゲート電極7とn+型ドレイン領域15との間に介在するオフセットドレイン領域を二重オフセット構造とし、ゲート電極7に最も近いn−型オフセットドレイン領域9の不純物濃度を相対的に低く、ゲート電極7から離間したn型オフセットドレイン領域13の不純物濃度を相対的に高くする。これにより、オン抵抗(Ron)と帰還容量(Cgd)を共に小さくすることができるので、増幅素子をシリコンパワーMOSFETで構成したRFパワーモジュールの小型化と電力付加効率の向上を図ることができる。
【選択図】図2
Description
本実施の形態1は、例えばGSM方式のネットワークを利用して情報を伝送するデジタル携帯電話に使用されるRF(Radio Frequency)パワーモジュールに搭載される半導体装置である。
前記実施の形態1のパワーMOSFETは、高濃度の不純物をドープしたp型多結晶シリコン膜を溝3の内部に埋め込むことによって、p型打抜き層4を形成している。このような方法で形成したp型打抜き層4は、不純物のイオン注入によって形成した打抜き層よりも寄生抵抗を小さくできる利点がある。
図27は、本実施の形態のパワーMOSFETを示す基板1の要部断面図である。本実施の形態のnチャネル型パワーMOSFETは、ゲート電極7をn型の多結晶シリコン膜のみで構成すると共に、ゲート電極7の上部の絶縁膜に長溝32を設け、この長溝32の内部に埋め込んだプラグ23でゲート電極7をシャントしている。プラグ23は、コンタクトホール22の内部に埋め込まれたプラグ23と同じく、W膜を主体とする金属膜からなる。長溝32は、ゲート電極7とほぼ同程度の長さを有し、ゲート電極7と平行して延在している。
1A 半導体チップ
2 エピタキシャル層
3 溝
4 p型打抜き層
5 p型ウエル
6 ゲート絶縁膜
7 ゲート電極
8 キャップ絶縁膜
9 n−型オフセットドレイン領域(第1低濃度領域)
10 n−型ソース領域
11 p型ハロー領域
12 サイドウォールスペーサ
13 n型オフセットドレイン領域
15 n+型ドレイン領域(高濃度オフセット領域)
16 n+型ソース領域(高濃度領域)
17 p+型半導体領域
20 窒化シリコン膜
21 酸化シリコン膜
22、22a コンタクトホール
23 プラグ
24 ドレイン電極
25 ソース電極
26 酸化シリコン膜
27 スルーホール
28 配線
29 表面保護膜
31 ソース裏面電極
32 長溝
33 抵抗素子
40〜45 フォトレジスト膜
50 モジュール基板
51 Auワイヤ
52 伝送線路
53 コンデンサ
54 電極
55 サーマルビア
56 GND電極
57 モールド樹脂
102A、102B 電力増幅回路
102A1〜102A3、102B1〜102B3 増幅段
102AM1〜102AM3、102BM1〜102BM3 整合回路
103 周辺回路
103A 制御回路
103B バイアス回路
103A1 電源制御回路
103A2 バイアス電圧生成回路
104a、104b 入力端子
Claims (18)
- 第1導電型の半導体基板の主面の一部に、チャネル形成領域を挟んで互いに離間して形成された第2導電型のソースおよびドレインと、
前記チャネル形成領域の上部にゲート絶縁膜を介して形成されたゲート電極と、
前記半導体基板の主面の他部に、前記ソースと接するように形成された第1導電型の複数の打抜き層とを備えたMOSFETを有する半導体装置であって、
前記ソースおよび前記ドレインは、前記半導体基板の主面の第1方向に沿って延在する平面パターンを有し、
前記複数の打抜き層は、前記第1方向に沿って配列され、
前記複数の打抜き層は、前記半導体基板に設けられた溝の内部に埋め込まれた導電膜からなり、
前記複数の打抜き層のそれぞれは、前記第1方向と交差する第2方向に長辺を有する形状の平面パターンを有していることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記ソースおよびドレインは、前記第1方向にそれぞれ複数配列され、
前記複数のソースは、互いに電気的に接続され、
前記複数のドレインは、互いに電気的に接続されていることを特徴とする半導体装置。 - 請求項1記載の半導体装置において、前記半導体基板の裏面には、前記複数の打抜き層を通じて前記ソースと電気的に接続されるソース電極が形成されていることを特徴とする半導体装置。
- 請求項3記載の半導体装置において、前記半導体基板は、モジュール基板に実装され、前記ソース電極は、前記モジュール基板の固定電位電極と電気的に接続されていることを特徴とする半導体装置。
- 請求項4記載の半導体装置において、前記複数の打抜き層は、その上部を覆う絶縁膜に形成されたコンタクトホール内のプラグを介して、前記絶縁膜上の金属配線と電気的に接続されていることを特徴とする半導体装置。
- 請求項1記載の半導体装置において、前記導電膜は、多結晶シリコンからなることを特徴とする半導体装置。
- 第1導電型の半導体基板の主面の第1領域にチャネル形成領域を挟んで互いに離間して形成された第2導電型のソースおよびドレインと、
前記チャネル形成領域の上部にゲート絶縁膜を介して形成された多結晶シリコン膜からなるゲート電極と、
前記ゲート電極の上部を覆うキャップ絶縁膜と、
前記キャップ絶縁膜の上部を覆い、前記キャップ絶縁膜とはエッチングレートが異なるストッパ絶縁膜と、
前記ストッパ絶縁膜の上部を覆う層間絶縁膜とを備えた半導体装置であって、
前記ゲート電極の上部には、前記層間絶縁膜、前記ストッパ絶縁膜および前記キャップ絶縁膜を貫通して前記ゲート電極の表面に達する溝が形成され、
前記溝の内部には、前記多結晶シリコン膜よりも電気抵抗が小さい導電膜が埋め込まれており、
前記ゲート電極の延在方向に垂直な第1平面内における前記溝の幅は、前記第1平面内における前記ゲート電極のゲート長よりも大きいことを特徴とする半導体装置。 - 請求項7記載の半導体装置において、前記半導体基板の主面の第2領域には、前記ゲート電極を構成する前記多結晶シリコン膜と同層の多結晶シリコン膜からなる抵抗素子が形成されていることを特徴とする半導体装置。
- 請求項7記載の半導体装置において、前記半導体基板の主面上には、前記溝の内部に埋め込まれた前記導電膜を一方の電極とする容量素子が形成されていることを特徴とする半導体装置。
- 請求項7記載の半導体装置において、前記ソースおよびドレインのそれぞれの上部の前記層間絶縁膜および前記ストッパ絶縁膜には、コンタクトホールが形成され、
前記コンタクトホールの内部には、前記溝の内部に形成された前記導電膜と同層の導電膜が形成されていることを特徴とする半導体装置。 - 第1導電型の半導体基板の主面上にゲート絶縁膜を介してゲート電極を形成した後、前記ゲート電極の両側の前記半導体基板に不純物をイオン注入することによって、ソース、ドレインを形成する半導体装置の製造方法であって、前記ドレインを形成する工程は、
(a)前記半導体基板のドレイン形成領域に不純物をイオン注入することによって、一端が前記ゲート電極の側壁下部に延在する第2導電型の第1ドレイン低濃度領域を形成する工程、
(b)前記(a)工程の後、前記ゲート電極の側壁にサイドウォールスペーサを形成する工程、
(c)前記(b)工程の後、前記半導体基板のドレイン形成領域に不純物をイオン注入することによって、前記第1ドレイン低濃度領域よりも不純物濃度が高い第2導電型の第2ドレイン低濃度領域を前記サイドウォールスペーサに対して自己整合で形成する工程、
(d)前記第2ドレイン低濃度領域の一部に不純物をイオン注入することによって、前記第2ドレイン低濃度領域よりも不純物濃度が高く、一端が前記ゲート電極の側壁下部から離間する第2導電型のドレイン高濃度領域を形成する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項11記載の半導体装置の製造方法において、前記ドレイン高濃度領域の深さは、前記第1ドレイン低濃度領域および前記第2ドレイン低濃度領域の深さよりも浅いことを特徴とする半導体装置の製造方法。
- 請求項11記載の半導体装置の製造方法において、前記ソースを形成する工程は、
(e)前記(b)工程に先立って、前記半導体基板のソース形成領域に不純物をイオン注入することによって、一端が前記ゲート電極の側壁下部に延在する第2導電型のソース低濃度領域を形成する工程、
(f)前記(b)工程の後、前記半導体基板のソース形成領域に不純物をイオン注入することによって、前記ソース低濃度領域よりも不純物濃度が高い第2導電型のソース高濃度領域を前記サイドウォールスペーサに対して自己整合で形成する工程、
を含むことを特徴とする半導体装置の製造方法。 - 請求項13記載の半導体装置の製造方法において、前記ソースの一部を構成する前記ソース低濃度領域の深さは、前記ソースの他部を構成する前記ソース高濃度領域の深さよりも浅いことを特徴とする半導体装置の製造方法。
- 請求項13記載の半導体装置の製造方法において、前記(e)工程と前記(a)工程は、別工程であることを特徴とする半導体装置の製造方法。
- 請求項13記載の半導体装置の製造方法において、前記(f)工程と前記(d)工程は、同一工程であることを特徴とする半導体装置の製造方法。
- 第1導電型の半導体基板の主面の一部に、チャネル形成領域を挟んで互いに離間して形成された第2導電型のソースおよびドレインと、
前記チャネル形成領域の上部にゲート絶縁膜を介して形成されたゲート電極と、
前記半導体基板の主面の他部に、前記ソースと接するように形成された第1導電型の複数の打抜き層とを備えたMOSFETを有する半導体装置の製造方法であって、前記複数の打抜き層を形成する工程は、
(a)前記半導体基板に溝を形成する工程と、
(b)前記溝の内部に導電膜を埋め込む工程と、
を含むことを特徴とする半導体装置の製造方法。 - 請求項17記載の半導体装置の製造方法において、前記ソースおよび前記ドレインは、前記半導体基板の主面の第1方向に沿って延在する平面パターンを有し、
前記複数の打抜き層は、前記第1方向に沿って配列され、
前記複数の打抜き層のそれぞれは、前記第1方向と交差する第2方向に長辺を有する形状の平面パターンを有していることを特徴とする半導体装置の製造方法。
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Also Published As
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US7176520B2 (en) | 2007-02-13 |
US20110254087A1 (en) | 2011-10-20 |
JPWO2005024931A1 (ja) | 2006-11-16 |
US20100258876A1 (en) | 2010-10-14 |
JP4891415B2 (ja) | 2012-03-07 |
TW200511580A (en) | 2005-03-16 |
JP2012089851A (ja) | 2012-05-10 |
JP4624924B2 (ja) | 2011-02-02 |
TWI361490B (en) | 2012-04-01 |
US20050051814A1 (en) | 2005-03-10 |
US7994567B2 (en) | 2011-08-09 |
US20070102757A1 (en) | 2007-05-10 |
US7791131B2 (en) | 2010-09-07 |
WO2005024931A1 (ja) | 2005-03-17 |
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