JP2010166620A - Electronic device, resonator, oscillator, and method for manufacturing electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To efficiently perform a manufacturing step of an electronic device and reduce the production cost. <P>SOLUTION: An electronic device 100 includes a board 1; a functional structure (MEMS structure) 3X formed on the board 1; and a coating structure, defining a cavity part S arranged with the functional structure 3X. The coating structure includes: interlayer insulating layers 4, 6 which are provided on the board 1 and surround the cavity part S; a sidewall 10Y, constituted of a lower surrounding wall 3Y and wiring layers 5, 7; a first coating layer 7Y, which coats an upper portion of the cavity part S and also is constituted of a laminated structure which has an opening 7a penetrating the cavity part S and contains a corrosion-resistant layer; and a second coating layer 9 closing the opening 7a. The corrosion-resistant layer is constituted of TiN, Ti, W, Au, Pt, or an alloy of each thereof. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a structure of an electronic device, a resonator, an oscillator, and a method for manufacturing the electronic device, in which a functional structure such as a MEMS (micro electro mechanical system) is disposed in a cavity formed on a substrate.

  In general, there is known an electronic device in which a functional structure such as a MEMS is disposed in a cavity formed on a substrate. For example, MEMS such as a micro vibrator, a micro sensor, and a micro actuator need to be arranged in a state in which a minute structure can be vibrated, deformed, or otherwise operated. (For example, refer to Patent Documents 1 and 2 below).

  By the way, as a method of forming the above-mentioned cavity, as disclosed in Patent Document 1, after forming a micro functional structure on the surface of one substrate, one substrate is formed via an O-ring in a vacuum chamber. And the other substrate are joined, and then a sealing agent is filled outside the O-ring.

  As another method, as disclosed in Patent Document 2, a MEMS structure is formed on a substrate, a sacrificial layer is formed thereon, and then a first sealing member having a through hole is formed. By removing the sacrificial layer through the through hole of the first sealing member to release the movable part of the MEMS structure, and finally covering the through hole of the first sealing member with a second sealing member such as a CVD film. Methods such as closing are also known.

  In addition, a method similar to Patent Documents 1 and 2 described above in which a cavity is simultaneously formed using a MOSFET wiring forming technique in a monolithic structure of a semiconductor integrated circuit device (CMOS) and a MEMS structure is described. (For example, refer to Patent Document 3).

JP 2005-297180 A JP-A-2005-123561 JP 2006-263902 A

  However, in the method of bonding two substrates as described in Patent Document 1 described above, a dedicated substrate for sealing is required, which increases material costs, and a micromachine using a general semiconductor manufacturing technology. Even if it is going to form an element, since the special process of bonding substrates together is required, there is a problem that the advantage of using the semiconductor manufacturing technique is reduced and the manufacturing cost increases.

  Further, in the method using the first sealing member having the through hole and the second sealing member for closing the through hole disclosed in Patent Document 2 described above, the release process of the MEMS structure is performed on the first sealing member. Since the etching time takes a long time because it is performed through the through hole, it is necessary to form the first sealing member with a material that can sufficiently withstand the etching in the release process, and as a result, in a process common to the semiconductor manufacturing process. There exists a subject that a 1st sealing member cannot be formed and manufacturing cost increases.

  Also, a structure in which a semiconductor integrated circuit device (CMOS) and a MEMS structure are monolithically configured has the same problem as described above.

  Accordingly, the present invention solves the above-described problems, and an object of the present invention is to efficiently carry out a manufacturing process of an electronic device including a functional structure and an electronic circuit disposed in a cavity on a substrate, and to achieve a manufacturing yield. It is to realize a structure of an electronic device, a resonator, and an oscillator, and a method for manufacturing the electronic device, which can secure the manufacturing cost and reduce the manufacturing cost.

  In view of such circumstances, an electronic device according to the present invention includes a substrate, a functional structure formed on the substrate, and a covering structure that defines a cavity in which the functional structure is disposed. The covering structure is provided on the substrate, covers a side wall made of an interlayer insulating layer and a wiring layer surrounding the cavity, and covers the upper part of the cavity and opens through the cavity. And a first covering layer having a laminated structure including a corrosion-resistant layer, and a second covering layer for closing the opening.

  According to such a configuration, the MEMS structure can be easily applied by applying the semiconductor manufacturing process by including the laminated structure of the interlayer insulating layer and the wiring layer in the covering structure that defines the cavity that accommodates the functional structure. Can be configured. In addition, the movable part can be released by removing the periphery of the functional structure through the opening of the first covering layer, and then the cavity is sealed by forming a second covering layer that closes the opening from the outside. It becomes possible to do. Furthermore, at this time, since the first coating layer covering the cavity from above includes the corrosion-resistant layer, even if the release process is performed for a long time, the corrosion-resistant layer has high etching resistance so that it remains without trouble. The closing process by the second coating layer can be reliably performed.

  Moreover, it is preferable that the said corrosion-resistant layer is comprised by a part of thickness direction of the said 1st coating layer.

  Since the corrosion-resistant layer is constituted by a part of the first coating layer, the coating structure that defines the cavity that accommodates the functional structure and the electronic circuit can be structurally highly integrated, and the functional structure. The manufacturing process and the manufacturing process of the electronic circuit can be easily made common, so that the electronic device can be downsized and the manufacturing cost can be reduced.

  Moreover, it is preferable that the said corrosion-resistant layer consists of TiN, Ti, W, Au, Pt, or each alloy.

  According to such a configuration, the corrosion-resistant layer is made of the above-described conductive material, so that the electromagnetic interaction between the functional structure and the outside can be reduced, and the corrosion-resistant layer is formed in a part of the wiring layer. It can also be formed. In addition, since the corrosion-resistant layer is made of a material that is also used as a surface layer or a barrier layer of the wiring layer, it is possible to simultaneously improve the function of the wiring layer and solve problems during the release process.

  Moreover, it is preferable that the said corrosion-resistant layer is comprised by the layer provided in the uppermost layer of the said 1st coating layer.

  Since the corrosion-resistant layer is provided on the uppermost layer of the first coating layer, the lower layer of the first coating layer is further difficult to be etched, and the rigidity of the first coating layer is easily secured. It becomes possible to perform the process of closing without trouble.

  Moreover, it is preferable that the said corrosion-resistant layer is comprised by the layer provided in the lowest layer of the said 1st coating layer.

  In this way, even if the etching solution accumulates in the lower space generated by the progress of etching in the release process because the corrosion-resistant layer is provided in the lowermost layer of the first coating layer, the first coating layer is used with the etching solution. Since it is difficult to etch other portions of the first coating layer, it is easy to secure the rigidity of the first coating layer. Therefore, the step of closing the opening with the second coating layer can be performed without any trouble.

  More preferably, the corrosion-resistant layer is composed of layers provided on the uppermost layer and the lowermost layer of the first coating layer.

  According to such a configuration, in particular, the corrosion-resistant layer is formed on both the uppermost layer and the lowermost layer of the first coating layer, thereby further facilitating the disappearance of the first coating layer and the decrease in rigidity.

  Moreover, it is desirable that the first covering layer has a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, and a TiN layer are laminated in this order from the surface facing the cavity.

  Moreover, it is desirable that the first covering layer has a laminated structure in which a TiN layer, an Al—Cu layer, a Ti layer, and a TiN layer are laminated in this order from the surface facing the cavity.

  Furthermore, it is desirable that the first covering layer has a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, a Ti layer, and a TiN layer are laminated in this order from the surface facing the cavity.

  Moreover, it is desirable that the first covering layer has a laminated structure in which a Ti layer, an Al—Cu layer, and a TiN layer are laminated in this order from the surface facing the cavity.

  Moreover, it is desirable that the first covering layer has a laminated structure in which a TiN layer, an Al—Cu layer, and a TiN layer are laminated in this order from the surface facing the cavity.

When a hydrofluoric acid-based solution is used to release and remove the sacrificial layer and the interlayer insulating layer, Ti and TiN are particularly difficult to dissolve. Therefore, the disappearance of the first coating layer and the decrease in rigidity can be prevented by forming the Ti layer and the TiN layer alone or in multiple layers on the uppermost layer and the lowermost layer of the first coating layer.
In addition, as the corrosion-resistant layer, W, Au, Pt, or an alloy thereof can be used.

  The electronic device according to the present invention is an electronic device in which a substrate, a functional structure and a CMOS circuit portion are provided on the substrate, and the cavity portion is defined. A covering structure is a first layered structure including a sidewall made of an interlayer insulating layer and a wiring layer surrounding the cavity, an upper portion of the cavity, an opening penetrating the cavity, and a corrosion-resistant layer. And at least one of the interlayer insulating layer and the wiring layer is a part of the interlayer insulating layer or the wiring layer of the CMOS circuit portion.

  According to such a configuration, since it can be made common to a part of the interlayer insulating layer and the wiring layer of each of the functional structure and the CMOS circuit portion, it can be reduced in thickness and size, and a semiconductor manufacturing process is used. Can be manufactured efficiently, and the manufacturing cost can be reduced.

The resonator of the present invention includes a substrate, a functional structure formed on the substrate, and a covering structure that defines a cavity in which the functional structure is disposed. A laminated structure including a corrosion-resistant layer provided on the substrate and including a sidewall made of an interlayer insulating layer and a wiring layer surrounding the cavity, an upper portion of the cavity, and an opening penetrating the cavity. And a second coating layer that closes the opening.
Here, the functional structure is, for example, a MEMS structure that resonates in a specific frequency band.

  According to such a configuration, the first coating layer covering the cavity from above includes the corrosion-resistant layer, so that even if the release process is performed for a long time, the corrosion-resistant layer has high etching resistance and remains without trouble. Therefore, the closing process by the second coating layer can be surely performed, and a highly reliable resonator can be realized.

The oscillator according to the present invention includes a substrate, a functional structure disposed inside the cavity, and a CMOS circuit including an oscillation circuit provided on the substrate to define the cavity. A covering structure comprising a laminated structure including a sidewall made of an interlayer insulating layer and a wiring layer surrounding the cavity, an upper portion of the cavity, an opening penetrating the cavity, and a corrosion-resistant layer. And at least one of the interlayer insulating layer and the wiring layer is a part of the interlayer insulating layer and the wiring layer of the CMOS circuit portion.
Here, the functional structure is, for example, a MEMS structure that resonates in a specific frequency band.

  According to such a configuration, since the functional structure region and the CMOS circuit portion region are provided on the substrate, the size of the oscillator can be reduced. In addition, since the first coating layer that covers the cavity from above includes the corrosion-resistant layer, the corrosion-resistant layer remains without any trouble even if the release process is performed for a long time. It is possible to reliably perform the closing process by the layer and to provide a highly reliable oscillator.

  According to another aspect of the present invention, there is provided an electronic device manufacturing method comprising: a substrate; a functional structure formed on the substrate; and a covering structure that defines a cavity in which the functional structure is disposed. A manufacturing method, the functional structure forming step of forming the functional structure together with a sacrificial layer on the substrate, the interlayer insulating layer forming step of forming an interlayer insulating layer on the periphery including the upper portion of the functional structure, A first covering layer forming step of forming a first covering layer having an opening having a laminated structure including a corrosion-resistant layer on the interlayer insulating layer; and the interlayer insulating layer and the sacrificial layer on the functional structure through the opening. And a release step for removing, and a second coating layer forming step for forming a second coating layer for closing the opening.

  According to such a manufacturing method, the release process is performed for a long time by performing the release process after the first coating layer forming process including the corrosion-resistant layer that covers the cavity where the functional structure is disposed from above. Even if it is carried out, the corrosion-resistant layer remains with no trouble because it has high etching resistance, so that the closing treatment by the second coating layer can be carried out reliably, and a highly reliable electronic device can be realized.

  Furthermore, a method for manufacturing an electronic device according to the present invention is a method for manufacturing an electronic device in which a substrate, a functional structure disposed inside a cavity portion, and a CMOS circuit portion are provided on the substrate. Forming a functional structure on the substrate together with a sacrificial layer, forming a CMOS transistor, and forming an interlayer insulating layer on the periphery including the upper part of the functional structure and the upper part of the CMOS transistor. Forming an interlayer insulating layer; a first covering layer covering the cavity and having an opening above the interlayer insulating layer; a wiring layer connected to the functional structure; and a wiring layer connected to the CMOS transistor Forming a protective film on the periphery including the wiring layer forming step of forming the first covering layer, the wiring layer connected to the functional structure, and the wiring layer connected to the CMOS transistor A protective film forming step, a release step of removing the interlayer insulating layer and the sacrificial layer on the functional structure through the opening, a second covering layer forming step of forming a second covering layer for closing the opening, It is characterized by including.

  According to such a manufacturing method, it is possible to form some of the interlayer insulating layers and the wiring layers of the functional structure and the CMOS circuit portion in a common process using a semiconductor manufacturing process, thereby simplifying the manufacturing process. And shortening.

FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. FIG. 3 is a schematic process cross-sectional view illustrating a manufacturing process according to the first embodiment. 1 is a schematic longitudinal sectional view of an element device according to Embodiment 1. FIG. FIG. 3 is an enlarged partial cross-sectional view illustrating a cross-sectional shape of a first coating layer according to the first embodiment. The longitudinal cross-sectional view which shows the structure of another electronic device. The longitudinal cross-sectional view which shows the structure of a different electronic device. (A)-(d) is a schematic partial process explanatory drawing which shows another manufacturing process. FIG. 6 is a plan layout diagram illustrating a schematic configuration of an electronic device according to a second embodiment. FIG. 6 is a cross-sectional view illustrating a schematic structure of a main part of an electronic device according to a second embodiment. FIG. 5 is a plan layout diagram showing a schematic structure of a MEMS structure region according to a second embodiment. FIG. 5 is a schematic process cross-sectional view illustrating a manufacturing process of an electronic device according to a second embodiment. FIG. 5 is a schematic process cross-sectional view illustrating a manufacturing process of an electronic device according to a second embodiment. FIG. 5 is a schematic process cross-sectional view illustrating a manufacturing process of an electronic device according to a second embodiment. FIG. 5 is a schematic process cross-sectional view illustrating a manufacturing process of an electronic device according to a second embodiment.

Next, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In addition, the figure referred in the following description is a schematic diagram from which the scale of the length of the member thru | or a part and thickness differs from an actual thing for convenience of illustration.
(Embodiment 1)

  First, a method for manufacturing an electronic device according to Embodiment 1 will be described. 1 to 8 are schematic process diagrams showing a method of manufacturing an electronic device according to the present invention.

  1 to 3 are cross-sectional views showing a functional structure forming process for forming the functional structure 3X together with the sacrificial layer 2 on the substrate 1. FIG. First, a substrate 1 made of a semiconductor substrate or the like shown in FIG. 1 is prepared. The substrate 1 is most preferably a semiconductor substrate such as a silicon substrate, but various substrates such as a ceramic substrate, a glass substrate, a sapphire substrate, a diamond substrate, and a synthetic resin substrate can be used. When a semiconductor substrate is used, a predetermined semiconductor integrated circuit (not shown, for example, a CMOS transistor) can be built in the substrate 1 in advance or in an appropriate process. In the manufacturing method of the present embodiment, a semiconductor substrate provided with appropriate impurity regions (not shown) in the surface layer portion of the substrate 1 is used. In addition, a manufacturing method is set so that an appropriate wiring structure is formed on the semiconductor substrate, and an electronic device (semiconductor integrated circuit) is formed by a CMOS process as a whole. However, the present invention can be applied not only to a semiconductor circuit but also to an electronic device including various electronic circuits (including a simple wiring pattern) other than the semiconductor circuit.

  Next, the sacrificial layer 2 is formed on the surface of the substrate 1. The sacrificial layer 2 can be composed of, for example, a silicon oxide film, a PSG (phosphorus doped glass) film, or the like, and is formed by a CVD method, a sputtering method, or the like. In the illustrated example, an appropriate patterning process such as a method of performing etching using a patterning mask in which an opening 2a for forming a support part of a MEMS structure described later is formed at a proper position of the sacrificial layer 2 by a photolithography method or the like. It is formed by.

  Next, as shown in FIG. 2, a functional layer 3 made of a conductive silicon film (doped polycrystalline silicon) or the like is formed on the sacrificial layer 2. The functional layer 3 is connected to the substrate 1 (for example, a lower electrode (not shown) formed on the substrate 1) through the opening 2a formed as described above. The functional layer 3 is formed by a sputtering method, a CVD method, or the like. Then, the functional layer 3X is formed by patterning the functional layer 3 by an appropriate patterning method as shown in FIG. Here, the functional structure 3X is a MEMS structure, and the functional structure 3X is illustrated as being configured by a single layer, but may be formed by a stacked structure of two or more layers. The functional structure 3X may be expressed as a MEMS structure 3X.

  In the illustrated example, a diaphragm-shaped MEMS structure 3X having a support portion corresponding to the opening 2a of the sacrificial layer 2 at the center lower portion is provided. However, the counter electrode and the like are not shown. In addition, the illustrated example schematically shows the MEMS structure 3X and does not accurately represent the actual structure. As the MEMS structure 3X, it is possible to form a movable portion having various planar patterns such as a comb shape, a beam shape, and a disk shape. In addition, an element configured as an element having an arbitrary function such as an element used as a vibrator, an actuator, or a sensor can be formed.

  Further, the functional structure 3X may constitute various functional structures such as a crystal resonator, a SAW (surface acoustic wave) element, an acceleration sensor, and a gyroscope other than the MEMS structure described above. In other words, the electronic device of the present invention only needs to have an arbitrary functional structure that can be disposed in the cavity.

  In the present embodiment, as shown in FIG. 3, a lower surrounding wall (guard ring) 3Y configured to surround the MEMS structure 3X in a plane is formed simultaneously with the MEMS structure 3X. The lower surrounding wall 3Y is formed of the same layer and the same material as the MEMS structure 3X, and is formed simultaneously with the MEMS structure 3X by patterning the functional layer 3. The planar shape of the lower surrounding wall 3Y is, for example, a quadrangle (square) in the illustrated example, but may be any shape such as a circle or a polygon as long as it is a closed shape that surrounds the MEMS structure 3X. The lower surrounding wall 3Y is made of a material that is not substantially removed in a release process for removing the sacrificial layer 2 and interlayer insulating layers 4 and 6 (see FIG. 4), which will be described later (in other words, a method for removing the release process). It is preferable to be a method having selectivity for etching between the material to be removed and the lower surrounding wall 3Y, and more preferably a conductive material. Examples of the conductive material include a conductive semiconductor (a highly doped semiconductor), such as polysilicon, or a metal material used for a corrosion-resistant layer described later.

FIG. 4 is a cross-sectional view showing an interlayer insulating layer forming step of forming an interlayer insulating layer on the periphery including the upper portion of the MEMS structure 3X.
As shown in FIG. 4, on the MEMS structure 3X and the lower surrounding wall 3Y, an interlayer insulating layer 4 made of an insulator such as silicon oxide (for example, TEOS; a CVD film using tetraethylorthosilicate as a source gas), aluminum A wiring layer 5 made of a conductor such as silicon and an interlayer insulating layer 6 made of an insulator such as silicon oxide are sequentially formed. This laminated structure is formed by a method similar to a normal CMOS process. This laminated structure constitutes a covering structure for defining a hollow portion that finally accommodates the MEMS structure 3X. A part of the wiring layer 5 is exposed by a through hole 6a for conductive connection to the upper layer structure. Note that the number of stacked layers of the interlayer insulating layer 4, the wiring layer 5, and the interlayer insulating layer 6 is appropriately configured as necessary. For example, in an actual CMOS process, more wiring layers may be stacked through interlayer insulating layers.

  In the case of this embodiment, an opening 4a that exposes the lower surrounding wall 3Y is formed in the interlayer insulating layer 4, and a part of the wiring layer 5 is formed in the opening 4a to surround the MEMS structure 3X. A surrounding wall (guard ring) 5Y having a planar shape is formed. Although the wiring layer 5 other than the surrounding wall 5Y is not illustrated in FIG. 4, the wiring layer 5 is actually formed so that a predetermined wiring pattern is formed, and a part of the wiring layer 5 is illustrated. It becomes. However, it is desirable that the surrounding wall 5Y is not conductively connected to other wiring patterns. Here, similarly to the lower surrounding wall 3Y, the surrounding wall 5Y has a closed planar shape surrounding the MEMS structure 3X such as a circle or a polygon. In this case, the connection portion of the opening 4a and the surrounding wall 5Y passing through the opening 4a has a closed shape surrounding the MEMS structure 3X, so that the lower surrounding wall 3Y and the surrounding wall 5Y are configured as an integral side wall. Is done.

  In the illustrated example, the wiring layer 5 is a single layer, but a plurality of wiring layers 5 may be stacked via another interlayer insulating layer (not shown). In this case, the surrounding wall 5Y is also a multilayer. . Here, it is preferable that the plurality of surrounding walls 5Y are connected through the opening of the interlayer insulating layer. In particular, the plurality of surrounding walls 5Y are formed as a single side wall by configuring the opening itself and the connecting portion of the surrounding wall through the inside thereof in a closed shape surrounding the MEMS structure 3X.

  Thereafter, a conductor layer is formed on the interlayer insulating layer 6 as shown in FIG. 5, and a wiring layer 7 is formed by patterning this conductor layer. As a part of the wiring layer 7, as shown in FIG. One covering layer 7Y is formed. Here, the 1st coating layer 7Y is arrange | positioned so that the upper direction of the MEMS structure 3X may be covered. In the case of the present embodiment, a plurality of openings 7a are formed in the first coating layer 7Y. For example, the openings 7a are arranged vertically and horizontally on a plane, and a part of the first coating layer 7Y is formed in a mesh shape as a whole. The opening 7a is formed at the same time when the wiring layer 7 is formed by patterning the conductor layer. Accordingly, the manufacturing process is the same as when the first covering layer 7Y is not formed (that is, when only the wiring pattern of the wiring layer 7 is formed).

  Here, the first coating layer 7Y is connected to the wiring layer 5 through the through hole 6a. In particular, the through hole 6a has a closed shape surrounding the MEMS structure 3X, and the connection portion of the first covering layer 7Y passing through the through-hole 6a with respect to the surrounding wall 5Y also has a closed shape surrounding the MEMS structure 3X. preferable.

  As described above, when the integrated side wall 10Y (see FIG. 8) is formed by the lower surrounding wall 3Y, the surrounding wall 5Y, and the first covering layer 7Y, the MEMS structure 3X includes the substrate 1 and the side wall 10Y. And the first covering layer 7Y is completely surrounded from below, above and from the side.

  The lower surrounding wall 3Y, the surrounding wall 5Y and the first covering layer 7Y, or the side wall 10Y formed by integrating them (see FIG. 8) are respectively or integrally provided with a predetermined potential (for example, (Ground potential) is preferably applied. Accordingly, the MEMS structure 3X can be shielded to some extent electromagnetically from the outside, and the electromagnetic interaction between the MEMS structure 3X and the outside can be increased as the shielding rate against the MEMS structure 3X is increased. (That is, noise) can be reduced. The configuration of the first coating layer 7Y will be described later with reference to FIG.

  Next, as shown in FIG. 7, by removing the interlayer insulating layer 6, the interlayer insulating layer 4 and the sacrificial layer 2 around the MEMS structure 3X through the plurality of scattered openings 7a, the MEMS structure 3X is removed. The cavity S to be accommodated is formed (release process). Here, the interlayer insulating layer 6, the interlayer insulating layer 4, and the sacrificial layer 2 are removed by wet etching with a hydrofluoric acid-based solution such as hydrofluoric acid (HF) or buffered hydrofluoric acid (BHF), or hydrofluoric acid-based It can be performed by dry etching using gas (vapor) or the like. Since such an etching method is isotropic etching, the MEMS structure 3X can be easily released even through the small opening 7a. This etching is performed in a state where the surface other than the surface of the first coating layer 7Y is covered with an etching mask made of resist or the like (shown by a dotted line in FIG. 7).

  Since the above etching method does not substantially exhibit the removal performance for the MEMS structure 3X, the lower surrounding wall 3Y, the surrounding wall 5Y, and the first covering layer 7Y, the interlayer insulating layer 6 around the MEMS structure 3X, Even if the interlayer insulating layer 4 and the sacrificial layer 2 are completely removed, the cavity S can be prevented from spreading outside the lower surrounding wall 3Y and the surrounding wall 5Y. Here, when the release process is completed, the cavity S is sufficiently cleaned. For example, the cavity S is washed with water, and then moisture is completely removed using a substitution method or the like. The lower surrounding wall 3Y, the surrounding wall 5Y, and the lower portion of the first covering layer 7Y (the connecting portion in the through hole 6a) constitute the surrounding covering portion.

  Next, as shown in FIG. 8, silicon oxide, silicon nitride, resin material, etc. are formed on the interlayer insulating layer 6, the first covering layer 7Y, and other portions (not shown) of the wiring layer 7 formed at the same time. Is formed. As the protective film 8, a surface protective film (passivation film) such as silicon nitride or insulating resist can be used. Then, by forming an opening 8a in the protective film 8 by dry etching or the like, the first covering layer 7Y and a part of the wiring layer 7 are exposed to form a pad portion for conductive connection. Further, the protective film 8 is formed with an opening 8b at the same time as the opening 8a, and a portion of the first covering layer 7Y located above the MEMS structure 3X (region where the opening 7a is formed) by the opening 8b. To expose. The formation and patterning of the protective film 8 will be described later if the protective film 8 is a material that can withstand the etching in the release process or if a mask such as a resist is formed on the surface of the protective film 8. Thus, it may be performed before the release step.

  As shown in FIG. 9, the wiring layer 7 (first covering layer 7Y) includes a first layer 7b made of Ti as a lowermost layer from a surface facing the cavity S, a second layer 7c made of TiN, and Al—Cu ( A fourth layer 7e made of an alloy) and a fourth layer 7e made of TiN as the uppermost layer. The first layer 7b is for improving the covering property (coverage property) to the lower interlayer insulating layer 6, and has a thickness of about 10 to 100 nm, preferably about 20 to 70 nm, for example, by vapor deposition or sputtering. It is formed. The second layer 7c is a barrier layer for preventing the lower constituent material (such as Si atoms) and impurities from entering, and is formed by, for example, a sputtering method, a CVD method, an ion plating method, or the like, and has a thickness of 50 to 200 nm. The thickness is preferably about 80 to 150 nm. The third layer 7d is composed of an alloy in which 1 wt% or less of Cu is added to Al, and is a main layer that ensures the conductivity of the wiring layer 7, and is formed by, for example, a vapor deposition method or a sputtering method, and has a thickness of about 500 to 1000 nm. The thickness is preferably about 700 to 900 nm. The fourth layer 7e is configured as an antireflection film for a photo process, and can be formed by the same method as the second layer 7c, for example, and has a thickness of about 20 to 200 nm, preferably about 50 to 100 nm.

  The first covering layer 7 </ b> Y described above has the same stacked structure as the wiring layer 7. Here, each material constituting the wiring layer 7 has resistance to etching used in a release process (to be described later) (the etching is basically used to remove a component mainly composed of silicon oxide). However, the third layer (Al—Cu) 7d has an etching selectivity ratio with respect to silicon oxide that is not sufficiently high, and therefore may be removed by the etching for a long time. On the other hand, the first layer (Ti) 7b, the second layer (TiN) 7c, and the fourth layer (TiN) 7e have a high etching selectivity and can sufficiently withstand long-time etching. ing.

  In the present embodiment, a layer made of a material having resistance to an etchant mainly composed of hydrofluoric acid is referred to as a corrosion resistant layer, and the first layer 7b, the second layer 7c, and the fourth layer 7e correspond to the corrosion resistant layer. To do. Here, various materials such as a resin material can be considered as the material constituting the corrosion-resistant layer, but those composed of metals or metal compounds such as TiN, Ti, W, Au, and Pt are preferable. The laminated structure of the wiring layer 7 can also be used for other wiring layers such as the wiring layer 5 described above. By doing so, the structure of the surrounding wall 5Y is more convenient because the etching resistance during the release process is improved.

  The laminated structure of the wiring layer 7 (first covering layer 7Y) is a configuration that can be suitably used as a wiring layer used in a semiconductor process, but the configuration may be other than the configuration of the illustrated example. Can be adapted.

  For example, the first covering layer 7Y may have a stacked structure in which a TiN layer, an Al—Cu layer, a Ti layer, and a TiN layer are stacked in this order from the surface facing the cavity S. A layered structure in which a layer, a TiN layer, an Al—Cu layer, a Ti layer, and a TiN layer are stacked in this order may be employed.

  Further, the first covering layer 7Y may have a laminated structure in which a Ti layer, an Al—Cu layer, and a TiN layer are laminated in this order from the surface facing the cavity S, and the TiN layer, Al A stacked structure in which a Cu layer and a TiN layer are stacked in this order may be used.

  Finally, as shown in FIG. 8, the opening 7a is closed by forming the second covering layer 9 on the first covering layer 7Y, and the cavity S is sealed. Thus, the electronic device 100 is completed. The second coating layer 9 is preferably formed by a vapor phase growth method such as a CVD method or a sputtering method. This is because the cavity S can be sealed in a reduced pressure state as it is. As the second coating layer 9 formed by the vapor phase growth method, for example, an insulator such as silicon oxide or silicon nitride (CVD method), or a metal or other conductive material such as Al, W, or Ti (sputtering method). Etc.

  In this step, when the second covering layer 9 is made of a metal or other conductive material, the connection pad conductively connected to the wiring layer 7 is formed by leaving the formed film on the opening 8a. You may make it form. Moreover, the above-mentioned upper coating | coated part is comprised by the 1st coating layer 7Y and the 2nd coating layer 9 in this embodiment.

  Furthermore, the opening 7a is preferably formed at a position offset from a position directly above the MEMS structure 3X. In the illustrated example, the opening 7a exists at a position shifted in the planar direction with respect to the MEMS structure 3X. In this way, it is possible to avoid problems such as the material such as the second coating layer 9 adhering to the MEMS structure 3X when the second coating layer 9 is formed. The amount of deviation in the planar direction differs depending on the formation method of the second coating layer 9 and the like, but if it is formed by the above-described vapor phase growth method, it is at least about 0.5 μm, actually 0.5 to It is preferably about 5.0 μm.

  In the electronic device according to the present embodiment, the cavity S that accommodates the MEMS structure 3X has a covering structure in which the laminated structure of the interlayer insulating layers 4 and 6 and the wiring layers 5 and 7 surrounds the cavity S. Is defined. Therefore, since the first covering layer 7Y covering the cavity S is constituted by a part of the wiring layer 7, the integrity with the electronic circuit that requires the above laminated structure can be improved, so that the electronic device can be downsized. In addition, the manufacturing cost can be reduced. In particular, since the first covering layer 7Y that covers the MEMS structure 3X from above is formed of a conductive material made of a part of the wiring layer 7, electromagnetic interaction with the outside can be reduced. In this case, it is needless to say that it is more preferable that the second covering layer 9 is also made of a conductive material.

  Further, in the above-described covering structure, the surrounding wall 5Y having a closed planar shape surrounding the MEMS structure 3X is provided by a part of the wiring layer, so that it is integrated with the electronic circuit that requires the laminated structure as described above. Therefore, the electronic device can be miniaturized and the manufacturing cost can be reduced. In particular, since the surrounding wall 5Y is present, the side etching range during the release process can be suppressed, so that the cavity S that accommodates the MEMS structure 3X can be easily reduced in size, and is formed of a part of the wiring layer 5. The presence of the surrounding wall 5Y made of a conductive material can reduce electromagnetic interaction between the MEMS structure 3X and the outside.

  In the present embodiment, the first coating layer 7Y formed of a part of the wiring layer 7 above the MEMS structure 3X is covered with the corrosion resistance layers of the first layer 7b, the second layer 7c, and the fourth layer 7e. Therefore, the first covering layer 7Y can be prevented from disappearing or thinning even if the etching time is increased in the release step. Normally, the release process through the opening 7a is significantly longer than the case where the first coating layer 7Y is not present, so that even a material that is inherently difficult to etch with a hydrofluoric acid-based etchant is partially There is a risk that it will disappear or the shape will collapse. However, if the corrosion-resistant layer is composed of a metal or a metal compound such as TiN, Ti, W, Au, or Pt described above, it remains without any problems even after the release process, and as a result, the second coating layer 9 is hindered. It becomes possible to form without.

  In particular, the TiN, Ti, W, Au, and Pt materials described above are not only highly resistant to hydrofluoric acid-based etching solutions, but also have conductivity, so that they can be used for conductive materials such as wiring layers. In particular, the affinity for the semiconductor manufacturing process is high. In addition, these materials are not merely conductive materials, for example, high barrier properties (TiN, etc.), ohmic contact properties (Au, etc.), corrosion resistance and oxidation resistance (Ti, TiN, It also has an additional function for conductive materials such as W and Pt. At the same time, since these additional functions are particularly useful as a surface layer of a conductive material, it is considered that there is a very wide range of scenes that can also be used for structures other than the MEMS structure of electronic devices (such as wiring of electronic circuits).

  In the first covering layer 7Y, the fourth layer 7e, which is a corrosion-resistant layer, is present at the uppermost layer, and the first layer 7b, which is a corrosion-resistant layer, is present at the lowermost layer, thereby eroding the third layer 7d with respect to the etching solution. Can be effectively avoided. Such an effect can be sufficiently obtained even if the corrosion-resistant layer is only on the uppermost layer or the lowermost layer, but it is preferable that the corrosion-resistant layer is particularly formed on the uppermost layer, and as described above, Most desirably, corrosion resistant layers are formed on both the upper and lower layers. In addition, although the case where the process different from a normal semiconductor manufacturing process will be needed is considered, the whole 1st coating layer 7Y (wiring layer 7) may be comprised with the corrosion-resistant layer. For example, the first coating layer 7Y may be composed of a single layer of TiN.

  In the above configuration, since the integral side wall 10Y is formed so as to surround the MEMS structure 3X, the removal range in the release process can be completely limited in a planar manner, so that the cavity S can be further downsized. Can do. In addition, if the side wall 10Y is entirely made of a conductive material, the degree of shielding of the MEMS structure 3X by the conductor can be further increased, so that the electromagnetic interaction between the MEMS structure 3X and the outside is further reduced. can do. In particular, the electromagnetic shielding effect of the MEMS structure 3X can be further enhanced by connecting the side wall 10Y and the first covering layer 7Y.

  FIG. 10 shows an example in which the protective film 8 is used as the second coating layer. In this case, the second coating layer is preferably made of an insulator. According to this, since the protective film 8 also serves as the second coating layer, the number of processes is reduced (the film formation and patterning of the second coating layer 9 is not necessary), so that the manufacturing cost can be further reduced.

  FIG. 11 shows an example in which the third covering layer 5Z that covers the upper portion of the MEMS structure 3X and includes the opening 5a is formed by a part of the wiring layer 5 described above. Here, the third coating layer 5Z is configured to overlap with the opening 7a of the first coating layer 7Y in a plane, and further, the opening 5a overlaps with the first coating layer 7Y in a plane. That is, the planar area exposed at the opening 7a is covered with the third covering layer 5Z, and the planar area exposed at the opening 5a is covered with the first covering layer 7Y. Even when the film is formed by the phase growth method, the material of the second coating layer 9 can be prevented from adhering to the MEMS structure 3X. Therefore, as described in the previous embodiment, it is not necessary to provide the planar range of the MEMS structure 3X and the opening range of the opening 7a offset in a plane. In this case, the above-described upper covering portion is configured by the first covering layer 7Y, the second covering layer 9, and the third covering layer 5Z, and the above-described first covering layer is formed by the first covering layer 7Y and the third covering layer 5Z. Composed.

  In this case, since the third coating layer 5Z is also exposed to the etching solution for a long time in the release step, the same structure as the first coating layer 7Y is used for the third coating layer 5Z. The third coating layer 5Z can be left without any trouble by the corrosion resistant layer included in the three coating layers 5Z. Here, like the first covering layer 7Y, the uppermost layer or the lowermost layer of the third covering layer 5Z is preferably composed of a corrosion-resistant layer, and in particular, the uppermost layer and the lowermost layer of the third covering layer 5Z. It is desirable that both are composed of corrosion resistant layers.

  FIG. 12 is a schematic explanatory view (a) to (d) showing a manufacturing process different from the above embodiment. Here, FIG. 12 shows only the wiring layer 7 (first covering layer 7Y) and its upper layer structure, and other structures are omitted. In this manufacturing process, as shown in FIG. 12A, the first covering layer 7Y is formed at the same time in the wiring forming step for forming the wiring layer 7, and the opening 7a is provided. Next, as shown in FIG. 12B, a protective film 8 is formed on the wiring layer 7 and the first covering layer 7Y.

  Thereafter, as shown in FIG. 12C, the protective film 8 on the first coating layer 7Y is removed by dry etching or the like using an etching mask 9 ′ formed of a photoresist or the like, and FIG. As shown, an opening 8b is formed in the protective film 8 to expose the first coating layer 7Y. At this time, at least a part of the fourth layer 7e remains on the surface of the first coating layer 7Y opened by the opening 8b. That is, if the fourth layer 7e is also removed by the partial removal of the protective film 8, the third layer 7d is more likely to be eroded in the release process, and therefore the corrosion resistance layer of the fourth layer 7e is increased. The processing time, processing conditions, etc. of the etching such as the dry etching are optimized so that at least a part of the first coating layer 7Y remains over the entire surface. Note that the processing contents of the process are the same in the above-described embodiment.

  In this manufacturing process, after forming the protective film 8 and forming the opening 8b as described above, a release step is performed through the opening 7a of the first coating layer 7Y. With this method, the protective film 8 can be used as an etching mask in the release process, so that the resist forming process for forming the etching mask 9 'in the above-described embodiment can be omitted.

  If the MEMS structure 3X having the above configuration is a SAW or a vibrating body including a mover and a stator, the electronic device 100 (see FIG. 8) of the present embodiment can form a resonator.

According to such a configuration and manufacturing method, the first coating layer 7Y that covers the cavity S from above includes the corrosion-resistant layer, so that the corrosion-resistant layer has high etching resistance even when the release process is performed for a long time. Therefore, the closing process by the second coating layer can be performed reliably, and a highly reliable resonator can be realized.
(Embodiment 2)

Next, an electronic device according to Embodiment 2 will be described with reference to the drawings. The electronic device according to the present embodiment is characterized in that a substrate is a semiconductor substrate, and a functional structure and a CMOS circuit portion are provided on the substrate and disposed inside the cavity.
FIG. 13 is a plan layout diagram illustrating a schematic configuration of the electronic device according to the second embodiment. In FIG. 13, the electronic device 200 is configured such that a functional structure region 150 and a CMOS circuit portion region 160 are provided on a substrate 11. In addition, it is good also as a structure where a part of each of the CMOS circuit part area | region 160 and each functional structure area | region 150 cross | intersects a cross-sectional direction. Hereinafter, the functional structure region may be expressed as a MEMS structure region.

Next, a cross-sectional structure of the electronic device 200 will be described.
FIG. 14 is a cross-sectional view illustrating a schematic structure of a main part of the electronic device according to the second embodiment. In FIG. 14, in this embodiment, a substrate 11 made of a semiconductor substrate such as silicon or a compound semiconductor is used. However, the substrate 11 may be made of other materials such as glass, ceramics, sapphire, diamond, and synthetic resin.

  On the substrate 11, an underlayer (element isolation layer) 12 made of silicon nitride or the like is formed. Further, in the MEMS structure region 150 on the substrate 11, a lower structure portion 13A and an upper structure portion 15A that constitute a MEMS structure such as a vibrating body, a filter, an actuator, and a sensor are formed. In this embodiment, a resonator having the lower structure portion 13A as a stator and the upper structure portion 15A as a mover is illustrated. Accordingly, the lower structure portion 13A and the upper structure portion 15A are spaced apart from each other.

  In the CMOS circuit portion region 160 on the substrate 11, a capacitor is configured in which the lower electrode 13B and the upper electrode 15B are disposed to face each other with the insulating film 14B interposed therebetween. Furthermore, a CMOS transistor including an active layer 11A, impurity regions 11B and 11C, a gate insulating film 14C, and a gate electrode 15C is formed on the surface layer portion of the substrate 11.

  The material of the lower structure portion 13A and the upper structure portion 15A is not particularly limited as long as it is a conductor. However, for example, the material can be implemented in the same process or the same process as the gate electrode 15C constituting the CMOS transistor. It is desirable to be composed of a silicon film (doped polycrystalline silicon). The conductive silicon film is a material constituting a functional layer formed in the semiconductor manufacturing process, and is not limited to the CMOS transistor, and has an advantage that the manufacturing process can be shared by forming simultaneously with the functional layer in the semiconductor circuit. .

On the substrate 11, an interlayer insulating layer made of silicon oxide (SiO ₂ ) as an insulating layer, more specifically PSG (phosphorus-doped glass), TEOS (CVD film formed using tetraethyl orthosilicate or the like as a source gas), or the like. 16, 18 and wiring layers 17A, 17B, 17C, and 17D made of a conductor layer such as aluminum, a first covering layer 19A, and wiring layers 19B, 19C, 19D, and 19E are formed. The wiring layers 19B, 19C, 19D, and 19E are conductive patterns for forming a predetermined circuit on the substrate 11. A protective film 21 made of silicon oxide (SiO ₂ ), silicon nitride (Si ₃ N ₄ ), or the like is laminated on each of the above layers. The protective film 21 is made of a material having patterning (etching) selectivity with respect to the interlayer insulating layers 16 and 18 and a later-described sacrificial layer. Further, a second coating layer 22 is formed on the first coating layer 19A.

  The interlayer insulating layers 16 and 18 are provided with openings, and the openings constitute a cavity C in which the above-described MEMS structure is disposed. The cavity C is hermetically sealed by being covered from above by a covering portion composed of the first covering layer 19A and the second covering layer 22. A plurality of openings 19a communicating with the cavity C are formed in the first covering layer 19A, and these openings 19a are closed by covering the second covering layer 22 from above.

  The first covering layer 19A is formed simultaneously with the wiring layers 19B, 19C, 19D, and 19E. For example, by forming a metal layer and then patterning, the first coating layer 19A having the opening 19a is formed simultaneously with the outer shape of the first coating layer 19A and each wiring layer. Here, the first coating layer 19 </ b> A may be formed of a multilayer structure having a plurality of layers like the other wiring layers. For example, the first layer (lowermost layer) has a thickness of 1-1000 nm, preferably about 50 nm of Ti or TiN, and the second layer (intermediate layer) has a thickness of about 10-10000 nm, preferably about 800 nm, an Al—Cu alloy layer, The layer (uppermost layer) is made of TiN having a thickness of 1-1000 nm, preferably about 50 nm. In this case, it is possible to easily perform the release process by removing the first layer to be disposed immediately above the cavity C.

  In addition, as described in the first embodiment (see FIG. 9), the first coating layer 19A includes a Ti layer, a TiN layer, an Al—Cu layer, and a TiN layer from the surface facing the cavity C. Laminated structure laminated in order, TiN layer, Al—Cu layer, Ti layer, TiN layer laminated in order from the surface facing the cavity C, Ti layer, TiN layer, Al—from the surface facing the cavity C From a laminated structure in which Cu layer, Ti layer, TiN layer are laminated in order, and from a face facing cavity C, a laminated structure laminated in order of Ti layer, Al-Cu layer, TiN layer, and face facing cavity C A laminated structure in which a TiN layer, an Al—Cu layer, and a TiN layer are laminated in this order can be adapted.

  Further, since the arrangement configuration described in the first embodiment can be applied to the opening 19a provided in the first coating layer 19A, the description thereof is omitted.

  In practice, the first insulating layer 19A is formed after the interlayer insulating layers 16 and 18 are formed, and the interlayer insulating layers 16 and 18 are etched and removed through the openings 19a of the first covering layer 19A by wet etching or dry etching. Thereafter, the cavity C is formed in a release process in which a cleaning process is performed.

  The second coating layer 22 is formed on the first coating layer 19A under a reduced pressure by a vapor phase growth method such as vacuum deposition, sputtering, or CVD, whereby the cavity C is decompressed through the opening 19a. In this state, the opening 19a is closed. The second coating layer 22 is formed of an insulator such as silicon oxide or silicon nitride, or a metal such as Al, Ti, or W.

Next, the structure of the MEMS structure region 150 will be described with reference to the drawings. Reference is also made to FIG.
FIG. 15 is a plan layout diagram showing a schematic structure of the MEMS structure region according to the present embodiment. In FIG. 15, a lower structure portion 13 </ b> A and an upper structure portion 15 </ b> A are formed in a substantially central portion of the MEMS structure region 150. A part of each of the lower structure portion 13A and the upper structure portion 15A intersects with each other in cross section and is spaced apart (see FIG. 14).

  The end portion of the lower structure portion 13A is connected to the wiring layer 19F through the through holes 17e and 19f and the wiring layer 17E. On the other hand, the end portion of the upper structure portion 15A is connected to the wiring layer 19B via the through holes 17a and 19b and the wiring layer 17A. Each of the wiring layers 17A and 19B is connected to one of the wiring layers of a CMOS circuit section (not shown).

  A first covering layer 19A is formed so as to cover the cavity C above the resonator composed of the lower structure portion 13A and the upper structure portion 15A. Then, the extended one end of the first covering layer 19A is connected to the interlayer wiring layer 17F through the through hole 17f, and is connected to the GND electrode of the CMOS circuit portion (not shown). In addition, lower surrounding walls 13a and 13b formed in the same process as the lower structure portion 13A are disposed around the cavity portion C.

  In this embodiment, at least an oscillation circuit is formed inside the CMOS circuit portion, one of the output portions thereof is connected to the upper structure portion 15A, and the other is connected to the lower structure portion 13A. An oscillation signal is output to the lower structure portion 13A. The MEMS structure is a resonator composed of a lower structure portion 13A and an upper structure portion 15A. When the same-polarity potentials are input to the upper structure portion 15A and the lower structure portion 13A, they repel each other and have different polarities. When an electric potential is input, the upper structure portion 15A vibrates in the cross-sectional direction. Accordingly, the electronic device 200 according to the present embodiment is exemplified by an oscillator in which a resonator and an oscillation circuit are provided on a semiconductor substrate.

  Then, the manufacturing method of the electronic device which concerns on Embodiment 2 is demonstrated. The manufacturing method described below shows an example in the case of manufacturing an electronic device in which a MEMS structure and a CMOS circuit unit are integrated. However, the present embodiment is not limited to such a mode, and a functional structure is described. It includes various functional devices in which the body is disposed in the cavity.

  16 to 19 are schematic process cross-sectional views illustrating the manufacturing process of the electronic device according to the present embodiment. As shown in FIG. 16, the active layer 11 </ b> A is first formed on the surface layer portion of the substrate 11. Further, a base layer 12 is formed on the substrate 11 by a film forming technique such as sputtering or CVD, and a fine patterning technique, and a film forming technique such as sputtering or CVD and a fine patterning technique are formed on the base layer 12. Thus, the lower structure portion 13A and the lower electrode 13B are simultaneously formed of the same material.

Subsequently, the sacrificial layer 14A, the insulating film 14B, and the gate insulating film 14C are simultaneously formed of the same material by a sputtering method or a CVD method. Thereafter, the upper structure portion 15A, the upper electrode 15B, and the gate electrode 15C are simultaneously formed of the same material by a sputtering method, a CVD method, or the like. After the formation of the gate electrode 15C, the impurity regions 11B and 11C are formed by self-alignment using the gate electrode 15C as a mask by an ion implantation method or the like.
The above is the functional structure forming process for forming the functional structure (MEMS structure) together with the sacrificial layer 14A and the process for forming the CMOS transistor.

  Next, an interlayer insulating layer 16 is formed on the structure by sputtering or CVD, and a through hole group including through holes 17a and 17e is formed by patterning. Thereafter, an appropriate wiring pattern is formed on the interlayer insulating layer 16 by a vapor deposition method, a sputtering method, a CVD method or the like, and the wiring layer 17E and the through hole 17a electrically connected to the lower structure portion 13A through the through hole 17e. Then, a wiring layer 17A connected to the upper structure portion 15A is formed.

  Further, a wiring layer 17B conductively connected to the upper electrode 15B through the through hole, and wiring layers 17C and 17D conductively connected to the impurity regions 11B and 11C through the through hole are formed. In addition, a lead wiring structure from a MEMS structure, a capacitor, and a CMOS transistor is formed by these wiring layers including other wiring layers not shown.

  Next, as shown in FIG. 17, an interlayer insulating layer 18 is formed on the periphery including the upper part of the MEMS structure and the upper part of the CMOS transistor by sputtering or CVD (interlayer insulating layer forming step). At this time, through holes 31 to 36 are formed by patterning.

  Next, as shown in FIG. 18, a first coating layer 19A and wiring layers 19B, 19C, 19D, 19E, and 19F are formed on the interlayer insulating layer 18 by vapor deposition, sputtering, CVD, or the like. In the MEMS structure, wiring layers 19F connected to the lower structure portion 13A, wiring layers 19B connected to the upper structure portion 15A, and wiring layers connecting the aforementioned CMOS circuit portion (CMOS transistor) are formed. (Wiring layer forming step). In the first covering layer 19A, an opening 19a is formed by a fine patterning technique together with the external pattern and the wiring pattern.

  After that, as shown in FIG. 19, a protective film 21 made of silicon nitride or the like is formed on the surfaces of the interlayer insulating layer 18 and the wiring layers 19B, 19C, 19D, 19E, and 19F by sputtering, CVD, etc. The region including the peripheral edge of the layer 19A is covered (protective film forming step).

  Subsequently, the underlying interlayer insulating layers 18 and 16 and the sacrificial layer 14A are removed through the opening 19a with a hydrofluoric acid aqueous solution, a buffered hydrofluoric acid aqueous solution, a hydrofluoric acid gas, or the like (release process). As a result, a cavity C is formed. Thereafter, the inner surface of the cavity C is washed with water or the like.

  Next, as shown in FIG. 14, the second coating layer 22 is formed in the decompressed space (reaction chamber) by vapor deposition, sputtering, CVD, or the like, thereby reducing the pressure in the cavity C. Then, the opening 19a is closed for sealing (second coating layer forming step).

  Therefore, the electronic device 200 according to the second embodiment described above is reduced in size because the functional structure (functional structure region 150) and the CMOS circuit portion (CMOS circuit portion region 160) are provided on the substrate 11 side by side. enable. That is, it is possible to reduce the size of the oscillator. In addition, since the first coating layer 19A that covers the cavity C from above includes the corrosion-resistant layer, the corrosion-resistant layer remains without any trouble even if the release process is performed for a long time, so that the first coating layer 19A has a high etching resistance. The closure process by the 2 coating layer 22 can be implemented reliably, and a reliable oscillator can be provided.

  Furthermore, since a part of the interlayer insulating layer and the wiring layer of each of the functional structure and the CMOS circuit portion can be made common, it can be efficiently manufactured using a semiconductor manufacturing process. Therefore, the manufacturing yield can be secured and the manufacturing cost can be reduced.

  Note that the electronic device and the manufacturing method thereof according to the present invention are not limited to the illustrated examples described above, and various modifications can be made without departing from the scope of the present invention.

  For example, in the above embodiment, a resonator or an oscillator is configured on a semiconductor substrate while performing a semiconductor manufacturing process similar to a CMOS process. However, a MEMS element (MEMS structure) as a functional structure such as an actuator or a high-frequency filter is formed. In addition to being applicable to the body 3X), the present invention can be applied to a structure including various functional structures other than the MEMS structure such as a crystal resonator, an acceleration sensor, and a gyro sensor.

  In the above embodiment, the semiconductor device is formed by integrating the functional structure with the semiconductor integrated circuit. However, a substrate other than the semiconductor substrate may be used, or another electronic circuit other than the semiconductor circuit may function. It may be connected to a structure.

  DESCRIPTION OF SYMBOLS 1 ... Board | substrate, 3X ... MEMS structure (functional structure), 3Y ... Lower surrounding wall, 4, 6 ... Interlayer insulation layer, 5 ... Wiring layer, 5Y ... Enclosing wall, 7Y ... 1st coating layer, 7a ... Opening, 9 ... 2nd coating layer, 10Y ... Side wall, 100 ... Electronic device.

Claims (16)

An electronic device comprising a substrate, a functional structure formed on the substrate, and a covering structure that defines a cavity in which the functional structure is disposed,
The covering structure is provided on the substrate and has a side wall made of an interlayer insulating layer and a wiring layer surrounding the cavity, and covers the upper part of the cavity and has an opening penetrating the cavity. An electronic device comprising: a first covering layer having a laminated structure including layers; and a second covering layer that closes the opening.   The electronic device according to claim 1, wherein the corrosion-resistant layer is configured by a part in a thickness direction of the first coating layer.   The electronic device according to claim 1, wherein the corrosion-resistant layer is made of TiN, Ti, W, Au, Pt, or an alloy thereof.   4. The electronic device according to claim 1, wherein the corrosion-resistant layer is formed of a layer provided on an uppermost layer of the first covering layer. 5.   4. The electronic device according to claim 1, wherein the corrosion-resistant layer is formed of a layer provided as a lowermost layer of the first covering layer. 5.   4. The electronic device according to claim 1, wherein the corrosion-resistant layer includes layers provided on an uppermost layer and a lowermost layer of the first coating layer. 5.   4. The structure according to claim 1, wherein the first covering layer has a laminated structure in which a Ti layer, a TiN layer, an Al—Cu layer, and a TiN layer are laminated in this order from the surface facing the cavity. An electronic device according to claim 1.   4. The structure according to claim 1, wherein the first covering layer has a laminated structure in which a TiN layer, an Al—Cu layer, a Ti layer, and a TiN layer are laminated in this order from the surface facing the cavity. An electronic device according to claim 1.   The first covering layer has a laminated structure in which a Ti layer, a TiN layer, an Al-Cu layer, a Ti layer, and a TiN layer are laminated in this order from the surface facing the cavity. 4. The electronic device according to any one of 3.   The said 1st coating layer is a laminated structure laminated | stacked in order of the Ti layer, the Al-Cu layer, and the TiN layer from the surface which faces the said cavity part, The Claim 1 thru | or 3 characterized by the above-mentioned. An electronic device according to 1.   The first covering layer has a stacked structure in which a TiN layer, an Al-Cu layer, and a TiN layer are stacked in this order from the surface facing the cavity. An electronic device according to 1. An electronic device comprising a substrate, a functional structure and a CMOS circuit portion disposed inside the cavity portion,
The covering structure that defines the cavity includes a sidewall made of an interlayer insulating layer and a wiring layer surrounding the cavity, an upper portion of the cavity, and an opening that penetrates the cavity. A first covering layer comprising a laminated structure including,
An electronic device, wherein at least one of the interlayer insulating layer and the wiring layer is a part of an interlayer insulating layer or a wiring layer of the CMOS circuit portion. A substrate, a functional structure formed on the substrate, and a covering structure that defines a cavity in which the functional structure is disposed;
The covering structure is provided on the substrate and has a side wall made of an interlayer insulating layer and a wiring layer surrounding the cavity, and covers the upper part of the cavity and has an opening penetrating the cavity. A resonator comprising: a first covering layer having a laminated structure including layers; and a second covering layer that closes the opening. A substrate, a functional structure disposed inside the hollow portion, and a CMOS circuit portion including an oscillation circuit are provided on the substrate,
The covering structure that defines the cavity includes a sidewall made of an interlayer insulating layer and a wiring layer surrounding the cavity, an upper portion of the cavity, and an opening that penetrates the cavity. A first covering layer comprising a laminated structure including,
An oscillator, wherein at least one of the interlayer insulating layer and the wiring layer is a part of the interlayer insulating layer and the wiring layer of the CMOS circuit portion. A method for manufacturing an electronic device, comprising: a substrate; a functional structure formed on the substrate; and a covering structure that defines a cavity in which the functional structure is disposed.
Forming a functional structure together with a sacrificial layer on the substrate;
An interlayer insulating layer forming step of forming an interlayer insulating layer on the periphery including the upper portion of the functional structure;
A first coating layer forming step of forming a first coating layer having an opening having a laminated structure including a corrosion-resistant layer on the interlayer insulating layer;
A release step of removing the interlayer insulating layer and the sacrificial layer on the functional structure through the opening;
And a second coating layer forming step of forming a second coating layer that closes the opening. A method of manufacturing an electronic device, wherein a substrate, a functional structure disposed inside a cavity, and a CMOS circuit portion are provided on the substrate,
Forming a functional structure together with a sacrificial layer on the substrate;
Forming a CMOS transistor;
An interlayer insulating layer forming step of forming an interlayer insulating layer on the periphery including the upper part of the functional structure and the upper part of the CMOS transistor;
A wiring layer forming step of forming a first covering layer covering the cavity and having an opening, a wiring layer connected to the functional structure, and a wiring layer connected to the CMOS transistor on the interlayer insulating layer When,
A protective film forming step of forming a protective film on a periphery including the first covering layer, a wiring layer connected to the functional structure, and a wiring layer connected to the CMOS transistor;
A release step of removing the interlayer insulating layer and the sacrificial layer on the functional structure through the opening;
And a second coating layer forming step of forming a second coating layer that closes the opening.

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