JP2010129950A - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
JP2010129950A
JP2010129950A JP2008306132A JP2008306132A JP2010129950A JP 2010129950 A JP2010129950 A JP 2010129950A JP 2008306132 A JP2008306132 A JP 2008306132A JP 2008306132 A JP2008306132 A JP 2008306132A JP 2010129950 A JP2010129950 A JP 2010129950A
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Prior art keywords
insulating film
interlayer insulating
wiring
film
semiconductor device
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JP2008306132A
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Japanese (ja)
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Akihisa Iwasaki
晃久 岩崎
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Panasonic Corp
パナソニック株式会社
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate
    • H01L21/02109Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02203Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being porous
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/3105After-treatment
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76822Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc.
    • H01L21/76825Modification of the material of dielectric layers, e.g. grading, after-treatment to improve the stability of the layers, to increase their density etc. by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc.
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers
    • H01L21/314Inorganic layers
    • H01L21/316Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31695Deposition of porous oxides or porous glassy oxides or oxide based porous glass
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2221/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/10Applying interconnections to be used for carrying current between separate components within a device
    • H01L2221/1005Formation and after-treatment of dielectrics
    • H01L2221/1042Formation and after-treatment of dielectrics the dielectric comprising air gaps
    • H01L2221/1047Formation and after-treatment of dielectrics the dielectric comprising air gaps the air gaps being formed by pores in the dielectric

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device which includes an interlayer insulating film with wiring lines formed thereon and prevents delamination at an interface therebetween between an interlayer insulating film and a lower layer formed under the interlayer insulating film. <P>SOLUTION: The semiconductor device includes a first interlayer insulating film 10 formed on a semiconductor substrate, a second interlayer insulating film 14 formed on the first interlayer insulating film 10, and a first wiring line 21 formed in an upper region of the second interlayer insulating film 14. The second interlayer insulating film 14 includes a porous region 14B containing air pores 14b and a non-porous region 14A. The porous region 14B is formed around the first wiring line 21 in the second interlayer insulating film 14, and the non-porous region 14A is formed at least between the first interlayer insulating film 10 and the porous region 14B. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an interlayer insulating film on which wiring is formed and a method for manufacturing the same.

  In recent years, in a semiconductor device having a wiring containing copper, a reduction in dielectric constant of an interlayer insulating film is required in order to reduce the capacitance between wirings and increase the speed of the semiconductor device. Therefore, it has been studied to use a porous low dielectric constant film as an interlayer insulating film.

  A semiconductor device using a porous low dielectric constant film as an interlayer insulating film will be described with reference to FIG. 7 (see, for example, Patent Document 1). FIG. 7 is a cross-sectional view showing a configuration of a conventional semiconductor device.

  As shown in FIG. 7, a conventional semiconductor device includes an insulating film 100 formed on a semiconductor substrate (not shown), and an insulating film formed on the insulating film 100 and made porous by detachment of the porogen 101a. 101, a coating insulating film 102 formed on the insulating film 101 and made of a non-porous insulating film, a via 103 formed in the insulating film 101, and formed in the coating insulating film 102 and connected to the via 103 Wiring 104 is provided. The insulating film 101 has a non-porous region 101A where the porogen 101a remains.

  The insulating film 101 has a dense region where the vias 103 are densely arranged and a sparse region where the vias 103 are arranged more sparsely than the dense region, and the non-porous region 101A is between the vias 103 in the sparse region. It is provided in the center.

Conventionally, since the insulating film 101 has the non-porous region 101A in the center between the vias 103 in the sparse region, the insulating film 101, the insulating film 100, and the like are compared with the insulating film in which the entire region is made porous. The contact area becomes larger. Accordingly, a decrease in adhesion between the insulating film 101 and the insulating film 100 can be suppressed, and occurrence of separation at the interface between the insulating film 101 and the insulating film 100 can be suppressed.
JP 2008-60498 A

  However, the conventional semiconductor device has the following problems.

  Conventionally, as shown in FIG. 7, the non-porous region 101A is provided only at the center between the vias 103 in the sparse region of the insulating film 101, and in the region other than the non-porous region 101A in the insulating film 101. The hole 101b exists. Therefore, a void 101b exists at the interface with the insulating film 100 in a region other than the non-porous region 101A in the insulating film 101, and the insulating film 101 (particularly, the insulating film 101 other than the non-porous region 101A). There is a possibility that peeling occurs at the interface between the region) and the insulating film 100.

  That is, conventionally, as described above, the non-porous region 101A suppresses the occurrence of peeling at the interface between the insulating film 101 and the lower layer (that is, the insulating film 100) formed under the insulating film 101. Although it is possible, there still remains a problem that peeling occurs at the interface between the insulating film 101 and the insulating film 100.

  In view of the foregoing, an object of the present invention is to prevent peeling at the interface between an interlayer insulating film and a lower layer formed under the interlayer insulating film in a semiconductor device having an interlayer insulating film in which wiring is formed. It is to be.

  In order to achieve the above object, a semiconductor device according to the present invention includes a first interlayer insulating film formed on a semiconductor substrate, and a second interlayer insulating film formed on the first interlayer insulating film. And a first wiring formed in an upper region of the second interlayer insulating film. The second interlayer insulating film is composed of a porous region containing pores and a non-porous region, and is porous. The porous region is formed in a region of the second interlayer insulating film located around the first wiring, and the non-porous region is interposed between at least the first interlayer insulating film and the porous region. It is characterized by being formed.

  According to the semiconductor device of the present invention, a porous region is provided in a region located around the first wiring in the second interlayer insulating film, and a non-porous region is provided in a region other than the porous region. Thus, a non-porous region can be provided between the first interlayer insulating film and the porous region (in other words, the region located at the interface with the lower layer in the second interlayer insulating film). Therefore, there is no hole at the interface between the second interlayer insulating film and the lower layer, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Peeling can be prevented from occurring at the interface between the insulating film and the lower layer. Here, the “lower layer” means a layer formed in contact with the second interlayer insulating film under the second interlayer insulating film.

  At the same time, by providing a porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.

  In addition, a non-porous region can be provided in the center portion between the first wirings having a relatively large wiring interval in the second interlayer insulating film. Thereby, it is possible to prevent the occurrence of peeling at the interface between the second interlayer insulating film and the upper layer. Here, the “upper layer” means a layer formed on the second interlayer insulating film in contact with the second interlayer insulating film.

  In the semiconductor device according to the present invention, the pores contained in the porous region are pores formed by desorption of porogen, and the non-porous region contains porogen that remains without being desorbed. Is preferred.

  In the semiconductor device according to the present invention, the porous region is formed within a range from the side surface of the first wiring to the first distance and within a range from the bottom surface of the first wiring to the second distance. Preferably it is.

  In the semiconductor device according to the present invention, the first distance is not less than a distance corresponding to the minimum wiring interval and not more than a distance corresponding to 1.5 times the minimum wiring interval, and the second distance is the first distance. It is preferable that the distance corresponds to about 0.5 times the bottom interface distance between the bottom surface of the wiring and the interface between the first interlayer insulating film and the second interlayer insulating film.

  In the semiconductor device according to the present invention, the non-porous region is adjacent to the interface region formed within the range from the interface between the second interlayer insulating film and the first interlayer insulating film to the third distance. An inter-wiring region formed in the center between the wirings having a spacing larger than the spacing corresponding to twice the first distance among the matching first wirings, and the third distance is: It is preferable that the distance corresponds to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film.

  This prevents the occurrence of delamination at the interface between the second interlayer insulating film and the lower layer due to the interface region of the non-porous region, as described above, and the inter-wiring region of the non-porous region. As described above, it is possible to prevent peeling from occurring at the interface between the second interlayer insulating film and the upper layer.

  The semiconductor device according to the present invention further includes a via formed in a lower region of the second interlayer insulating film, the via penetrating the non-porous region and the upper region penetrating the porous region. It is preferable that it is formed.

  In this case, since the lower region of the via is surrounded by the non-porous region, there is no hole in the bottom region of the via, for example, moisture trapped in the hole or remaining in the hole It is possible to prevent the reliability of the via from being deteriorated due to the etching of the etching gas or the like to oxidize the bottom area of the via or to corrode the bottom area of the via.

  Preferably, the semiconductor device according to the present invention further includes a second wiring formed in the first interlayer insulating film, and the first wiring is connected to the second wiring through a via.

  In this case, a non-porous region having a film thickness substantially the same as the film thickness of the porous region is provided in a region located between the second wiring and the first wiring in the second interlayer insulating film. be able to. Therefore, the mechanical strength of the region located between the second wiring and the first wiring in the second interlayer insulating film is ensured (specifically, for example, the second interlayer insulating film includes the second interlayer insulating film. The region located between the first wiring and the first wiring can secure a Young's modulus of 8 GPa or more), so that it is located between the second wiring and the first wiring in the second interlayer insulating film. It is possible to prevent cracks from occurring in the region.

  In the semiconductor device according to the present invention, the Young's modulus of the region located between the second wiring and the first wiring in the second interlayer insulating film is preferably 8 GPa or more.

  In the semiconductor device according to the present invention, the semiconductor device further includes a barrier film formed between the first interlayer insulating film and the second interlayer insulating film, and the via includes a lower region of the second interlayer insulating film, and a barrier film It is preferable to be formed so as to pass through.

  The semiconductor device according to the present invention further includes a cap film formed on the second interlayer insulating film, and the first wiring is formed in the upper region of the second interlayer insulating film and the cap film. Is preferred.

  In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step (a) of forming a first interlayer insulating film on a semiconductor substrate, and a porogen on the first interlayer insulating film. A step (b) of forming a second interlayer insulating film-forming film containing, and a step of forming a hard mask in which a wiring groove forming groove is formed on the second interlayer insulating film-forming film (c) ) And the porogen formed by detaching the porogen present in the region located in the vicinity of the wiring groove forming groove in the second interlayer insulating film forming film using the hard mask. A step (d) of forming a second interlayer insulating film composed of a porous region containing a non-porous region containing porogen remaining without being desorbed, and using a hard mask, Forming a first wiring groove in an upper region of the second interlayer insulating film (e And a step (f) of forming the first wiring in the first wiring groove after removing the hard mask, and in the step (e), the first wiring groove is formed in the porous region. It is characterized by being.

  According to the method for manufacturing a semiconductor device of the present invention, the first wiring is formed in the first wiring groove formed in the porous region, so that the first interlayer insulating film of the first interlayer insulating film is formed. A porous region can be provided in a region located around the wiring, and a non-porous region can be provided in a region other than the porous region. Thereby, a non-porous region can be provided between the first interlayer insulating film and the porous region (in other words, a region located at the interface with the lower layer in the second interlayer insulating film). Therefore, there is no hole at the interface with the lower layer in the second interlayer insulating film, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Therefore, for example, it is possible to prevent peeling at the interface between the second interlayer insulating film and the lower layer during the CMP process or the like in the first wiring formation process.

  At the same time, by providing a porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.

  In addition, a non-porous region can be provided in the center portion between the first wirings having a relatively large wiring interval in the second interlayer insulating film. Thereby, for example, it is possible to prevent the separation at the interface between the second interlayer insulating film and the upper layer during the CMP process or the like in the first wiring formation process.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or an electron beam. In c), the hard mask is made of a metal film that reflects ultraviolet light or an electron beam, and the step (d) is preferably a process of irradiating the semiconductor substrate with ultraviolet light or an electron beam.

  If it does in this way, ultraviolet rays or an electron beam with which an ultraviolet ray or an electron beam is irradiated to a hard mask will be reflected by a hard mask, and among the 2nd interlayer insulation film formation films, it will be a wiring groove formation groove. A region located in the vicinity is irradiated with ultraviolet rays or an electron beam.

  In the method of manufacturing a semiconductor device according to the present invention, the step (d) is a step of irradiating the semiconductor substrate with the first ultraviolet ray or the first electron beam in a direction perpendicular to the main surface of the semiconductor substrate. It is preferable to include (d1) and a step (d2) of irradiating the second ultraviolet ray or the second electron beam on the semiconductor substrate in a direction inclined with respect to the main surface of the semiconductor substrate.

  In the method of manufacturing a semiconductor device according to the present invention, the material of the metal film that reflects ultraviolet rays or electron beams is one type selected from the group consisting of Ti, TiN, Ta, TaN, W, and WN, or a plurality of types. It is preferable that the metal material.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or an electron beam. In c), the hard mask is made of an insulating film that absorbs ultraviolet rays or electron beams, and the step (d) is preferably a step of irradiating the semiconductor substrate with ultraviolet rays or electron beams.

  If it does in this way, ultraviolet rays or an electron beam irradiated to a hard mask among ultraviolet rays or an electron beam will be absorbed by a hard mask, and it will become a groove | channel of wiring groove | channel formation groove | channel among 2nd interlayer insulation film formation films. A region located in the vicinity is irradiated with ultraviolet rays or an electron beam.

In the method of manufacturing a semiconductor device according to the present invention, the material of the insulating film that absorbs ultraviolet rays or electron beams is one or more selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , and SiN. A type of insulating material is preferred.

  In the method for manufacturing a semiconductor device according to the present invention, in step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by heat treatment, and in step (c), a hard mask is used. Is made of a film having a higher density than the first interlayer insulating film containing no porogen, and the step (d) is preferably a step of performing a heat treatment on the entire surface of the semiconductor substrate.

In the method for manufacturing a semiconductor device according to the present invention, the hard mask material is made of a metal material group composed of Ti, TiN, Ta, TaN, W, and WN, and SiCN, SiCO, SiCH, SiON, SiO 2 , and SiN. It is preferable that the material is one type or a plurality of types of materials selected from the insulating material group.

  In the method for manufacturing a semiconductor device according to the present invention, the step (e) further includes a step of forming a via hole in a lower region of the second interlayer insulating film, and the step (f) includes a step of forming a via in the via hole. In the step (e), the via hole is preferably formed such that the lower region penetrates the non-porous region and the upper region penetrates the porous region.

  In this case, since the lower region of the via is surrounded by the non-porous region, there is no hole in the bottom region of the via, for example, moisture trapped in the hole or remaining in the hole It is possible to prevent the reliability of the via from being deteriorated due to the etching of the etching gas or the like to oxidize the bottom area of the via or to corrode the bottom area of the via.

  In the method for manufacturing a semiconductor device according to the present invention, after the step (a) and before the step (b), the second wiring trench is formed in the first interlayer insulating film, and then in the second wiring trench. It is preferable to further include a step (g) of forming the second wiring.

  In this case, a non-porous region having a film thickness substantially the same as the film thickness of the porous region is provided in a region located between the second wiring and the first wiring in the second interlayer insulating film. be able to. Therefore, the mechanical strength of the region located between the second wiring and the first wiring in the second interlayer insulating film can be ensured. For example, the wire to be formed after the first wiring forming step In the bonding process, the probe inspection process, or the like, it is possible to prevent a crack from occurring in a region located between the second wiring and the first wiring in the second interlayer insulating film.

  In the method for manufacturing a semiconductor device according to the present invention, a step (h) of forming a barrier film on the first interlayer insulating film and the second wiring after the step (g) and before the step (b). In the step (b), the second interlayer insulating film forming film is formed on the barrier film. In the step (e), the via hole is formed in the lower region of the second interlayer insulating film, and the barrier film. It is preferable to be formed to penetrate through.

  The method for manufacturing a semiconductor device according to the present invention further includes a step (i) of forming a cap film on the second interlayer insulating film forming film after the step (b) and before the step (c). In step (c), a cap film in which a groove is formed and a hard mask in which a groove for forming a wiring groove that communicates with the groove is sequentially formed on the second interlayer insulating film forming film. In e), the first wiring trench is preferably formed in the upper region of the second interlayer insulating film and the cap film.

  In the method for manufacturing a semiconductor device according to the present invention, in the step (c), a hard mask is formed on the cap film, and after the step (c1), a wiring groove forming groove is formed in the hard mask. And a step (c2) of forming a groove in the cap film.

  According to the semiconductor device and the manufacturing method thereof according to the present invention, a porous region is provided in a region located around the first wiring in the second interlayer insulating film, and a non-porous region is provided in a region other than the porous region. By providing a region, a non-porous region is provided between the first interlayer insulating film and the porous region (in other words, the region located at the interface with the lower layer in the second interlayer insulating film). Can do. Therefore, there is no hole at the interface between the second interlayer insulating film and the lower layer, and the adhesion between the second interlayer insulating film and the lower layer is not reduced by the hole. Peeling can be prevented from occurring at the interface between the insulating film and the lower layer.

  At the same time, by providing a porous region in a region located around the first wiring in the second interlayer insulating film, it is effective in reducing the capacitance between the wirings in the second interlayer insulating film. Since the porous region can be provided in the contributing region, the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.

  In addition, a non-porous region can be provided in the center portion between the first wirings having a relatively large wiring interval in the second interlayer insulating film. Thereby, it is possible to prevent the occurrence of peeling at the interface between the second interlayer insulating film and the upper layer.

  Embodiments of the present invention will be described below with reference to the drawings.

(One embodiment)
Hereinafter, a semiconductor device and a manufacturing method thereof according to an embodiment of the present invention will be described with reference to FIGS. 1 (a) and (b), FIG. 2, FIGS. 3 (a) to (c), and FIGS. ) And FIGS. 5 (a) to 5 (c).

  The configuration of the semiconductor device according to one embodiment of the present invention will be described below with reference to FIGS. 1 (a) and 1 (b). 1A and 1B are diagrams showing a configuration of a semiconductor device according to an embodiment of the present invention. Specifically, FIG. 1A is a plan view, and FIG. FIG. 2 is a cross-sectional view taken along line Ib-Ib shown in FIG.

  As shown in FIG. 1 (a), on a semiconductor substrate (not shown), a first interlayer insulating film (see FIG. 1 (b): 10), a barrier film (see FIG. 1 (b): 13), A second interlayer insulating film (see FIG. 1B: 14) and a cap film 15 are sequentially formed. A via 20 is formed in the lower region of the second interlayer insulating film, and a wiring 21 connected to the via 20 is formed in the upper region of the second interlayer insulating film and the cap film 15.

  As shown in FIG. 1B, the semiconductor device according to the present embodiment is formed on a first interlayer insulating film 10 formed on a semiconductor substrate (not shown) and the first interlayer insulating film 10. A lower layer wiring (second wiring) 12, a barrier film 13 formed on the first interlayer insulating film 10 and the lower layer wiring 12, a second interlayer insulating film 14 formed on the barrier film 13, A cap film 15 formed on the second interlayer insulating film 14, a barrier film 13, a via 20 connected to the lower layer wiring 12 formed in a lower region of the second interlayer insulating film 14, and a second interlayer insulating film An upper layer wiring (first wiring) 21 formed in the upper region of the film 14 and the cap film 15 and connected to the via 20 is provided.

  Here, the lower layer wiring 12 includes a barrier metal film 12a formed on the bottom and side surfaces of the lower layer wiring groove 11, and a conductive film 12b embedded in the lower layer wiring groove 11 via the barrier metal film 12a. The via 20 includes a barrier metal film 20a formed on the bottom and side surfaces of the via hole 18 and a conductive film 20b embedded in the via hole 18 via the barrier metal film 20a. The upper layer wiring 21 includes a barrier metal film 21a formed on the bottom and side surfaces of the upper layer wiring groove 19 and a conductive film 21b embedded in the upper layer wiring groove 19 via the barrier metal film 21a.

  As shown in FIG. 1 (b), the second interlayer insulating film 14 contains a porous region 14B containing pores 14b from which porogens 14a are detached, and porogen 14a remaining without being detached. The non-porous region 14A is configured.

  As shown in FIG. 1B, the porous region 14B is formed in a region located around the upper layer wiring 21 in the second interlayer insulating film 14. As shown in FIG. Specifically, as shown in FIG. 2, the porous region 14 </ b> B is within the range from the side surface of the upper layer wiring 21 to the first distance Ds (see FIG. 2) and from the bottom surface of the upper layer wiring 21 to the second distance. It is formed within the range up to Db (see FIG. 2). Here, the first distance Ds is a distance along a direction perpendicular to the side surface of the upper layer wiring 21, and the second distance Db is a distance along a direction perpendicular to the bottom surface of the upper layer wiring 21. It is. FIG. 2 is the same as the diagram shown in FIG.

  Here, the first distance Ds is not less than a distance corresponding to the minimum wiring interval Smin and not more than a distance corresponding to 1.5 times the minimum wiring interval Smin (Smin ≦ Ds ≦ Smin × 1.5). Is preferred. The second distance Db is a distance corresponding to 0.5 times the bottom surface interface distance Dbi (see FIG. 2) between the bottom surface of the upper wiring 21 and the interface between the second interlayer insulating film 14 and the barrier film 13. It is preferable (Db = Dbi × 0.5). Here, the “minimum wiring interval Smin” corresponds to the smallest interval among the wiring intervals of the upper layer wirings 21 adjacent to each other.

  In other words, the non-porous region 14A is not overlapped between the barrier film 13 and the porous region 14B and between the porous regions 14B adjacent to each other (particularly, the porous regions 14B adjacent to each other do not overlap each other). Between the spaced apart porous regions 14B). Specifically, as shown in FIG. 2, the non-porous region 14A is formed within a range from the interface between the second interlayer insulating film 14 and the barrier film 13 to the third distance Di (see FIG. 2). The inter-wiring region 14As formed in the central portion between the interfacial region 14Ai and the wiring of the upper-layer wiring 21 adjacent to each other having a spacing larger than the spacing corresponding to twice the first distance Ds. Including. Here, the third distance Di is preferably a distance corresponding to 0.5 times the bottom interface distance Dbi (Di = Dbi × 0.5). In other words, the third distance Di is preferably substantially the same as the second distance Db.

  The inter-wiring region 14As of the non-porous region 14A is an inter-wiring region having an interval (> Ds × 2) larger than an interval corresponding to twice the first distance Ds among the wirings of the upper layer wirings 21 adjacent to each other. Is formed between the wirings having an interval (≦ Ds × 2) that is equal to or less than an interval corresponding to twice the first distance Ds.

  In the second interlayer insulating film 14, the via 20 has a lower region penetrating the interface region 14Ai of the non-porous region 14A and an upper region of the via 20 as the bottom surface of the porous region 14B, as shown in FIG. It is formed through the region. In the second interlayer insulating film 14, the upper layer wiring 21 is formed in the porous region 14B. Here, the “bottom surface region” refers to a region formed in the range from the bottom surface of the upper layer wiring 21 to the second distance Db (see FIG. 2) in the porous region 14B.

  In the region between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14, the film thickness (see FIG. 2: Db) substantially the same as the film thickness of the bottom region of the porous region 14B (see FIG. 2). 2: Refer to Di) to form an interface region 14Ai of the non-porous region 14A. Here, it is preferable that the Young's modulus of the region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 is 8 GPa or more.

  In the following, referring to FIGS. 3 (a) to (c), FIGS. 4 (a) to (c), and FIGS. 5 (a) to (c) for a method of manufacturing a semiconductor device according to an embodiment of the present invention. While explaining. FIG. 3A to FIG. 5C are principal part process cross-sectional views illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention in the order of processes.

  First, as shown in FIG. 3 (a), a first interlayer insulation made of, for example, a carbon-containing silicon oxide film (SiOC (H) film) having a relative dielectric constant of 3.0 on a semiconductor substrate (not shown). A film 10 is formed. Subsequently, after a resist pattern (not shown) having a lower wiring groove pattern is formed on the first interlayer insulating film 10 by photolithography, the first interlayer insulating film is used using the resist pattern as a mask. 10 is dry-etched to form a lower wiring trench 11 in the first interlayer insulating film 10. Subsequently, the resist pattern is removed.

  Next, a barrier in which, for example, a tantalum film (Ta film) and a tantalum nitride film (TaN film) are sequentially stacked on the first interlayer insulating film 10 and on the bottom and side surfaces of the lower wiring trench 11 by sputtering. Deposit metal film. Subsequently, after a seed film containing, for example, copper is formed on the barrier metal film by sputtering, a plating film containing, for example, copper is buried by embedding the lower wiring groove 11 on the seed film by electrolytic plating. To deposit. Subsequently, portions of the plating film, the seed film, and the barrier metal film formed outside the lower wiring trench 11 are sequentially removed by a CMP (Chemical Mechanical Polishing) method. In this way, the lower layer wiring 12 is formed in which the conductive film 12b containing copper is buried in the lower layer wiring trench 11 via the barrier metal film 12a. In FIG. 3A, the boundary line between the seed film and the plating film in the conductive film 12b is not shown because it is difficult to show.

Next, as shown in FIG. 3B, a silicon carbonitride film (for example, having a film thickness of 40 nm) is formed on the first interlayer insulating film 10 and the lower layer wiring 12 by plasma CVD (Chemical Vapor Deposition). A barrier film 13 made of SiCN film is deposited. Here, as the deposition conditions of the barrier film 13 by the plasma CVD method, the following conditions may be mentioned. For example, under the temperature of 400 ° C., as a material gas, tetramethylsilane (Si (CH 3) 4) gas, and using ammonia (NH 3) gas, as a diluent gas, using helium (He) gas, plasma The barrier film 13 is deposited by the CVD method. Here, the barrier film 13 preferably has a density of, for example, 1.8 g / cm 3 , and preferably has a refractive index of, for example, 1.8 to 2.2 (wavelength 633 nm).

  Subsequently, from the SiOC (H) film having a film thickness of 200 nm containing the porogen 14a desorbed by, for example, ultraviolet (UV) irradiation on the barrier film 13 by the plasma CVD method or the spin coating method. A second interlayer insulating film forming film 14X is deposited. Here, as a deposition method of the second interlayer insulating film forming film 14X, it is more preferable to use a plasma CVD method.

  Next, as shown in FIG. 3C, a cap film 15 made of, for example, a SiOC (H) film having a thickness of 40 nm is deposited on the second interlayer insulating film forming film 14X by plasma CVD. Thereafter, a hard mask 16 made of a metal film that reflects ultraviolet rays, such as a TiN film having a film thickness of 30 nm, is deposited on the cap film 15 by sputtering.

  Next, as shown in FIG. 4A, a resist pattern (not shown) having an upper wiring groove pattern is formed on the hard mask 16 by photolithography. Subsequently, using the resist pattern as a mask, dry etching is sequentially performed on the hard mask 16 and the cap film 15 to form the upper wiring groove forming groove 16y in the hard mask 16 and the groove 15y in the cap film 15. Then, a groove 16Y that penetrates the hard mask 16 and the cap film 15 and exposes the upper surface of the second interlayer insulating film forming film 14X is formed. Subsequently, the resist pattern is removed. In this manner, the cap film 15 in which the groove 15y is formed and the hard mask 16 in which the upper-layer wiring groove forming groove 16y communicating with the groove 15y is sequentially formed on the second interlayer insulating film forming film 14X. Form.

  Next, as shown in FIG. 4B, for example, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays at an irradiation angle (that is, an angle inclined with respect to the normal of the main surface of the semiconductor substrate) of 0 °. That is, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction perpendicular to the main surface of the semiconductor substrate (see UV1). At this time, the ultraviolet ray irradiated to the hard mask 16 out of the ultraviolet rays is reflected by the hard mask 16, and the ultraviolet ray is irradiated to a region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X. Is done. Here, it is preferable to irradiate the ultraviolet rays with a low energy of 150 nm to 380 nm, for example, for a short time of 10 seconds to 20 seconds. Further, here, “the region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X” appearing in this specification refers to the second interlayer insulating film forming film 14X. 1) A region located directly below the groove 16Y and 2) a region located below the outer periphery of the groove 16Y.

  Subsequently, for example, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays at an irradiation angle of 45 °, that is, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction inclined with respect to the main surface of the semiconductor substrate (UV2). reference). At this time, the ultraviolet ray irradiated to the hard mask 16 out of the ultraviolet rays is reflected by the hard mask 16, and the ultraviolet ray is irradiated to a region located in the vicinity of the groove 16Y in the second interlayer insulating film forming film 14X. Is done. Here, it is preferable to irradiate the ultraviolet rays with a low energy of 150 nm to 380 nm, for example, for a short time of 10 seconds to 20 seconds.

  As a result, as shown in FIG. 4 (c), the hard mask 16 is used to irradiate the region located in the vicinity of the groove 16Y (that is, ultraviolet rays) in the second interlayer insulating film forming film 14X. The porogen 14a existing in the region) is desorbed, and is composed of a porous region 14B containing the holes 14b formed by desorbing the porogen 14a and a non-porous region 14A containing the porogen 14a remaining without being desorbed. A second interlayer insulating film 14 is formed.

  Here, the porous region 14B is formed so as to expand outward with respect to the center point C of the bottom surface of the groove 16Y, and within a range from the center point C to a distance Dh (see FIG. 4C), and It is formed within the range from the center point C to the distance Dv (see FIG. 4C). Here, the distance Dh is a distance along a direction parallel to the bottom surface of the groove 16Y, and the distance Dv is a distance along a direction perpendicular to the bottom surface of the groove 16Y. As can be seen from the above, the distance Dh corresponds to the sum of the distance corresponding to 0.5 times the wiring width L of the upper wiring 21 and the first distance Ds (Dh = L × 0.5 + Ds). The distance Dv corresponds to the sum of the distance corresponding to the wiring height H of the upper layer wiring 21 and the second distance Db (Dv = H + Db).

  Next, as shown in FIG. 5A, after a resist pattern (not shown) having a via hole pattern is formed on the hard mask 16 by photolithography, the trench 16Y is formed using the resist pattern as a mask. The second interlayer insulating film 14 exposed inside is dry-etched to form a hole 17 that penetrates the second interlayer insulating film 14 and exposes the upper surface of the barrier film 13. Subsequently, the resist pattern is removed.

  Next, as shown in FIG. 5B, the barrier film 13 exposed in the holes 17 is removed by an etch back method, and the lower layer wiring 12 is formed in the lower regions of the barrier film 13 and the second interlayer insulating film 14. A via hole 18 is formed to expose the upper surface of. At the same time, the upper region of the second interlayer insulating film 14 exposed in the trench 16Y is removed using the hard mask 16, and the upper layer wiring trench is formed in the upper region of the second interlayer insulating film 14 and the cap film 15. 19 is formed. At this time, as shown in FIG. 5 (b), the lower region of the via hole 18 passes through the interface region of the non-porous region 14A (see FIG. 1 (b): 14Ai), and the upper region thereof is the porous region. It is formed through the bottom area of 14B. At the same time, the upper wiring trench 19 is formed in the porous region 14B as shown in FIG. 5 (b).

  Next, as shown in FIG. 5 (c), Ta is formed on the hard mask 16, the side surface of the upper wiring groove forming groove 16y, the bottom surface and side surfaces of the upper wiring groove 19, and the bottom surface and side surfaces of the via hole 18 by sputtering. A barrier metal film in which a film and a TaN film are sequentially stacked is deposited. Subsequently, a seed film containing copper is formed on the barrier metal film by a sputtering method, and then plating containing copper so as to bury the via hole 18 and the upper wiring groove 19 on the seed film by an electrolytic plating method. Deposit a film.

  Next, portions of the plating film, seed film, barrier metal film, and hard mask 16 formed outside the via hole 18 and the upper wiring groove 19 are sequentially removed by CMP. After the hard mask 16 is removed in this way, vias 20 are formed in the via holes 18 by burying the conductive films 20b containing copper via the barrier metal films 20a. Then, an upper layer wiring 21 is formed in which a conductive film 21b containing copper is embedded through a barrier metal film 21a. At this time, as shown in FIG. 5 (c), the lower region of the via 20 passes through the interface region of the non-porous region 14A (see FIG. 1 (b): 14Ai), and the upper region thereof is the porous region. It is formed through the bottom area of 14B. At the same time, the upper layer wiring 21 is formed in the porous region 14B as shown in FIG. 5 (c) (in other words, the porous region 14B is the upper layer wiring 21 of the second interlayer insulating film 14). In the area located around the Here, in FIG. 5C, the boundary line between the seed film and the plating film in the conductive films 20b and 21b is not illustrated because it is difficult to illustrate.

  As described above, the semiconductor device according to this embodiment can be manufactured.

  Here, in this embodiment, after forming a resist pattern (not shown) having an upper wiring groove pattern in the step shown in FIG. 4A, a resist having a via hole pattern is formed in the step shown in FIG. A pattern (not shown) is formed. Subsequently, in the step shown in FIG. 5C, the via 20 is formed in the via hole 18 and the upper wiring 21 is formed in the upper wiring groove 19. That is, in this embodiment, the via 20 and the upper layer wiring 21 are formed by a trench first method in which a resist pattern having an upper layer wiring groove pattern is formed first and a via last dual damascene method in which a resist pattern having a via hole pattern is formed later. Is adopted.

  According to the present embodiment, as shown in FIG. 1B, a porous region 14B is provided in a region located around the upper layer wiring 21 in the second interlayer insulating film 14, and other than the porous region 14B. By providing the non-porous region 14A in the region, the interface region 14Ai of the non-porous region 14A can be provided in the region located in the interface with the barrier film 13 in the second interlayer insulating film 14. Therefore, there is no hole 14b at the interface between the second interlayer insulating film 14 and the barrier film 13, and the adhesion between the second interlayer insulating film 14 and the barrier film 13 is reduced by the hole 14b. There is no. Therefore, for example, a CMP step in the step shown in FIG. 5C, a step of connecting a wire bond to a pad (not shown) formed on the upper layer wiring 21 (hereinafter referred to as “wire bonding step”), or a pad Prevents the occurrence of delamination at the interface between the second interlayer insulating film 14 and the barrier film 13 during an inspection process (hereinafter referred to as “probe inspection process”) in which an internal circuit is inspected by applying a probe needle to can do.

  At the same time, as shown in FIG. 1B, by providing a porous region 14B in a region located around the upper wiring 21 in the second interlayer insulating film 14, the second interlayer insulating film 14 is provided. Among these, the porous region 14B can be provided in a region that effectively contributes to the reduction of the inter-wiring capacitance, so that the inter-wiring capacitance can be effectively reduced and the speed of the semiconductor device can be increased.

  In addition, as shown in FIG. 1B, the second interlayer insulating film 14 has a relatively large wiring interval (specifically, a wiring interval larger than an interval corresponding to twice the first distance Ds). The inter-wiring region 14As of the non-porous region 14A can be provided in the central portion between the upper-layer wirings 21 having (). Here, the area between the upper layer wirings 21 having a relatively large wiring interval has a relatively large contact area with the cap film 15, and the possibility that separation occurs at the interface with the cap film 15 is relatively high. Therefore, by providing the inter-wiring region 14As of the non-porous region 14A in the center between the upper layer wirings 21 having a relatively large wiring interval, for example, in the CMP process, the second interlayer insulating film 14 and It is possible to prevent the peeling from occurring at the interface with the cap film 15. On the other hand, the area between the upper layer wirings 21 having a relatively small wiring interval has a smaller contact area with the cap film 15 than the region between the upper layer wirings 21 having a relatively large wiring interval, and the interface with the cap film 15. Is less likely to peel. Therefore, it is not necessary to provide a non-porous region in a region between the upper layer wirings 21 having a relatively small wiring interval.

  In addition, as shown in FIG. 1B, by providing an interface region 14Ai of the non-porous region 14A in a region located at the interface with the barrier film 13 in the second interlayer insulating film 14, vias Since the lower region of 20 is surrounded by the interface region 14Ai of the non-porous region 14A, there is no hole 14b in the bottom region of the via 20, for example, moisture trapped in the hole 14b, or It can be prevented that the bottom surface region of the via 20 is oxidized or the bottom surface region of the via 20 is corroded by the etching gas or the like remaining in 14b and the reliability of the via 20 is lowered.

  In addition, as shown in FIG. 1B, the thickness of the bottom region of the porous region 14B (see FIG. 2) in the region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14. : Db) can be provided with the interface region 14Ai of the non-porous region 14A having substantially the same film thickness (see FIG. 2: Di). Therefore, the mechanical strength of a region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14 is ensured (specifically, for example, the lower layer wiring in the second interlayer insulating film 14). 12 and the upper layer wiring 21 can secure a Young's modulus of 8 GPa or more). Therefore, for example, in the wire bonding process or the probe inspection process, it is possible to prevent the second interlayer insulating film 14 from being cracked in a region located between the lower layer wiring 12 and the upper layer wiring 21. Can do.

As described above, by providing the porous region 14B in the region located around the upper wiring 21 in the second interlayer insulating film 14, and providing the nonporous region 14A in the region other than the porous region 14B. In addition, the inter-wiring capacitance can be effectively reduced and the occurrence of peeling at the interface between the second interlayer insulating film 14 and the barrier film 13 can be prevented. In addition, while effectively reducing the capacitance between wires,
1) Prevent peeling from occurring at the interface between the second interlayer insulating film 14 and the cap film 15;
2) Prevent the reliability of the via 20 from being lowered,
3) It is possible to prevent a crack from occurring in a region located between the lower layer wiring 12 and the upper layer wiring 21 in the second interlayer insulating film 14.

  In the present embodiment, in order to easily explain the present invention, as shown in FIG. 1 (b), the porous region 14B contains only the pores 14b, does not contain the porogen 14a, Although the non-porous region 14A contains only the porogen 14a and does not contain the pores 14b, a specific example has been described, but the present invention is not limited to this. For example, the porous region 14B contains not only the holes 14b but also a smaller number of porogens 14a than the number of the holes 14b, while the non-porous region 14A includes not only the porogens 14a but also the number of porogens 14a. A smaller number of holes 14b may be contained. In particular, pores 14b and porogens 14a may be mixed in the boundary region between the porous region 14B and the non-porous region 14A.

  That is, the “porous region” in the present specification is a region mainly containing pores, while the “non-porous region” in the present specification is a region not mainly containing pores. The “porous region” is a region having a higher pore density than the “non-porous region”, while the “non-porous region” is lower than the “porous region”. This is a region having a void density.

  In the present embodiment, the case where TiN is used as the metal material of the hard mask 16 that reflects ultraviolet rays has been described as a specific example, but the present invention is not limited to this. As the metal material of the hard mask that reflects ultraviolet rays, for example, one or more kinds of metal materials selected from the group consisting of Ti, Ta, TaN, W, WN, and the like may be used.

  In the present embodiment, as shown in FIG. 4B, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays in a direction perpendicular to the main surface of the semiconductor substrate (see UV1), and then on the semiconductor substrate. Although the case where ultraviolet rays are irradiated on the entire surface in a direction inclined with respect to the main surface of the semiconductor substrate (see UV2) has been described as a specific example, the present invention is not limited to this. First, for example, the entire surface of the semiconductor substrate is irradiated with ultraviolet rays only in a direction perpendicular to the main surface of the semiconductor substrate. Second, for example, the entire surface of the semiconductor substrate is irradiated on the main surface of the semiconductor substrate. The ultraviolet rays may be irradiated only in the direction inclined with respect to the surface.

  Further, in the present embodiment, as a method of detaching the porogen 14a existing in the region located near the trench 16Y in the second interlayer insulating film forming film 14, the hard mask 16 is a metal that reflects ultraviolet rays. A case where a film is used and a porogen that is desorbed by irradiation of ultraviolet rays is adopted as the porogen 14a and the entire surface of the semiconductor substrate is irradiated with ultraviolet rays has been described as a specific example, but the present invention is not limited thereto. It is not something.

First, for example, an insulating film that absorbs ultraviolet rays may be employed as the hard mask, and porogen that is desorbed by ultraviolet irradiation may be employed as the porogen, and the entire surface of the semiconductor substrate may be irradiated with ultraviolet rays. As described above, the cap film having the groove and the hard mask having the upper wiring groove forming groove are sequentially formed on the second interlayer insulating film forming film and then irradiated with ultraviolet rays. Thus, the ultraviolet ray irradiated to the hard mask among the ultraviolet rays is absorbed by the hard mask, and in the second interlayer insulating film forming film, the region located in the vicinity of the groove and the upper wiring groove forming groove, Ultraviolet rays are irradiated. Here, as the insulating material of the hard mask that absorbs ultraviolet light, for example, SiCN, SiCO, SiCH, SiON, 1 kind selected from the group consisting of SiO 2, and SiN or the like, or a plurality of types of insulating material .

  Second, for example, a metal film that reflects an electron beam is used as a hard mask, and a porogen that is detached by irradiation with an electron beam is used as a porogen. Good.

  Third, for example, an insulating film that absorbs an electron beam is used as a hard mask, and a porogen that is desorbed by irradiation with an electron beam is used as a porogen. Good.

Fourth, for example, a film having a relatively high density may be employed as the hard mask, and a porogen that is desorbed by heat treatment may be employed as the porogen, and the entire surface of the semiconductor substrate may be heat treated. In this way, heat treatment is performed in a state in which the cap film in which the groove is formed and the hard mask in which the groove for forming the upper wiring groove is formed in order on the second interlayer insulating film forming film. In the second interlayer insulating film forming film, the porogen present in the region located in the vicinity of the groove and the upper wiring groove forming groove can be removed. Here, the heat treatment temperature is preferably a low temperature of 300 ° C., for example, and the heat treatment time is preferably a short time of about several tens of seconds to 3 minutes, for example. Here, the density of the hard mask is preferably about 2.21 g / cm 3 , for example. Here, as the material of the hard mask, for example, a metal material group made of Ti, TiN, Ta, TaN, W, WN, etc., and an insulation made of SiCN, SiCO, SiCH, SiON, SiO 2 , SiN, etc. One type or a plurality of types of materials selected from the material group can be mentioned. However, when the density of the cap film is relatively high, without providing a hard mask on the cap film, only the cap film in which the groove is formed is formed on the second interlayer insulating film forming film. Heat treatment may be performed.

In the present embodiment, the case where a SiCN film is used as the barrier film 13 has been described as a specific example, but the present invention is not limited to this. First, for example, a silicon carbonate film (SiCO film) may be used instead of the SiCN film. Second, for example, instead of the single-layer film of the SiCN film, a stacked film in which a SiCN film and a SiCO film are sequentially stacked may be used. Here, as a method for forming the SiCO film, tetramethylsilane (Si (CH 3 ) 4 ) gas and carbon dioxide (CO 2 ) gas are used as the source gas at a temperature of 400 ° C., and as the dilution gas, Examples include a method performed by plasma CVD using helium (He) gas.

<Specific example>
The configuration of the semiconductor device according to a specific example of one embodiment of the present invention will be described below with reference to FIGS. 6 (a) and 6 (b). FIGS. 6A and 6B are cross-sectional views showing the configuration of a semiconductor device according to a specific example of one embodiment of the present invention.

As shown in FIG. 6 (a), as a semiconductor device according to this example,
The wiring widths La, Lb, and Lc of the wirings 41a, 41b, and 41c are substantially the same, and the wiring widths La, Lb, and Lc are widths corresponding to the minimum wiring width Lmin (La, Lb, Lc = Lmin),
The wiring heights Ha, Hb, Hc of the wirings 41a, 41b, 41c are substantially the same, and the wiring heights Ha, Hb, Hc are equivalent to twice the minimum wiring width Lmin (Ha, Hb, Hc = Lmin × 2),
The wiring interval Sbc between the adjacent wirings 41b and 41c is the minimum wiring interval Smin (Sbc = Smin).
The interval of the wiring interval Sab between the adjacent wirings 41a and 41b is larger than the interval corresponding to three times the minimum wiring interval Smin (Sab> Smin × 3).
The width of the minimum wiring width Lmin is substantially the same as the minimum wiring interval Smin (Lmin = Smin)
The total film thickness T of the second interlayer insulating film 34 and the cap film 35 is equivalent to four times the minimum wiring interval Smin (T = Smin × 4).
The semiconductor device is shown.

  As shown in FIG. 6 (a), the porous region 34B has a first distance Ds (Ds = Smin × 1.5) corresponding to 1.5 times the minimum wiring interval Smin from the side surfaces of the upper layer wirings 41a to 41c. ) And the second distance Db (Db = Dbi × 0.5) corresponding to 0.5 times the bottom interface distance Dbi from the bottom surface of the upper wirings 41a to 41c. ing.

  As shown in FIG. 6A, the interface region of the non-porous region 34A is a third region corresponding to 0.5 times the bottom surface interface distance Dbi from the interface between the second interlayer insulating film 34 and the barrier film 33. Is formed within a range up to a distance Di (Di = Dbi × 0.5, that is, Di = Db).

  As shown in FIG. 6A, the inter-wiring region of the non-porous region 34A has a wiring interval Sab larger than the interval corresponding to twice the first distance Ds among the wirings of the upper layer wirings adjacent to each other. Formed in the center between the wirings having

In the semiconductor device according to this example, when the minimum wiring interval Smin is “1”, as shown in FIG.
・ Wiring widths La, Lb, and Lc are “1”.
・ Wiring heights Ha, Hb, Hc are “2”
-Wiring interval Sbc is "1"
・ Total film thickness T is "4"
The first distance Ds is “1.5”
・ The second distance Db is "1"
・ The third distance Di is "1"
-Bottom interface distance Dbi is "2"
・ The via height of via 40 is “2”
It becomes. FIG. 6 (b) is the same diagram as that shown in FIG. 6 (a).

According to this example, a porous region 34B is provided in a region located around the upper wirings 41a to 41c in the second interlayer insulating film 34, and a non-porous region 34A is provided in a region other than the porous region 34B. By providing, it is possible to effectively reduce the capacitance between the wirings and to prevent peeling at the interface between the second interlayer insulating film 34 and the barrier film 33. In addition, while effectively reducing the capacitance between wires,
1) Prevent peeling from occurring at the interface between the second interlayer insulating film 34 and the cap film 35.
2) Prevent the reliability of the via 40 from being lowered.
3) In the second interlayer insulating film 34, it is possible to prevent a crack from occurring in a region located between the lower layer wirings 32a to 32c and the upper layer wirings 41a to 41c.

  In this specific example, the case where the first distance Ds is a distance corresponding to 1.5 times the minimum wiring interval Smin (Ds = Smin × 1.5) has been described as a specific example. The invention is not limited to this, and the first distance may be not less than a distance corresponding to the minimum wiring interval Smin and not more than a distance corresponding to 1.5 times the minimum wiring interval Smin.

  Further, this specific example is merely an example, and the present invention is not limited to this specific example.

  Since the present invention can prevent peeling at the interface between the interlayer insulating film in which the wiring is formed and the lower layer formed in contact with the interlayer insulating film under the interlayer insulating film, the wiring is formed. The present invention is useful for a semiconductor device having an interlayer insulating film and a manufacturing method thereof.

(a) And (b) is a figure which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. It is sectional drawing which shows the structure of the semiconductor device which concerns on one Embodiment of this invention. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention to process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention to process order. (a)-(c) is principal part process sectional drawing which shows the manufacturing method of the semiconductor device which concerns on one Embodiment of this invention to process order. (a) And (b) is sectional drawing which shows the structure of the semiconductor device based on the specific example of one Embodiment of this invention. It is sectional drawing which shows the structure of the conventional semiconductor device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 1st interlayer insulation film 11 Lower layer wiring groove | channel 12 Lower layer wiring 12a Barrier metal film 12b Conductive film 13 Barrier film 14X 2nd interlayer insulation film formation film 14 2nd interlayer insulation film 14A Non-porous area | region 14As Between wiring area | region 14Ai interface region 14B porous region 14a porogen 14b hole 15 cap film 15y groove 16 hard mask 16y upper layer wiring groove forming groove 16Y groove 17 hole 18 via hole 19 upper layer wiring groove 20 via 20a barrier metal film 20b conductive film 21 upper layer wiring 21a Barrier metal film 21b Conductive film Ds First distance Db Second distance Di Third distance Dbi Bottom interface distance UV1, UV2 Ultraviolet light 32a, 32b, 32c Lower layer wiring 33 Barrier film 34 Second interlayer insulating film 34A Non-porous Region 34B Porous region 35 Cap membrane 40 V 41a, 41b, 41c upper wiring La, Lb, Lc wiring width Ha, Hb, Hc wiring height Sab, Sbc wiring interval T total thickness

Claims (23)

  1. A first interlayer insulating film formed on the semiconductor substrate;
    A second interlayer insulating film formed on the first interlayer insulating film;
    A first wiring formed in an upper region of the second interlayer insulating film,
    The second interlayer insulating film is composed of a porous region containing pores and a non-porous region,
    The porous region is formed in a region located around the first wiring in the second interlayer insulating film,
    The non-porous region is formed at least between the first interlayer insulating film and the porous region.
  2. The semiconductor device according to claim 1,
    The pores contained in the porous region are pores formed by removing porogen,
    The non-porous region contains a porogen that remains without being desorbed.
  3. The semiconductor device according to claim 1 or 2,
    The porous region is formed in a range from a side surface of the first wiring to a first distance and in a range from a bottom surface of the first wiring to a second distance. Semiconductor device.
  4. The semiconductor device according to claim 3.
    The first distance is not less than a distance corresponding to the minimum wiring interval and not more than a distance corresponding to 1.5 times the minimum wiring interval.
    The second distance is a distance corresponding to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film. A semiconductor device.
  5. The semiconductor device according to claim 3 or 4,
    The non-porous region is
    An interface region formed in a range from the interface between the second interlayer insulating film and the first interlayer insulating film to a third distance;
    An inter-wiring region formed at a central portion between wirings having a spacing larger than a spacing corresponding to twice the first distance among wirings of the first wirings adjacent to each other;
    The third distance is a distance corresponding to about 0.5 times the bottom interface distance between the bottom surface of the first wiring and the interface between the first interlayer insulating film and the second interlayer insulating film. A semiconductor device.
  6. The semiconductor device according to any one of claims 1 to 5,
    A via formed in a lower region of the second interlayer insulating film;
    The semiconductor device according to claim 1, wherein a lower region of the via penetrates the non-porous region and an upper region penetrates the porous region.
  7. The semiconductor device according to claim 6.
    A second wiring formed in the first interlayer insulating film;
    The semiconductor device, wherein the first wiring is connected to the second wiring through the via.
  8. The semiconductor device according to claim 7,
    A semiconductor device, wherein a Young's modulus of a region located between the second wiring and the first wiring in the second interlayer insulating film is 8 GPa or more.
  9. The semiconductor device according to any one of claims 6 to 8,
    A barrier film formed between the first interlayer insulating film and the second interlayer insulating film;
    The semiconductor device according to claim 1, wherein the via is formed so as to penetrate a lower region of the second interlayer insulating film and the barrier film.
  10. The semiconductor device according to claim 6, wherein:
    A cap film formed on the second interlayer insulating film;
    The semiconductor device according to claim 1, wherein the first wiring is formed in an upper region of the second interlayer insulating film and the cap film.
  11. A step (a) of forming a first interlayer insulating film on the semiconductor substrate;
    Forming a second interlayer insulating film forming film containing porogen on the first interlayer insulating film (b);
    A step (c) of forming a hard mask having a wiring groove forming groove formed on the second interlayer insulating film forming film;
    Using the hard mask, the porogen formed by detaching the porogen present in the region located in the vicinity of the wiring groove forming groove in the second interlayer insulating film forming film is removed. A step (d) of forming a second interlayer insulating film composed of a porous region containing a non-porous region containing a porogen remaining without being desorbed;
    Forming a first wiring trench in an upper region of the second interlayer insulating film using the hard mask; and
    A step (f) of forming a first wiring in the first wiring groove after removing the hard mask;
    In the step (e), the first wiring groove is formed in the porous region.
  12. In the manufacturing method of the semiconductor device according to claim 11,
    In the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams,
    In the step (c), the hard mask is made of a metal film that reflects ultraviolet rays or electron beams,
    The process (d) is a process for irradiating the semiconductor substrate with ultraviolet rays or an electron beam.
  13. In the manufacturing method of the semiconductor device according to claim 12,
    The step (d)
    Irradiating the semiconductor substrate with a first ultraviolet ray or a first electron beam in a direction perpendicular to the principal surface of the semiconductor substrate (d1);
    A step (d2) of irradiating the semiconductor substrate with a second ultraviolet ray or a second electron beam in a direction inclined with respect to the main surface of the semiconductor substrate. Method.
  14. In the manufacturing method of the semiconductor device according to claim 12 or 13,
    The material of the metal film that reflects ultraviolet rays or electron beams is one or more kinds of metal materials selected from the group consisting of Ti, TiN, Ta, TaN, W, and WN. A method for manufacturing a semiconductor device.
  15. In the manufacturing method of the semiconductor device according to claim 11,
    In the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen that is desorbed by irradiation with ultraviolet rays or electron beams,
    In the step (c), the hard mask is made of an insulating film that absorbs ultraviolet rays or electron beams,
    The process (d) is a process for irradiating the semiconductor substrate with ultraviolet rays or an electron beam.
  16. In the manufacturing method of the semiconductor device according to claim 15,
    The material of the insulating film that absorbs ultraviolet rays or electron beams is one or a plurality of types of insulating materials selected from the group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 and SiN. A method for manufacturing a semiconductor device.
  17. In the manufacturing method of the semiconductor device according to claim 11,
    In the step (b), the porogen contained in the second interlayer insulating film forming film is a porogen desorbed by heat treatment,
    In the step (c), the hard mask is composed of a film having a higher density than the first interlayer insulating film not containing porogen,
    The method of manufacturing a semiconductor device, wherein the step (d) is a step of performing a heat treatment on the entire surface of the semiconductor substrate.
  18. In the manufacturing method of the semiconductor device according to claim 17,
    The hard mask material is selected from a metal material group consisting of Ti, TiN, Ta, TaN, W, and WN, and an insulating material group consisting of SiCN, SiCO, SiCH, SiON, SiO 2 , and SiN. Or a method of manufacturing a semiconductor device, wherein the material is a plurality of types of materials.
  19. In the manufacturing method of the semiconductor device of any one of Claims 11-18,
    The step (e) further includes a step of forming a via hole in a lower region of the second interlayer insulating film,
    The step (f) further includes a step of forming a via in the via hole,
    In the step (e), the via hole is formed such that a lower region penetrates the non-porous region and an upper region penetrates the porous region.
  20. In the manufacturing method of the semiconductor device according to claim 19,
    After the step (a) and before the step (b), a second wiring groove is formed in the first interlayer insulating film, and then a second wiring is formed in the second wiring groove. A method of manufacturing a semiconductor device, further comprising a step (g).
  21. In the manufacturing method of the semiconductor device according to claim 20,
    A step (h) of forming a barrier film on the first interlayer insulating film and the second wiring after the step (g) and before the step (b);
    In the step (b), the second interlayer insulating film forming film is formed on the barrier film,
    In the step (e), the via hole is formed so as to penetrate a lower region of the second interlayer insulating film and the barrier film.
  22. In the manufacturing method of the semiconductor device according to claim 21,
    A step (i) of forming a cap film on the second interlayer insulating film forming film after the step (b) and before the step (c);
    In the step (c), the hard mask in which the cap film in which the groove is formed and the wiring groove forming groove communicating with the groove are sequentially formed on the second interlayer insulating film forming film is sequentially formed. Formed,
    In the step (e), the first wiring trench is formed in an upper region of the second interlayer insulating film and in the cap film.
  23. In the manufacturing method of the semiconductor device according to claim 22,
    The step (c)
    Forming the hard mask on the cap film (c1);
    After the step (c1), the method includes the step (c2) of forming the groove for forming the wiring groove in the hard mask and forming the groove in the cap film.
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US8993436B2 (en) 2013-04-10 2015-03-31 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device that includes forming passivation film along side wall of via hole
US9053948B2 (en) 2013-04-22 2015-06-09 Samsung Electronics Co., Ltd. Semiconductor devices

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JP3887175B2 (en) * 2001-02-02 2007-02-28 沖電気工業株式会社 Semiconductor device and manufacturing method thereof
JP4578816B2 (en) * 2004-02-02 2010-11-10 Okiセミコンダクタ株式会社 Semiconductor device and manufacturing method thereof
JP2005327873A (en) * 2004-05-13 2005-11-24 Toshiba Corp Semiconductor device and its manufacturing method
US7544608B2 (en) * 2006-07-19 2009-06-09 International Business Machines Corporation Porous and dense hybrid interconnect structure and method of manufacture
JP4419025B2 (en) * 2006-09-04 2010-02-24 ソニー株式会社 Manufacturing method of semiconductor device
JP4919871B2 (en) * 2007-02-09 2012-04-18 東京エレクトロン株式会社 Etching method, semiconductor device manufacturing method, and storage medium

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8993436B2 (en) 2013-04-10 2015-03-31 Samsung Electronics Co., Ltd. Method for fabricating semiconductor device that includes forming passivation film along side wall of via hole
US9053948B2 (en) 2013-04-22 2015-06-09 Samsung Electronics Co., Ltd. Semiconductor devices

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