JP2010085997A - Display - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To asynchronously display two different display signals without using a frame memory and to control superposition of two images on horizontal lines. <P>SOLUTION: A plurality of horizontal display control lines CTL are arranged in parallel with signal lines D and connected to respective switching elements ctl of pixels. Out of pixels in which the switching elements sw are turned on by selection voltages from gate lines G, a pixel which does not rewrite a display signal turns off the switching element ct1 and does not apply a display signal to a liquid crystal cell, and a pixel which rewrites the display signal turns on the switching element ct1 by applying a rewrite selection signal by a horizontal display control circuit 109, wherein the display signal output from a signal circuit and corresponding to the pixel is applied to the liquid crystal cell to rewrite the display signal. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a display device that displays a plurality of videos having different signal sources on one screen.

  In a conventional display device, a signal line driving circuit and a gate line scanning circuit are generally arranged one by one. Therefore, even when displaying a video signal of any format (for example, an image signal that requires high definition such as a photograph or an image signal that does not interfere with low definition such as a standby screen of a portable device). The same circuit will operate and the power consumption will hardly change.

  In recent years, in view of the above-described problems, a display device that can be driven in accordance with each request during use and during standby, and that can display a plurality of image data without combining them in advance. And electronic devices using the same have been proposed.

  The image display device described in Patent Document 1 includes a data signal line driving circuit and a scanning signal line driving circuit having a plurality of different configurations. Each data signal line driving circuit or scanning signal line driving circuit has a different displayable format. By switching the drive circuit to be operated in accordance with the type of input video and the usage environment, it is possible to display in an optimal display format and to reduce power consumption. In addition, by writing video signals to the signal line with a time difference using a plurality of drive circuits, the image can be overwritten, so that the video signals can be displayed in an overlapping manner without external signal processing. It becomes possible.

JP 2002-32048

  In Patent Document 1, it is difficult to arbitrarily control the superposition (overwriting) of video on one horizontal line. Also, in order to synthesize and display two signals having different frame rates, such as video data and image data, it is necessary to synchronize the respective videos. In order to perform this synchronization, an external system (video signal or System that outputs image signals).

  An object of the present invention is to provide a display device capable of combining and displaying a plurality of display signals in the horizontal direction.

  An object of the present invention is to provide a display device capable of asynchronously displaying a plurality of display signals having different periods.

  The present invention provides a horizontal display in which a plurality of horizontal display control lines are arranged in parallel with a signal line, and a rewrite selection signal for controlling rewriting of a display signal in a plurality of pixels connected to a gate line is applied to the horizontal display control line. It has a control circuit, and the pixel is composed of at least two switching elements sw and ctl and a liquid crystal cell. The switching element sw included in the pixel is controlled by a gate line, and the other switching element ctl is controlled by a horizontal display control line. Among the plurality of pixels in which the selection voltage is applied to the gate line and the switching element sw is turned on, the pixel that does not rewrite the display signal turns off the switching element ctl included in the pixel and turns the liquid crystal A pixel that does not apply a display signal to a cell and rewrites the display signal applies a rewrite selection signal by the horizontal display control circuit. The switching elements ctl included in the pixel is turned on, the display signal corresponding to the pixel signal circuit outputs to rewrite the display signal by applying to the liquid crystal cell.

  In addition, according to the present invention, a display signal corresponding to the pixel generated by the signal circuit is output to a signal line corresponding to a pixel whose display signal is rewritten among a plurality of pixels to which a selection voltage is applied to the gate line. A horizontal display control circuit that outputs a potential that is at least higher (or lower) than a potential that is lower (or higher) than a selection voltage by a threshold voltage of the TFT element, on a signal line corresponding to a pixel that does not rewrite a display signal. , Out of a plurality of pixels having a selection voltage applied to the gate line, a common electrode voltage serving as a reference potential of the display signal output from the signal circuit is output to a common line corresponding to a pixel that rewrites the display signal. In a common line corresponding to a pixel that does not rewrite a display signal, the pixel electrode potential of the pixel is at least higher than a potential that is at least lower (or higher) than the selection voltage by the threshold voltage of the TFT element ( A common driving circuit that applies a voltage to the common line so that the potential is low, and a pixel that rewrites a display signal among a plurality of pixels to which a selection voltage is applied to the gate line is a TFT element. Is turned on, and a display signal corresponding to the liquid crystal cell and the compensation capacitor of the pixel is applied and rewritten, and among the plurality of pixels to which the selection voltage is applied to the gate line, the TFT that does not rewrite the display signal The element is turned off, and the pixel performs a holding operation.

  According to the present invention, a plurality of display signals can be combined and displayed in the horizontal direction.

  According to the present invention, a plurality of display signals having different periods can be displayed asynchronously.

Schematic showing the configuration of the display device in Example 1 Pixel configuration diagram in Example 1 Timing chart of video signal and display control signal in embodiment 1 Display screen of display device by video signal and display control signal in embodiment 1 Timing chart of DA conversion circuit and signal synthesis circuit in Embodiment 1 Timing chart of double scanning circuit in embodiment 1 Timing chart of double scanning circuit in embodiment 1 Timing chart for driving pixels in each display region in Embodiment 1 Timing chart for driving pixels in each display region in Embodiment 1 Timing chart for driving pixels in each display region in Embodiment 1 Schematic showing the configuration of the display device in Example 2 Schematic showing the configuration of the display device in Example 3 Timing chart for driving pixels in each display area in Embodiment 3 Timing chart for driving pixels in each display area in Embodiment 3 Timing chart for driving pixels in each display area in Embodiment 3

  Hereinafter, the best mode for carrying out the present invention will be described.

  In the following description of the embodiments, an example of a liquid crystal display device using a liquid crystal material in the pixel portion is shown, but the basic structure and driving method thereof is a display device using an electroluminescent material or a light emitting diode element in the pixel portion. It can also be applied to.

  First, a display device and a driving method according to a first embodiment of the present invention will be described with reference to FIGS.

  FIG. 1 is a schematic view showing a configuration of a display device according to the present invention. Hereinafter, the configuration of the display device will be described. In FIG. 1, the first signal source 101 outputs a digital display signal DATA1 and a control signal SYNC1, which are first video signals, to the display device 103. The second signal source 102 outputs a digital display signal DATA 2 and a control signal SYNC 2 that are second video signals to the display device 103. The display device 103 includes a first DA conversion circuit 104, a second DA conversion circuit 105, a display control circuit 106, a signal synthesis circuit 107, a double scanning circuit 108, a horizontal display control circuit 109, and a pixel array 110. . Note that the number of signal sources may be three or more.

  Here, the pixel array 110 includes n pixels 114 arranged in a matrix (n is a natural number) in the horizontal direction and m (m is a natural number) in the vertical direction, and n pixels are arranged to supply display signals to the pixels. , Dn, and n horizontal display control lines CTL1, CTL2,..., CTLn arranged to control the horizontal display area, and arranged in a matrix. .., Gm arranged in order to select n pixels in the horizontal direction (hereinafter referred to as one horizontal line) among the pixels.

  Here, the pixel 114 will be described. The pixel 114 includes two switching elements sw and cnt, a liquid crystal capacitor Clc, and a common electrode to which a common electrode voltage Vcom is applied. Here, an n-type thin film transistor (TFT) will be described as a switching element, but the switching element is not limited to this. Although not shown, a storage capacitor (or compensation capacitor) for holding the effective voltage of the liquid crystal capacitor Clc is provided. In FIG. 1, the switching element sw has a gate terminal connected to the gate line G, a drain terminal (or source terminal) connected to the signal line D, and a source terminal (or drain terminal) connected to the switching element cnt. On the other hand, the switching element cnt has a gate terminal connected to the horizontal display control line CTL, a drain terminal (or source terminal) connected to the switching element sw, and a source terminal (or drain terminal) applied a display signal to the liquid crystal capacitor Clc. Connected to the pixel electrode. The other electrode of the liquid crystal capacitor Clc is a common electrode. Here, a potential difference between the pixel electrode and the common electrode is applied to the liquid crystal capacitor Clc. Here, in the pixel 114, when the gate line G and the horizontal display control line CTL are in a selected state, an analog display signal transferred from the signal line D is applied to the pixel electrode. Here, FIG. 2 is another configuration diagram of the pixel 114 in the first embodiment. In FIG. 2, the switching element cnt has a gate terminal connected to the horizontal display control line CTLx, a drain terminal (or source terminal) connected to the signal line Dx, and a source terminal (or drain terminal) connected to the switching element sw. . The switching element sw has a gate terminal connected to the gate line Gy, a drain terminal (or source terminal) connected to the switching element cnt, and a source terminal (or drain terminal) that applies an analog display signal to the liquid crystal capacitor Clc. Connected to. Also in the pixel 114 shown in FIG. 2, when the gate line Gy and the horizontal display control line CTLx are in a selected state, an analog display signal transferred from the signal line Dx is applied to the pixel electrode. The pixel 114 included in the pixel array 110 of this embodiment has a structure shown in FIG. 1 or FIG. The analog display signal is preferably a voltage (gray scale voltage) determined for each gray scale.

  1, the display control circuit 106 includes a control signal SYNC1 output from the first signal source 101, a control signal SYNC2 output from the second signal source 102, and a first signal in the display device 103. A timing signal 111 for controlling the display timing of the first video signal and a timing signal for controlling the display timing of the second video signal in response to the display control signal DCNT for controlling the display state of the first and second video signals 112 and a display area control signal 113 for controlling the display area. The first DA conversion circuit 104 receives the digital display signal DATA1 that is the first video signal, converts the digital display signal DATA1 into an analog display signal ANA1, and outputs the analog display signal ANA1 to the signal synthesis circuit 107. The second DA conversion circuit 105 receives the digital display signal DATA2 that is the second video signal, converts it to the analog display signal ANA2, and outputs it to the signal synthesis circuit 107. The signal synthesis circuit 107 receives the first video signal ANA1 and the second video signal ANA2, and synthesizes the signals based on the timing signals 111 and 112 output from the display control circuit 106, and the signal line D1. , D2,..., Dn. The double scanning circuit 108 receives the timing signals 111 and 112 output from the display control circuit 106 and the display area control signal 113, and selects the gate lines G1, G2,..., Gm based on these signals. The horizontal display control circuit 109 receives the display area control signal 113 output from the display control circuit 106 and drives the horizontal display control lines CTL1, CTL2,..., CTLn.

  Accordingly, in the display device shown in FIG. 1, among the pixels connected to the gate line G to which the selection voltage is applied by the double scanning circuit 108, the selection signal is applied to the horizontal display control line CTL by the horizontal display control circuit 109. The display signal output from the signal synthesis circuit 107 is applied to the pixels.

  Here, the display device shown in FIG. 1 may have a configuration in which the pixel array 110 is formed on the glass substrate with amorphous Si and the remaining circuits are installed around the glass, or the pixel array 110 and the double scanning circuit are arranged. 108 and the horizontal display control circuit 109 may be formed on a glass substrate by using polycrystalline Si, and the remaining circuits may be installed around the glass. Also, the circuit and pixel array included in the display device 103 may be used. 110 may be formed on a glass substrate by using polycrystalline Si, and a circuit of a display device formed on the same substrate as the pixel array 110 is not limited.

  Next, the display on the display device 103 shown in FIG. 1 will be described with reference to FIGS.

  FIG. 3 illustrates a vertical display control signal among signals related to the first video output from the first signal source 101, signals related to the second video output from the second signal source 102, and the display control signal DCNT. It is a timing chart which shows VDCNT. FIG. 4 simply shows a screen displayed by the display device 103 according to the first embodiment of the present invention using the signal related to the first video, the signal related to the second video, and the display control signal DCNT. is there.

In FIG. 3, the first video signal is composed of the digital display signal DATA1 and the control signal SYNC1 as described above, and the signals included in SYNC1 include a vertical synchronization signal VCLK1 and a horizontal synchronization signal HCLK1. Although not shown in FIG. 3, SYNC1 includes a dot clock for transferring a digital display signal, a display signal for determining an effective range of the digital display signal, and the like. Here, the first video signal is a signal output at a speed of a frame period Tf1 that is a period of the vertical synchronization signal VCLK1 and a horizontal period Th1 that is a period of the horizontal synchronization signal HCLK1. Here, the horizontal period Th1 includes digital display signals corresponding to n pixels, and the frame period Tf1 includes digital display signals for m lines.
On the other hand, the configuration (type) of the second video signal is the same as that of the first video signal as shown in FIG. The second video signal is a signal output at a speed of a frame period Tf2 that is a period of the vertical synchronization signal VCLK2 and a horizontal period Th2 that is a period of the horizontal synchronization signal HCLK2. Here, the horizontal period Th2 includes digital display signals corresponding to n pixels, and the frame period Tf2 includes m lines of digital display signals. Here, m and n are natural numbers. In the description of the embodiment of the present invention, the case where the number of pixels and the number of horizontal lines of the first video signal and the second video signal are the same will be described, but they may be different.

  Here, the frame period Tf1 (or horizontal period Th1) of the first video signal is equal to or longer than the frame period Tf2 (or horizontal period Th2) of the second video signal. Here, for ease of explanation, the number m of horizontal lines is set to 10, and the frame period Tf2 (horizontal period Th2) of the second video signal is set to be twice the frame period Tf1 (horizontal period Th1) of the first video signal. Although described, the present invention is not limited to this. Further, the phase of the first video signal and the phase of the second video signal are not limited to the relationship shown in FIG.

  VDCNT1 and VDCNT2 are vertical display control signals included in the display control signal DCNT. The former is a display level only for the horizontal period displayed on the display device 103 by the first video signal, and the other is a non-display level. In the latter case, the display level is set only for the horizontal period in which the second video signal is displayed on the display device 103, and the other is set to the non-display level. FIG. 3 shows, for example, the Hi level of the VDCNT signal as the display level, the Low level as the non-display level, VDCNT1 as the display level (Hi level), and VDCNT2 from the fourth horizontal line to the seventh horizontal line. The display level (Hi level) is set in the corresponding horizontal period, and the other periods are set as the non-display level.

  FIG. 4 simply shows a screen displayed on the display device 103. The control in the vertical direction (scanning direction) of the screen shown in FIG. 4 is controlled by the display control signals VDCNT1 and VDCNT2 in the vertical direction shown in FIG. This is a display area (single display area) in which only one video signal is displayed. Since the VDCNT1 and VDCNT2 are both at the display level in the fourth to seventh horizontal lines, the first video signal and the second video signal are It becomes a composite display area to be displayed. On the other hand, control in the horizontal direction of the screen (direction along the horizontal line) is performed by a horizontal display control signal HDCNT included in the display control signal DCNT. The control signal HDCNT is a signal that distinguishes a pixel that displays the first video signal and a pixel that displays the second video signal among the pixels present on one horizontal line. Although the control signal HDCNT is not shown in FIG. 3, in the single display area of the first to third and eighth to tenth horizontal lines, control is performed to display the first video signal on all pixels, and the fourth to seventh horizontal lines are controlled. In the combined display area of the lines, control is performed to distinguish between the area A for displaying the first video signal and the area B for displaying the second video signal. As described above, the display device 103 according to the present invention displays the second video signal in the area designated by the display control signal DCNT and displays the first video signal in the other area.

  Next, the operation of the display device 103 when displaying the screen as shown in FIG. 4 will be described with reference to FIGS.

  First, FIG. 5 is a timing chart showing operations of the first DA converter circuit 104, the second DA converter circuit 105, and the signal synthesis circuit 107. The first DA conversion circuit 104 temporarily stores the digital display signal DATA1 for one horizontal line output from the first signal source, and then outputs the analog display signal ANA1 for one horizontal line. In FIG. 5, the first DA converter circuit 104 stores, for example, a digital display signal for one horizontal line transferred within one horizontal period Th1, and an analog corresponding to the stored digital display signal in the next horizontal period. Output the display signal. Similarly, the second DA conversion circuit 105 temporarily stores the digital display signal DATA2 for one horizontal line output from the second signal source, and then outputs the analog display signal ANA2 for one horizontal line. In FIG. 5, the second DA conversion circuit 105 stores, for example, a digital display signal for one horizontal line transferred within one horizontal cycle Th2, and an analog corresponding to the stored digital display signal in the next horizontal cycle. Output the display signal. The numbers DATA1, DATA2, ANA1, and ANA2 shown in FIG. 5 indicate the numbers of the corresponding horizontal lines.

  The signal synthesis circuit 107 is based on the display timing signal DTM1 of the first video signal included in the timing signal 111 output from the display control circuit 106 and the display timing signal DTM2 of the second video signal included in the timing signal 112. The analog display signals ANA1 and ANA2 output from the first DA conversion circuit 104 and the second DA conversion circuit 105 are combined, and the analog display signal ANA applied to the signal line D is output.

  Here, the display timing signals DTM1 and DTM2 output from the display control circuit 106 will be described. The display control circuit 106 time-divides the horizontal cycle having the shorter horizontal cycle of the first video signal and the second video signal into a plurality of periods. Here, when the horizontal period of the first video signal is the same as that of the second video signal, the horizontal period of one of the video signals is time-divided. Therefore, in the description of the present embodiment, for example, Th1 is shorter than Th2, and therefore the horizontal period Th1 of the first video signal is time-divided into a plurality of periods (ThA, ThB). Then, the display control circuit 106 uses a video signal obtained by time-sharing the horizontal period ThA (or ThB) of one of the time-divided periods in each horizontal period Th1 (in the description of this embodiment, the first 1), the signal level of the display timing signal DTM1 is output as the display level. FIG. 5 shows a case where, for example, the display level of DTM1 is set to the Hi level, and the first half of the time-division horizontal period Th1 is assigned to the display of the first video signal. On the other hand, the display control circuit 106 selects the second period from the period excluding the period allocated to the display of the first video signal (the video signal in which the horizontal period is time-divided) among the plurality of periods in which Th1 is previously time-divided. One period is selected within the horizontal cycle Th2 of the video signal, and assigned as the display period of the second video signal (video signal whose horizontal period is not time-divided). The video signal display timing signal DTM2 is output. In FIG. 5, for example, the display level of DTM2 is set to Hi level, and the display period of the second video signal is changed from the second half of the time-divided period that is not the display period of the first video signal. This shows a case where one is selected and assigned within 2 horizontal periods Th2.

  Accordingly, the signal synthesis circuit 107 selects the analog display signal ANA1 of the first video signal based on the timing signal output from the display control circuit 106 during the period when the display timing signal DTM1 of the first video signal is at the display level. The analog signal ANA2 to be applied to the signal line D is output, and the analog signal ANA2 of the second video signal is selected during the period when the display timing signal DTM2 of the second video signal is at the display level. The analog signal ANA to be applied is output.

FIG. 6 is a timing chart for explaining the operation of the double scanning circuit 108 when the frame period Tf2 of the second video signal is twice the frame period Tf2 of the first video signal. Hereinafter, the operation of the double scanning circuit will be described with reference to FIG. VDSP1 and VDSP2 are vertical display period signals generated by the display control circuit 106 with reference to the timing of the vertical display control signals VDCNT1 and VDCNT2. VG1, VG10 are gate lines (G1, G2,..., G10) of corresponding horizontal lines (first horizontal line, second horizontal line,..., Tenth horizontal line), respectively. The gate line scanning voltage applied by the double scanning circuit 108 is shown in FIG. In the description of the present embodiment, for example, the case where an n-type MOS transistor is used as the switching element sw is cited, but the present invention is not limited to this. Here, the switching element sw is turned on when the gate line scanning voltage VG is at the Hi level, and the switching element sw is turned off when the gate line scanning voltage VG is at the Low level.

  The double scanning circuit 108 scans the horizontal line at two timings: a display timing signal DTM1 for the first video signal and a display timing signal DTM2 for the second video signal. First, the operation of the double scanning circuit 108 based on DTM1 of the first video signal sequentially selects horizontal lines using DTM1 as a clock. At that time, only when the vertical display period signal VDSP1 is at the display level, the gate line scanning voltage of the selected level is applied to the gate line of the selected horizontal line. Here, the period during which the double scanning circuit applies the gate line scanning voltage of the selected level to the gate line in the operation based on DTM1 corresponds to the period of the display level of DTM1. As described above, the signal synthesis circuit 107 applies the analog display signal ANA1 corresponding to the first video signal to the signal line D while DTM1 is at the display level. Therefore, during the period in which the double scanning circuit 108 applies a gate scanning voltage of a selected level to the gate line of a certain horizontal line based on DTM1, the signal synthesizing circuit 107 outputs the first video signal corresponding to the horizontal line. An analog display signal ANA1 is applied to the signal line D. In FIG. 6, for example, the display level of VDSP1 is set to Hi level, and VDSP1 is at the display level over the frame period Th1, so that the gate scanning voltage of the selected level is applied to all horizontal lines (here, the first to tenth horizontal lines). Applied. Next, the operation of the double scanning circuit 108 based on DTM2 of the second video signal sequentially selects horizontal lines using DTM2 as a clock. At this time, only when the vertical display period signal VDSP2 is at the display level, the gate line scanning voltage of the selected level is applied to the gate line of the selected horizontal line. Here, the period during which the double scanning circuit applies the gate line scanning voltage of the selected level to the gate line by the operation based on DTM2 corresponds to the period of the display level of DTM2. As described above, the signal synthesis circuit 107 applies the analog display signal ANA2 corresponding to the second video signal to the signal line D while DTM2 is at the display level. Therefore, during the period in which the double scanning circuit 108 applies the gate scanning voltage of the selected level to the gate line of a certain horizontal line based on DTM2, the signal synthesizing circuit 107 outputs the second video signal corresponding to the horizontal line. An analog display signal ANA2 is applied to the signal line D. In FIG. 6, for example, the display level of VDSP2 is set to Hi level, and VDSP2 is at the display level in the period of the fourth to seventh horizontal lines, so that the gate line scanning voltage of the selected level is applied to the fourth to seventh horizontal lines. Is done. For reference, FIG. 7 shows a timing chart for explaining the driving when the frame period Tf1 of the first video signal and the frame period Tf2 of the second video signal are the same.

  Here, the double scanning circuit 108 may be a circuit configured based on a shift register or a circuit configured based on a decoder. In the case of a circuit based on a shift register, the timing signals 111 and 112 include a start pulse that defines the head of each frame at least in the first and second video signals. In addition, in the case of a circuit based on a decoder, the timing signals 111 and 112 include the start pulse that defines the head of each frame or the position of the horizontal line in at least the first and second video signals. Contains address information to be specified. When the double scanning circuit 108 is a circuit constituted by a decoder and the signal included in the timing signals 111 and 112 includes address information specifying the position of the horizontal line, the horizontal line is arbitrarily selected and displayed. It is also possible.

  Next, the operation of the horizontal display control circuit 109 and the horizontal display operation of the display device 103 will be described with reference to FIGS.

The horizontal display operation of the display device 103 is controlled by the horizontal display control circuit 109. A display area control signal 113 generated by the display control circuit 106 from the display control signal DCNT controls an operation state (signal writing or signal non-writing) of pixels belonging to the horizontal line selected by the double scanning circuit 108. Contains a horizontal display area control signal. The horizontal display control circuit 109 receives the horizontal display area control signal, and the horizontal display control line to which the pixel performing the signal writing operation is connected among the pixels of the horizontal line selected by the double scanning circuit 108. A signal at a writable level is applied to CTL, and a signal at a writable level is applied to display area control line CTL to which a pixel performing signal non-writing operation is connected. (In the following description, for example, the writable level of the horizontal display control line CTL is set to the Hi level, the writable level is set to the Low level, and the switch element cnt included in the pixel 114 is described as an n-type TFT.)
Here, in the display device 103, as shown in FIG. 4, a single display region for displaying only the first video signal (only one type of video signal) (for example, the first to third in the description of the present embodiment). The operation of pixels in the eighth to tenth horizontal lines (for example, the i th horizontal line and the pixel PIXij in the j th column) will be described with reference to FIG. In FIG. 8, during the period ThA in which the selection level is applied by the gate line scanning signal VGi, the signal synthesis circuit 107 converts the analog display signal ANA1ij corresponding to the first video signal of the pixel PIXij to the jth column. Applied to the signal line Dj. During this period, the horizontal display control circuit 109 applies the Hi level to the horizontal display control line CTLj to which the pixel PIXij is connected. Thereby, ANA1ij corresponding to the first video signal is applied to the liquid crystal Clc of the pixel PIXij, and the effective voltage corresponding to the display signal is held.

  Next, in the display device 103, as shown in FIG. 4, a horizontal line area (synthesized display area, for example, the present embodiment) including pixels for displaying the first video signal and pixels for displaying the second video signal. Regarding the operation of the pixels (for example, the sth horizontal line, the tth column of pixels PIXst) in the area (area A in the figure) for displaying the first video signal in the fourth to seventh horizontal lines in the description of the example, This will be described with reference to FIG. In FIG. 9, in the period ThA1 in which the analog display signal ANA1st of the first video signal is output from the signal synthesis circuit 107 and applied to the signal line Dt in the t-th column, the double scanning circuit 108 is the gate line of the s-th horizontal line. The Hi level is output to the scanning signal VGs. During this period, since the pixel PIXst displays the first video signal, the horizontal display control circuit 109 applies the Hi level to the horizontal display control line CTLt of the t-th column to which the pixel PIXst is connected. Thus, ANA1st corresponding to the first video signal is applied to the liquid crystal Clc of the pixel PIXst, and the effective voltage corresponding to the display signal is held. On the other hand, in the period ThB2 in which the analog display signal ANA2st of the second video signal is output from the signal synthesis circuit 107 and applied to the signal line Dt of the t-th column, the double scanning circuit 108 performs the gate line scanning signal of the s-th horizontal line. Output Hi level to VGs. During this period, since the pixel PIXst does not display the second video signal, the horizontal display control circuit 109 applies the Low level to the horizontal display control line CTLt in the t-th column. Thus, even if the t-th horizontal line is selected in the period ThB2, the analog display signal ANA2st of the second video signal is not applied to the pixel PIXst, and the liquid crystal Clc corresponds to the first video signal ANA1st. The effective voltage is maintained.

  Next, in the display device 103, in the composite display area shown in FIG. 4, pixels (for example, pth horizontal line, qth column pixel PIXpq) in the area (area B in the figure) for displaying the second video signal are displayed. The operation will be described with reference to FIG. In FIG. 10, during the period ThB1 in which the analog display signal ANA2pq of the second video signal is output from the signal synthesis circuit 107 and applied to the signal line Dq of the qth column, the double scanning circuit 108 is the gate line of the pth horizontal line. The Hi level is output to the scanning signal VGp. During this period, since the pixel PIXpq displays the second video signal, the horizontal display control circuit 109 applies the Hi level to the q-th column horizontal display control line CTLq to which the pixel PIXpq is connected. Thereby, ANA2pq corresponding to the second video signal is applied to the liquid crystal Clc of the pixel PIXpq, and the effective voltage corresponding to the display signal is held. On the other hand, in the period ThA2 in which the analog display signal ANA1pq of the first video signal is output from the signal synthesis circuit 107 and applied to the signal line Dq in the qth column, the double scanning circuit 108 performs the gate line scanning signal of the pth horizontal line. Output Hi level to VGp. During this period, since the pixel PIXpq does not display the first video signal, the horizontal display control circuit 109 applies the Low level to the horizontal display control line CTLq in the q-th column. Thus, even if the qth horizontal line is selected in the period ThA2, the analog display signal ANA1pq of the first video signal is not applied to the pixel PIXpq, and the second video signal ANA2pq is applied to the liquid crystal Clc. The effective voltage is maintained.

  In the above-described example, the horizontal display control circuit 109 is configured to stop the writing operation of the other video signal after performing the writing operation of the video signal in the display region of a certain display signal in the composite display region. Works. However, when the frame frequencies of the two input video signals are different, the non-writing operation of the video signal with the low frame frequency is not performed in the display region for displaying the video signal with the high frame frequency in the composite display region. Processing for overwriting the other video signal having a higher frame frequency may be performed.

  As described above, by using the two video signals supplied from the two signal sources and the signals for controlling the display areas of the two video signals as inputs, the display device 103 according to the first embodiment of the present invention is used. The corresponding video can be displayed in each area arbitrarily designated by a signal for controlling the display area.

  In addition, in a video signal displayed by one signal source, a still image area such as a background is output as a background video signal with a low frame frequency, and a video image signal of a video area such as other characters and characters is output with a high frame frequency. In the display device 103 according to the first embodiment of the present invention, the drive frequency can be lowered and the power can be reduced by outputting the control signal specifying the moving image area.

  Also, even when two video signals with different frame frequencies are used as input signal sources, each display area specified by a signal for controlling the display area is asynchronously synchronized without synchronizing the frames of the two video signals. The corresponding video signal can be displayed. This also eliminates the need for frame memory (capacity that can store display data for one screen) required for synchronization (image composition), reducing costs, and reducing the peripheral circuit area. Etc. can be realized.

  Next, a second embodiment of the display device and the driving method according to the present invention will be described with reference to FIG. FIG. 11 is a schematic diagram showing the configuration of a display device that is Embodiment 2 of the present invention. Hereinafter, the configuration of the display device will be described with reference to FIG. 11, but the same parts as those of the display device according to the first embodiment are denoted by the same numbers and symbols, and the description thereof is omitted.

  The first DA conversion circuit 104 and the second DA conversion circuit 105 may be located only on one side (only the upper side) with respect to the pixel array 110 as shown in FIG. (Not shown). Part or all of the first DA conversion circuit 104, the second DA conversion circuit 105, the signal synthesis circuit 107, the double scanning circuit 108, and the horizontal display control circuit 109 constitutes the pixel array 110, that is, the pixel array 110. It may be located on the glass substrate. Further, a part or all of the first DA conversion circuit 104, the second DA conversion circuit 105, the signal synthesis circuit 107, and the horizontal display control circuit 109 may be configured by one LSI (signal circuit), or the second DA conversion circuit. 105, the signal synthesis circuit 107 and the horizontal display control circuit 109 may be configured by separate LSIs. When the first DA conversion circuit 104 and the second DA conversion circuit 105 have an interface circuit, the first DA conversion circuit 104 and the second DA conversion circuit 105 are directly connected from the first signal source 101 and the second signal line 102 as shown in FIG. When the first DA converter circuit 104 and the second DA converter circuit 105 do not have an interface circuit, the first DA converter circuit 104 and the second DA converter circuit 105 receive the first signal source 101. In addition, it is preferable to receive DATA1, SYNC1, DATA2, and SYNC2 indirectly from the second signal line 102 via the display control circuit 106.

  As shown in FIG. 1, the signal synthesis circuit 107 is located on the rear stage side (pixel array 110 side) of the first DA conversion circuit 104 and the second DA conversion circuit 105, and combines the analog display signal ANA1 and the analog display signal ANA2. Alternatively, the digital display signal DATA1 and the digital display signal DATA2 may be synthesized by being located on the first stage side (the first signal source 101 and the second signal source 102 side) of the first DA conversion circuit 104 and the second DA conversion circuit 105. (Not shown).

  The display device 1103 according to the second embodiment, which is the present invention, has a different display signal processing path than the display device 103 according to the first embodiment. In the display device 1103, the first data latch circuit 1104 temporarily stores the digital display signal DATA 1 that is the first video signal transferred from the first signal source 101, and outputs the digital display signal LDATA 1 to the signal synthesis circuit 1107. . The second data latch circuit 1105 temporarily stores the digital display signal DATA2 that is the second video signal transferred from the second signal source 102, and outputs the digital display signal LDATA2 to the signal synthesis circuit 1107. The signal synthesis circuit 1107 receives the digital display signal LDATA1 input from the first data latch circuit 1104 and the second data latch circuit 1105 based on the display timing signals DTM1 and DTM2 described in the first embodiment of the present invention. Either one of the two digital display signals and the digital display signal LDATA2 is selected and output to the DA conversion circuit 1115. The DA conversion circuit 1115 converts the digital display signal output from the signal synthesis circuit 1107 into an analog display signal ANA and outputs the analog display signal ANA to the signal line Dx.

  Next, the operation of the circuit of the display device 1103 will be described. The first data latch circuit 1104 has at least two storage units. One storage means functions to sequentially store the digital display signal DATA1 transferred from the first signal source, and the other storage means stores the display signals sequentially stored by the former storage means at an arbitrary time point. The digital display signal LDATA1 is output to an external device. Therefore, for example, the former storage means sequentially stores the digital display signal DATA1 corresponding to one horizontal line, and then stored in the former at an arbitrary time before the display signal of the next one horizontal line is transferred. The latter storage means stores the display signal for one horizontal line and outputs it as a digital display signal LDATA1. While the latter storage means is outputting LDATA1, the former storage means sequentially stores the digital display signal DATA1 of the next one horizontal line again. The first data latch circuit 1104 repeats this operation. The second data latch circuit 1105 also has at least two storage means. One storage means functions to sequentially store the digital display signal DATA2 transferred from the second signal source, and the other storage means stores the display signals sequentially stored by the former storage means at an arbitrary time point. The digital display signal LDATA2 is output to an external device. Therefore, for example, the former storage means sequentially stores the digital display signal DATA2 corresponding to one horizontal line, and then stored in the former at an arbitrary time before the display signal of the next one horizontal line is transferred. The latter storage means stores the display signal for one horizontal line and outputs it as a digital display signal LDATA2. While the latter storage means is outputting LDATA2, the former storage means sequentially stores the digital display signal DATA2 of the next one horizontal line again. The second data latch circuit 1105 also repeats this operation. The signal synthesis circuit 1107 selects and outputs the first data latch circuit LDATA1 to the DA conversion circuit 1115 within the period when the display timing signal DTM1 of the first video signal output from the display control circuit 106 is at the display level. The second data latch circuit LDATA2 is selected and output to the DA conversion circuit 1115 within the period when the display timing signal DTM2 of the second video signal output from the control signal 106 is at the display level. The DA conversion circuit 1115 converts the digital display signal ANA output from the signal synthesis circuit 1107 into an analog display signal ANA and applies it to the signal line Dx.

  As described above, the first DA converter circuit 104, the second DA converter circuit, and the signal synthesis circuit 107 included in the display device 103 according to the first embodiment of the present invention have the same function as that of generating the analog display signal ANA. The first data latch circuit 1104, the second data latch circuit 1105, the signal synthesis circuit 1107, and the DA conversion circuit 1115 included in the display device 1103 according to the second embodiment of the present invention can be used.

  Therefore, by using the two video signals supplied from the two signal sources and the signals for controlling the display areas of these two video signals as inputs, the display device 1103 according to the second embodiment of the present invention is used, so that the display area is reduced. The corresponding video can be displayed in each area arbitrarily designated by the control signal.

  In addition, in a video signal displayed by one signal source, a still image area such as a background is output as a background video signal with a low frame frequency, and a video image signal of a video area such as other characters and characters is output with a high frame frequency. In the display device 1103 according to the second embodiment of the present invention, the driving frequency can be lowered and the power can be reduced by outputting together with the control signal designating the moving image area.

  Also, even when two video signals with different frame frequencies are used as input signal sources, each display area specified by a signal for controlling the display area is asynchronously synchronized without synchronizing the frames of the two video signals. The corresponding video signal can be displayed. This also eliminates the need for the frame memory required for synchronization (image synthesis), and can realize cost reduction and narrowing of the frame by reducing the peripheral circuit area.

  Next, a display device and a driving method according to a third embodiment of the present invention will be described with reference to FIGS.

  FIG. 12 is a schematic diagram showing the configuration of a display apparatus that is Embodiment 3 of the present invention. Hereinafter, the configuration of the display device will be described with reference to FIG. 12, but the same parts as those of the display device according to the first embodiment are denoted by the same numbers and symbols, and the description thereof is omitted.

  The display device 1203 according to the third embodiment of the present invention relates to a method for generating an analog display signal ANA from each signal source and a method for controlling a vertical display area by the double scanning circuit 108. Although it is the same as the display apparatus 103, the control method of the display area of a horizontal direction differs. In addition, the configuration of the pixel array 1210 and the pixel 1214 are different due to different control methods of the display area in the horizontal direction.

  First, the pixel array 1210 has n pixels (n is a natural number) in the horizontal direction and m pixels (m is a natural number) in the vertical direction, and n pixels are arranged to supply display signals to the pixel columns. , Dn, and n common lines COM1, COM2,..., COMn arranged to supply a common electrode voltage to the pixel columns, and arranged in a matrix. Among the pixels, m gate lines G1, G2,..., Gm are arranged in order to select n pixels in the horizontal direction (hereinafter referred to as one horizontal line).

  A configuration of the pixel 1214 included in the pixel array 1210 will be described. The pixel 1214 includes one switching element sw, a liquid crystal capacitor Clc, and a storage capacitor Cst. Here, an n-type thin film transistor (TFT) will be described as a reference for the switching element sw, but the switching element is not limited to this. In the figure, the switching element sw has a gate terminal connected to the gate line Gy, a drain terminal (or source terminal) connected to the signal line Dx, and a source terminal (or drain terminal) signaled to the liquid crystal capacitor Clc and the holding capacitor Cst. It is connected to a pixel electrode to which a voltage is applied. The common electrode COM, which is the other electrode of the liquid crystal capacitor Clc and the storage capacitor Cst, is connected to the common line COMx, and the common electrode voltage Vcom is applied. In the pixel 1214, when the switching element sw is on, the analog display signal applied to the signal line Dx is applied to the pixel electrode. When the switching element sw is in the off state, the potential difference between the pixel electrode and the common electrode COM is held in the liquid crystal capacitor Clc and the holding capacitor Cst.

  On the other hand, in the configuration of the display device 1203 according to the third embodiment of the present invention shown in FIG. 12, the circuits for controlling the display area in the horizontal direction are a horizontal display control circuit 1215 and a common drive circuit 1209. The horizontal display control circuit 1215 is based on the horizontal display area control signal included in the display area control signal 113 output from the display control circuit 106, or the analog display signal ANA output from the signal synthesizing circuit 107 or the write disabled level. Either one is selected and applied to the signal line Dx. The common drive circuit 1209 also has a writable level common electrode voltage Vcom and a writable level common electrode voltage based on the horizontal display area control signal included in the display area control signal 113 output from the display control circuit 106. One voltage of Vcom_n is selected and applied to the common line COMx.

  Hereinafter, a method for controlling the display area in the horizontal direction will be described with reference to a simplified diagram of the display screen of the display device 1203 shown in FIG. 4 and a timing chart of driving voltages of the pixels 1214 in each display area shown in FIGS. .

  In the display device 1203, as shown in FIG. 4, a single display area for displaying only the first video signal (only one type of video signal) (for example, the first to the third in the description of the present embodiment, The operation of the pixels (e.g., the 8th to 10th horizontal lines) (for example, the i th horizontal line and the pixels PIXij in the j th column) will be described with reference to FIG. Since the display control circuit 106 is a single display area in which the i-th horizontal line displays only the first video signal, the common drive circuit 1209 is set at a writable level during the period ThA for displaying the first video signal. The common electrode voltage Vcom is selected and applied to the common line COM, and the horizontal display control circuit 1215 selects the analog display signal ANA output from the signal synthesis circuit 107 and outputs it to the signal line D. A horizontal display area control signal included in the area control signal 113 is generated and output. Therefore, in FIG. 13, during the period ThA, the selection level is applied to the gate line of the i-th horizontal line by the gate line scanning signal VGi, and the first video of the pixel PIXij output from the signal synthesis circuit 107 within the same period. The analog display signal ANA1ij corresponding to the signal is selected by the horizontal display control circuit 1215 and output to the signal line Dj in the j-th column, and the common drive circuit 1209 selects the common electrode voltage Vcom at a writable level to the j-th column. Output to the common line COMj of the eyes. Here, for example, when the switching element of the pixel 1214 is an n-type TFT, the selection level of the gate line scanning signal VG is higher than the highest voltage level in the analog display signal output from the DA conversion circuit. The potential level is higher than the threshold voltage Vth of the switching element sw. This is because when the selection level is applied, the switching element sw included in the pixel is turned on, and the analog display signal ANA transferred from the signal line D is applied to the pixel electrode of the liquid crystal capacitor Clc. As a result, the analog display signal ANA1ij is applied to the pixel electrode VSij of the pixel PIXij, the common electrode voltage Vcom is applied to the common electrode COMij, and the effective voltage VLCDij corresponding to the display signal is held in the liquid crystal capacitor Clc and the holding capacitor Cst. The

  Next, in the display device 1203, as shown in FIG. 4, a horizontal line area (synthesized display area, for example, this embodiment) including pixels for displaying the first video signal and pixels for displaying the second video signal. Regarding the operation of the pixels (for example, the sth horizontal line, the tth column of pixels PIXst) in the area (area A in the figure) for displaying the first video signal in the fourth to seventh horizontal lines in the description of the example, This will be described with reference to FIG. In the display control circuit 106, since the pixel PIXst is a pixel that displays the first video signal, the common drive circuit 1209 performs the common electrode voltage Vcom at a writable level during the period ThA1 during which the first video signal is displayed. And the horizontal display control circuit 1215 selects the analog display signal ANA1st corresponding to the first video signal output from the signal synthesis circuit 107, and applies it to the t-th common line COMt. The common drive circuit 1209 selects the common electrode voltage Vcom_n at a non-writable level during the period ThB2 during which the second video signal is displayed while outputting the signal to the signal line Dt in the column, and the common in the t-th column. So that it is applied to the line COMt, and the horizontal display control circuit 1215 selects a non-writable level and outputs it to the signal line Dt in the t-th column. It generates and outputs a horizontal direction of the display area control signal included in the display area control signal 113. Therefore, in FIG. 14, during the period ThA1, the selection level is applied to the gate line of the s-th horizontal line by the gate line scanning signal VGs, and the first video of the pixel PIXst output from the signal synthesis circuit 107 within the same period. The analog display signal ANA1st corresponding to the signal is selected by the horizontal display control circuit 1215 and output to the signal line Dt in the t-th column, and the common drive circuit 1209 applies the common electrode voltage Vcom of the writable level to the common in the t-th column. Output to line COMt. As a result, the analog display signal ANA1st is applied to the pixel electrode VSst of the pixel PIXst, the writable level common electrode voltage Vcomt is applied to the common electrode COMst, and the effective voltage VLCD1st corresponding to the display signal is applied to the liquid crystal capacitor Clc and the storage capacitor. Held in Cst. On the other hand, during the period ThB2 for displaying the second video signal, the selection level is applied to the gate line of the s-th horizontal line by the gate line scanning signal VGs, and the horizontal display control circuit 1215 has the write disable level VD_n within the same period. Is output to the signal line Dt in the t-th column, and the common drive circuit 1209 also outputs the common electrode voltage Vcom_n at a write-impossible level to the common line COMt in the t-th column. Here, for example, the voltage level of the non-writable level VD_n selected by the horizontal display control circuit 1209 is set to be equal to or higher than the selection level of the gate scanning signal VG. Here, for example, the voltage level of the non-writable level Vcom_n selected by the common drive circuit 1215 is set so that the pixel electrode potential VSst ′ after the change of the common electrode voltage is equal to or higher than the selection level of the gate scanning signal VG. Thus, the switching element sw of the pixel PIXst is also turned off in the period ThB2, and the effective voltage VLCD1st written in the period ThA1 is held in the pixel PIXst.

  Next, in the display device 1203, as shown in FIG. 4, a horizontal line area (synthesized display area, for example, this embodiment) including pixels for displaying the first video signal and pixels for displaying the second video signal. Regarding the operation of the pixels (for example, the pth horizontal line and the qth column of pixels PIXpq) in the region (region B in the drawing) for displaying the second video signal in the fourth to seventh horizontal lines in the description of the example, This will be described with reference to FIG. In the display control circuit 106, since the pixel PIXpq is a pixel for displaying the second video signal, the common drive circuit 1209 has a writable level common electrode voltage Vcom during the period ThB1 during which the second video signal is displayed. And the horizontal display control circuit 1215 selects the analog display signal ANA2pq corresponding to the second video signal output from the signal synthesis circuit 107, and applies the qth common line COMq. The common driving circuit 1209 selects the common electrode voltage Vcom_n at the write-impossible level during the period ThA2 during which the first video signal is displayed, and outputs the signal to the column signal line Dq. So that it is applied to the line COMq, and the horizontal display control circuit 1215 selects a non-writable level and outputs it to the signal line Dt in the q-th column. It generates and outputs a horizontal direction of the display area control signal included in the display area control signal 113. Therefore, in FIG. 15, during the period ThB1, the selection level is applied to the gate line of the p-th horizontal line by the gate line scanning signal VGp, and the second image of the pixel PIXpq output from the signal synthesis circuit 107 within the same period. The analog display signal ANA2pq corresponding to the signal is selected by the horizontal display control circuit 1215 and output to the signal line Dq in the q-th column, and the common drive circuit 1209 outputs the common electrode voltage Vcom at a writable level to the common in the q-th column. Output to line COMq. As a result, the analog display signal ANA2pq is applied to the pixel electrode VSpq of the pixel PIXpq, the writable level common electrode voltage Vcomq is applied to the common electrode COMpq, and the effective voltage VLCD2pq corresponding to the display signal is changed to the liquid crystal capacitance Clc and the holding capacitance. Held in Cst. On the other hand, during the period ThA2 during which the first video signal is displayed, the selection level is applied to the gate line of the p-th horizontal line by the gate line scanning signal VGp, and the horizontal display control circuit 1215 has the write disable level VD_n within the same period. Is output to the signal line Dq in the q-th column, and the common drive circuit 1209 also outputs the common electrode voltage Vcom_n at a write-impossible level to the common line COMq in the q-th column. Thus, the switching element sw of the pixel PIXpq is also turned off in the period ThA2, and the effective voltage VLCD2pq written in the period ThB1 is held in the pixel PIXpq.

  In the above-described example, the horizontal display control circuit 1209 stops the writing operation of the other video signal after performing the writing operation of the video signal in the display region of a certain display signal in the composite display region. The common drive circuit 1215 operates. However, when the frame frequencies of the two input video signals are different, the non-writing operation of the video signal with the low frame frequency is not performed in the display region for displaying the video signal with the high frame frequency in the composite display region. Processing for overwriting the other video signal having a higher frame frequency may be performed.

  As described above, by using the two video signals supplied from the two signal sources and the signal for controlling the display area of the two video signals as inputs, the display device 1203 according to the third embodiment of the present invention is used. The corresponding video can be displayed in each area arbitrarily designated by a signal for controlling the display area.

  In addition, in a video signal displayed by one signal source, a still image area such as a background is output as a background video signal with a low frame frequency, and a video image signal of a video area such as other characters and characters is output with a high frame frequency. In the display device 1203 according to the third embodiment of the present invention, the driving frequency can be lowered and the power can be reduced by outputting together with the control signal designating the moving image area.

  Also, even when two video signals with different frame frequencies are used as input signal sources, each display area specified by a signal for controlling the display area is asynchronously synchronized without synchronizing the frames of the two video signals. The corresponding video signal can be displayed. This also eliminates the need for the frame memory required for synchronization (image synthesis), and can realize cost reduction and narrowing of the frame by reducing the peripheral circuit area.

  In addition, the first DA converter circuit 104, the second DA converter circuit 105, and the signal synthesis circuit 107 included in the display device 1203 according to the third embodiment of the present invention are included in the display device 1103 according to the second embodiment of the present invention. As described above, even when the first data latch circuit 1104, the second data latch circuit 1105, the signal synthesis circuit 1107, and the DA conversion circuit 1115 are replaced, the same effect as described above can be obtained.

  By using the display device and the driving method according to the embodiment of the present invention, when two video signals supplied from two signal sources and a signal for controlling the display area of these two video signals are input. The corresponding video can be displayed in each area arbitrarily designated by a signal for controlling the display area. In other words, it is possible to select an arbitrary area and display an arbitrary video in that area. In addition, in a video signal displayed by one signal source, a still image area such as a background is output as a background video signal with a low frame frequency, and a video image signal of a video area such as other characters and characters is output with a high frame frequency. As described above, by outputting together with the control signal designating the moving image area, the drive frequency can be lowered, and a display device with reduced power consumption can be realized. Also, even when two video signals with different frame frequencies are used as input signal sources, each display area specified by a signal for controlling the display area is asynchronously synchronized without synchronizing the frames of the two video signals. The corresponding video signal can be displayed. As a result, the frame memory required for synchronization (image synthesis) is not required, and a display device that achieves cost reduction and a narrow frame by reducing the peripheral circuit area can be obtained.

  The present invention can be applied to a display device that displays a plurality of videos having different signal sources on one screen.

101 first signal source 102 second signal source 103 display device 104 first DA converter circuit 105 second DA converter circuit 106 display control circuit 107 signal synthesis circuit 108 double scanning circuit 109 horizontal display control circuit 110 pixel array 111 first video signal Timing signal 112 second video signal timing signal 113 display area control signal 114 pixel 1103 display device 1104 first data latch circuit 1105 second data latch circuit 1107 signal synthesis circuit 1115 DA conversion circuit 1203 display device 1209 common drive circuit 1210 Pixel array 1214 Pixel 1215 Horizontal display control circuit

Claims (10)

A plurality of signal lines and a plurality of gate lines intersecting each other, a plurality of common lines intersecting with the gate lines and disposed along the signal lines, and pixels disposed corresponding to the intersections. An n-type TFT element having a liquid crystal cell, a compensation capacitor corresponding to the liquid crystal cell, a gate connected to the gate line, a drain connected to the signal line, and a source connected to the liquid crystal cell and the pixel electrode of the compensation capacitor A pixel array having a pixel in which a common electrode of the liquid crystal cell and the compensation capacitor is connected to the common line;
A scanning circuit for applying a selection voltage to the gate line;
In a display device having a signal circuit that generates a display signal corresponding to the pixel to which the selection voltage is applied by the gate line,
A display signal corresponding to the pixel generated by the signal circuit is output to the signal line corresponding to a pixel that rewrites the display signal among a plurality of pixels to which the selection voltage is applied to the gate line, and the display A horizontal display control circuit for outputting a potential higher than a potential lower than the selection voltage by a threshold voltage of the TFT element to the signal line corresponding to a pixel whose signal is not rewritten;
A common electrode voltage serving as a reference potential of the display signal output by the signal circuit is output to the common line corresponding to a pixel that rewrites the display signal among a plurality of pixels to which the selection voltage is applied to the gate line. Then, a voltage is applied to the common line so that the pixel electrode potential of the pixel is higher than the selection voltage by a threshold voltage of the TFT element to the common line corresponding to the pixel in which the display signal is not rewritten. And a common drive circuit that
The horizontal display control circuit turns on the TFT element of a pixel that rewrites the display signal among a plurality of pixels to which a selection voltage is applied to the gate line, and the TFT element of a pixel that does not rewrite the display signal A display device characterized in that is turned off. A plurality of signal lines and a plurality of gate lines intersecting each other, a plurality of common lines intersecting with the gate lines and disposed along the signal lines, and pixels disposed corresponding to the intersections. A p-type TFT element having a liquid crystal cell, a compensation capacitor corresponding to the liquid crystal cell, a gate connected to the gate line, a drain connected to the signal line, and a source connected to the liquid crystal cell and the pixel electrode of the compensation capacitor A pixel array having a pixel in which a common electrode of the liquid crystal cell and the compensation capacitor is connected to the common line;
A scanning circuit for applying a selection voltage to the gate line;
In a display device having a signal circuit that generates a display signal corresponding to the pixel to which the selection voltage is applied by the gate line,
A display signal corresponding to the pixel generated by the signal circuit is output to the signal line corresponding to a pixel that rewrites the display signal among a plurality of pixels to which the selection voltage is applied to the gate line, and the display A horizontal display control circuit that outputs a potential lower than a potential that is higher than the selection voltage by a threshold voltage of the TFT element to the signal line corresponding to a pixel that does not rewrite a signal;
A common electrode voltage serving as a reference potential of the display signal output by the signal circuit is output to the common line corresponding to a pixel that rewrites the display signal among a plurality of pixels to which the selection voltage is applied to the gate line. Then, a voltage is applied to the common line so that the pixel electrode potential of the pixel is lower than the potential that is higher than the selection voltage by the threshold voltage of the TFT element. A common drive circuit to apply,
The horizontal display control circuit turns on the TFT element of a pixel that rewrites the display signal among a plurality of pixels to which a selection voltage is applied to the gate line, and the TFT element of a pixel that does not rewrite the display signal A display device characterized in that is turned off. A display control circuit for controlling display areas of the first display signal and the second display signal having different signal sources, and display timings of the first display signal and the second display signal;
The signal circuit includes a first DA conversion circuit that converts the first display signal into an analog first display signal, and a second DA that converts the second display signal into an analog second display signal. A DA conversion circuit; and a signal combining circuit that combines the first display signal from the first DA conversion circuit and the second display signal from the second DA conversion circuit;
The scanning circuit applies the selection voltage to the gate line at a first scanning frequency of the first display signal based on a control signal output from the display control circuit, and outputs a second voltage of the second display signal. 3. The display device according to claim 1, wherein a selection voltage is applied to the gate line at a scanning frequency of 2 . A display control circuit for controlling display areas of the first display signal and the second display signal having different signal sources, and display timings of the first display signal and the second display signal;
The signal circuit includes a first latch circuit that latches the first display signal, a second latch circuit that latches the second display signal, and the first display from the first latch circuit. A signal combining circuit for combining the signal and the second display signal from the second latch circuit, and a DA converter circuit for converting the combined display signal into an analog display signal,
The scanning circuit applies the selection voltage to the gate line at a first scanning frequency of the first display signal based on a control signal output from the display control circuit, and outputs a second voltage of the second display signal. 3. The display device according to claim 1, wherein the selection voltage is applied to the gate line at a scanning frequency of 2 . The display control circuit time-divides and obtains the time division of the shorter horizontal period of the first horizontal period of the first display signal and the second horizontal period of the second display signal. The selection voltage is applied to the gate line when the scanning circuit scans the gate line at the first scanning frequency of the first display signal during at least one of a plurality of period periods. The scanning circuit scans the gate line at the second scanning frequency of the second video signal in at least one other period among the plurality of period periods obtained by time division. 5. The display device according to claim 3 , wherein the display device is assigned as a second period in which the selection voltage is applied to the gate line. The scanning circuit selects the gate line to which the selection voltage is applied at the first scanning frequency and the second scanning frequency according to a vertical display period signal output from the display control circuit,
The horizontal display control circuit is configured to display the first display among the pixels connected to the gate line to which the scanning circuit has applied the selection voltage based on a horizontal display area control signal output from the display control circuit. Selecting the pixel to write a signal or the pixel to write the second display signal;
A first region of the pixel array displays the first display signal;
The display device according to claim 5 , wherein the second region of the pixel array displays the second display signal. 5. The display according to claim 3 , wherein at least one of the scanning circuit, the signal circuit, the horizontal display control circuit, and the display control circuit is formed on the same substrate as the pixel array. apparatus. The external display signal includes each of a plurality of display signals from different signal sources,
The display control circuit selects the pixel column corresponding to the partial display signal and updates the other display signal when updating a partial display signal among the plurality of display signals having different signal sources. 3. The display device according to claim 1, wherein the pixel column corresponding to is deselected. The signal circuit, wherein the each of the plurality of different display signals of said signal source, to any one of claims 1 or 2, characterized in that the output to the pixel of the image sparse array in a time division collectively pixel rows Display device. The plurality of display signals from different signal sources are different from each other in at least one period of a horizontal synchronizing signal and a period of a vertical synchronizing signal,
The scanning circuit, in the period and the period of the vertical synchronizing signal of each said horizontal synchronizing signals of a plurality of different display signals of said signal source, any claim 1 or 2, characterized in that selects the pixel row the display device according to either.

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