JP2010050147A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a high-breakdown voltage semiconductor device having a field limiting ring forming a voltage blocking region and a field plate for improving stabilization of blocked voltage and reliability. <P>SOLUTION: In the semiconductor device 50, an element region including a semiconductor element and a voltage blocking region surrounding the element region are formed on a first semiconductor layer 2 of a first conductivity type. The voltage blocking region, which is arranged to continuously surround the element region on the first semiconductor layer 2, is provided with one or more second semiconductor layers 4-6 of a second conductivity type, an insulation film 14, which is formed to cover the first semiconductor layer 2 including the second semiconductor layers 4-6 and contains an insulation thin film part 14a located above the second semiconductor layers 4-6 and reduced in thickness and the rest of insulation thick film part 14b, and plate electrodes 10-12 formed along the upper parts of the second semiconductor layers 4-6 via the insulation thin film part 14a to extend above the first semiconductor layer 2 via the insulation thick film part 14b on the element region side and its opposite side. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a semiconductor element, and more particularly to a high breakdown voltage semiconductor device including a field limiting ring and a field plate constituting a voltage blocking region.

  As one method for obtaining a high breakdown voltage in a semiconductor device, a field limiting ring (hereinafter, sometimes abbreviated as FLR) is known. Hereinafter, a conventional semiconductor device having an FLR will be described using the semiconductor device described in Patent Document 1 as an example.

  5 and 6 are a plan view and a cross-sectional view schematically showing a conventional semiconductor device 100 having an FLR.

As shown in FIG. 5, an element region 116 in which a semiconductor element or the like is formed on an N ⁻ type semiconductor layer 102 (see FIG. 6), and a voltage blocking region surrounding the element region 116 are provided. . The voltage blocking region includes a first electrode 109 that surrounds the element region 116, a plate electrode 110, a plate electrode 111, a plate electrode 112, and a second electrode 113. FIG. 6 shows a cross section taken along line VI-VI ′ in FIG. 5, which corresponds to the voltage blocking region.

As shown in FIG. 6, the semiconductor device 100 is formed using a P ⁺ type substrate 101. An N ⁻ type semiconductor layer 102 is provided on the P ⁺ type substrate 101.

A P-type semiconductor layer 103 is provided on the N ⁻ -type semiconductor layer 102, and three P-type semiconductor layers that surround the P-type semiconductor layer 103 are formed as FLR 104 and FLR 105 in order from the P-type semiconductor layer 103 side. And FLR 106 are provided by impurity diffusion. Further, an N ⁺ type semiconductor layer 107 functioning as a channel stopper is provided so as to surround the outer side further than the FLR 106.

Further, a first insulating film 114 covering the N ⁻ type semiconductor layer 102 and opened in a groove shape along the P type semiconductor layer 103, the FLRs 104 to 106, and the N ⁺ type semiconductor layer 107 is formed. Is provided.

A first electrode 109 is provided on the P-type semiconductor layer 103 so as to make a low-resistance contact and partially extend above the N ⁻ -type semiconductor layer 102 via the first insulating film 114. Further, a plate electrode 110, a plate electrode 111, and a plate electrode 112 are provided on the FLR 104, FLR 105, and FLR 106, respectively, which are in low resistance contact. The plate electrodes 110, 111, and 112 are also partly first in the inner direction (the direction of the P-type semiconductor layer 103 and the element region 116) and the outer direction (the direction of the N ⁺ -type semiconductor layer 107) of the semiconductor device 100. The N ⁻ type semiconductor layer 102 is extended through the insulating film 114. Further, a second electrode 113 is provided so as to be in a low resistance contact with the N ⁺ type semiconductor layer 107 and partly extend above the N ⁻ type semiconductor layer 102 via the first insulating film 114. It has been. Further, a second insulating film 115 is provided so as to cover the above components.

Here, in the above electrodes, a portion extending to the upper part of the N ⁻ type semiconductor layer 102 via the first insulating film 114 is called a field plate (hereinafter sometimes referred to as FP). In particular, the FP extending in the outer direction is called a forward field plate (forward FP), and the FP extending in the inner direction is called a reverse field plate (reverse FP). The first electrode 109 includes the forward FP, the second electrode 113 includes only the reverse FP, and the plate electrodes 110 to 112 include both the forward FP and the reverse FP. In FIG. 6, the forward FP 111 a and the reverse FP 111 b are denoted by reference symbols only for the plate electrode 111.

The third electrode 108 is provided on the back surface of the P ⁺ -type substrate 101 (the surface opposite to the N ⁻ -type semiconductor layer 102) so as to make a low resistance contact.

  FLR and FP are provided to maintain the breakdown voltage in the peripheral direction of the semiconductor device 100. This will be described below.

In the high breakdown voltage semiconductor device 100 having the conventional FLR shown in FIGS. 5 and 6, a depletion layer is formed from a PN junction (a PN junction formed at the interface between the P-type semiconductor layer 103 and the N ⁻ -type semiconductor layer 102). When it reaches the vicinity of the FLR, the depletion layer further extends to the outside of the FLR. When a plurality of FLRs are provided, the depletion layer spreads in accordance with the number of FLRs, so that the electric field to the curved surface portion of the PN junction portion (the corner portion of the planar shape where the electrode is likely to be strong) is relaxed. Thereby, the withstand voltage is improved.

However, since the FLR structure is easily affected by charges, a plate electrode or the like having an FP is usually disposed on the FLR to shield charges caused by movable ions in the resin above the FP. Further, the distance between the plate electrodes 110, 111, and 112 is reduced to reduce the area where the upper surface of the N ⁻ type semiconductor layer 102 is exposed. This also shields the influence of mobile ion polarization, stabilizes the blocking voltage, and contributes to the improvement of reliability.
Japanese Patent No. 3424635 Japanese Unexamined Patent Publication No. 06-97469 (FIG. 7 etc.)

However, in the conventional semiconductor device 100 described in Patent Document 1, in order to stabilize the blocking voltage by making it less susceptible to the influence of ionic substances, moisture, etc., and to improve the reliability of the semiconductor device, the plate electrode 110 is used. Even when the equipotential lines on ˜112 are disturbed, the equipotential lines in the N ⁻ -type semiconductor layer 102 need to be stable without being disturbed. For this purpose, the length of the forward FP and the reverse FP, the interval between the forward FP and the reverse FP, etc. are set, respectively, and the field plate is applied to the charge distribution caused by ions, moisture, etc. in the resin on the plate electrode. The structure of must be optimized. This will be further described with reference to FIGS.

  FIG. 7 is a diagram showing a range including FLRs 104, 105, and 106 in FIG. 6 and field plates 110, 111, and 112 formed respectively. FIG. 7 shows potentials and capacitances related to the FLR 105 and the plate electrode 111 provided thereon.

The potential Vm on the second insulating film 115 is generated when mobile ions in the resin are polarized by the surface potential of the second insulating film 115 in, for example, a high-temperature DC reverse bias test (Patent Document 2). (See FIG. 7 etc.). The potential V1 and the potential V3 are potentials in the N ⁻ type semiconductor layer 102 in the lower part of the reverse field plate 111b and the forward field plate 111a in the plate electrode 111, respectively. Further, the potential V <b> 2 is the potential of the plate electrode 111 and is substantially the same potential as the P-type semiconductor layer 103.

The capacitor C0 is a capacitor through the second insulating film 115 between the potential Vm and the potential V2. Further, the capacitance between the forward FP 111 a and the N ⁻ type semiconductor layer 102 configured via the first insulating film 114 is a capacitance C 1, and the capacitance between the reverse FP 111 b and the N ⁻ type semiconductor layer 102. Is also a capacity C1. Here, a case is considered in which the forward FP 111a and the reverse FP 111b have the same area, and as a result, the capacities are the same C1.

Next, FIG. 8 shows an equivalent circuit of the capacitor shown in FIG. Here, if the charge amount q1 is accumulated in the capacitor C1 between the potential V1 and the potential V2, and the charge amount q3 is accumulated in the capacitor C1 between the potential V3 and the potential V2, the potential V2 and the potential Vm are The charge amount q1 + q3 is accumulated in the capacitor C0. In this case,
C0 × (V2−Vm) = q1 + q3
C1 * (V1-V2) = q1
C1 × (V3−V2) = q3
Therefore, the potential V2 is
V2 = C0 * Vm / (C0 + 2C1) + C1 * (V1 + V3) / (C0 + 2C1)
Can be expressed as

Here, in order to make the influence of the potential Vm with respect to the potential V2 small and negligible, the size of the capacitor C1 may be sufficiently larger than the capacitor C0. That is, if the relationship of C1 >> C0 is established, the potential V2 is
V2 = (V1 + V3) / 2
Thus, the potential V2 is not affected by the potential Vm. In order to increase the capacity C1, the field plate should be sufficiently large. Thereby, the blocking voltage can be stabilized so as not to be affected by the movable ions in the resin.

  Here, the potential V2 of the plate electrode 111 is substantially the same as the potential of the FLR 105, and the potential of the FLR 105 is a value between the potential V1 and the potential V3. However, the potential of the FLR 105 is not necessarily a half of the sum of the potential V1 and the potential V3.

In order to stabilize the semiconductor device 100, it is desirable to match the potential V2 with the internal potential of the FLR 105. To that end, regarding the capacitance between the forward FP and the N ⁻ type semiconductor layer 102 and the capacitance between the reverse FP and the N ⁻ type semiconductor layer 102, which are all the same C1 in the previous example, Must be individually adjusted (optimized). Further, it is necessary to perform the same adjustment for the plate electrodes 110 and 112. However, this means that the semiconductor device 100, particularly the field plate, requires a fine and strict design and manufacturing accuracy, which can be difficult. Therefore, the solution of such a point is an issue.

  In view of the above, an object of the present invention is to provide a semiconductor device that easily realizes high reliability due to stabilization of the blocking voltage.

  In order to achieve the above object, a semiconductor device according to the present application includes an element region including a semiconductor element and a voltage blocking region surrounding the element region on a first semiconductor layer of a first conductivity type. The element region is provided on the first semiconductor layer so as to continuously surround the element region, and is formed so as to surround the element region along the second semiconductor layer with at least one second semiconductor layer of the second conductivity type. An insulating film comprising: an insulating thin film portion; an insulating thick film portion formed so as to cover both end portions of the second semiconductor layer and the first semiconductor layer so as to sandwich the insulating thin film portion; and the second semiconductor layer And a plate electrode extending to the upper side of the first semiconductor layer via the insulating thick film portion on the element region side and the opposite side thereof.

  According to the semiconductor device of the present invention, the second semiconductor layer provided so as to surround the element region extends to the field limiting ring (FLR) and the insulating thick film portion of the plate electrode provided on the second semiconductor layer. The extended portion functions as a field plate (FP) and exhibits the effect of maintaining the breakdown voltage. Further, the plate electrode provided with the FP that shields the upper charge and stabilizes the blocking voltage is not in contact with the second semiconductor layer (FLR) but is provided via the insulating film (insulating thin film portion). . This eliminates the need for FP optimization as described below.

  In the semiconductor device of the present invention, in addition to the capacitance (capacitance of the FP portion) constituted by the FP and a portion of the first semiconductor layer located below the FP across the insulating thin film portion, A capacitor (bottom capacitor) is formed by a portion of the plate electrode provided on the insulating thin film portion therebetween. Here, if the capacitance at the bottom is sufficiently increased, the influence of the capacitance at the FP portion can be ignored, and the potential of the plate electrode is approximately determined only by the potential of the second semiconductor layer. For this reason, it is not necessary to optimize the FP. Since the insulating film related to the capacitance at the bottom is an insulating thin film portion and is thinner than the insulating thick film portion related to the capacitance at the FP portion, it is easy to make the capacitance at the bottom larger than the capacitance at the FP portion.

  Note that it is preferable that a plurality of second semiconductor layers are provided and spaced apart from each other with the first semiconductor layer interposed therebetween.

  In other words, it is preferable that the element region is surrounded by multiple layers without contacting each other by a plurality of field limiting rings (and therefore without intersecting). Thereby, the electric field can be expanded according to the number of FLRs, and the breakdown voltage can be further improved.

  In addition, a third semiconductor layer of a second conductivity type that continuously surrounds the element region and is surrounded by the second semiconductor layer is provided on the first semiconductor layer, and the insulating film exposes an upper surface of the third semiconductor layer. It is preferable to further include a first electrode provided so as to surround the element region along the third semiconductor layer and to be in contact with the third semiconductor layer.

  Furthermore, it is preferable that the first electrode is formed so as to extend above the first semiconductor layer via the insulating thick film portion on the second semiconductor layer side.

  In addition, the second semiconductor layer is continuously surrounded on the first semiconductor layer, the fourth semiconductor layer having the first conductivity type and the impurity concentration higher than that of the first semiconductor layer is provided, and the insulating film is formed of the fourth semiconductor layer. A second electrode provided to expose the upper surface, surrounding the second semiconductor layer along the fourth semiconductor layer, and formed to contact the fourth semiconductor layer; Is preferred.

  Furthermore, it is preferable that the second electrode is formed so as to extend above the first semiconductor layer via the insulating thick film portion on the second semiconductor layer side.

  The first electrode and the third electrode are used as electrodes for passing a current through the semiconductor device. The fourth semiconductor layer functions as a channel stopper, and the second electrode provided on the fourth semiconductor layer prevents the depletion layer extending from the element region side into the first semiconductor layer from reaching the fourth semiconductor layer. It serves to prevent. A portion of the first electrode and the second electrode that extends on the insulating thick film portion functions as a field plate.

  The capacitance formed between the plate electrode on the insulating thin film portion and the second semiconductor layer is formed between the plate electrode on the insulating thick film portion and the first semiconductor layer. The capacity is preferably ten times or more of the capacity.

  Moreover, it is preferable that the film thickness of an insulating thick film part is ten times or more of the film thickness of an insulating thin film part.

  In this way, the effect that the potential of the plate electrode is determined only by the potential of the second semiconductor layer is more reliably exhibited.

  According to the semiconductor device of the present invention, a plate electrode is provided on the field limiting ring via a thin insulating film, thereby forming a capacitor between the field limiting ring and the plate electrode. As a result, the influence of the capacitance formed between the field plate of the plate electrode and the semiconductor layer below it can be avoided, and as a result, the semiconductor device can be easily blocked without requiring optimization of the field plate. Voltage can be stabilized and reliability can be improved.

  A high voltage semiconductor device having a voltage blocking region including a field limiting ring (FLR) and a field plate (FP) according to an embodiment of the present invention will be described below with reference to the drawings. 1 and 2 are a plan view and a cross-sectional view schematically showing the semiconductor device 50 of the present embodiment.

As shown in FIG. 1, a semiconductor device 50 includes an element region 16 in which a semiconductor element or the like is formed on an N ⁻ type semiconductor layer 2 (see FIG. 2), and the element region 16 includes an IGBT (Insulated Gate). Bipolar Transistor) is formed. A voltage blocking region is provided so as to surround the element region 16. The voltage blocking region includes a first electrode 9, three plate electrodes 10, a plate electrode 11 and a plate electrode 12, and a second electrode 13. Each of these electrodes has a quadrangular planar shape with rounded corners that continuously surround the element region 16 and is arranged so as not to contact each other (and therefore do not cross). That is, the first electrode 9 surrounds the element region 16, the three plate electrodes 10 to 12 are surrounded by three layers on the outer side, and the second electrode 13 is further surrounded on the outer side.

  A cross section taken along line II-II ′ in FIG. 1 is shown in FIG. This is a portion corresponding to the voltage blocking region.

As shown in FIG. 2, the semiconductor device 50 is formed using a P ⁺ type semiconductor substrate 1. In order to reduce the resistance component of the substrate, the impurity concentration of the P ⁺ type semiconductor substrate 1 is preferably set to 10 ¹⁹ cm ⁻³ or more. An N ⁻ type semiconductor layer 2 is provided on the P ⁺ type semiconductor substrate 1. As an example, when the reverse breakdown voltage is about 500 V, the N ⁻ type semiconductor layer 2 has an impurity concentration of about 10 to 20 Ω · cm and a thickness of about 20 to 40 μm.

On the upper surface of the N ⁻ type semiconductor layer 2 (surface opposite to the P ⁺ type semiconductor substrate 1), a P type semiconductor layer 3 continuously surrounding the element region 16 is formed by diffusion of P type impurities. Further, FLR4, FLR5, and FLR6 are formed in order from the P-type semiconductor layer 3 side as three P-type semiconductor layers that surround the P-type semiconductor layer 3 in a triple manner. The P-type semiconductor layer 3 and each of the FLRs 4 to 6 are formed apart from each other with the N− type semiconductor layer 2 interposed therebetween, and P-type diffusion layers formed under the same conditions may be used. For example, the impurity concentration of P-type impurities in the P-type semiconductor layer 3 and each of the FLRs 4 to 6 is 10 ¹⁷ to 10 ¹⁸ cm ⁻³ , the junction depth to the N ⁻ -type semiconductor layer 2 is several μm, The charge neutral region is maintained while avoiding the complete depletion of.

Further, an N ⁺ type semiconductor layer 7 formed by diffusion of N type impurities and functioning as a channel stopper is provided so as to surround the outer side further than the FLR 6. The impurity concentration of the N-type impurity in the N ⁺ -type semiconductor layer 7 is, for example, about 10 ²⁰ cm ⁻³ . The N ⁺ type semiconductor layer 7 is formed away from the FLR 6 with the N ⁻ type semiconductor layer 2 interposed therebetween, and the interval between the N ⁺ type semiconductor layer 7 and the FLR 6 is determined by the P type semiconductor layer 3 and the FLRs 4 to 6. It is formed wider than each interval.

A first insulating film 14 is formed so as to cover the N ⁻ type semiconductor layer 2 and each of the FLRs 4 to 6, and cover part of the ends of the P type semiconductor layer 3 and the N ⁺ type semiconductor layer 7. . The first insulating film 14 includes an insulating thin film portion 14a having a small thickness in the portion on each of the FLRs 4 to 6, and another insulating thick film portion 14b having a large thickness. That is, an opening is provided in the first insulating film 14 on the P-type semiconductor layer 3 and the N ⁺ -type semiconductor layer 7, while each FLR 4-6 is provided in the first insulating film 14 on each FLR 4-6. The insulating thin film portion 14a is formed with a width narrower than the width of. The insulating thin film portion 14a extends continuously on the FLRs 4 to 6 respectively. As a result, the first insulating film 14 is formed on the FLR 4 to 6 with respect to the insulating thick film portion 14b. Since the thickness is small, the grooves are provided on the FLRs 4 to 6, respectively.

A first electrode 9 is formed on the P-type semiconductor layer 3 so as to make a low resistance contact. The first electrode 9 is directly connected to the P-type semiconductor layer 3 in the opening provided in the first insulating film 14, and a part of the first electrode 9 is interposed through the first insulating film 14 (insulating thick film portion 14b). A forward field plate (FP extending outward in the semiconductor device 50), which is a portion extending to above the N ⁻ type semiconductor layer 2, is provided. A second electrode 13 is formed on the N ⁺ type semiconductor layer 7 so as to make a low resistance contact. The second electrode 13 is directly connected to the N-type semiconductor layer 7 in the opening provided in the first insulating film 14, and a part of the second electrode 13 is located above the N ⁻ -type semiconductor layer 2 via the first insulating film 14. A reverse field plate which is a portion extending up to. The first electrode 9 and the second electrode 13 are made of a metal such as Al.

A plate electrode 10, a plate electrode 11, and a plate electrode 12 are formed on the FLR4, FLR5, and FLR6 via a first insulating film 14 (insulating thin film portion 14a), respectively. Each of these plate electrodes 10 to 12 has a forward FP extending to the upper side of the N ⁻ type semiconductor layer 2 through the insulating thick film portion 14b toward the outside of the semiconductor device 50, and the opposite side (on the element region 16 side). ) And an inverted FP extending to above the N ⁻ type semiconductor layer 2 via the insulating thick film portion 14b. Each plate electrode 10-12 is formed of polysilicon, Al or the like. Note that, as a representative, only the plate electrode 11 is given the reference numerals of the forward field plate 11a and the reverse field plate 11b.

Further, a second insulating film 15 is formed so as to cover the first electrode 9, the FLRs 4 to 6, the second electrode 13, and the first insulating film 14. Further, the third electrode 8 is formed on the lower surface of the P ⁺ type semiconductor substrate 1 (surface opposite to the N ⁻ type semiconductor layer 2) so as to be in a low resistance contact. This is formed of a metal such as Al.

  As in the case of the conventional semiconductor device 100 shown in FIGS. 5 and 6, in this embodiment, each FLR 4 to 6 and each plate electrode 10 to 12 maintain a breakdown voltage in the peripheral direction of the semiconductor device 50. Is provided.

  Next, FIG. 3 shows a region including each FLR 4 to 6 in FIG. 2 and each plate electrode 10 to 12 provided thereon. Further, FIG. 3 shows potentials and capacitances related to the FLR 5 and the plate electrode 11 thereabove.

The potential Vm on the second insulating film 15 is such that, for example, in the high-temperature DC reverse bias test, the movable ions in the resin formed further above the second insulating film 15 are the surface potential of the second insulating film 15. Caused by causing polarization. The potential V1 and the potential V3 are the potentials in the N ⁻ type semiconductor layer 2 in the lower part of the reverse FP 11b and the forward FP 11a in the plate electrode 11, respectively, in other words, in the part located inside the FLR 5 and the part located outside This is the potential of the N ⁻ type semiconductor layer 2. The potential Vps is a potential in the plate electrode 11, and the potential V2 is a potential in the FLR 5 that is a P-type semiconductor layer.

Next, the capacitor C0 is a capacitor configured via the second insulating film 15 between the potential Vm and the potential Vps. C1 is a first insulating film 14 (insulating thickness) between the forward FP 11a and the N ⁻ type semiconductor layer 2 in the lower part and between the reverse FP 11b and the N ⁻ type semiconductor layer 2 in the lower part. The capacities are respectively configured via the membrane part 14b). Here, by adjusting the length and the like of the forward FP 11a and the reverse FP 11b, the capacitance C1 has the same value. Further, the capacitor C2 is a capacitor formed between the FLR 5 and the plate electrode 11 via the first insulating film 14 (insulating thin film portion 14a).

  FIG. 4 shows an equivalent circuit of each capacitor shown in FIG. Here, the capacitance C1 between the potential V1 and the potential Vps has a charge amount q1, the capacitance C1 between the potential V3 and the potential Vps has a charge amount q3, and the capacitance C2 between the potential V2 and the potential Vps has a capacitance C2. If the charge amount q2 is accumulated, the charge amount q1 + q2 + q3 is accumulated in the capacitor C0 between the potential Vm and the potential Vps.

In this case,
C0 × (Vps−Vm) = q1 + q2 + q3
C1 × (V1−Vps) = q1
C2 × (V2−Vps) = q2
C1 × (V3−Vps) = q3
Therefore, the potential Vps is
Vps = C0 × Vm / (C0 + 2C1 + C2) + C1 × (V1 + V3) / (C0 + 2C1 + C2) + C2 × V2 / (C0 + 2C1 + C2)
It can be expressed as.

Here, in order to make the influence of the potential Vm on the potential Vps small and negligible, the size of the capacitor C2 may be sufficiently larger than the capacitors C0 and C1. That is, the relationship between the capacitance values C2 >> C0 and C2 >> C1 is established. In this way, for the potential Vps, Vps = V2.
It becomes. That is, when the above relationship is established for the capacitance, the potential Vps is approximately equal to the potential V2. In this case, the potential Vps of the plate electrode 11 is determined only by the potential V2 of the FLR 5, and is not affected by the potential V1 and the potential V3 of the N ⁻ type semiconductor layer 2 in the inner part and the outer part of the FLR 5. Of course, since such conditions are set, Vps in this case is not affected by the potential Vm.

  This stabilizes the blocking voltage and improves the reliability. In addition, since the capacitance C1 related to the forward FP 11a and the reverse FP 11b does not affect the potential Vps at the plate electrode 11, unlike the structure of the prior art, the strict and fine design and manufacturing accuracy for the forward FP 11a and the reverse FP 11b are different. It is never required.

  In order that the capacitance C0 and the capacitance C1 can be ignored as compared with the capacitance C2, it is desirable that the capacitance C2 has a capacitance value more than ten times the capacitance C0 and the capacitance C1.

In addition, although it has been described that the capacities relating to the forward FP 11a and the reverse FP 11b are equal to C1, this is not essential, and Vps = V2 is approximately established even when they are different from each other. In this case, assuming that the capacitance between the forward field 11a and the N ⁻ type semiconductor layer 2 below it is C3, C3 × (V3−Vps) is substituted for the relationship of C1 × (V3−Vps) = q3 described above. = Q3 may be considered.

in this case,
Vps = (C1V1 + C2V2 + C3V3 + C0Vm) / (C0 + C1 + C2 + C3)
Therefore, if the relationship C2 >> C3 is satisfied in addition to the relationship C2 >> C0 and C2 >> C1, Vps = V2 is also approximately satisfied.

As an example, consider the case where the FLR interval is set so that the potential difference between adjacent FLRs is 100 V, and the insulating film of the capacitor C2, that is, the insulating thin film portion 14a of the first insulating film 14, is used as a thermal oxide film. At this time, in order to avoid dielectric breakdown of the insulating thin film portion 14a, since the dielectric breakdown strength of the thermal oxide film is about 8 to 10 × 10 ⁶ V / cm, the film thickness of the insulating thin film portion 14a is at least several tens. nm is required.

  Further, when the insulating film of the capacitor C1, that is, the insulating thick film portion 14b of the first insulating film 14 is also formed as a thermal oxide film, the thickness of the insulating thick film portion 14b is set to satisfy C2 >> C1. It is desirable that the thickness be several hundred nm or more. It is also desirable that the thickness of the insulating thick film portion 14b is ten times or more that of the insulating thin film portion 14a.

  Furthermore, in order to establish C2 >> C0, the thickness of the second insulating film 15 is also set to several hundred nm or more.

Further, the shielding effect can be enhanced by narrowing the distance between the field plates and reducing the area of the N ⁻ type semiconductor layer 2 exposed without being covered with the plate electrodes 10 to 12. In this case, since the area of the field plate is increased and the capacitance values of the capacitors C0 and C1 are increased, it is necessary to design so as to maintain C2 >> C1 and C2 >> C0. Specifically, the thickness of the insulating thick film portion 14b and the thickness of the second insulating film 15 may be further increased to reduce the capacitance values of the capacitors C0 and C1. Further, the capacitance value of the capacitor C2 may be increased by increasing the width of the FLR5.

  In the above description, FLR5 of FLR4, FLR5, and FLR6, which is a field limiting ring provided by three semiconductor devices 50, has been described, but other FLR4 and FLR6 (and formed above each other) The above contents can be applied to the plate electrodes 10 and 12).

  Furthermore, the number of FLRs (and plate electrodes) is not limited to three in the present embodiment. If there is at least one, the function is demonstrated, and the withstand voltage improves as the number increases. In addition, the FLR, the plate electrode, and the like have a rectangular planar shape with rounded corners in the case of this embodiment, but the present invention is not limited to this, and other planar shapes such as a circular shape may be used. good.

As described above, in the semiconductor device 50 according to the present embodiment, the plate electrodes 10 to 12 are provided on the field limiting rings (FLR 4 to 6) via the thin insulating film (insulating thin film portion 14a). As a result, a large capacity is formed between each of the FLRs 4 to 6 and each of the plate electrodes 10 to 12, and in addition to avoiding the influence of potential due to ions or the like in the resin above the second insulating film 15. The influence of the potential on the N ⁻ type semiconductor layer 2 on both sides of the FLRs 4 to 6 can also be avoided. As a result, it is possible to realize a high breakdown voltage semiconductor device in which the blocking voltage is stabilized and the reliability is improved. At this time, since the field plate does not require strict and fine design and manufacturing accuracy, the semiconductor device 50 of this embodiment can be easily realized.

  The semiconductor device of the present invention has a high blocking voltage and high reliability, and is useful as a high breakdown voltage semiconductor device having a field limiting ring and a field plate.

FIG. 1 is a plan view illustrating a main part of a semiconductor device including a field limiting ring and a field plate according to an embodiment of the present invention. FIG. 2 is a diagram showing a cross-sectional configuration taken along the line II-II ′ of FIG. 1 for the semiconductor device according to one embodiment of the present invention. FIG. 3 is a diagram showing capacitance and potential with respect to one field limiting ring and a plate electrode above the semiconductor device according to an embodiment of the present invention. FIG. 4 is an equivalent circuit diagram corresponding to the capacitance and potential in FIG. FIG. 5 is a plan view for explaining a main part of a semiconductor device provided with a field limiting ring and a field plate according to the prior art. FIG. 6 is a diagram showing a cross-sectional configuration taken along line VI-VI ′ of FIG. FIG. 7 is a diagram showing a capacitance and a potential with respect to one field limiting ring and a plate electrode thereabove for a semiconductor device according to the prior art. FIG. 8 is an equivalent circuit diagram corresponding to the capacitance and potential in FIG.

Explanation of symbols

1 type semiconductor substrate 2 N-type semiconductor layer 3 P type semiconductor layer 4, 5, 6 Field limiting ring (FLR)
7 type semiconductor layer 8 3rd electrode 9 1st electrode 10, 11, 12 Plate electrode 11a Forward field plate (FP)
11b Reverse field plate (FP)
13 Second electrode 14 First insulating film 14a Insulating thin film portion 14b Insulating thick film portion 15 Second insulating film 16 Element region 50 Semiconductor device

Claims (9)

An element region including a semiconductor element and a voltage blocking region surrounding the element region on the first semiconductor layer of the first conductivity type;
The voltage blocking region is
At least one second semiconductor layer of a second conductivity type provided to continuously surround the element region on the first semiconductor layer;
An insulating thin film portion formed so as to surround the element region along the second semiconductor layer, and both end portions of the second semiconductor layer and the first semiconductor layer are covered so as to sandwich the insulating thin film portion. An insulating film including an insulating thick film portion formed as described above,
A plate electrode formed on the second semiconductor layer via the insulating thin film portion and extending to the upper side of the first semiconductor layer via the insulating thick film portion on the element region side and the opposite side thereof; A semiconductor device. The semiconductor device according to claim 1.
A semiconductor device comprising a plurality of the second semiconductor layers and being spaced apart from each other with the first semiconductor layer interposed therebetween. The semiconductor device according to claim 1 or 2,
A third semiconductor layer of a second conductivity type that continuously surrounds the element region and is surrounded by the second semiconductor layer on the first semiconductor layer;
The insulating film is provided to expose an upper surface of the third semiconductor layer;
A semiconductor device, further comprising a first electrode provided so as to surround the element region along the third semiconductor layer, and formed so as to be in contact with the third semiconductor layer. The semiconductor device according to claim 3.
The semiconductor device according to claim 1, wherein the first electrode is formed on the second semiconductor layer side so as to extend above the first semiconductor layer via the insulating thick film portion. The semiconductor device according to claim 1,
A fourth semiconductor layer that continuously surrounds the second semiconductor layer on the first semiconductor layer, has a first conductivity type, and has a higher impurity concentration than the first semiconductor layer;
The insulating film is provided to expose an upper surface of the fourth semiconductor layer;
And a second electrode provided so as to surround the second semiconductor layer along the fourth semiconductor layer and in contact with the fourth semiconductor layer. . The semiconductor device according to claim 5.
The semiconductor device, wherein the second electrode is formed so as to extend above the first semiconductor layer through the insulating thick film portion on the second semiconductor layer side. The semiconductor device according to any one of claims 1 to 6,
The first semiconductor layer is formed on a second conductivity type substrate;
3. A semiconductor device, wherein a third electrode is formed on a surface of the substrate opposite to the first semiconductor layer. The semiconductor device according to any one of claims 1 to 7,
The capacitance formed between the plate electrode on the insulating thin film portion and the second semiconductor layer is between the plate electrode on the insulating thick film portion and the first semiconductor layer. A semiconductor device characterized in that the capacity is 10 times or more of the capacity configured in the above. The semiconductor device according to any one of claims 1 to 8,
The semiconductor device is characterized in that the thickness of the insulating thick film portion is ten times or more than the thickness of the insulating thin film portion.

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