JP2010040880A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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JP2010040880A
JP2010040880A JP2008203638A JP2008203638A JP2010040880A JP 2010040880 A JP2010040880 A JP 2010040880A JP 2008203638 A JP2008203638 A JP 2008203638A JP 2008203638 A JP2008203638 A JP 2008203638A JP 2010040880 A JP2010040880 A JP 2010040880A
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semiconductor device
marking
built
relay substrate
semiconductor chip
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JP4995156B2 (en
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Masanori Onodera
正徳 小野寺
Koji Inoue
広司 井上
Masahiko Harayama
雅彦 原山
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Spansion LLC
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01Chemical elements
    • H01L2924/01079Gold [Au]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/1515Shape
    • H01L2924/15153Shape the die mounting substrate comprising a recess for hosting the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191Disposition
    • H01L2924/19101Disposition of discrete passive components
    • H01L2924/19107Disposition of discrete passive components off-chip wires

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device easily discriminating an imprinting put on a built-in semiconductor device, and obtaining an imprinting information. <P>SOLUTION: The semiconductor device has: a first semiconductor chip 12 loaded on the top face of a first relay substrate 10; a first resin section 14 formed on the top face of the first relay substrate 10 and sealing the first semiconductor chip 12; the built-in semiconductor device 30 formed to the top face of the first resin section 14 and electrically connected to the first relay substrate 10; a second resin section 34 formed on the top face of the first relay substrate 10 and sealing the first resin section 14 and the built-in semiconductor device 30; a first imprinting section 50 being formed to the built-in semiconductor device 30 and indicating an information for discriminating the built-in semiconductor device 30; and a second imprinting section 52 being formed to the second resin section 34 and indicating the information for discriminating either one of the semiconductor device 100 and the first semiconductor chip 12. The first imprinting section 50 and the second imprinting section 52 are arranged not to overlap, seen from the upper section of the second resin section 34. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

本発明は、半導体装置に関し、特に、半導体チップと内蔵半導体装置とを積層した半導体装置に関する。   The present invention relates to a semiconductor device, and more particularly to a semiconductor device in which a semiconductor chip and a built-in semiconductor device are stacked.

半導体装置の高密度実装化を目的としたパッケージ形態の1つとして、複数の半導体チップを積層して搭載したマルチ・チップ・パッケージ(以下、MCP)と呼ばれる技術がある。このMCPは、携帯電話やデジタルスチルカメラなど、小型の携帯型電子機器において広く使用されている。   As one of package forms aimed at high-density mounting of semiconductor devices, there is a technique called a multi-chip package (hereinafter referred to as MCP) in which a plurality of semiconductor chips are stacked and mounted. This MCP is widely used in small portable electronic devices such as mobile phones and digital still cameras.

MCPの歩留まりは、内蔵している半導体チップの歩留まりに大きく依存する。このため、歩留まりが特に低い半導体チップを使用する場合や内蔵する半導体チップの数が多い場合等は、MCPの製造歩留まりが顕著に低下するという課題が生じている。   The yield of MCP greatly depends on the yield of built-in semiconductor chips. For this reason, when a semiconductor chip with a particularly low yield is used or when the number of built-in semiconductor chips is large, there is a problem that the manufacturing yield of the MCP is significantly reduced.

この課題を解決するために開発された技術が、半導体チップの代わりに、半導体チップを搭載した半導体装置を内蔵(以下、内蔵半導体装置)させる技術である。   A technique developed to solve this problem is a technique for incorporating a semiconductor device on which a semiconductor chip is mounted instead of a semiconductor chip (hereinafter referred to as a built-in semiconductor device).

内蔵半導体装置は、予め良否確認の試験を行うことが可能であり、内蔵半導体装置を積層させる際に、良品の内蔵半導体装置を選別して積層することができるため、半導体装置全体の製造歩留まりの向上を図ることができる。   The built-in semiconductor device can be tested in advance to confirm pass / fail, and when stacking the built-in semiconductor device, it is possible to select and stack non-defective built-in semiconductor devices, so that the manufacturing yield of the entire semiconductor device can be improved. Improvements can be made.

また、一般的に半導体装置には、市場や製造現場において何らかの不具合が発生した場合のトレース(製造履歴の追跡調査)を容易にするため、製造者(会社)名、ロット番号、製造場所、製造日等の情報を示す捺印が付されている。   In addition, in general, in order to facilitate tracing (manufacturing history tracking survey) in the case of a failure in the market or manufacturing site, the manufacturer (company) name, lot number, manufacturing location, manufacturing A stamp indicating information such as date is attached.

例えば、特許文献1には、モールド材の内部に実装した内蔵電子部品に付された捺印を外部から認識する技術について開示されている。例えば、特許文献2には、半導体チップを樹脂封止したパッケージにおいて、半導体チップとパッケージとの両方に捺印を付すことが開示されている。
特開2005−123246号公報 特開平11−8328号公報
For example, Patent Document 1 discloses a technique for recognizing a seal attached to a built-in electronic component mounted inside a mold material from the outside. For example, Patent Document 2 discloses that in a package in which a semiconductor chip is sealed with a resin, both the semiconductor chip and the package are marked.
JP 2005-123246 A Japanese Patent Laid-Open No. 11-8328

半導体チップと内蔵半導体装置とを積層してパッケージングした半導体装置において、前述した捺印は、内蔵半導体装置と半導体装置との両方に付される。このため、内蔵半導体装置に付された捺印と半導体装置に付された捺印とが、半導体装置の上方から見て重なっている場合は、内蔵半導体装置に付された捺印を判別することが難しくなり、捺印情報を得ることができないという課題が生じている。   In a semiconductor device in which a semiconductor chip and a built-in semiconductor device are stacked and packaged, the above-described marking is given to both the built-in semiconductor device and the semiconductor device. For this reason, when the seal attached to the built-in semiconductor device and the seal attached to the semiconductor device overlap when viewed from above the semiconductor device, it becomes difficult to determine the seal attached to the built-in semiconductor device. However, there is a problem that the stamp information cannot be obtained.

本発明は、上記課題に鑑みなされたものであり、内蔵半導体装置に付された捺印を容易に判別することができ、捺印情報を得ることが可能な半導体装置を提供することを目的とする。   The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of easily discriminating a stamp attached to a built-in semiconductor device and obtaining stamp information.

本発明は、第1中継基板の上面に搭載された第1半導体チップと、前記第1中継基板の上面に設けられ、前記第1半導体チップを封止する第1樹脂部と、前記第1樹脂部の上面に設けられ、前記第1中継基板に電気的に接続する内蔵半導体装置と、前記第1中継基板の上面に設けられ、前記第1樹脂部と前記内蔵半導体装置とを封止する第2樹脂部と、前記内蔵半導体装置に設けられ、前記内蔵半導体装置を識別するための情報を示す第1捺印部と、前記第2樹脂部に設けられ、半導体装置及び前記第1半導体チップのいずれか一方を識別するための情報を示す第2捺印部と、を具備し、前記第1捺印部と前記第2捺印部とは、前記第2樹脂部の上方から見て重ならないように配置されていることを特徴とする半導体装置である。本発明によれば、内蔵半導体装置に設けられた第1捺印部を容易に判別することができ、第1捺印部の捺印情報を得ることができる。   The present invention provides a first semiconductor chip mounted on an upper surface of a first relay substrate, a first resin portion provided on the upper surface of the first relay substrate and sealing the first semiconductor chip, and the first resin. A built-in semiconductor device that is provided on the top surface of the portion and electrically connected to the first relay substrate; and a first semiconductor device that is provided on the top surface of the first relay substrate and seals the first resin portion and the built-in semiconductor device. 2 resin portions, a first marking portion provided in the built-in semiconductor device and indicating information for identifying the built-in semiconductor device, and any one of the semiconductor device and the first semiconductor chip provided in the second resin portion A second marking portion indicating information for identifying one of them, and the first marking portion and the second marking portion are arranged so as not to overlap each other when viewed from above the second resin portion. It is a semiconductor device characterized by the above. According to the present invention, it is possible to easily determine the first stamped portion provided in the built-in semiconductor device, and to obtain the stamping information of the first stamped portion.

上記構成において、前記第1樹脂部に設けられ、前記第1半導体チップを識別するための情報を示す第3捺印部を具備し、前記第3捺印部は、前記第2樹脂部の上方から見て、前記第1捺印部と前記第2捺印部とに重ならないように配置されている構成とすることができる。この構成によれば、第1樹脂部に設けられた第3捺印部を容易に判別することができ、第3捺印部の捺印情報を得ることができる。   In the above configuration, a third marking portion is provided in the first resin portion and indicates information for identifying the first semiconductor chip, and the third marking portion is viewed from above the second resin portion. Thus, the first marking portion and the second marking portion may be arranged so as not to overlap each other. According to this configuration, the third marking portion provided in the first resin portion can be easily discriminated, and the marking information of the third marking portion can be obtained.

上記構成において、前記第1捺印部は、インク捺印により形成されている構成とすることができる。この構成によれば、第1捺印部の捺印文字を鮮明にすることができる。   The said structure WHEREIN: The said 1st marking part can be set as the structure currently formed by the ink marking. According to this configuration, it is possible to make the marking character of the first marking portion clear.

上記構成において、前記第3捺印部は、インク捺印により形成されている構成とすることができる。この構成によれば、第3捺印部の捺印文字を鮮明にすることができる。   The said structure WHEREIN: The said 3rd marking part can be set as the structure currently formed by the ink marking. According to this configuration, it is possible to make the marking character of the third marking portion clear.

上記構成において、前記インク捺印は、金属粉末を含有するインクを用いている構成とすることができる。この構成によれば、X線により捺印情報を得ることができる。   The said structure WHEREIN: The said ink seal | sticker can be set as the structure which uses the ink containing a metal powder. According to this configuration, the stamp information can be obtained by X-rays.

上記構成において、前記内蔵半導体装置は、第2中継基板の上面に搭載された第2半導体チップと、前記第2中継基板の上面に設けられ、前記第2半導体チップを封止する第3樹脂部と、からなり、前記内蔵半導体装置は、前記第3樹脂部が前記第1樹脂部に接合することで、前記第1樹脂部の上面に設けられていて、前記第1捺印部は、前記第2半導体チップが搭載された面と反対側の前記第2中継基板の面に設けられている構成とすることができる。   In the above configuration, the built-in semiconductor device includes a second semiconductor chip mounted on the upper surface of the second relay substrate, and a third resin portion provided on the upper surface of the second relay substrate and sealing the second semiconductor chip. The built-in semiconductor device is provided on the upper surface of the first resin portion by bonding the third resin portion to the first resin portion, and the first marking portion is 2 It can be configured to be provided on the surface of the second relay substrate opposite to the surface on which the semiconductor chip is mounted.

上記構成において、前記内蔵半導体装置は、第2中継基板の上面に搭載された第2半導体チップと、前記第2中継基板の上面に設けられ、前記第2半導体チップを封止する第3樹脂部と、からなり、前記内蔵半導体装置は、前記第2中継基板が前記第1樹脂部に接合することで、前記第1樹脂部の上面に設けられていて、前記第1捺印部は、前記第3樹脂部の上面に設けられている構成とすることができる。   In the above configuration, the built-in semiconductor device includes a second semiconductor chip mounted on the upper surface of the second relay substrate, and a third resin portion provided on the upper surface of the second relay substrate and sealing the second semiconductor chip. The built-in semiconductor device is provided on the upper surface of the first resin portion by bonding the second relay substrate to the first resin portion, and the first marking portion is It can be set as the structure provided in the upper surface of 3 resin parts.

上記構成において、前記第1中継基板に凹部が設けられていて、前記第1半導体チップは、前記凹部に搭載されている構成とすることができる。   The said structure WHEREIN: The recessed part is provided in the said 1st relay substrate, The said 1st semiconductor chip can be set as the structure mounted in the said recessed part.

本発明によれば、内蔵半導体装置に設けられた第1捺印部を容易に判別することができ、第1捺印部の捺印情報を得ることができる。   According to the present invention, it is possible to easily determine the first stamped portion provided in the built-in semiconductor device, and to obtain the stamping information of the first stamped portion.

まず初めに、課題を明確にするため、図1の模式的断面図を用いて、比較例1に係る半導体装置について説明する。図1を参照に、比較例1に係る半導体装置100は、第1半導体チップ12と内蔵半導体装置30とが積層してパッケージングされた構造をしている。   First, in order to clarify the problem, a semiconductor device according to Comparative Example 1 will be described with reference to the schematic cross-sectional view of FIG. Referring to FIG. 1, a semiconductor device 100 according to Comparative Example 1 has a structure in which a first semiconductor chip 12 and a built-in semiconductor device 30 are stacked and packaged.

第1半導体チップ12は、第1中継基板10の上面に、接着剤16を介して搭載されている。第1中継基板10は、例えばガラスエポキシ等の絶縁体からなり、厚さは例えば約200μmである。第1半導体チップ12の上面には回路が形成されており、第1半導体チップ12と第1中継基板10のランド電極17とは、ボンディングワイヤ18により電気的に接続されている。第1中継基板10の上面には、第1半導体チップ12を封止する第1樹脂部14が形成されている。第1樹脂部14は、例えば熱硬化性エポキシ樹脂からなる。   The first semiconductor chip 12 is mounted on the upper surface of the first relay substrate 10 via an adhesive 16. The first relay substrate 10 is made of an insulator such as glass epoxy, and has a thickness of about 200 μm, for example. A circuit is formed on the upper surface of the first semiconductor chip 12, and the first semiconductor chip 12 and the land electrode 17 of the first relay substrate 10 are electrically connected by a bonding wire 18. A first resin portion 14 for sealing the first semiconductor chip 12 is formed on the upper surface of the first relay substrate 10. The first resin portion 14 is made of, for example, a thermosetting epoxy resin.

内蔵半導体装置30は、第2中継基板20と第2半導体チップ22と第3樹脂部24とを有している。第2中継基板20は、例えばガラスエポキシ等の絶縁体からなる。第2半導体チップ22は、第2中継基板20の上面に接着剤26を介して搭載されている。第2半導体チップ22の上面には回路が形成されており、第2半導体チップ22と第2中継基板20のランド電極27とは、ボンディングワイヤ28により電気的に接続されている。第2中継基板20の上面には、第2半導体チップ22を封止する第3樹脂部24が形成されている。第3樹脂部24は、例えば熱硬化性エポキシ樹脂からなる。   The built-in semiconductor device 30 includes a second relay substrate 20, a second semiconductor chip 22, and a third resin portion 24. The second relay substrate 20 is made of an insulator such as glass epoxy. The second semiconductor chip 22 is mounted on the upper surface of the second relay substrate 20 via an adhesive 26. A circuit is formed on the upper surface of the second semiconductor chip 22, and the second semiconductor chip 22 and the land electrode 27 of the second relay substrate 20 are electrically connected by a bonding wire 28. A third resin portion 24 that seals the second semiconductor chip 22 is formed on the upper surface of the second relay substrate 20. The third resin portion 24 is made of, for example, a thermosetting epoxy resin.

内蔵半導体装置30は、第3樹脂部24と第1樹脂部14とが、接着剤32を介して接合することで、第1樹脂部14の上面に設けられている。したがって、図1において、前述した第2中継基板20の上面と第2半導体チップ22の上面とは、第1樹脂部14側を向いた面のことを指す。第2中継基板20の下面(第2半導体チップ22が搭載された面と反対側の面)には、パッド電極36を含む配線が設けられていて、ランド電極27とパッド電極36とは、貫通接続部(不図示)により電気的に接続している。内蔵半導体装置30は、第2中継基板20下面のパッド電極36と第1中継基板10上面のランド電極17とを、ボンディングワイヤ38で接続することで、第1中継基板10に電気的に接続されている。   The built-in semiconductor device 30 is provided on the upper surface of the first resin portion 14 by bonding the third resin portion 24 and the first resin portion 14 via an adhesive 32. Therefore, in FIG. 1, the upper surface of the second relay substrate 20 and the upper surface of the second semiconductor chip 22 described above are surfaces facing the first resin portion 14 side. A wiring including a pad electrode 36 is provided on the lower surface of the second relay substrate 20 (the surface opposite to the surface on which the second semiconductor chip 22 is mounted), and the land electrode 27 and the pad electrode 36 pass through. It is electrically connected by a connection part (not shown). The built-in semiconductor device 30 is electrically connected to the first relay substrate 10 by connecting the pad electrode 36 on the lower surface of the second relay substrate 20 and the land electrode 17 on the upper surface of the first relay substrate 10 with bonding wires 38. ing.

第1中継基板10の上面には、第1樹脂部14と内蔵半導体装置30とを封止する第2樹脂部34が設けられている。第2樹脂部34は、例えば熱硬化性エポキシ樹脂からなる。   A second resin portion 34 that seals the first resin portion 14 and the built-in semiconductor device 30 is provided on the upper surface of the first relay substrate 10. The second resin portion 34 is made of, for example, a thermosetting epoxy resin.

第1中継基板10の下面(第1半導体チップ12が搭載された面と反対側の面)には、パッド電極46が設けられている。パッド電極46は、貫通接続部44を介してランド電極17に電気的に接続されている。パッド電極46には半田ボール42が設けられている。   A pad electrode 46 is provided on the lower surface of the first relay substrate 10 (the surface opposite to the surface on which the first semiconductor chip 12 is mounted). The pad electrode 46 is electrically connected to the land electrode 17 through the through connection portion 44. A solder ball 42 is provided on the pad electrode 46.

内蔵半導体装置30の、第1樹脂部14に対して反対側に相当する面に、内蔵半導体装置30を識別するための情報、例えば、製造社(会社)名、ロット番号、製造場所、製造日等が捺印されている。内蔵半導体装置30に付された捺印を第1捺印部50とする。よって、比較例1において、第2中継基板20の下面(第2半導体チップ22が搭載された面と反対側の面)に、第1捺印部50が設けられている。また、第2樹脂部34の上面には、例えば、半導体装置100を識別するための情報(製造社(会社)名、ロット番号、製造場所、製造日等)が捺印されている。第2樹脂部34の上面に付された捺印を第2捺印部52とする。第1捺印部50と第2捺印部52とは、第2樹脂部34の上方からみて重なって配置されている。   Information for identifying the built-in semiconductor device 30 on the surface corresponding to the side opposite to the first resin portion 14 of the built-in semiconductor device 30, for example, the manufacturer (company) name, lot number, production location, and production date Etc. are imprinted. The stamp attached to the built-in semiconductor device 30 is referred to as a first stamp unit 50. Therefore, in Comparative Example 1, the first marking part 50 is provided on the lower surface of the second relay substrate 20 (the surface opposite to the surface on which the second semiconductor chip 22 is mounted). In addition, for example, information (manufacturer (company) name, lot number, manufacturing location, date of manufacture, etc.) for identifying the semiconductor device 100 is stamped on the upper surface of the second resin portion 34. The marking applied on the upper surface of the second resin portion 34 is referred to as a second marking portion 52. The first marking part 50 and the second marking part 52 are arranged so as to overlap each other when viewed from above the second resin part 34.

内蔵半導体装置30は第2樹脂部34で封止されているため、第1捺印部50を直接視認することはできない。そのため、例えば超音波探傷装置を用いて、第1捺印部50の捺印情報の確認を行う。しかしながら、比較例1の半導体装置100のように、第1捺印部50と第2捺印部52とが、第2樹脂部34の上方からみて重なって配置されている場合は、第1捺印部50の捺印文字が、第2捺印部52の捺印文字と重なるため、第1捺印部50の判別が難しくなり、結果として、第1捺印部50の捺印情報の確認を行うことができない。   Since the built-in semiconductor device 30 is sealed with the second resin portion 34, the first marking portion 50 cannot be directly visually recognized. Therefore, for example, using the ultrasonic flaw detector, the marking information of the first marking unit 50 is confirmed. However, when the first marking part 50 and the second marking part 52 are overlapped as viewed from above the second resin part 34 as in the semiconductor device 100 of the comparative example 1, the first marking part 50 Since the stamped character overlaps with the stamped character of the second stamped part 52, it becomes difficult to distinguish the first stamped part 50, and as a result, the stamped information of the first stamped part 50 cannot be confirmed.

図2は、比較例2に係る半導体装置の模式的断面図である。図2を参照に、内蔵半導体装置30は、第2中継基板20下面のパッド電極36と第1中継基板10上面のランド電極17とを、半田端子48で接続することで、第1中継基板10に電気的に接続している。したがって、比較例2においては、第2中継基板20の上面と第2半導体チップ22の上面とは、第1樹脂部14に対して反対側を向いた面を指す。第1樹脂部14は、第1半導体チップ12と半田端子48とを封止している。その他の構成については、比較例1と同じであり、図1に示しているので説明を省略する。   FIG. 2 is a schematic cross-sectional view of a semiconductor device according to Comparative Example 2. Referring to FIG. 2, the built-in semiconductor device 30 connects the pad electrode 36 on the lower surface of the second relay substrate 20 and the land electrode 17 on the upper surface of the first relay substrate 10 with a solder terminal 48, thereby Is electrically connected. Therefore, in Comparative Example 2, the upper surface of the second relay substrate 20 and the upper surface of the second semiconductor chip 22 indicate surfaces facing the opposite side with respect to the first resin portion 14. The first resin portion 14 seals the first semiconductor chip 12 and the solder terminal 48. Other configurations are the same as those in the first comparative example and are shown in FIG.

図2のような、比較例2の半導体装置100においても、第1捺印部50と第2捺印部52とは、第2樹脂部34の上方からみて重なって配置されている。したがって、第1捺印部50の判別が難しくなり、第1捺印部50の捺印情報の確認を行うことができない。   Also in the semiconductor device 100 of the comparative example 2 as shown in FIG. 2, the first marking part 50 and the second marking part 52 are arranged so as to overlap each other when viewed from above the second resin part 34. Accordingly, it becomes difficult to determine the first marking unit 50, and the marking information of the first marking unit 50 cannot be confirmed.

図3は、比較例3に係る半導体装置の模式的断面図である。図3を参照に、第1中継基板10に、凹部40が設けられている。凹部40の深さは、例えば第1中継基板10の厚さの1/2以上である場合が好ましい。凹部40の面積は第1半導体チップ12の面積よりやや大きく、第1半導体チップ12は、凹部40に搭載されている。その他の構成については、比較例2と同じであり、図2に示しているので説明を省略する。   FIG. 3 is a schematic cross-sectional view of a semiconductor device according to Comparative Example 3. With reference to FIG. 3, a recess 40 is provided in the first relay substrate 10. The depth of the recess 40 is preferably, for example, not less than ½ of the thickness of the first relay substrate 10. The area of the recess 40 is slightly larger than the area of the first semiconductor chip 12, and the first semiconductor chip 12 is mounted in the recess 40. The other configuration is the same as that of the comparative example 2 and is shown in FIG.

図3のような、比較例3の半導体装置100においても、第1捺印部50と第2捺印部52とは、第2樹脂部34の上方からみて重なって配置されている。したがって、第1捺印部50の判別が難しくなり、第1捺印部50の捺印情報を確認することができない。   Also in the semiconductor device 100 of the comparative example 3 as shown in FIG. 3, the first marking part 50 and the second marking part 52 are arranged so as to overlap each other when viewed from above the second resin part 34. Therefore, it becomes difficult to distinguish the first marking part 50, and the marking information of the first marking part 50 cannot be confirmed.

そこで、上記課題の解決を図り、内蔵半導体装置30に付された第1捺印部50を容易に判別することができ、第1捺印部50の捺印情報を確認することが可能な実施例を以下に示す。   Accordingly, an embodiment in which the above-described problems can be solved, the first marking unit 50 attached to the built-in semiconductor device 30 can be easily identified, and the marking information of the first marking unit 50 can be confirmed is as follows. Shown in

図4(a)は、実施例1に係る半導体装置の模式的断面図であり、図4(b)は、模式的上面図である。図4(a)及び図4(b)を参照に、内蔵半導体装置30に付された第1捺印部50と、第2樹脂部34の上面に付された第2捺印部52とが、第2樹脂部34の上方からみて重ならないように配置されている。第1捺印部50は、内臓半導体装置30を識別するための情報を示し、第2捺印部52は、例えば半導体装置100を識別するための情報を示す。その他の構成については、比較例1と同じであり、図1に示しているので説明を省略する。   FIG. 4A is a schematic cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 4B is a schematic top view. Referring to FIGS. 4A and 4B, the first marking portion 50 attached to the built-in semiconductor device 30 and the second marking portion 52 attached to the upper surface of the second resin portion 34 are The two resin portions 34 are arranged so as not to overlap when viewed from above. The first marking unit 50 indicates information for identifying the built-in semiconductor device 30, and the second marking unit 52 indicates information for identifying the semiconductor device 100, for example. Other configurations are the same as those in the first comparative example and are shown in FIG.

次に、図5(a)から図5(c)の模式的断面図を用いて、実施例1に係る半導体装置の製造方法を説明する。図5(a)を参照に、接着剤16を用い、第1中継基板10の上面に第1半導体チップ12を搭載する。この状態で、第1中継基板10の上面に形成された第1半導体チップ12の良否確認の試験を行う。その後、良品と確認された第1半導体チップ12とランド電極17とをボンディングワイヤ18を用いて接続する。更に、樹脂封止を行い、第1中継基板10の上面に、第1樹脂部14を形成する。   Next, a method for manufacturing the semiconductor device according to the first embodiment will be described with reference to schematic cross-sectional views of FIGS. Referring to FIG. 5A, the first semiconductor chip 12 is mounted on the upper surface of the first relay substrate 10 using an adhesive 16. In this state, a test for checking the quality of the first semiconductor chip 12 formed on the upper surface of the first relay substrate 10 is performed. Thereafter, the first semiconductor chip 12 confirmed to be non-defective and the land electrode 17 are connected using the bonding wire 18. Further, resin sealing is performed, and the first resin portion 14 is formed on the upper surface of the first relay substrate 10.

図5(b)を参照に、接着剤32を用いて、第1樹脂部14の上面に内蔵半導体装置30を搭載する。ここで、内蔵半導体装置30は、事前に良否確認の試験を実施しており、良品と確認された内蔵半導体装置30を搭載する。また、搭載する内蔵半導体装置30の第2中継基板20の下面には、予め第1捺印部50が形成されている。第1捺印部50は、例えば、Au(金)、Ag(銀)、Cu(銅)等の金属粉末をインクの中に含有させ、この金属粉末を含有したインクを、第2中継基板20の下面に印刷することで形成することができる。   With reference to FIG. 5B, the built-in semiconductor device 30 is mounted on the upper surface of the first resin portion 14 using the adhesive 32. Here, the built-in semiconductor device 30 is subjected to a test for confirming whether it is good or bad in advance, and the built-in semiconductor device 30 that has been confirmed as good is mounted. In addition, a first marking part 50 is formed in advance on the lower surface of the second relay substrate 20 of the built-in semiconductor device 30 to be mounted. The first marking unit 50 contains, for example, a metal powder such as Au (gold), Ag (silver), or Cu (copper) in the ink, and the ink containing the metal powder is added to the second relay substrate 20. It can be formed by printing on the lower surface.

図5(c)を参照に、第1中継基板10の上面に、第1樹脂部14と内蔵半導体装置30とを封止する第2樹脂部34を形成する。第2樹脂部34の上面に、第2捺印部52を形成する。第2捺印部52の形成方法は、例えば、第1捺印部50と同じ方法を用いることができる。その後、第1中継基板10のパッド電極46に半田ボール42を形成して、実施例1に係る半導体装置が完成する。   With reference to FIG. 5C, a second resin portion 34 that seals the first resin portion 14 and the built-in semiconductor device 30 is formed on the upper surface of the first relay substrate 10. A second marking part 52 is formed on the upper surface of the second resin part 34. For example, the same method as that for the first marking portion 50 can be used as the method for forming the second marking portion 52. Thereafter, solder balls 42 are formed on the pad electrodes 46 of the first relay substrate 10 to complete the semiconductor device according to the first embodiment.

実施例1に係る半導体装置100は、図4(a)および図4(b)のように、第1中継基板10の上面に搭載され、第1樹脂部14により封止された第1半導体チップ12と、第1樹脂部14の上面に搭載された内蔵半導体装置30と、第1樹脂部14及び内蔵半導体装置30を封止する第2樹脂部34と、を有している。内蔵半導体装置30の第1樹脂部14に対して反対側の面に、内蔵半導体装置30を識別するための情報を示す第1捺印部50が形成されている。第2樹脂部34の上面には、半導体装置100を識別するための情報を示す第2捺印部52が形成されている。そして、第1捺印部50と第2捺印部52とは、第2樹脂部34の上方からみて重ならないように配置されている。   As shown in FIGS. 4A and 4B, the semiconductor device 100 according to the first embodiment is mounted on the upper surface of the first relay substrate 10 and sealed by the first resin portion 14. 12, a built-in semiconductor device 30 mounted on the upper surface of the first resin portion 14, and a second resin portion 34 that seals the first resin portion 14 and the built-in semiconductor device 30. A first marking portion 50 indicating information for identifying the built-in semiconductor device 30 is formed on the surface of the built-in semiconductor device 30 opposite to the first resin portion 14. On the upper surface of the second resin portion 34, a second marking portion 52 indicating information for identifying the semiconductor device 100 is formed. The first marking part 50 and the second marking part 52 are arranged so as not to overlap when viewed from above the second resin part 34.

内蔵半導体装置30は、第2樹脂部34で封止されているため、第1捺印部50を直接視認することはできない。そこで、超音波探傷装置等を用いて、第1捺印部50の捺印情報の確認を行う。この際、比較例1の図1のように、第1捺印部50と第2捺印部52とが重なって配置されている場合は、第1捺印部50を判別することができない。しかしながら、実施例1によれば、図4(a)および図4(b)のように、第1捺印部50と第2捺印部52とは重ならないように配置されているため、第1捺印部50を容易に判別することができ、第1捺印部50の捺印情報の確認を行うことができる。よって、実施例1によれば、内蔵半導体装置30と半導体装置100とについての識別情報を得ることができる。   Since the built-in semiconductor device 30 is sealed with the second resin portion 34, the first marking portion 50 cannot be directly visually recognized. Therefore, the marking information of the first marking unit 50 is confirmed using an ultrasonic flaw detector or the like. At this time, as shown in FIG. 1 of the first comparative example, when the first marking portion 50 and the second marking portion 52 are arranged to overlap each other, the first marking portion 50 cannot be determined. However, according to the first embodiment, as shown in FIG. 4A and FIG. 4B, the first marking portion 50 and the second marking portion 52 are arranged so as not to overlap with each other. The part 50 can be easily identified, and the marking information of the first marking part 50 can be confirmed. Therefore, according to the first embodiment, identification information about the built-in semiconductor device 30 and the semiconductor device 100 can be obtained.

図4(a)のように、内蔵半導体装置30は、第2中継基板20と、第2中継基板20の上面に搭載された第2半導体チップ22と、第2中継基板20の上面に設けられ、第2半導体チップ22を封止する第3樹脂部24と、を有する。内蔵半導体装置30の第1捺印部50は、第2中継基板20の下面(第2半導体チップ22が搭載された面と反対側の面)に形成されている。図5(b)で説明したように、第1捺印部50の捺印情報(捺印文字)は、インク捺印により形成されている。   As shown in FIG. 4A, the built-in semiconductor device 30 is provided on the second relay substrate 20, the second semiconductor chip 22 mounted on the upper surface of the second relay substrate 20, and the upper surface of the second relay substrate 20. And a third resin portion 24 for sealing the second semiconductor chip 22. The first marking part 50 of the built-in semiconductor device 30 is formed on the lower surface of the second relay substrate 20 (the surface opposite to the surface on which the second semiconductor chip 22 is mounted). As described with reference to FIG. 5B, the stamp information (marked characters) of the first stamp portion 50 is formed by ink stamping.

このように、第1捺印部50の捺印情報(捺印文字)が、インク捺印により形成されることで、捺印文字を鮮明にすることができる。したがって、超音波探傷装置等を用いて行う、第1捺印部50の捺印情報の確認を容易に行うことができる。また、第1捺印部50は、第2中継基板20に付されている。捺印方法としては、インク捺印の他に、例えばレーザー捺印もあるが、レーザー捺印は、第2中継基板20を彫りこむため、捺印が困難である。したがって、実施例1のように、第2中継基板20に第1捺印部50を形成する場合は、インク捺印を用いることで、容易に第1捺印部50を形成することができる。   As described above, the stamp information (the stamp character) of the first stamp portion 50 is formed by the ink stamp, so that the stamp character can be made clear. Therefore, it is possible to easily check the marking information of the first marking unit 50 using an ultrasonic flaw detector or the like. The first marking part 50 is attached to the second relay board 20. As the marking method, there is, for example, laser stamping in addition to ink stamping. However, since laser stamping engraves the second relay substrate 20, the stamping is difficult. Therefore, when the first marking part 50 is formed on the second relay substrate 20 as in the first embodiment, the first marking part 50 can be easily formed by using ink marking.

また、インク捺印に用いるインクは、例えばAu、Ag、Cu等の金属粉末を含有している。このように、金属粉末を含有したインクを用いることで、第1捺印部50の捺印情報の確認を、X線装置を用いて行うことが可能となる。つまり、インクに金属粉末を含有させることで、X線を吸収するようになるため、X線を透過する箇所と透過しない箇所とを識別することで、第1捺印部50の捺印情報の確認を行える。よって、インクに含有させる金属粉末は、Au、Ag、Cuに限らず、X線の透過率の高い材料であれば、その他の材料を用いてもよい。さらに、金属粉末は、第1捺印部50の捺印文字の線幅より小さい文字を描画できる材料であることが望ましい。   Moreover, the ink used for ink stamping contains metal powders, such as Au, Ag, Cu, for example. As described above, by using the ink containing the metal powder, it is possible to confirm the marking information of the first marking unit 50 by using the X-ray apparatus. That is, since X-rays are absorbed by including metal powder in the ink, confirmation of the stamping information of the first stamping unit 50 can be performed by identifying a portion that transmits X-rays and a portion that does not transmit X-rays. Yes. Therefore, the metal powder contained in the ink is not limited to Au, Ag, and Cu, and other materials may be used as long as the material has a high X-ray transmittance. Furthermore, the metal powder is preferably a material that can draw characters smaller than the line width of the stamped characters of the first stamping portion 50.

図1で説明したように、第2中継基板20の下面には配線が形成されている。したがって、金属粉末を含有したインクを用いる場合は、配線とインクとが導通しないように、配線を覆うように形成されているソルダーレジストに、第1捺印部50を形成することが望ましい。   As described with reference to FIG. 1, wiring is formed on the lower surface of the second relay substrate 20. Therefore, when ink containing metal powder is used, it is desirable to form the first marking portion 50 in a solder resist formed so as to cover the wiring so that the wiring and the ink do not conduct.

図4(a)のように、第2捺印部52は、第2樹脂部34の上面に形成される。つまり、第2捺印部52は直接視認することができる。このため、金属粉末を含有しないインクを用いた場合でも、第2捺印部52の捺印情報の確認は容易に行える。また、第2捺印部52は、第2樹脂部34の上面に形成されるため、レーザー捺印を用いた場合でも、第2捺印部52を容易に形成することができる。したがって、第2捺印部52の形成方法は、一般的に用いられている種々多様な方法を用いることができる。   As shown in FIG. 4A, the second marking part 52 is formed on the upper surface of the second resin part 34. That is, the second marking part 52 can be visually recognized directly. For this reason, even when ink that does not contain metal powder is used, the stamp information of the second stamp portion 52 can be easily confirmed. Further, since the second marking portion 52 is formed on the upper surface of the second resin portion 34, the second marking portion 52 can be easily formed even when laser marking is used. Accordingly, various methods that are generally used can be used as a method of forming the second stamped portion 52.

実施例1において、第2捺印部52は、半導体装置100を識別するための情報を示す場合を例に示したが、第1半導体チップ12を識別するための情報を示す場合でもよい。   In the first embodiment, the second marking unit 52 shows information for identifying the semiconductor device 100 as an example. However, the second marking unit 52 may show information for identifying the first semiconductor chip 12.

図6(a)は、実施例2に係る半導体装置の模式的断面図であり、図6(b)は、模式的上面図である。図6(a)及び図6(b)を参照に、内蔵半導体装置30に付された第1捺印部50と、第2樹脂部34の上面に付された第2捺印部52とが、第2樹脂部34の上方からみて重ならないように配置されている。その他の構成については、比較例2と同じであり、図2に示しているので説明を省略する。   FIG. 6A is a schematic cross-sectional view of the semiconductor device according to the second embodiment, and FIG. 6B is a schematic top view. Referring to FIGS. 6A and 6B, the first marking portion 50 attached to the built-in semiconductor device 30 and the second marking portion 52 attached to the upper surface of the second resin portion 34 are The two resin portions 34 are arranged so as not to overlap when viewed from above. The other configuration is the same as that of the comparative example 2 and is shown in FIG.

次に、図7(a)から図7(c)の模式的断面図を用いて、実施例2に係る半導体装置の製造方法を説明する。図7(a)を参照に、接着剤16を用い、第1中継基板10の上面に第1半導体チップ12を搭載する。この状態で、第1半導体チップ12の良否確認の試験を行う。その後、良品と確認された第1半導体チップ12とランド電極17とをボンディングワイヤ18を用いて接続する。   Next, a method for manufacturing a semiconductor device according to the second embodiment will be described with reference to schematic cross-sectional views of FIGS. 7A to 7C. With reference to FIG. 7A, the first semiconductor chip 12 is mounted on the upper surface of the first relay substrate 10 using an adhesive 16. In this state, a test for checking the quality of the first semiconductor chip 12 is performed. Thereafter, the first semiconductor chip 12 confirmed to be non-defective and the land electrode 17 are connected using the bonding wire 18.

図7(b)を参照に、第1中継基板10の上面に形成した半田端子48を用いて、内蔵半導体装置30を搭載する。内蔵半導体装置30は、第1半導体チップ12の上方に配置される。ここで、内蔵半導体装置30は、事前に良否確認の試験を実施しており、良品と確認された内蔵半導体装置30を搭載する。また、搭載する内蔵半導体装置30の第3樹脂部24の上面には、予め第1捺印部50が形成されている。第1捺印部50の形成方法は、例えば金、銀、銅等の金属粉末をインクの中に含有させ、この金属粉末を含有したインクを、第3樹脂部24の上面に印刷することで形成することができる。   With reference to FIG. 7B, the built-in semiconductor device 30 is mounted using the solder terminals 48 formed on the upper surface of the first relay substrate 10. The built-in semiconductor device 30 is disposed above the first semiconductor chip 12. Here, the built-in semiconductor device 30 is subjected to a test for confirming whether it is good or bad in advance, and the built-in semiconductor device 30 that has been confirmed as good is mounted. In addition, a first marking part 50 is formed in advance on the upper surface of the third resin part 24 of the built-in semiconductor device 30 to be mounted. The first stamped portion 50 is formed by, for example, containing metal powder such as gold, silver, or copper in the ink and printing the ink containing the metal powder on the upper surface of the third resin portion 24. can do.

図7(c)を参照に、内蔵半導体装置30と第1半導体チップ12との間に、アンダーフィル材を充填する。これにより、第1半導体チップ12と半田端子48とを封止する第1樹脂部14が形成される。第1中継基板10の上面に、第1樹脂部14と内蔵半導体装置30とを封止する第2樹脂部34を形成する。第2樹脂部34の上面に、例えば第1捺印部50の形成方法と同じ方法を用いて、第2捺印部52を形成する。その後、第1中継基板10のパッド電極46に半田ボール42を形成して、実施例2に係る半導体装置が完成する。   With reference to FIG. 7C, an underfill material is filled between the built-in semiconductor device 30 and the first semiconductor chip 12. Thus, the first resin portion 14 that seals the first semiconductor chip 12 and the solder terminal 48 is formed. A second resin portion 34 for sealing the first resin portion 14 and the built-in semiconductor device 30 is formed on the upper surface of the first relay substrate 10. The second marking part 52 is formed on the upper surface of the second resin part 34 by using, for example, the same method as the method for forming the first marking part 50. Thereafter, solder balls 42 are formed on the pad electrodes 46 of the first relay substrate 10 to complete the semiconductor device according to the second embodiment.

実施例2によれば、図6(a)および図6(b)のように、第1捺印部50と第2捺印部52とは、第2樹脂部34の上方からみて重ならないように配置されている。したがって、実施例2においても、実施例1と同じように、第1捺印部50を容易に判別することができ、第1捺印部50の捺印情報の確認を行うことができる。   According to the second embodiment, as shown in FIGS. 6A and 6B, the first marking portion 50 and the second marking portion 52 are arranged so as not to overlap each other when viewed from above the second resin portion 34. Has been. Accordingly, also in the second embodiment, as in the first embodiment, the first stamped portion 50 can be easily determined, and the stamp information of the first stamped portion 50 can be confirmed.

図6(a)のように、内蔵半導体装置30は、第2中継基板20と、第2中継基板20の上面に搭載された第2半導体チップ22と、第2中継基板20の上面に設けられ、第2半導体チップ22を封止する第3樹脂部24と、を有する。内蔵半導体装置30の第1捺印部50は、第3樹脂部24の上面に形成されている。   As shown in FIG. 6A, the built-in semiconductor device 30 is provided on the second relay substrate 20, the second semiconductor chip 22 mounted on the upper surface of the second relay substrate 20, and the upper surface of the second relay substrate 20. And a third resin portion 24 for sealing the second semiconductor chip 22. The first marking part 50 of the built-in semiconductor device 30 is formed on the upper surface of the third resin part 24.

実施例1では、第1捺印部50は、第2中継基板20の下面に形成するため、レーザー捺印を用いた方法では、捺印が困難であった。しかしながら、実施例2では、第1捺印部50は、第3樹脂部24の上面に形成するため、レーザー捺印を用いた方法でも、捺印を容易に行うことができる。したがって、実施例2では、インク捺印に加え、レーザー捺印を用いることもできる。   In the first embodiment, since the first marking portion 50 is formed on the lower surface of the second relay substrate 20, it is difficult to perform the marking by the method using the laser marking. However, in the second embodiment, since the first marking portion 50 is formed on the upper surface of the third resin portion 24, the marking can be easily performed even by a method using laser marking. Therefore, in Example 2, in addition to ink stamping, laser stamping can also be used.

また、実施例1と同じように、インク捺印を用いることで、捺印文字が鮮明となるため、第1捺印部50の捺印情報の確認を容易に行うことができ、インクに金属粉末を含有させることで、X線装置による第1捺印部50の捺印情報の確認を行うことができる。   Further, as in the first embodiment, by using the ink stamp, the stamp character becomes clear, so that the stamp information of the first stamp portion 50 can be easily confirmed, and the ink contains a metal powder. Thus, the stamp information of the first stamp unit 50 can be confirmed by the X-ray apparatus.

図8(a)は、実施例3に係る半導体装置の模式的断面図であり、図8(b)は、模式的上面図である。図8(a)及び図8(b)を参照に、内蔵半導体装置30に付された第1捺印部50と、第2樹脂部34の上面に付された第2捺印部52とが、第2樹脂部34の上方からみて重ならないように配置されている。その他の構成については、比較例3と同じであり、図3に示しているので説明を省略する。   FIG. 8A is a schematic cross-sectional view of the semiconductor device according to the third embodiment, and FIG. 8B is a schematic top view. Referring to FIGS. 8A and 8B, the first marking portion 50 attached to the built-in semiconductor device 30 and the second marking portion 52 attached to the upper surface of the second resin portion 34 are The two resin portions 34 are arranged so as not to overlap when viewed from above. Other configurations are the same as those in Comparative Example 3 and are shown in FIG.

実施例3に係る半導体装置の製造方法は、凹部40を有する第1中継基板10を用い、第1半導体チップ12を凹部40に搭載すること以外は、実施例2と同じであり、図7(a)から図7(c)に示しているので説明を省略する。   The manufacturing method of the semiconductor device according to the third embodiment is the same as that of the second embodiment except that the first relay substrate 10 having the recess 40 is used and the first semiconductor chip 12 is mounted in the recess 40. FIG. Since it is shown in FIG.7 (c) from a), description is abbreviate | omitted.

実施例3によれば、図8(a)および図8(b)のように、第1捺印部50と第2捺印部52とは、第2樹脂部34の上方からみて重ならないように配置されている。したがって、実施例3においても、実施例1と同じように、第1捺印部50を容易に判別することができ、第1捺印部50の捺印情報の確認を行うことができる。   According to the third embodiment, as shown in FIGS. 8A and 8B, the first marking part 50 and the second marking part 52 are arranged so as not to overlap each other when viewed from above the second resin part 34. Has been. Accordingly, also in the third embodiment, as in the first embodiment, the first stamped portion 50 can be easily determined, and the stamp information of the first stamped portion 50 can be confirmed.

また、第1捺印部50は、第3樹脂部24の上面に形成するため、実施例2と同じように、第1捺印部50の形成方法は、インク捺印に加え、レーザー捺印を用いることができる。インク捺印を用いた場合は、実施例1と同じように、捺印文字を鮮明にでき、第1捺印部50の捺印情報の確認が容易に行え、インクに金属粉末を含有させることで、捺印情報の確認にX線装置を用いることができる。   Further, since the first marking part 50 is formed on the upper surface of the third resin part 24, the method for forming the first marking part 50 is to use laser marking in addition to ink marking as in the second embodiment. it can. When ink stamping is used, as in the first embodiment, the stamped characters can be made clear, the stamping information of the first stamping part 50 can be easily confirmed, and the stamping information can be obtained by including metal powder in the ink. An X-ray apparatus can be used for confirmation.

図8(a)のように、第1半導体チップ12を、第1中継基板10に設けられた凹部40に搭載することで、半導体装置100の低背化を図ることができる。   As shown in FIG. 8A, the semiconductor device 100 can be reduced in height by mounting the first semiconductor chip 12 in the recess 40 provided in the first relay substrate 10.

図9(a)は、実施例4に係る半導体装置の模式的断面図であり、図9(b)は、模式的上面図である。図9(a)および図9(b)を参照に、第1樹脂部14の上面に、例えば第1半導体チップ12を識別するための情報(製造社(会社)名、ロット番号、製造場所、製造日等)が捺印されている。第1樹脂部14の上面に付された捺印を第3捺印部54とする。第3捺印部54は、第2樹脂部34の上方からみて、第1捺印部50と第2捺印部52とに重ならないように配置されている。その他の構成については、実施例1と同じであり、図4(a)および図4(b)に示しているので説明を省略する。   FIG. 9A is a schematic cross-sectional view of a semiconductor device according to Example 4, and FIG. 9B is a schematic top view. 9A and 9B, on the upper surface of the first resin portion 14, for example, information for identifying the first semiconductor chip 12 (manufacturer (company) name, lot number, manufacturing location, The date of manufacture etc.) is stamped. The marking affixed to the upper surface of the first resin portion 14 is referred to as a third marking portion 54. The third marking portion 54 is disposed so as not to overlap the first marking portion 50 and the second marking portion 52 when viewed from above the second resin portion 34. Other configurations are the same as those of the first embodiment and are shown in FIG. 4A and FIG.

実施例4に係る半導体装置の製造方法は、第3捺印部54を形成する工程以外は、実施例1と同じであり、図5(a)から図5(c)に示しているので説明を省略する。第3捺印部54は、図5(a)で説明した、第1中継基板10の上面に、第1半導体チップ12を封止する第1樹脂部14を形成した後、第1樹脂部14の上面に形成する。第3捺印部54の形成方法は、例えば金属粉末を含有するインクを用いたインク捺印やレーザー捺印を使用することができる。   The manufacturing method of the semiconductor device according to the fourth embodiment is the same as that of the first embodiment except for the step of forming the third stamped portion 54, and the description thereof is shown in FIGS. 5 (a) to 5 (c). Omitted. The third marking part 54 is formed by forming the first resin part 14 for sealing the first semiconductor chip 12 on the upper surface of the first relay substrate 10 described with reference to FIG. Form on the top surface. As a method of forming the third marking portion 54, for example, ink marking using a metal powder-containing ink or laser marking can be used.

実施例4によれば、図9(a)および図9(b)のように、第3捺印部54は、第2樹脂部34の上方からみて、第1捺印部50と第2捺印部52とに重ならないように配置されている。このため、例えば超音波探傷装置を用いて、第3捺印部54の捺印情報の確認を行った場合でも、第1捺印部50と第2捺印部52との影響を受けることがなく、第3捺印部54を容易に判別することができる。したがって、第3捺印部54の捺印情報の確認を行うことができる。よって、実施例4によれば、例えば、第1半導体チップ12と、内蔵半導体装置30と、半導体装置100とのそれぞれについて、識別情報を得ることが可能となる。   According to the fourth embodiment, as shown in FIGS. 9A and 9B, the third marking portion 54 is seen from above the second resin portion 34, and the first marking portion 50 and the second marking portion 52. It is arranged so as not to overlap. For this reason, even when the marking information of the third marking portion 54 is confirmed using, for example, an ultrasonic flaw detector, the third marking portion 50 and the second marking portion 52 are not affected by the third marking portion 54 and the third marking portion 54 is not affected. The stamp portion 54 can be easily identified. Accordingly, it is possible to confirm the stamp information of the third stamp portion 54. Therefore, according to the fourth embodiment, for example, identification information can be obtained for each of the first semiconductor chip 12, the built-in semiconductor device 30, and the semiconductor device 100.

第3捺印部54についても、インク捺印を用いることで、捺印文字が鮮明となるため、第3捺印部54の捺印情報の確認を容易に行うことができ、金属粉末を含有するインクを用いることで、X線装置により第3捺印部54の捺印情報の確認を行うことができる。   Also for the third marking part 54, the use of ink marking makes the stamped characters clear, so that the marking information of the third marking part 54 can be easily confirmed, and ink containing metal powder is used. Thus, the marking information of the third marking unit 54 can be confirmed by the X-ray apparatus.

実施例1から4において、第1半導体チップ12は、第1中継基板10にフェースアップで実装されている場合を例に示したが、第1半導体チップ12は、フェースダウン実装されている場合でもよい。また、実施例2および3において、接続端子として半田端子48を用いる場合を例に示したが、第1中継基板10と内蔵半導体装置30とを接続する端子であればよい。例えばAuバンプでもよい。   In the first to fourth embodiments, the case where the first semiconductor chip 12 is mounted face-up on the first relay substrate 10 has been described as an example, but the first semiconductor chip 12 may be mounted face-down. Good. In the second and third embodiments, the case where the solder terminal 48 is used as the connection terminal has been described as an example. However, any terminal that connects the first relay substrate 10 and the built-in semiconductor device 30 may be used. For example, Au bumps may be used.

以上、本発明の好ましい実施例について詳述したが、本発明は係る特定の実施例に限定されるものではなく、特許請求の範囲に記載された本発明の要旨の範囲内において、種々の変形・変更が可能である。   The preferred embodiments of the present invention have been described in detail above, but the present invention is not limited to such specific embodiments, and various modifications can be made within the scope of the gist of the present invention described in the claims.・ Change is possible.

図1は比較例1に係る半導体装置の模式的断面図である。FIG. 1 is a schematic cross-sectional view of a semiconductor device according to Comparative Example 1. 図2は比較例2に係る半導体装置の模式的断面図である。FIG. 2 is a schematic cross-sectional view of a semiconductor device according to Comparative Example 2. 図3は比較例3に係る半導体装置の模式的断面図である。FIG. 3 is a schematic cross-sectional view of a semiconductor device according to Comparative Example 3. 図4(a)は実施例1に係る半導体装置の模式的断面図であり、図4(b)は模式的上面図である。FIG. 4A is a schematic cross-sectional view of the semiconductor device according to the first embodiment, and FIG. 4B is a schematic top view. 図5(a)から図5(c)は実施例1に係る半導体装置の製造方法を示す模式的断面図である。FIG. 5A to FIG. 5C are schematic cross-sectional views illustrating the method for manufacturing the semiconductor device according to the first embodiment. 図6(a)は実施例2に係る半導体装置の模式的断面図であり、図6(b)は模式的上面図である。FIG. 6A is a schematic cross-sectional view of the semiconductor device according to the second embodiment, and FIG. 6B is a schematic top view. 図7(a)から図7(c)は実施例2に係る半導体装置の製造方法を示す模式的断面図である。FIG. 7A to FIG. 7C are schematic cross-sectional views illustrating a method for manufacturing a semiconductor device according to the second embodiment. 図8(a)は実施例3に係る半導体装置の模式的断面図であり、図8(b)は模式的上面図である。FIG. 8A is a schematic cross-sectional view of a semiconductor device according to the third embodiment, and FIG. 8B is a schematic top view. 図9(a)は実施例4に係る半導体装置の模式的断面図であり、図9(b)は模式的上面図である。FIG. 9A is a schematic cross-sectional view of a semiconductor device according to Example 4, and FIG. 9B is a schematic top view.

符号の説明Explanation of symbols

10 第1中継基板
12 第1半導体チップ
14 第1樹脂部
16 接着剤
17 ランド電極
18 ボンディングワイヤ
20 第2中継基板
22 第2半導体チップ
24 第3樹脂部
26 接着剤
27 ランド電極
28 ボンディングワイヤ
30 内蔵半導体装置
32 接着剤
34 第2樹脂部
36 パッド電極
38 ボンディングワイヤ
40 凹部
42 半田ボール
44 貫通接続部
46 パッド電極
48 半田端子
50 第1捺印部
52 第2捺印部
54 第3捺印部
100 半導体装置
DESCRIPTION OF SYMBOLS 10 1st relay substrate 12 1st semiconductor chip 14 1st resin part 16 Adhesive 17 Land electrode 18 Bonding wire 20 2nd relay substrate 22 2nd semiconductor chip 24 3rd resin part 26 Adhesive 27 Land electrode 28 Bonding wire 30 Built-in Semiconductor device 32 Adhesive 34 Second resin portion 36 Pad electrode 38 Bonding wire 40 Recess 42 Solder ball 44 Through-connection portion 46 Pad electrode 48 Solder terminal 50 First marking portion 52 Second marking portion 54 Third marking portion 100 Semiconductor device

Claims (8)

第1中継基板の上面に搭載された第1半導体チップと、
前記第1中継基板の上面に設けられ、前記第1半導体チップを封止する第1樹脂部と、
前記第1樹脂部の上面に設けられ、前記第1中継基板に電気的に接続する内蔵半導体装置と、
前記第1中継基板の上面に設けられ、前記第1樹脂部と前記内蔵半導体装置とを封止する第2樹脂部と、
前記内蔵半導体装置に設けられ、前記内蔵半導体装置を識別するための情報を示す第1捺印部と、
前記第2樹脂部に設けられ、半導体装置及び前記第1半導体チップのいずれか一方を識別するための情報を示す第2捺印部と、を具備し、
前記第1捺印部と前記第2捺印部とは、前記第2樹脂部の上方からみて重ならないように配置されていることを特徴とする半導体装置。
A first semiconductor chip mounted on the upper surface of the first relay substrate;
A first resin portion provided on an upper surface of the first relay substrate and sealing the first semiconductor chip;
A built-in semiconductor device provided on an upper surface of the first resin portion and electrically connected to the first relay substrate;
A second resin portion provided on an upper surface of the first relay substrate and sealing the first resin portion and the built-in semiconductor device;
A first marking unit provided in the built-in semiconductor device and indicating information for identifying the built-in semiconductor device;
A second marking portion provided in the second resin portion and indicating information for identifying one of the semiconductor device and the first semiconductor chip;
The semiconductor device according to claim 1, wherein the first marking portion and the second marking portion are arranged so as not to overlap each other when viewed from above the second resin portion.
前記第1樹脂部に設けられ、前記第1半導体チップを識別するための情報を示す第3捺印部を具備し、
前記第3捺印部は、前記第2樹脂部の上方から見て、前記第1捺印部と前記第2捺印部とに重ならないように配置されていることを特徴とする請求項1記載の半導体装置。
A third marking portion provided on the first resin portion and indicating information for identifying the first semiconductor chip;
2. The semiconductor according to claim 1, wherein the third marking portion is arranged so as not to overlap the first marking portion and the second marking portion when viewed from above the second resin portion. apparatus.
前記第1捺印部は、インク捺印により形成されていることを特徴とする請求項1または2記載の半導体装置。   The semiconductor device according to claim 1, wherein the first marking portion is formed by ink marking. 前記第3捺印部は、インク捺印により形成されていることを特徴とする請求項2記載の半導体装置。   The semiconductor device according to claim 2, wherein the third marking portion is formed by ink marking. 前記インク捺印は、金属粉末を含有するインクを用いていることを特徴とする請求項3または4記載の半導体装置。   5. The semiconductor device according to claim 3, wherein the ink seal uses an ink containing a metal powder. 前記内蔵半導体装置は、第2中継基板の上面に搭載された第2半導体チップと、前記第2中継基板の上面に設けられ、前記第2半導体チップを封止する第3樹脂部と、からなり、
前記内蔵半導体装置は、前記第3樹脂部が前記第1樹脂部に接合することで、前記第1樹脂部の上面に設けられていて、前記第1捺印部は、前記第2半導体チップが搭載された面と反対側の前記第2中継基板の面に設けられていることを特徴とする請求項1から5のいずれか一項記載の半導体装置。
The built-in semiconductor device includes a second semiconductor chip mounted on an upper surface of a second relay substrate, and a third resin portion provided on the upper surface of the second relay substrate and sealing the second semiconductor chip. ,
The built-in semiconductor device is provided on the upper surface of the first resin portion by joining the third resin portion to the first resin portion, and the second semiconductor chip is mounted on the first marking portion. 6. The semiconductor device according to claim 1, wherein the semiconductor device is provided on a surface of the second relay substrate opposite to the formed surface.
前記内蔵半導体装置は、第2中継基板の上面に搭載された第2半導体チップと、前記第2中継基板の上面に設けられ、前記第2半導体チップを封止する第3樹脂部と、からなり、
前記内蔵半導体装置は、前記第2中継基板が前記第1樹脂部に接合することで、前記第1樹脂部の上面に設けられていて、前記第1捺印部は、前記第3樹脂部の上面に設けられていることを特徴とする請求項1から5のいずれか一項記載の半導体装置。
The built-in semiconductor device includes a second semiconductor chip mounted on an upper surface of a second relay substrate, and a third resin portion provided on the upper surface of the second relay substrate and sealing the second semiconductor chip. ,
The built-in semiconductor device is provided on the upper surface of the first resin portion by bonding the second relay substrate to the first resin portion, and the first marking portion is an upper surface of the third resin portion. The semiconductor device according to claim 1, wherein the semiconductor device is provided.
前記第1中継基板に凹部が設けられていて、前記第1半導体チップは、前記凹部に搭載されていることを特徴とする請求項1から7のいずれか一項記載の半導体装置。   The semiconductor device according to claim 1, wherein a recess is provided in the first relay substrate, and the first semiconductor chip is mounted in the recess.
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118328A (en) * 1997-06-17 1999-01-12 Hitachi Ltd Semiconductor device, its manufacturing method and method is identifying the same
JP2002314040A (en) * 2001-04-18 2002-10-25 Toshiba Corp Laminated semiconductor device
JP2005123246A (en) * 2003-10-14 2005-05-12 Seiko Epson Corp Electronic component, piezoelectric oscillator, recognition method of built-in electronic component and recognition method of piezoelectric vibrator
JP2008042111A (en) * 2006-08-10 2008-02-21 Toshiba Corp Semiconductor device, and method of manufacturing the same
WO2008050724A1 (en) * 2006-10-24 2008-05-02 Lintec Corporation Composite semiconductor device, semiconductor package and spacer sheet used in the same, and method for manufacturing composite semiconductor device
JP2008166438A (en) * 2006-12-27 2008-07-17 Spansion Llc Semiconductor device, and manufacturing method thereof
JP2009152463A (en) * 2007-12-21 2009-07-09 Toyota Motor Corp Semiconductor apparatus, identification device of semiconductor apparatus and manufacturing device of semiconductor apparatus

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH118328A (en) * 1997-06-17 1999-01-12 Hitachi Ltd Semiconductor device, its manufacturing method and method is identifying the same
JP2002314040A (en) * 2001-04-18 2002-10-25 Toshiba Corp Laminated semiconductor device
JP2005123246A (en) * 2003-10-14 2005-05-12 Seiko Epson Corp Electronic component, piezoelectric oscillator, recognition method of built-in electronic component and recognition method of piezoelectric vibrator
JP2008042111A (en) * 2006-08-10 2008-02-21 Toshiba Corp Semiconductor device, and method of manufacturing the same
WO2008050724A1 (en) * 2006-10-24 2008-05-02 Lintec Corporation Composite semiconductor device, semiconductor package and spacer sheet used in the same, and method for manufacturing composite semiconductor device
JP2008166438A (en) * 2006-12-27 2008-07-17 Spansion Llc Semiconductor device, and manufacturing method thereof
JP2009152463A (en) * 2007-12-21 2009-07-09 Toyota Motor Corp Semiconductor apparatus, identification device of semiconductor apparatus and manufacturing device of semiconductor apparatus

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