JP2010026762A - Data transfer device and data transfer method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To suppress the number of value storage parts and schedulers to be arranged from being increased according to the number of setting values, in a data transfer device which transfer data by a direct memory access transfer system. <P>SOLUTION: A data transfer device has a setting value storage part which stores a setting value having the combination of a transfer source memory address and a transfer destination memory address of data transfer. The data transfer device transfers the setting value stored in an external storage part to the setting value storage part, and transfers data by direct memory access from the transfer source memory address to the transfer destination memory address according to the setting value stored in the setting value storage part. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a data transfer apparatus that transfers data by direct memory access and a data transfer method thereof.

  2. Description of the Related Art Conventionally, a direct memory access (DMA) transfer method that transfers data without applying a load to a CPU (Central Processing Unit) has been proposed (see, for example, Patent Document 1). In the direct memory access transfer method, a direct memory access controller (DMAC: DMA Controller) performs data transfer between memories according to a set value indicating data transfer processing contents without going through CPU processing.

  FIG. 8 is a functional block diagram showing the configuration of a conventional DMAC. The DMAC 200 includes a start pulse counter 201, a local counter 202, a plurality of set value storage units 203, a plurality of schedulers 204, and a transfer unit 205, and operates upon receiving a start pulse from the start pulse generation unit 100.

  First, each functional unit of the conventional DMAC 200 will be described. The activation pulse counter 201 counts the number of times that the DMAC 200 has received the activation pulse generated from the activation pulse generator 100. The local counter 202 starts counting at a cycle shorter than the cycle of the startup pulse when the DMAC 200 receives the startup pulse, and outputs a signal representing each count value (local count value). The set value storage unit 203 stores a set value indicating a plurality of data transfer processing contents (transfer source memory address and transfer destination memory address) in association with the local count value. The scheduler 204 is arranged for each setting value storage unit 203 and instructs the transfer unit 205 to transfer data according to the setting value stored in the corresponding setting value storage unit 203. The transfer unit 205 performs data transfer according to the DMA transfer method in accordance with an instruction from the scheduler 204.

Next, the operation of the conventional DMAC 200 will be described. FIG. 9 is a schematic diagram showing an outline of the operation of the conventional DMAC. When the DMAC 200 receives a start pulse from the start pulse generator 100, the start pulse counter 201 of the DMAC 200 counts the number of times the start pulse is received, and transmits a signal representing the number to each scheduler 204. In addition, when receiving the activation pulse from the activation pulse generator 100, the local counter 202 starts transmitting the local count value to each scheduler 204. Each scheduler 204 determines whether or not it is a timing for operating itself according to the number of times of receiving the activation pulse. The scheduler 204 that has determined that it is the timing at which the device itself operates reads the data transfer processing content corresponding to the local count value from the corresponding set value storage unit 203 and instructs the transfer unit 205 to perform data transfer. In the case of FIG. 9, first, the scheduler 204 that instructs data transfer A, B, and C determines that it is time to operate the own apparatus. Then, the scheduler 204 sequentially reads out the processing details of the data transfer A, the processing details of the data transfer B, and the processing details of the data transfer C corresponding to the received local count value from the set value storage unit 203 and sends them to the transfer unit 205. A data transfer instruction corresponding to each processing content is issued. Next, when the activation pulse is received, the scheduler 204 instructing the data transfer D, E, and F determines that it is the timing at which the own apparatus operates, and performs the same processing.
JP 2007-310735 A

  The conventional DMAC 200 has to include the same number of setting value storage units 203 and schedulers 204 as the number of setting values necessary for the operation of the DMAC 200. For example, in the case of FIG. 9, the setting value storage unit 203 and the scheduler 204 corresponding to the setting value representing the data transfer A, B, and C, and the setting value storage unit 203 corresponding to the setting value representing the data transfer D, E, and F. And a scheduler 204 are required. Therefore, conventionally, there is a problem that the number of setting value storage units 203 and schedulers 204 arranged in the DMAC 200 increases according to the number of setting values set in the DMAC 200.

  In view of the above circumstances, the present invention can suppress an increase in the number of setting value storage units and schedulers arranged according to the number of setting values in a data transfer device that performs data transfer using the direct memory access transfer method. An object of the present invention is to provide a data transfer apparatus and a data transfer method.

  [1] In order to solve the above-described problem, a data transfer device according to an aspect of the present invention includes a set value storage unit that stores a set value having a combination of a transfer source memory address and a transfer destination memory address for data transfer; A set value transfer unit that transfers the set value stored in an external storage unit to the set value storage unit, and a combination of the transfer source memory addresses according to the set value stored in the set value storage unit A transfer unit that transfers data to the transfer destination memory address by direct memory access.

  [2] Further, according to one aspect of the present invention, in the data transfer device, the setting value stored in the setting value storage unit includes a plurality of the combinations, and is stored in the setting value storage unit. The setting value includes a memory address at which the external storage unit stores the setting value, a memory address at which the setting value storage unit stores the setting value, a transfer source memory address and a transfer destination memory address, respectively. The set value transfer unit transfers a memory address at which the external storage unit stores the set value and a memory address at which the set value storage unit stores the set value, respectively. The setting stored in the setting value storage unit after the transfer unit has transferred data for all combinations other than the combination of the original memory address and the transfer destination memory address Accordingly transfers the data set values into the setting value storing unit from the external storage unit by direct memory access, characterized in that.

  [3] Further, according to one aspect of the present invention, in the above data transfer device, the set value storage unit functions as a slave of the data transfer device.

  [4] Further, one aspect of the present invention may be specified as a data transfer method performed by a data transfer device including the set value storage unit described above.

  According to the present invention, in a data transfer apparatus that performs data transfer by the direct memory access transfer method, it is possible to prevent the number of setting value storage units and schedulers to be arranged from increasing according to the number of setting values.

FIG. 1 is a functional block diagram showing a functional configuration of a DMAC (corresponding to a “data transfer apparatus” in the present invention). As shown in the figure, the DMAC 3 is connected to the activation pulse generator 1 and the external memory 2.
The start pulse generator 1 periodically generates a start pulse.
The external memory 2 (corresponding to an “external storage unit” in the present invention) is configured as a device different from the DMAC 3, is connected to a data bus, and stores setting values. The external memory 2 is realized using, for example, a main memory or an auxiliary storage device in a computer system in which the DMAC 3 is mounted.

The DMAC 3 includes a set value storage unit 31, a local counter 32, a scheduler 33, a schedule rewriting unit 34, and a transfer unit 35.
The set value storage unit 31 is connected to a data bus external to the DMAC 3, operates as a slave of the schedule rewriting unit 34, and receives data rewriting from the schedule rewriting unit 34. The set value storage unit 31 stores one set value including a plurality of pieces of data transfer information (corresponding to “combination” in the present invention). Each data transfer information includes a data transfer source memory address (transfer source address), a data transfer destination memory address (transfer destination address), and a transferred data amount (data amount).

When receiving the start pulse from the start pulse generator 1, the local counter 32 starts counting at a cycle shorter than the start pulse, and outputs a signal representing the accumulated count value (local count value) every time the count is performed. To do.
The scheduler 33 reads the data transfer information corresponding to the local count value output from the local counter 32 from the set value storage unit 31, and instructs the schedule rewriting unit 34 and the transfer unit 35 to transfer the data according to the read data transfer information. I do.

  A schedule rewriting unit (corresponding to a “setting value transfer unit” in the present invention) 34 is connected to a data bus external to the DMAC 3, and is in accordance with an instruction from the scheduler 33 according to a DMA transfer method, that is, without CPU processing. The set value stored in the memory 2 is transferred to the set value storage unit 31.

  The transfer unit 35 is connected to an external data bus of the DMAC 3 and controls data transfer between devices connected to the data bus by the DMA transfer method, that is, without passing through the processing of the CPU, according to the instruction of the scheduler 33. .

  FIG. 2 is a schematic diagram showing an outline of data stored in the external memory 2. The external memory 2 stores a plurality of setting values in a memory area accessible by the schedule rewriting unit 34 of the DMAC 2.

  FIG. 3 is a schematic diagram showing an outline of the contents of the set value. The setting value includes a plurality of data transfer information in which a local count value, a transfer source address, a transfer destination address, and a data amount are associated with each other. For example, in the case of FIG. 3, the combination of the local count value 1, the transfer source address S_A, the transfer destination address D_A, and the data amount A_A represents one data transfer information, and the set value has four data transfer information.

  Specific contents of each item of the set value will be described. The local count value corresponds to the counter value output from the local counter 32 and indicates the timing at which data transfer according to each data transfer information is executed. The transfer source address indicates a memory address of a transfer source of data transfer performed by the schedule rewriting unit 34 and the transfer unit 35. The transfer destination address indicates a memory address of a transfer destination of data transfer performed by the schedule rewriting unit 34 and the transfer unit 35. The data amount indicates the amount of data transferred in the data transfer performed by the schedule rewriting unit 34 and the transfer unit 35. For example, when the setting value of FIG. 3 is stored in the setting value storage unit 31, when the local counter 32 outputs the local count value “1”, the scheduler 33 instructs the transfer unit 35 to transfer data, and follows this instruction. The transfer unit 35 transfers the data amount A_A from the memory address S_A to the memory address D_A.

  Of the plurality of pieces of data transfer information included in one set value, the data transfer information executed last (that is, the data transfer information with the maximum local count value) is the contents of the data transfer executed by the schedule rewriting unit 34. To express. In such data transfer information, the transfer source address indicates the memory address where the set value is stored in the external memory 2, the transfer destination address indicates the memory address where the set value is stored in the set value storage unit 31, and the data amount Indicates the data amount of the set value. In the case of FIG. 3, S_X 1 indicates a memory address where the external memory 2 stores the set value, and D_X 1 indicates a memory address of the set value storage unit 31.

  FIG. 4 is a flowchart illustrating an operation example of the DMAC 3. FIG. 5 is a schematic diagram showing an outline of the operation of the DMAC 3. Hereinafter, the operation of the DMAC 3 when the set value storage unit 31 stores the set values shown in FIG. 3 will be described with reference to FIGS. 4 and 5.

  First, the DMAC 3 waits until a start pulse is received from the start pulse generator 1 (step S01-NO). When the DMAC 3 receives the activation pulse from the activation pulse generator 1 (step S01-YES), the local counter 32 periodically outputs a signal representing the local count value (step S02).

  Thereafter, the scheduler 33 reads data transfer information corresponding to the local count value output by the local counter 32 from the set value storage unit 31. First, when a signal representing the local count value 1 is output from the local counter 32, the scheduler 33 reads data transfer information corresponding to the local count value 1 from the set value storage unit 31. Specifically, the scheduler 33 reads the transfer source address S_A, the transfer destination address D_A, and the data amount A_A. If data transmission information corresponding to the local count value is not stored in the set value storage unit 31, the scheduler 33 waits until a signal representing the next local count value is output.

  Next, the scheduler 33 determines whether or not the transfer destination of the read data transfer information is the set value storage unit 31 (step S04). Specifically, the scheduler 33 stores in advance a memory address (hereinafter referred to as “setting value storage memory address”) in which the setting value storage unit 31 stores setting value data, and stores the read data transfer information. If the memory address of the transfer destination is the set value storage memory address, it is determined that the transfer destination of the read data transfer information is the set value storage unit 31. Conversely, the scheduler 33 determines that the read destination of the data transfer information is not the set value storage unit 31 if the memory address of the read destination of the data transfer information is not the set value storage memory address. to decide. In this description, a case where the set value storage memory address is D_X1 will be described. In this case, since the transfer destination address read as described above is D_A and not D_X1, the transfer destination is not the set value storage unit 31.

  When the transfer destination of the read data transfer information is not the set value storage unit 31 (NO in step S04), the scheduler 33 instructs the transfer unit 35 to transfer data according to the read data transfer information (step S04). S05). The transfer unit 35 transfers data by DMA from the transfer source address to the transfer destination address according to the data transfer information read by the scheduler 33 (step S06). Specifically, the transfer unit 35 transfers data having a data amount corresponding to A_A from the memory address S_A to the memory address D_A (corresponding to the rectangle A in FIG. 5). Thereafter, the transfer unit 35 performs data transfer at the timing when the local count value is 3 or 5 (corresponding to rectangles B and C in FIG. 5).

  Thereafter, at the timing when the local count value is 7, the scheduler 33 reads the transfer source address S_X1, the transfer destination address D_X1, and the data amount A_X1. In this case, the read transfer destination address is the set value storage memory address, and the transfer destination of the data transfer information is the set value storage unit 31. When the transfer destination of the read data transfer information is the set value storage unit 31 (step S04-YES), the scheduler 33 instructs the schedule rewriting unit 34 to transfer data according to the read data transfer information ( Step S07). The schedule rewriting unit 34 transfers data representing the set value from the transfer source address in the external memory 2 to the transfer destination address in the set value storage unit 31 by DMA according to the data transfer information read by the scheduler 33. Then, the contents of the set value stored in the set value storage unit 31 are rewritten (step S08). Specifically, the schedule rewriting unit 34 transfers data of the set value of the data amount for A_X1 from the memory address S_X1 in the external memory 2 to the memory address D_A in the set value storage unit 31 (FIG. 5). Equivalent to rectangle X1).

  Thereafter, the DMAC 3 enters a standby state, and when the activation pulse is received again from the activation pulse generator 1 (step S01-YES), the processing after step S02 is performed according to the new set value rewritten by the processing of step S08 (FIG. 5). Rectangles D, E, F, and X2).

  In the DMAC 3 configured as described above, the setting value stored in the setting value storage unit 31 is rewritten to another setting value stored in the external memory 2 by the schedule rewriting unit 34. Therefore, even if the DMAC 3 requires a plurality of setting values, the DMAC 3 does not need to store all the setting values in the setting value storage unit 31. That is, one set value is stored in the set value storage unit 31, the remaining other set values are stored in the external memory 2, and the schedule rewrite unit 34 stores the set value stored in the set value storage unit 31 in the external memory 2. By rewriting the stored setting values, the number of setting values held in the DMAC 3 can be reduced. Therefore, it is not necessary to place a plurality of setting value storage units 31 and schedulers 33 in the DMAC 3 for each of a plurality of setting values as in the prior art, and the number of setting value storage units 31 and schedulers 33 arranged in the DMAC 3 increases. Can be suppressed.

  In addition, since the DMAC 3 configured as described above does not need to include an activation pulse counter that counts the number of receptions of activation pulses, the circuit area of the DMAC 3 can be reduced and the circuit configuration can be simplified.

<Modification>
FIG. 6 is a diagram illustrating functional blocks of a modified example of the DMAC 3. In the above description, the setting value storage unit 31 receives the setting value data via the data bus, but the setting value storage unit 31 is not connected to the data bus and directly receives the setting value data from the schedule rewriting unit 34. You may do it. That is, the schedule rewriting unit 34 does not transfer the set value data from the external memory 2 to the set value storage unit 31 via the data bus, but reads the set value data from the external memory 2 and transfers the read data to the DMAC 3 The setting value storage unit 31 may be configured to write through the internal bus.

  FIG. 7 is a diagram illustrating functional blocks of another modification of the DMAC 3. In the above description, the DMAC 3 includes the schedule rewriting unit 34, and the schedule rewriting unit 34 transfers data between the external memory 2 and the set value storage unit 31 and rewrites the set value stored in the set value storage unit 31. However, the transfer unit 35 may be configured to perform the process of the schedule rewriting unit 34. In this case, the scheduler 33 instructs the transfer unit 35 to transfer data for all data transfer information without performing the determination process of step S04 in the flowchart of FIG. Further, the transfer unit 35 performs DMA transfer according to the data transfer instruction. When the transfer source address of the data transfer information is the external memory 2 and the transfer destination address is the set value storage unit 31, the transfer unit 35 starts from the transfer source address of the external memory 2 according to the data transfer information. The set value data is DMA transferred to the transfer destination address of the setting storage unit 31.

  In addition, the set value storage unit 31 uses, as an initial value, a memory address that stores a set value indicating the content of data transfer to be executed first by the external memory 2 as a transfer source address. A set value with the memory address as the transfer destination address may be fixedly stored in a ROM (Read Only Memory). In that case, the scheduler 33 reads the set value from this ROM when it first operates. Further, the set value storage unit 31 may dynamically write the set value from an external processor (for example, CPU) as an initial value.

  The embodiment of the present invention has been described in detail with reference to the drawings. However, the specific configuration is not limited to this embodiment, and includes designs and the like that do not depart from the gist of the present invention.

It is a functional block diagram showing the functional structure of a direct memory access controller. It is the schematic showing the outline of the data which an external memory memorize | stores. It is the schematic showing the outline of the content of a setting value. It is a flowchart showing the operation example of a direct memory access controller. It is the schematic showing the outline of operation | movement of a direct memory access controller. It is a functional block diagram showing the function structure of the modification of a direct memory access controller. It is a functional block diagram showing the function structure of the modification of a direct memory access controller. It is a functional block diagram showing the functional structure of the direct memory access controller in a prior art. It is the schematic showing the outline of operation | movement of the direct memory access controller in a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Startup pulse generation part, 2 ... External memory, 3 ... DMAC (data transfer device), 31 ... Setting value memory | storage part (setting value memory | storage part), 32 ... Local counter, 33 ... Scheduler, 34 ... Schedule rewriting part (setting) Value transfer unit), 35 ... transfer unit

Claims (4)

A set value storage unit for storing a set value having a combination of a transfer source memory address and a transfer destination memory address of data transfer;
A set value transfer unit for transferring the set value stored in an external storage unit to the set value storage unit;
A transfer unit that transfers data by direct memory access from the transfer source memory address to the transfer destination memory address in combination according to the set value stored in the set value storage unit;
A data transfer device comprising: The set values stored in the set value storage unit have a plurality of the combinations,
The setting value stored in the setting value storage unit includes a memory address at which the external storage unit stores the setting value, and a memory address at which the setting value storage unit stores the setting value, respectively. It has a combination of a transfer source memory address and a transfer destination memory address,
The set value transfer unit includes a memory address at which the external storage unit stores the set value and a memory address at which the set value storage unit stores the set value, a transfer source memory address and a transfer destination, respectively. After the transfer unit transfers data for all combinations other than the combination used as a memory address, the set value storage unit from the external storage unit by direct memory access according to the set value stored in the set value storage unit Transfer set value data to
The data transfer device according to claim 1.   The data transfer device according to claim 1, wherein the set value storage unit functions as a slave of the data transfer device. A data transfer apparatus including a setting value storage unit that stores a setting value having a combination of a transfer source memory address and a transfer destination memory address for data transfer, and the setting value storage unit stores the setting value stored in an external storage unit Transferring to
The data transfer device transferring data by direct memory access from the transfer source memory address to the transfer destination memory address in combination according to the set value stored in the set value storage unit;
Data transfer method including:

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