JP2010011056A - Solid-state imaging element and camera system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a solid-state imaging element and a camera system capable of realizing a normal cycle and a normal clock duty by a pulse without hazard in an output clock when a frame rate changes during image transfer, and of eliminating distortion of a displayed image. <P>SOLUTION: A solid-state imaging element has: a picture element part 110; a picture element driving part 120 and 150 that can operate so as to read out image data from the picture element part; and a clock controller 170 that implements control for read out image data transfer using an operation clock depending on a frequency selected depending on at least one master clock. The clock controller 170 stops the master clock when switching a frame rate, supplies the master clock after selecting the operation clock during stop of the master clock, and outputs the operation clock with normal pulse width, cycle, and clock duty which are proper to the frame rate after change. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a solid-state imaging device represented by a CMOS image sensor and a camera system.

In recent years, CMOS image sensors have attracted attention as solid-state imaging devices (image sensors) that replace CCDs.
This is because the CMOS image sensor overcomes the following problems.
That is, a dedicated process is required for manufacturing a CCD pixel, a plurality of power supply voltages are required for its operation, and a plurality of peripheral ICs need to be operated in combination.
This is because, in the case of such a CCD, the CMOS image sensor overcomes various problems such as a very complicated system.

The CMOS image sensor can be manufactured by using a manufacturing process similar to that of a general CMOS integrated circuit, can be driven by a single power source, and further, an analog circuit or logic using the CMOS process. Circuits can be mixed in the same chip.
For this reason, the CMOS image sensor has a plurality of great merits such that the number of peripheral ICs can be reduced.

The output circuit of a CCD is mainly a 1-channel (ch) output using an FD amplifier having a floating diffusion layer (FD).
In contrast, a CMOS image sensor has an FD amplifier for each pixel, and the output is mainly a column parallel output type in which a row in a pixel array is selected and read out in the column direction at the same time. It is.
This is because it is difficult to obtain a sufficient driving capability with an FD amplifier arranged in a pixel, and therefore it is necessary to lower the data rate, and parallel processing is advantageous.

In general, in a CMOS image sensor, when resetting pixels, a method of resetting successive pixels for each row is often used.
This method is called a rolling shutter.

  FIG. 1 is a diagram illustrating a pixel example of a CMOS image sensor including four transistors.

  This pixel 1 has a photoelectric conversion element 11 made of, for example, a photodiode. For this one photoelectric conversion element 11, there are four transistors: a transfer transistor 12, a reset transistor 13, an amplification transistor 14, and a selection transistor 15. As an active element.

The photoelectric conversion element 11 photoelectrically converts incident light into an amount of electric charges (here, electrons) corresponding to the amount of light.
The transfer transistor 12 is connected between the photoelectric conversion element 11 and the floating diffusion FD, and a transmission signal (drive signal) TG is given to the gate (transfer gate) through the transfer control line LTx.
Thereby, the electrons photoelectrically converted by the photoelectric conversion element 11 are transferred to the floating diffusion FD.

The reset transistor 13 is connected between the power supply line LVDD and the floating diffusion FD, and a reset signal RST is given to the gate through the reset control line LRST.
As a result, the potential of the floating diffusion FD is reset to the potential of the power supply line LVDD.

The gate of the amplification transistor 14 is connected to the floating diffusion FD. The amplification transistor 14 is connected to the signal line 16 via the selection transistor 15, and constitutes a constant current source and a source follower outside the pixel portion.
Then, an address signal (selection signal) SEL is given to the gate of the selection transistor 15 through the selection control line LSEL, and the selection transistor 15 is turned on.
When the selection transistor 15 is turned on, the amplification transistor 14 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line 16. The voltage output from each pixel through the signal line 16 is output to a column circuit (column processing circuit).

This pixel reset operation means that the charge accumulated in the photoelectric conversion element 11 is turned on by transferring the transfer transistor 12 and the charge accumulated in the photoelectric conversion element 11 is transferred to the floating diffusion FD.
At this time, the floating diffusion FD turns on the reset transistor 13 so as to receive the electric charge of the photoelectric conversion element 11 in advance, and releases the electric charge to the power supply side. Alternatively, while the transfer transistor 12 is turned on, the reset transistor 13 is turned on in parallel with the transfer transistor 12 to directly charge the power supply.
These series of operations are simplified and referred to as “pixel reset operation” or “shutter operation”.

On the other hand, in the read operation, first, the reset transistor 13 is turned on to reset the floating diffusion FD, the reset transistor 13 is turned off, and the signal is output to the output signal line 16 through the selection transistor 15 turned on in that state. This is called P-phase output.
Next, the transfer transistor 12 is turned on to transfer the charge accumulated in the photoelectric conversion element 11 to the floating diffusion FD, and the output is output to the output signal line 16. This is called D-phase output.
The difference between the D-phase output and the P-phase output is taken outside the pixel circuit, and the reset noise of the floating diffusion FD is canceled to obtain an image signal.
For simplicity, these series of operations are simply referred to as “pixel readout operations”.

  FIG. 2 is a diagram illustrating a general configuration example of a CMOS image sensor (solid-state imaging device) in which the pixels of FIG. 1 are arranged in a two-dimensional array.

  A CMOS image sensor 20 in FIG. 2 includes a pixel array unit 21 in which the pixel circuits shown in FIG. 1 are arranged in a two-dimensional array, a pixel driving circuit (vertical scanning circuit) 22, and a column circuit (column processing circuit) 23. Has been.

  The pixel drive circuit 22 controls on / off of the transfer transistor 12 reset transistor 13 and the selection transistor 15 of each row of pixels.

  The column circuit 23 is a circuit that receives data of a pixel row that is controlled to be read out by the pixel driving circuit 22 and transfers the data to a signal processing circuit at a subsequent stage.

The CMOS image sensor having such a configuration has a plurality of drive modes.
An example of the drive mode of the CMOS image sensor is shown below.
As a driving mode of the CMOS image sensor, an all-pixel reading mode, a variable window cutting mode, a horizontal / vertical 2 × 2 line addition reading mode, and a vertical ½ thinning reading mode are known.

In the all pixel readout mode, all pixels are read out.
In the variable window cutout mode, arbitrary horizontal and vertical areas are cut out from all pixels, and the window areas are read out.

  In the horizontal / vertical 2 × 2 line addition readout mode, the pixels are read out after addition in the same color of RGB, 2 pixels in the horizontal direction, 2 pixels in the vertical direction. This mode is used at low illumination. The pixel density is 1/4.

  In the vertical ½ thinning readout mode, readout is performed by thinning the vertical direction of the pixels by ½. In this mode, the vertical area is halved.

  3A to 3C are diagrams showing output formats of the CMOS image sensor.

The output format (Format) of the CMOS image sensor includes 1DDR, 1SDR, and 2SDR, as shown in FIGS.
A circuit (such as a DSP) that captures image data output from the CMOS image sensor performs data capture according to the output format.

  In the case of the 1DDR output format, as shown in FIG. 3 (A), the output data MUXDATA0 is fetched by the output clock MUXDCK of 1/2 cycle at one port.

  In the case of the 1SDR output format, as shown in FIG. 3B, the output data MUXDATA0 is fetched with the output clock MUXDCK having the same cycle at one port.

  In the case of the 2SDR output format, as shown in FIG. 3C, the output data MUXDATA0 and MUXDATA1 are fetched by the output clock MUXDCK having the same cycle in two ports.

  In the CMOS image sensor, the frame rate (Frame_Rate: N_Frame / Sec) is selected from the combination of the drive mode, the output format, and the master clock for image transfer (Master Clock), and from the pixel area (H x V) of 1 frame, The period of the output clock is determined.

For example, when the specification is that the master clock frequency is 100 MHz, the frame rate is 30 frames / second, the output format is 1 SDR, the pixel area of 1 frame is 1600 pixels in the horizontal direction (H), and 1000 pixels in the vertical direction (V), The period of the output clock is as follows.
Since the number of pixels in one frame is 1,600,000 and the number of pixels in one second is 48,000,000 (= 48M), the output clock cycle is 1 / 48M, that is, 20.8nsec. (Sec).
JP 2004-166269 A

  Incidentally, in the CMOS image sensor, there are cases where two master clocks MCK for transferring image data are used, one for asynchronous high transfer rate and one for low transfer rate.

  FIG. 4 is a timing chart when two asynchronous high transfer rate and low transfer rate are used as the master clock for image transfer.

In FIG. 4, in the clock switching Case1, the negative pulse width of the clock Clock1 disappears.
In Clock switching Case2, the positive pulse width of clock Clock2 becomes narrower.
In Clock switching Case 3, the positive pulse width of clock Clock 2 becomes narrower.
In Clock switching Case4, the negative pulse width of clock Clock1 becomes wide.

  In the case of FIG. 4, there are the following problems in switching the frame rate in the asynchronous master clocks MCK1 and MCK2.

A hazard occurs when the master clock MCK is switched during image data transfer.
The normal pulse width, period, and clock duty (Clock_Duty) cannot be compensated at the start of output clock generation. As a result, the display image may be distorted.
The operation mode switching trigger cannot be detected by the circuit (DSP, etc.) that receives the image data.
If an irregular output clock is used, a malfunction may occur in, for example, 1H line or 1 line.

  FIG. 5 is a timing chart when a single master clock for image transfer is used.

In FIG. 5, in the clock switching Case 1, the positive pulse width of divide by 4 is widened.
In Clock switching Case 2, the negative pulse width divided by 2 disappears.
In Clock switching Case3, the negative pulse width of 4 divisions disappears.
In Clock switching Case4, the negative pulse width of 8 division is narrowed.

  In the case of FIG. 5, there is the following problem when the frame rate is switched in one master clock MCK1.

The normal pulse width, period, and clock duty cannot be compensated at the start of output clock generation. As a result, the display image may be distorted.
The operation mode switching trigger cannot be detected by the circuit (DSP, etc.) that receives the image data.
If an irregular output clock is used, a malfunction may occur in, for example, 1H line or 1 line.

  The present invention provides a solid-state imaging device capable of realizing a normal period and a clock duty with a pulse having no hazard in an output clock when a frame rate is changed during image transfer, and eliminating distortion of a display image. It is to provide a camera system.

  A solid-state imaging device according to a first aspect of the present invention includes a pixel unit in which a plurality of pixel circuits having a mechanism for converting an optical signal into an electrical signal and storing the electrical signal in accordance with an exposure time are arranged in a matrix. , A pixel drive unit that can be driven to read out image data of the pixel unit, and control to transfer the read image data using an operation clock corresponding to a frequency selected according to at least one master clock A clock controller that stops the master clock when the frame rate is switched, and supplies the master clock after the operation clock is selected while the master clock is stopped. The operation clock is output with a normal pulse width, period and clock duty adapted to the changed frame rate.

  Preferably, when transferring image data using a plurality of master clocks having different frequencies, the clock control unit stops the master clock when the frame rate is switched, and the new master clock is stopped while the master clock is stopped. After selecting the clock and the operation clock, the selected new master clock is supplied, and the operation clock is output with a normal pulse width, period, and clock duty adapted to the changed frame rate.

  Preferably, when transferring the image data using one master clock, the clock control unit stops the master clock at the switching of the frame rate, and selects the operation clock while the master clock is stopped. After that, the master clock is supplied again, and the operation clock is output with a normal pulse width, period, and clock duty adapted to the changed frame rate.

  Preferably, the pixel circuit includes an output node, a photoelectric conversion element that converts an optical signal into an electric signal and accumulates a signal charge, and is turned on and off by the transmission signal, and charges the photoelectric conversion element in an on state. A transfer element that transfers the output node; and a reset element that is turned on and off by the second reset signal and resets the output node in the on state.

  Preferably, the pixel unit includes a pixel signal readout circuit that reads out pixel signals in units of a plurality of pixels, and the pixel signal readout circuit is supplied with the operation clock and is arranged corresponding to the column arrangement of pixels. A plurality of comparators that compare and determine the read signal potential and the reference voltage and output the determination signal, and a plurality of comparators that control the operation to the output of the comparator and count the comparison time of the corresponding comparator. A counter and a latch for latching the output of the counter.

  A camera system according to a second aspect of the present invention includes a solid-state imaging device, an optical system that forms a subject image on the imaging device, and a signal processing circuit that processes an output image signal of the imaging device, The solid-state imaging device includes a pixel unit in which a plurality of pixel circuits having a mechanism for converting an optical signal into an electrical signal and storing the electrical signal according to an exposure time are arranged in a matrix, and image data of the pixel unit A pixel driver that can be driven so as to perform reading, and a clock controller that controls the read image data to be transferred using an operation clock corresponding to a frequency selected according to at least one master clock. And the clock control unit stops the master clock by switching the frame rate, selects the operation clock while the master clock is stopped, and then selects the master clock. It performs supply, the pulse width of the normal adapted to the frame rate after the change period and outputs the operation clock in the clock duty.

According to the present invention, the master clock is stopped by switching the frame rate in the clock control unit.
Then, the clock controller supplies the master clock after selecting the operation clock while the master clock is stopped. Next, the clock control unit outputs an operation clock with a normal pulse width, period, and clock duty adapted to the changed frame rate.

  According to the present invention, when the frame rate is changed during image transfer, a normal cycle and clock duty can be realized with pulses having no hazard in the output clock, and distortion of the display image can be eliminated.

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 6 is a diagram illustrating a configuration example of a CMOS image sensor (solid-state imaging device) according to the embodiment of the present invention.

  The CMOS image sensor 100 includes a pixel array unit 110, a vertical scanning circuit 120 as a pixel driving unit, a horizontal scanning circuit 130, a column readout circuit 140, a control unit 150, a data processing unit 160, and a clock control unit 170.

In the pixel array section 110, a plurality of pixel circuits 110A are arranged in a two-dimensional form (matrix form).
In addition, the solid-state imaging device 100 includes a configuration unit as a control system for sequentially reading signals from the pixel array unit 110.
That is, the solid-state imaging device 100 includes a control unit 150 including an internal clock and clock control unit 170, a vertical scanning circuit 120 that controls row addresses and row scanning, a horizontal scanning circuit 130 that controls column addresses and column scanning, and column readout. A circuit 140 is arranged.
The clock control unit 170 arranged in the control unit 150 will be described in detail later.

  FIG. 7 is a diagram illustrating an example of a pixel of a CMOS image sensor including four transistors according to the present embodiment.

The pixel circuit 110A includes a photoelectric conversion element 111 made of, for example, a photodiode.
The pixel circuit 110 </ b> A has four transistors, which are a transfer transistor 112, a reset transistor 113, an amplification transistor 114, and a selection transistor 115, as active elements for the one photoelectric conversion element 111.

The photoelectric conversion element 111 photoelectrically converts incident light into an amount of electric charges (here, electrons) corresponding to the amount of light.
The transfer transistor 112 is connected between the photoelectric conversion element 111 and the floating diffusion FD as an output node, and a transmission signal TG as a control signal is given to a gate (transfer gate) through the transfer control line LTx.
Thereby, the transfer transistor 112 transfers the electrons photoelectrically converted by the photoelectric conversion element 111 to the floating diffusion FD.

The reset transistor 113 is connected between the power supply line LVDD and the floating diffusion FD, and a reset signal RST that is a control signal is given to the gate of the reset transistor 113 through the reset control line LRST.
As a result, the reset transistor 113 resets the potential of the floating diffusion FD to the potential of the power supply line LVDD.

The gate of the amplification transistor 114 is connected to the floating diffusion FD. The amplification transistor 114 is connected to the signal line 116 via the selection transistor 115, and constitutes a constant current source and a source follower outside the pixel portion.
A selection signal SEL, which is a control signal corresponding to the address signal, is supplied to the gate of the selection transistor 115 through the selection control line LSEL, and the selection transistor 115 is turned on.
When the selection transistor 115 is turned on, the amplification transistor 114 amplifies the potential of the floating diffusion FD and outputs a voltage corresponding to the potential to the signal line 116. The voltage output from each pixel through the signal line 116 is output to the column readout circuit 140.
These operations are performed simultaneously for each pixel for one row because, for example, the gates of the transfer transistor 112, the reset transistor 113, and the selection transistor 115 are connected in units of rows.

A reset control line LRST, a transfer control line LTx, and a selection control line LSEL wired to the pixel array unit 110 are wired as a set for each row of the pixel array.
These reset control line LRST, transfer control line LTx, and selection control line LSEL are driven by the vertical scanning circuit 120.

  The vertical scanning circuit 120 has a function of specifying a row when performing a shutter operation / reading operation of the solid-state imaging device.

The column readout circuit 140 receives the pixel row data controlled to be read out by the vertical scanning circuit 120, and transfers the readout data to the subsequent data processing unit 160 via the horizontal scanning circuit 130.
The column readout circuit 140 has a function of performing signal processing such as correlated double sampling (CDS).

  Hereinafter, a specific configuration and function of the clock control unit 170 according to the present embodiment will be described.

As driving modes of the CMOS image sensor, for example, there are an all-pixel reading mode, a variable window cutting mode, a horizontal / vertical 2 × 2 line addition reading mode, and a vertical 1/2 thinning reading mode.
The output format (Format) of the CMOS image sensor includes 1DDR, 1SDR, and 2SDR, as shown in FIGS.
A circuit (such as a DSP) that captures image data output from the CMOS image sensor performs data capture according to the output format.

  In the CMOS image sensor, the frame rate (Frame_Rate: N_Frame / Sec) is selected from the combination of the drive mode, the output format, and the master clock for image transfer (Master Clock), and from the pixel area (H x V) of 1 frame, The period of the output clock is determined.

  The clock controller 170 is configured such that when the frame rate is changed during image transfer, a normal cycle and clock duty can be realized with a pulse having no hazard in the output clock, and distortion of the display image can be eliminated. ing.

  Specifically, the clock control unit 170 is configured to perform the following characteristic processing.

<Process when transferring image data using two or more master clocks MCK>
(1). The master clock MCK is stopped when the frame rate is switched.
(2) The receiving circuit (DSP or the like) can detect the stop period of the master clock MCK as a trigger for changing the frame rate by sampling with the clock used.
(3). While the master clock MCK is stopped, a new master clock and operation clock are selected.
(4) After that, the master clock MCK is switched to a new master clock MCK, and the operation clock CLK is output with a normal pulse width, period and clock duty adapted to the changed frame rate.

<Processing when image data is transferred with one master clock MCK>
(1). The master clock MCK is stopped when the frame rate is switched.
(2) The receiving circuit (DSP or the like) can detect the stop period of the master clock MCK as a trigger for changing the frame rate by sampling with the clock used.
(3). The operation clock is selected while the master clock MCK is stopped.
(4) After that, the master clock MCK is supplied again, and the operation clock CLK is output with a normal pulse width, period and clock duty adapted to the changed frame rate.

  Hereinafter, the control content of the clock switching timing in the clock control unit 170 will be described in more detail with reference to FIGS.

FIG. 8 is a diagram illustrating a configuration example of a master clock switching circuit in the clock control unit according to the present embodiment.
FIG. 9 is a diagram illustrating a configuration example of an operation clock generation circuit in the clock control unit according to the present embodiment.
FIG. 10 is a timing chart of the circuit of FIG.
FIG. 11 is a timing chart of the entire clock control unit.

The master clock switching circuit 180 of FIG. 8 includes a master clock selection register (MCLOCK_SEL_reg [6: 0]) 181, a first master clock selection unit (Master_Clock1_Sel) 182, and a second master clock selection unit (Master_Clock2_Sel) 183.
Master clock switching circuit 180 further includes latches 184 and 185, AND gates 186 and 187, and OR gate 188.

For example, seven registers REG0 to REG6 are cascade-connected to the master clock selection register 181.
The registers REG0 to REG6 and latches 184 and 185 are formed by D-type flip-flops.
The registers REG0 to REG7 and the latch 184 are supplied to the clock terminals using the first master clock MCK1 as a clock. The latch 185 is supplied to the clock terminal using the second master clock MCK2 as a clock.
The D input of the latch 184 is connected to the output of the first master clock selection unit (Master_Clock1_Sel) 182, and the D input of the latch 185 is connected to the output of the second master clock selection unit (Master_Clock2_Sel) 183.
One input of the AND gate 186 is connected to the Q output of the latch 184, and the other input is connected to the supply line of the first master clock MCK1.
One input of the AND gate 187 is connected to the Q output of the latch 185, and the other input is connected to the supply line of the second master clock MCK2.
The outputs of the AND gates 186 and 187 are connected to the input of the OR gate 188, respectively. The master clock selected from the OR gate 188 is output to the operation clock generation circuit 190 of FIG. 9 as an output Master_Clock_out1 or Master_Clock_out2.

The operation clock generation circuit 190 includes a register (muxdckreg) 191 for outputting the operation clock MUXDCK, a synchronous hexadecimal counter 192, a clock division ratio selection decoder 193, AND gates 194 to 199, and an OR gate 200.
FIG. 9 shows a correspondence table 210 of the 3-bit clock selection signal MUXSEL and the decoding result.
The register 191 is formed by a D-type flip-flop.
The D input of the register 191 is connected to the output of the OR gate 200, and the master clock MCK output as Master_Clock_out1 or Master_Clock_out2 from the OR gate 188 of FIG. 8 is supplied to the clock terminal.
Further, the master clock MCK output as Master_Clock_out1 or Master_Clock_out2 from the OR gate 188 in FIG. 8 is also supplied to the clock terminal of the synchronous hex counter 192.

A clear signal xclr is supplied to the clear terminals of the register 191 and the synchronous 64-ary counter 192.
The decoder 193 decodes the frequency division ratio of the clock and outputs the result to the corresponding AND gates 194 to 199.
In the present embodiment, 256 MHz is used as the frequency of the master clock MCK. Then, the frequency is divided into 128 MHz, 64 MHz, 32 MHz, 16 MHz, 8 MHz, and 4 MHz.

One input of the AND gates 194 to 199 is supplied with the corresponding result of the synchronous hex counter 192, and the other input is supplied with the corresponding decoding result of the decoder 193.
The outputs of the AND gates 194 to 199 are connected to the inputs of the OR gate 200.

  Next, the clock switching operation with the above configuration will be described.

When the frame rate is changed during image data transfer, as shown in FIG. 11, the D input (Din) of the register (muxdckreg) 191 is set to 0, and the Q output of the register (muxdckreg) 191 is set to 0 by the master clock MCK. To. That is, the output clock is fixed to 0.
Next, after the Q output of the register (muxdckreg) 191 is set to 0, the supply of the master clock MCK is stopped.
A new master clock MCK corresponding to the changed frame rate is selected during the stop period of the master clock MCK.

The selection of the master clock MCK is performed as shown below (FIG. 10).
The master clocks MCK1 and MCK2 are selected by the master clock selection signal MCLOCK_SEL.
The master clock selection signal MCLOCK_SEL is scanned by the high-speed first master clock MCK1 and continuously held in the master clock selection register (MCLOCK_SEL_reg [6: 0]) 181.

The value of the master clock register (MCLOCK_SEL_reg [6: 0]) 181 is 7Fh, and the first master clock selection unit (Master_Clock1_Sel) 182 selects the first master clock MCK1.
The value of the master clock register (MCLOCK_SEL_reg [6: 0]) 181 is 00h, and the second master clock selection unit (Master_Clock2_Sel) 183 selects the second master clock MCK2.

The output signal of the first master clock selection unit (Master_Clock1_Sel) 182 is taken into the latch 184 at the falling timing of the first master clock MCK1.
The master clock output Master_Clock_out1 is output as an AND of the first master clock MCK1 and the latch 184, and no positive pulse width reduction occurs.
The output signal of the second master clock selection unit (Master_Clock2_Sel) 183 is taken into the latch 185 at the falling timing of the second master clock MCK2.
The master clock output Master_Clock_out2 is output as an AND of the second master clock MCK2 and the latch 185, and the positive pulse width is not reduced.

Since the master clock register (MCLOCK_SEL_reg [6: 0]) 181 has a 7-bit configuration, the output signal of the first master clock selection unit (Master_Clock1_Sel) 182 and the output signal of the second master clock selection unit (Master_Clock2_Sel) 183 are valid at the same time. It will not be.
The output Master_Clock_out of the OR gate 188 is output as either Master_Clock_out1 or Master_Clock_out2.

In addition, during a period in which the supply of the master clock MCK is stopped, the decoder 193 having a master clock frequency division ratio of 1/2 to 1/64 is selected for the output clock MUXDCK corresponding to the changed frame rate.
The output clock MUXDCK is selected by the clock selection signal MUXSEL = 0, 1, 2, 3, 4, 5 and corresponds to mux 4, 8, 16, 32, 64, 128.
In this example, the synchronous 64-hexadecimal counter 192 is divided into 128, 64, 32, 16, 8, 4 MHz from the frequency of the master clock MCK = 256 MHz.
The output clock MUXDCK is selected by AND of mux4, 8, 16, 32, 64, 128 and 128, 64, 32, 16, 8, 4 MHz.

The output clock MUXDCK is output from the register 191 from the start of supply of the master clock MCK, and has a normal pulse width, cycle, and clock duty free from hazards.
Then, the pulse width of the output clock is not reduced and no instantaneous pulse interruption occurs, and the display image is not distorted in the first frame.

As described above, according to the present embodiment, the following effects can be obtained in the circuit configuration for capturing image data output from the CMOS image sensor.
By sampling the output clock with the clock used in the receiving circuit, a frame rate switching trigger can be generated.
Since the pulse rate of the output clock does not increase / decrease and the instantaneous interruption of the pulse does not occur when the frame rate is switched, the image data can be captured normally.

  Although the CMOS image sensor according to each embodiment is not particularly limited, for example, it may be configured as a CMOS image sensor equipped with a column parallel type analog-digital converter (hereinafter abbreviated as ADC (Analog digital converter)). Is possible.

  FIG. 12 is a block diagram illustrating a configuration example of a solid-state image pickup device (CMOS image sensor) with column-parallel ADCs according to the present embodiment.

As shown in FIG. 12, the solid-state imaging device 300 includes a pixel array unit 310 serving as an imaging unit, a vertical scanning circuit 320 serving as a pixel driving unit, a horizontal transfer scanning circuit 330, and a timing control circuit 340.
Further, the solid-state imaging device 300 includes an ADC group 350, a digital-analog converter (hereinafter abbreviated as DAC (Digital Analog converter)) 360, an amplifier circuit (S / A) 370, and a signal processing circuit 380.

The pixel section array 310 includes photodiodes and in-pixel amplifiers, for example, pixels as shown in FIG. 7 arranged in a matrix (matrix).
Further, in the solid-state imaging device 300, the following circuit is arranged as a control circuit for sequentially reading out signals from the pixel array unit 310.
That is, the solid-state imaging device 300 includes a timing control circuit 340 that generates an internal clock as a control circuit, a vertical scanning circuit 320 that controls row addresses and row scanning, and a horizontal transfer scanning circuit 330 that controls column addresses and column scanning. Be placed.

  The timing control circuit 340 includes a control unit 340 including the clock control unit 170 described with reference to FIGS.

In the ADC group 350, a plurality of ADCs each having a comparator 351, a counter 352, and a latch 353 are arranged.
The comparator 351 compares the reference voltage Vslop, which is a ramp waveform (RAMP) obtained by changing the reference voltage generated by the DAC 360 in a stepped manner, with an analog signal obtained from a pixel via a vertical signal line for each row line. To do.
The counter 352 counts the comparison time of the comparator 351.
The ADC group 350 has an n-bit digital signal conversion function and is arranged for each vertical signal line (column line) to constitute a column parallel ADC block.
The output of each latch 353 is connected to a horizontal transfer line 390 having a width of 2n bits, for example.
Then, 2n amplifier circuits 370 and signal processing circuits 380 corresponding to the horizontal transfer lines 390 are arranged.

In the ADC group 350, an analog signal (potential Vsl) read out to the vertical signal line is compared with a reference voltage Vslop (a linearly changing slope waveform having a certain slope) by a comparator 351 arranged for each column. The
At this time, the counter 352 arranged for each column is operating similarly to the comparator 351, and the potential of the vertical signal line (analogue) is changed by changing the potential Vslop having a ramp waveform and the counter value in a one-to-one correspondence. Signal) Vsl is converted into a digital signal.
The change in the reference voltage Vslop is to convert the change in voltage into a change in time, and is converted into a digital value by counting the time in a certain period (clock).
When the analog electric signal Vsl and the reference voltage Vslop intersect, the output of the comparator 351 is inverted, the input clock of the counter 352 is stopped, and AD conversion is completed.
After the above AD conversion period, the data held in the latch 353 is input to the signal processing circuit 380 via the horizontal transfer line 390 and the amplifier circuit 370 by the horizontal transfer scanning circuit 330, and a two-dimensional image is generated.
In this way, column parallel output processing is performed.

In the CMOS image sensor 300 having the clock controller 170, the column ADC clock uses a frequency of 218 MHz as the basic clock, performs AD conversion, and is stored in a memory (latch).
As the master clocks MCK1 and MCK2 for image data transfer, asynchronous frequency 218 MHz or 54 MHz is used, and the image data stored in the memory (latched) after AD conversion is taken in with the operation clock selected by changing the frame rate.

  A solid-state imaging device having such an effect can be applied as an imaging device for a digital camera or a video camera.

  FIG. 13 is a diagram illustrating an example of a configuration of a camera system to which the solid-state imaging device according to the embodiment of the present invention is applied.

  As shown in FIG. 13, the camera system 400 guides incident light to an imaging device 410 to which the CMOS image sensors (solid-state imaging devices) 100 and 300 according to the present embodiment can be applied, and a pixel region of the imaging device 410. An optical system (imaging a subject image), for example, a lens 420 that forms incident light (image light) on an imaging surface, a drive circuit (DRV) 430 that drives the imaging device 410, and an output signal of the imaging device 410 And a signal processing circuit (PRC) 440 for processing.

  The drive circuit 430 includes a timing generator (not shown) that generates various timing signals including a start pulse and a clock pulse that drive a circuit in the imaging device 410, and drives the imaging device 410 with a predetermined timing signal. .

In addition, the signal processing circuit 440 performs predetermined signal processing on the output signal of the imaging device 410.
The image signal processed by the signal processing circuit 440 is recorded on a recording medium such as a memory. The image information recorded on the recording medium is hard copied by a printer or the like. Further, the image signal processed by the signal processing circuit 440 is displayed as a moving image on a monitor including a liquid crystal display.

  As described above, in the imaging apparatus such as a digital still camera, by mounting the above-described imaging elements 100 and 300 as the imaging device 410, a highly accurate camera with low power consumption can be realized.

It is a figure which shows the pixel example of the CMOS image sensor comprised by four transistors. It is a figure which shows the general structural example of the CMOS image sensor (solid-state image sensor) which has arrange | positioned the pixel of FIG. 1 in the two-dimensional array form. It is a figure which shows the output format of a CMOS image sensor. 6 is a timing chart when two asynchronous high transfer rate and low transfer rate are used as master clocks for image transfer. 6 is a timing chart when one master clock for image transfer is used. It is a figure which shows the structural example of the CMOS image sensor (solid-state image sensor) which concerns on embodiment of this invention. It is a figure which shows an example of the pixel of the CMOS image sensor comprised by four transistors which concern on this embodiment. It is a figure which shows the structural example of the master clock switching circuit in the clock control part which concerns on this embodiment. It is a figure which shows the structural example of the operation clock generation circuit in the clock control part which concerns on this embodiment. FIG. 9 is a timing chart of the circuit of FIG. 8. It is a timing chart of the whole clock control part. It is a block diagram which shows the structural example of the column parallel ADC mounting solid-state image sensor (CMOS image sensor) which concerns on this embodiment. It is a figure which shows an example of a structure of the camera system with which the solid-state image sensor which concerns on embodiment of this invention is applied.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 100 ... Solid-state image sensor, 110 ... Pixel array part, 110A ... Pixel, 111 ... Photoelectric conversion element, 112 ... Transfer transistor, 113 ... Reset transistor, 114 ... Amplification transistor , 115 ... selection transistor, 120 ... vertical scanning circuit (pixel drive unit), 130 ... horizontal scanning circuit, 140 ... column readout circuit, 150 ... control unit, 160 ... data processing 170, clock control unit, 171 ... serial / parallel conversion unit, 172 ... data holding unit, 173 ... 1 frame delay update timing generation unit, 174 ... reflection control unit, 175 ..Gain holding unit, 176 ... switching unit, 180 ... master clock switching circuit, 181 ... master clock selection register (MCLOCK_SEL_reg [6: 0]) , 182 ... 1st master clock selection part (Master_Clock1_Sel), 183 ... 2nd master clock selection part (Master_Clock2_Sel), 184, 185 ... Latch, 186, 187 ... AND gate, 188 ... OR gate, 190... Operation clock generation circuit, 191... Register (muxdckreg), 192... Synchronous hex counter, 193... Clock division ratio selection decoder, 194 to 199. , 200... OR gate, 300... Solid-state image sensor, 310... Pixel array unit, 320... Vertical scanning circuit, 330. ... ADC group, 360 ... DAC, 370 ... Amplifier circuit (S / A), 380 ... Signal processing circuit, 400 ... Camera system, 10 ... imaging device, 420 ... lens, 430 ... driving circuit, 440 ... signal processing circuit.

Claims (6)

A pixel unit in which a plurality of pixel circuits having a mechanism for converting an optical signal into an electrical signal and storing the electrical signal according to an exposure time are arranged in a matrix;
A pixel driver that can be driven to read image data of the pixel unit;
A clock control unit for controlling the read image data to be transferred using an operation clock corresponding to a frequency selected according to at least one master clock;
The clock control unit
The master clock is stopped by switching the frame rate, and the master clock is supplied after the operation clock is selected while the master clock is stopped, and the normal pulse width, period, A solid-state image sensor that outputs the above operation clock with a clock duty. The clock control unit
When transferring image data using multiple master clocks with different frequencies, select the new master clock and operation clock after stopping the master clock by switching the frame rate and selecting the new master clock and operation clock while the master clock is stopped. The solid-state imaging device according to claim 1, wherein the new master clock is supplied and the operation clock is output with a normal pulse width, cycle, and clock duty adapted to the changed frame rate. The clock control unit
When transferring image data using one master clock, the master clock is stopped by switching the frame rate, and the master clock is supplied again after selecting the operation clock while the master clock is stopped. The solid-state imaging device according to claim 1, wherein the operation clock is output with a normal pulse width, period, and clock duty adapted to the changed frame rate. The pixel circuit is
An output node;
A photoelectric conversion element that converts an optical signal into an electrical signal and accumulates signal charges;
A transfer element that is turned on and off by the transmission signal and transfers the charge of the photoelectric conversion element to the output node in an on state;
The solid-state imaging device according to claim 1, further comprising: a reset device that is turned on and off by the second reset signal and resets the output node in an on state. A pixel signal readout circuit that reads out pixel signals from the pixel unit in units of a plurality of pixels;
The pixel signal readout circuit is
The above operating clock is supplied,
A plurality of comparators that are arranged corresponding to the column arrangement of pixels, compare and determine a read signal potential and a reference voltage, and output the determination signal;
A plurality of counters whose operation is controlled by the outputs of the comparators and counting the comparison time of the corresponding comparators;
The solid-state imaging device according to claim 4, further comprising: a latch that latches an output of the counter. A solid-state image sensor;
An optical system for forming a subject image on the image sensor;
A signal processing circuit for processing an output image signal of the imaging device,
The solid-state imaging device is
A pixel unit in which a plurality of pixel circuits having a mechanism for converting an optical signal into an electrical signal and storing the electrical signal according to an exposure time are arranged in a matrix;
A pixel driver that can be driven to read image data of the pixel unit;
A clock control unit for controlling the read image data to be transferred using an operation clock corresponding to a frequency selected according to at least one master clock;
The clock control unit
The master clock is stopped by switching the frame rate, and the master clock is supplied after the operation clock is selected while the master clock is stopped, and the normal pulse width, period, A camera system that outputs the above operating clock with a clock duty.

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