JP2010004347A - Multiantenna receiving circuit and multiantenna receiver and multiantenna receiving method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To increase the speed of the synthesis of signals received by a plurality of antennas. <P>SOLUTION: A multiantenna receiving circuit includes: a plurality of down converters frequency-converting receiving signals output from each of a plurality of the antennas respectively; and a plurality of power detecting circuit detecting the power values of the frequency-converted signals respectively. The multiantenna receiving circuit further includes: a comparison circuit generating phase control signals indicating phase correction quantities to each of the frequency-converted signals according to the power values detected by each of a plurality of the power detectors; a plurality of phase correction circuits correcting phases to the frequency-converted signals respectively according to the phase control signals; and a synthetic circuit synthesizing the signals corrected by each of a plurality of the phase correction circuits. The comparison circuit determines relationships among the power values and the phase correction quantities according to the detected power values, and finds the phase correction quantities to each of the frequency-converted signals by using the relationships from the power values detected regarding the signals. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a multi-antenna reception technique for receiving a signal using a plurality of antennas.

  There is known a multi-antenna receiving apparatus that combines signals received by a plurality of antennas. FIG. 14 is a block diagram illustrating a configuration example of a conventional receiving apparatus. The receiving apparatus in FIG. 14 is described in Patent Document 1 below.

  Signals received by the antennas 91A and 91B in FIG. 14 are input to the phase synthesis circuit 93A via a matching circuit and a low noise amplifier (LNA). The phase synthesis circuit 93A synthesizes and outputs the signal received by the antenna 91A and the signal received by the antenna 91B. At this time, the phase synthesizing circuit 93A shifts the phase of the signal received by the antenna 91B in accordance with an instruction from the phase control unit 95 so that the level of the synthesized signal becomes maximum.

  The phase synthesis circuit 93B synthesizes and outputs the output signal of the phase synthesis circuit 93A and the signal received by the antenna 91C. At this time, the phase synthesis circuit 93B shifts the phase of the signal received by the antenna 91C so that the level of the synthesized signal becomes maximum. The phase synthesis circuit 93C synthesizes the output signal of the phase synthesis circuit 93B and the signal received by the antenna 91D and outputs the synthesized signal to the reception unit 94. At this time, the phase combining circuit 93C shifts the phase of the signal received by the antenna 91D so that the level of the combined signal becomes maximum.

Patent Document 2 listed below describes a receiving apparatus that corrects a phase shift that occurs in a receiving amplifier. This receiving apparatus refers to a table for obtaining a phase amount to be shifted from the gain of the receiving amplifier for phase control.
JP-A-9-321526 (FIG. 7) Japanese Patent Laid-Open No. 11-46113 (FIG. 1)

  However, since the receiving apparatus of FIG. 14 repeats combining two signals while performing phase control so that the level of the combined signal is maximized, a signal obtained by combining the reception signals from all antennas is obtained. It takes a long time to get it. For this reason, high-speed operation is difficult. The receiving apparatus of Patent Document 2 requires a table in which the gain of the receiving amplifier is associated with the phase amount to be shifted. For this reason, when using a table prepared in advance, the receiving apparatus needs to be used in an environment to which the table can be applied. Further, it is considered that the table may be created every time the receiving apparatus is used, but in this case, there is a problem that it takes time to create the table at the start of use of the receiving apparatus. For this reason, it is impossible to respond to a request to communicate anywhere anytime.

  An object of the present invention is to speed up the synthesis of signals received by a plurality of antennas.

  A multi-antenna receiving circuit according to the present invention includes: a plurality of down-converters that respectively perform frequency conversion on reception signals output from a plurality of antennas and output frequency-converted signals; and a power value of the frequency-converted signals. And a comparison circuit for generating a phase control signal indicating a phase correction amount for each of the frequency-converted signals according to a power value detected by each of the plurality of power detection circuits. A plurality of phase correction circuits that respectively perform phase correction on the frequency-converted signal according to the phase control signal, and a synthesis circuit that combines the signals corrected by the plurality of phase correction circuits. The comparison circuit determines a relationship between a power value and a phase correction amount according to a power value detected by the plurality of power detection circuits, and determines a phase correction amount for each of the frequency converted signals for the signal. It calculates | requires using the said relationship from the detected electric power value, and produces | generates the said phase control signal which shows the calculated | required phase correction amount.

  According to this, since the received signal is phase-corrected by the phase correction amount determined by the comparison circuit and the corrected signal is synthesized, there is no need to feedback control the phase. For this reason, the time required to obtain a synthesized signal can be shortened.

  The multi-antenna receiving apparatus according to the present invention includes a plurality of antennas, a plurality of down-converters that respectively perform frequency conversion on reception signals output from the plurality of antennas, and output frequency-converted signals, and the frequency conversion A plurality of power detection circuits that respectively detect the power value of the received signal, and a phase control signal that indicates a phase correction amount for each of the frequency converted signals according to the power value detected by each of the plurality of power detection circuits And a plurality of phase correction circuits that respectively perform phase correction on the frequency-converted signal according to the phase control signal, and a signal corrected by each of the plurality of phase correction circuits. And a synthesis circuit. The comparison circuit determines a relationship between a power value and a phase correction amount according to a power value detected by the plurality of power detection circuits, and determines a phase correction amount for each of the frequency converted signals for the signal. It calculates | requires using the said relationship from the detected electric power value, and produces | generates the said phase control signal which shows the calculated | required phase correction amount.

  The multi-antenna reception method according to the present invention includes a down-conversion step for frequency-converting a reception signal output from each of a plurality of antennas, a power detection step for detecting a power value of the frequency-converted signal, and the power detection A step of generating a phase control signal indicating a phase correction amount for each of the frequency converted signals according to the power value detected in the step; and a phase correction for the frequency converted signal according to the phase control signal And a synthesis step for synthesizing the signals corrected in the phase correction step. The comparison step determines a relationship between the power value and the phase correction amount according to the power value detected in the power detection step, and the phase correction amount for each of the frequency converted signals is detected for the signal. The phase control signal is obtained from the obtained power value using the relationship and the phase control signal indicating the obtained phase correction amount is generated.

  According to the present invention, it is not necessary to prepare a table for obtaining the phase amount to be shifted, and phase correction is performed in parallel with respect to the received signals of the respective antennas. Can be

  Hereinafter, embodiments of the present invention will be described with reference to the drawings.

  FIG. 1 is a block diagram illustrating a first configuration example of a multi-antenna reception apparatus according to an embodiment of the present invention. 1 includes antennas 2A, 2B, 2C, down converters 12A, 12B, 12C, AD converters (ADC) 14A, 14B, 14C, phase correction circuits 16A, 16B, 16C, and a demodulation circuit. 18A, 18B, 18C, a synthesis circuit 22, power detection circuits 24A, 24B, 24C, and a comparison circuit 26. In the multi-antenna receiving apparatus of FIG. 1, the parts other than the antennas 2A, 2B, and 2C constitute a multi-antenna receiving circuit.

  The down converter 12A, the AD converter 14A, the phase correction circuit 16A, the demodulation circuit 18A, and the power detection circuit 24A constitute a first branch. Similarly, the down converter 12B, the AD converter 14B, the phase correction circuit 16B, the demodulation circuit 18B, and the power detection circuit 24B constitute a second branch, and the down converter 12C, the AD converter 14C, the phase correction circuit 16C, and the demodulation circuit. The 18C and the power detection circuit 24C constitute a third branch. Although the apparatus of FIG. 1 has three antennas and three branches, it may have more antennas and branches.

  The down converters 12A to 12C in FIG. 1 respectively convert the signals received by the antennas 2A to 2C into intermediate frequency signals. The frequency of the received signal is, for example, 60 GHz, and the intermediate frequency is, for example, 2 GHz. The power detection circuits 24A to 24C respectively detect the power values of the reception signals converted into intermediate frequencies by the down converters 12A to 12C, and compare the voltages indicating the detected power values as detection voltages V1, V2, and V3, respectively. It outputs to the circuit 26. The comparison circuit 26 generates phase control signals for controlling the phase correction circuits 16A to 16C according to the detection voltages V1 to V3.

  The AD conversion circuits 14A to 14C convert the reception signals converted to the intermediate frequency by the down converters 12A to 12C into digital signals, respectively, and output the digital signals to the phase correction circuits 16A to 16C, respectively. The phase correction circuits 16A to 16C perform phase control on each signal after AD conversion according to the phase control signal, and output the result to the demodulation circuits 18A to 18C, respectively.

  The demodulating circuits 18 </ b> A to 18 </ b> C demodulate the signals input thereto and output the demodulation results to the combining circuit 22. The synthesizing circuit 22 simultaneously synthesizes the demodulated results from the demodulating circuits 18A to 18C and outputs the obtained result.

  The synthesizing circuit 22 may obtain correct received data by a majority decision between the demodulation results of the demodulation circuits 18A to 18C, that is, a majority decision between 3 bits. As described above, the synthesis circuit 22 may perform simple error correction.

  FIG. 2 is an explanatory diagram for explaining a first example of control in the comparison circuit 26 of FIG. FIG. 3 is a flowchart showing the flow of processing in each branch of FIG. FIG. 2 shows the relationship between the power (received power) value of the input signal and the corresponding output voltage for the power detection circuits 24A to 24C.

  For example, suppose that there is a signal G1 received without being reflected, a signal G2 received after being reflected once, and a signal G3 received after being reflected twice. Among these, the received signal that has not been reflected is the strongest signal, and the amount of phase rotation is very small. The received signal reflected twice is the most attenuated signal, and the phase is most rotated. When the strongest received signal is used as a reference, the phase of the minimum received signal is delayed, so the phase of the minimum received signal needs to be advanced.

  In FIG. 2, it is assumed that the reception signals of the power detection circuits 24A to 24C are represented by signals G1, G2, and G3, respectively. Of the signals G1, G2, and G3, it is assumed that the reception power of the signal G1 is the maximum and the reception power of the signal G3 is the minimum.

  The comparison circuit 26 determines the relationship between the power value and the phase correction amount according to the power value detected by the power detection circuits 24A to 24C. Specifically, the comparison circuit 26 obtains the maximum value Vt1 and the minimum value Vt3 as reference voltages from the detection voltages of the power detection circuits 24A to 24C. As shown in FIG. 2, the maximum value Vt1 corresponds to the reception signal G1, and the minimum value Vt3 corresponds to the reception signal G3. Next, the comparison circuit 26 obtains an average value Vt2 of the maximum value Vt1 and the minimum value Vt3 as a threshold voltage, divides the interval between the maximum value Vt1 and the minimum value Vt3 into two sections by the average value Vt2, and Vt2 < A phase correction amount SF = 0 ° is assigned to Vn ≦ Vt1, and a phase correction amount SF = 180 ° is assigned to Vt3 <Vn ≦ Vt2.

  Thereafter, with respect to the first branch of FIG. 1, the process of FIG. 3 is performed as follows (in this case, n = 1). In step S2 of FIG. 3, the power detection circuit 24A detects the received power value. In step S4, the comparison circuit 26 determines whether or not the detection voltage Vn satisfies Vt2 <Vn ≦ Vt1. If it is satisfied, the comparison circuit 26 generates a phase control signal indicating that the phase correction amount SF is 0 ° so that the phase correction is not performed, and performs the process of step S6. In other cases, the process of step S8 is performed.

  In step S8, the comparison circuit 26 generates a phase control signal indicating that the phase correction amount SF is 180 ° so as to perform phase correction for advancing the phase by 180 °, and the phase correction circuit 16A follows the phase control signal. Then, phase correction is performed on the signal after AD conversion to advance the phase by 180 °. In step S <b> 6, the demodulation circuit 18 </ b> A demodulates and outputs the demodulation result to the synthesis circuit 22.

  The processing of FIG. 3 is similarly performed on the second and third branches of FIG. 1 (n = 2, 3 respectively). The processing of FIG. 3 in each branch is performed in parallel. Thereafter, the synthesis circuit 22 synthesizes the demodulation results obtained by the demodulation circuits 18A to 18C. As a result, for example, phase correction is not performed on the received signal G2, but when a received signal G2B having a detection voltage of Vt2 or less is received, phase correction is performed on the received signal G2B to advance the phase by 180 °. Is called.

  As described above, the multi-antenna receiving apparatus of FIG. 1 corrects the phase of the received and digitally converted signal by the phase correction amount determined by the comparison circuit, and synthesizes the corrected signal. Therefore, it is necessary to feedback control the phase. There is no. The combining circuit 22 combines signals received by all antennas at the same time. For this reason, the time required to obtain a synthesized signal can be shortened.

  In addition, the multi-antenna receiving apparatus of FIG. 1 uses the maximum value and the minimum value of the voltage corresponding to the received power value as the reference voltage, and equally divides between the two reference voltages, for each section obtained by the division. Assign a phase correction amount to. According to such a method, even when the interval between the two reference voltages is divided into many sections and the phase control resolution is made fine, the phase correction amount can be easily assigned. Further, it is not necessary to prepare a table indicating the relationship between the received power value and the phase correction amount in advance. Furthermore, there is no case where the effect of phase correction is obtained only in a limited reception situation as in the case of using a previously obtained table.

  In addition, although the case where the range between the maximum value Vt1 and the minimum value Vt3 is equally divided into two sections and different phase correction amounts are assigned to each of the sections has been described, the phase correction amount is divided into three or more sections and is different from each other. May be assigned. For example, the interval between the maximum value Vt1 and the minimum value Vt3 may be divided into a number of sections corresponding to the sampling speeds of the AD converters 14A to 14C. When the AD converters 14A to 14C perform, for example, double or triple oversampling, the AD converters 14A to 14C are divided into four sections or six sections. When the phase difference between the received signals is large, the S / N ratio can be further improved by dividing the received signal into many sections.

  FIG. 4 is a block diagram showing a second configuration example of the multi-antenna reception apparatus according to the embodiment of the present invention. The multi-antenna receiving apparatus of FIG. 4 is the same as the multi-antenna receiving apparatus of FIG. 1 except that the phase correction circuit 16A and the demodulation circuit 18A are interchanged, the phase correction circuit 16B and the demodulation circuit 18B are interchanged, and the phase correction circuit 16C and the demodulation circuit 18C. And the comparison circuit 226 is used in place of the comparison circuit 26.

  The comparison circuit 226 generates a phase control signal for controlling the phase correction circuits 16A to 16C according to the detection voltages V1 to V3 of the power detection circuits 24A to 24C, almost the same as the comparison circuit 26. The phase correction circuits 16A to 16C perform phase control on the signals after demodulation processing by the demodulation circuits 18A to 18C, respectively, according to the phase control signal output from the comparison circuit 226.

  When the phase correction is performed on the demodulated signal as in the multi-antenna reception apparatus of FIG. 4, the resolution of the phase control does not depend on the sampling speed of the AD converters 14A to 14C. When the resolution of the phase control does not have to be fine, such as near field communication (when the phase shift is either binary of 0 ° or 180 °), the configuration of FIG. 4 can be employed.

  FIG. 5 is an explanatory diagram showing an example of phase correction in the multi-antenna receiving apparatus of FIG. Assume that the signals DS1, DS2, and DS3 after AD conversion correspond to the signals G1, G2, and G3 in FIG. Since the signal DS1 having the maximum received power is the received signal having the smallest attenuation (short propagation distance), the phase of this signal is used as a reference. Since the signal DS3 having the smallest received power is the received signal having the largest attenuation (long propagation distance), the phase is rotated.

  Since the detection voltage V2 corresponding to the received power value of the signal DS2 is greater than the voltage Vt2, the phase correction circuit 16B does not perform phase correction on the signal DS2. Since the detection voltage V3 corresponding to the received power value of the signal DS3 satisfies Vt3 <Vn ≦ Vt2, the phase correction circuit 16C performs a 180 ° phase shift on the signal DS3 and outputs the signal DS3C.

  When the combining circuit 22 combines these signals DS1, DS2, DS3C, sufficient combined received power can be obtained. It can be seen that it is sufficient that the phase shift can only be either binary.

  FIG. 6 is an explanatory diagram for describing a second example of control in the comparison circuit 26 of FIG. In the case of FIG. 2, the phase correction amount is assigned according to the maximum value and the minimum value of the detection voltage indicating the power value of the received signal. However, when the difference between the maximum value and the minimum value is very small, it is difficult to assign the phase correction amount.

  Therefore, as shown in FIG. 6, the comparison circuit 26 uses the detection voltage corresponding to the reception signal GR with the maximum reception power as the reference voltage Vt1, and obtains threshold voltages Vt2 and Vt3 that are sequentially lower by a predetermined voltage ΔV than the reference voltage Vt1. , Vt2 <Vn ≦ Vt1 is assigned a phase correction amount SF = 0 °, and Vt3 <Vn ≦ Vt2 is assigned a phase correction amount SF = 180 °. The phase correction as shown in FIG. 6 is relatively easy to control, and is suitable for communication at an extremely short distance, that is, wireless communication under a condition where the probability that a signal is reflected is small and attenuation is small.

  The voltage ΔV may be a value corresponding to the reference voltage Vt1. Similarly, in the multi-antenna receiving apparatus of FIG. 4, the comparison circuit 226 may perform the control as shown in FIG.

  FIG. 7 is an explanatory diagram for explaining a third example of control in the comparison circuit 26 of FIG. In the case of FIG. 6, the maximum value of the detection voltage corresponding to the power value of the received signal is used as the reference voltage. However, when the detection signal is small, phase correction may not be possible.

  Therefore, as shown in FIG. 7, the comparison circuit 26 sets the detection voltage corresponding to the reception signal GR with the smallest reception power as the reference voltage Vt1, and sequentially increases the threshold voltages Vt2, Vt3, and Vt4 by a predetermined voltage ΔV from the reference voltage Vt1. For Vt1 <Vn ≦ Vt2, phase correction amount SF = −θ for Vt2 <Vn ≦ Vt3, phase correction amount SF = −2θ, and phase correction amount SF = −3θ for Vt3 <Vn ≦ Vt4. assign. Here, θ = 360 ° / k (k is a natural number). The phase correction as shown in FIG. 7 is suitable for long-distance communication, that is, wireless communication under a condition where all signals are reflected and attenuation is large.

  The voltage ΔV may be a value corresponding to the reference voltage Vt1. For example, the voltage ΔV may be increased as the voltage Vt1 is decreased.

  FIG. 8 is an explanatory diagram for explaining a fourth example of control in the comparison circuit 26 of FIG. 2, 6, and 7, when the received power of signals other than the reference received signal is concentrated in the vicinity of a value that is significantly different from the received power of the reference received signal. May not be able to properly assign the phase delay amount.

  Therefore, as shown in FIG. 8, the comparison circuit 26 sets the detection voltage corresponding to the reception signal GR having the reception power value closest to the average value VAV of the reception power of each reception signal as the reference voltage VR, and sequentially from the reference voltage VR. The threshold voltages Vt1 and Vt2 that are higher by the predetermined voltage ΔV and the threshold voltages Vt1 ′ and Vt2 ′ that are lower by the predetermined voltage ΔV in order from the reference voltage VR are obtained. Further, the comparison circuit 26 sets the phase correction amount SF = −180 ° when Vt1 <Vn ≦ Vt2, sets the phase correction amount SF = 0 ° when Vt1 ′ <Vn ≦ Vt1, and sets the phase correction amount when Vt2 ′ <Vn ≦ Vt1 ′. A correction amount SF = 180 ° is assigned.

  According to the phase correction as shown in FIG. 8, even if the attenuated signal is received by a large number of fixed antennas and only one antenna receives a strong signal, the signal can be effectively transmitted. Synthesis can be performed.

  FIG. 9A is an explanatory diagram for explaining a fifth example of control in the comparison circuit 26 of FIG. FIG. 9B is a graph showing the distribution of the detection voltage in the case of FIG. According to the control of FIG. 8, when the reception power of a large number of received signals is concentrated in the vicinity of a certain value, the reception power of the reference reception signal is far from the range where the reception power is concentrated. There may be.

  Therefore, as shown in FIG. 9B, the comparison circuit 26 obtains the average value VAV and the standard deviation σ of the detection voltage from the received power values of all the received signals, and 1.5σ sequentially from the average value VAV (reference voltage). The threshold voltages Vt1 and Vt2 ′ which are lower by 1.5σ in order from the higher threshold voltages Vt1 and Vt2 and the average value VAV are obtained. Further, the comparison circuit 26 sets the phase correction amount SF = −180 ° when Vt1 <Vn ≦ Vt2, sets the phase correction amount SF = 0 ° when Vt1 ′ <Vn ≦ Vt1, and sets the phase correction amount when Vt2 ′ <Vn ≦ Vt1 ′. A correction amount SF = 180 ° is assigned.

  The phase correction as shown in FIG. 9A is suitable for reception using a large number of antennas. When receiving a signal that is highly linear and easily attenuated, such as millimeter waves, using multiple antennas, the received power value of the received signal is normal due to the effects of reflection and the difference in propagation distance between the received signals. It is considered to be distributed. For this reason, according to the phase correction as shown in FIG. 9A, the reference voltage can be easily determined, and the relationship between the detected voltage and the phase correction amount can be made appropriate.

  FIG. 10 is a flowchart showing a modification of the processing flow of FIG. The process of FIG. 10 may be performed instead of the process of FIG. Here, the case where the phase correction according to FIG. 6 is performed will be described. In step S7 in FIG. 10, the comparison circuit 26 determines whether or not Vt3 <Vn ≦ Vt2 is satisfied. If it is satisfied, the process of step S8 is performed. If not satisfied, the phase correction circuits 16A to 16C do not perform phase correction and output on the weak reception signal from which the detection signal Vn is detected, and the synthesis circuit 22 synthesizes this reception signal. Do not use.

  That is, a received signal whose detected voltage is not more than the minimum value of the reference voltage and the threshold voltages (Vt1 to Vt3) is not subject to phase correction and synthesis. Similarly, in the case of performing the phase correction according to FIGS. 7, 8, and 9A, the detected voltage is the minimum value in each figure of the reference voltage and the threshold voltage (in FIG. 7, Vt1, FIG. 8, and FIG. In 9 (a), a received signal that is equal to or lower than Vt2 ′) may not be subjected to phase correction and synthesis. Other processes are the same as those in FIG.

  Since the signal that reaches the antenna after repeated reflections is very small and has a high probability of error, the signal with low reception power (low detection voltage) is blocked because it is attenuated, and only strong signals are synthesized. Thus, a better synthesis result can be obtained and the operation of the circuit can be reduced. It is particularly effective for millimeter wave band wireless communication to avoid using such weak received signals for synthesis.

  FIG. 11 is a flowchart showing a modification of the processing flow of FIG. The process of FIG. 11 may be performed instead of the process of FIG. Here, the case where the phase correction according to FIG. 6 is performed will be described. If the condition in step S7 of FIG. 11 is not satisfied, the process proceeds to step S9.

  In the process of FIG. 10, weak received signals are blocked, but reception is impossible when the detection voltages of all received signals are equal to or lower than the minimum threshold voltage. Therefore, the antennas 2A to 2C are configured so that the directions of the antennas 2A to 2C can be controlled according to the control signal. Further, in step S9 in FIG. 11, the comparison circuit 26 generates an antenna control signal for driving the antenna so as to change the direction of the antenna that has received the signal that does not satisfy the condition in step S7. To do. The comparison circuit 26 controls the direction of the antenna that receives the signal so that the reception power of the signal is increased (for example, maximized).

  Then, it returns to step S2. Other processes are the same as those in FIG. As a result, even if all received signals are significantly attenuated, all received signals can be used for synthesis.

  FIG. 12 is a block diagram showing a third configuration example of the multi-antenna reception apparatus according to the embodiment of the present invention. The multi-antenna receiving apparatus of FIG. 12 has phase correction circuits 316A, 316B, and 316C instead of the phase correction circuits 16A, 16B, and 16C, and has a comparison circuit 326 instead of the comparison circuit 26. It is different from the antenna receiver. Other points are the same as those of the multi-antenna receiving apparatus of FIG. Further, the phase correction circuits 316A to 316C perform phase correction on the output signals of the down converters 12A to 12C, and give the corrected signals to the AD converters 14A to 14C. That is, the phase correction circuits 316A to 316C perform phase correction on the analog signal before AD conversion.

  FIG. 13 is an explanatory diagram showing an example of phase correction by the multi-antenna receiving apparatus of FIG. The phase correction circuits 316A to 316C perform phase correction on the reception signals converted to the intermediate frequencies by the down converters 12A to 12C according to the detection voltage Vn indicating the power value detected by the power detection circuits 24A to 24C. Do each.

  The phase correction circuits 316A to 316C are, for example, 0 ° when Vn> Vt1, 90 ° when Vt1 ≧ Vn> Vt2, 180 ° when Vt2 ≧ Vn> Vt3, and 270 when Vt3 ≧ Vn> Vt4. Perform phase correction of °. Further, when Vt4> Vn, the phase correction circuits 316A to 316C do not output the input signal so as not to be used for synthesis. The threshold voltages Vt1 to Vt4 in FIG. 13 are reference voltages or threshold voltages obtained as described with reference to FIGS. 2 and 6 to 9, for example. However, in the case of FIG. 13, four voltages are obtained.

  Thus, the power of the combined signal can be increased even if phase correction is performed on the analog signal before AD conversion according to the detection voltage Vn indicating the power value.

  Although the case where the phase control signal indicating the phase correction amount is generated according to the power value of the signal corresponding to the received signal has been described, the phase control signal is generated similarly according to the amplitude of the signal corresponding to the received signal. May be.

  As described above, the present invention can speed up the synthesis of signals received by a plurality of antennas, and thus is useful for a multi-antenna reception circuit and the like.

It is a block diagram which shows the 1st structural example of the multi-antenna receiver which concerns on embodiment of this invention. It is explanatory drawing for demonstrating the 1st example of control in the comparison circuit of FIG. It is a flowchart which shows the flow of a process in each branch of FIG. It is a block diagram which shows the 2nd structural example of the multi-antenna receiver which concerns on embodiment of this invention. FIG. 5 is an explanatory diagram illustrating an example of phase correction in the multi-antenna reception apparatus of FIG. 4. FIG. 6 is an explanatory diagram for describing a second example of control in the comparison circuit of FIG. 1. FIG. 9 is an explanatory diagram for explaining a third example of control in the comparison circuit of FIG. 1. FIG. 10 is an explanatory diagram for describing a fourth example of control in the comparison circuit of FIG. 1. (A) is explanatory drawing for demonstrating the 5th example of control in the comparison circuit of FIG. FIG. 9B is a graph showing a distribution of detection voltages in the case of FIG. It is a flowchart which shows the modification of the flow of the process of FIG. It is a flowchart which shows the modification of the flow of the process of FIG. It is a block diagram which shows the 3rd structural example of the multi-antenna receiver which concerns on embodiment of this invention. It is explanatory drawing which shows the example of the phase correction by the multi-antenna receiving apparatus of FIG. It is a block diagram which shows the structural example of the conventional receiver.

Explanation of symbols

12A to 12C Down converter 14A to 14C AD converter 16A to 16C, 316A to 316C Phase correction circuit 18A to 18C Demodulation circuit 22 Synthesis circuit 24A to 24C Power detection circuit 26, 226, 326 Comparison circuit

Claims (32)

A plurality of down-converters that respectively convert the frequency of the received signals output from each of the plurality of antennas and output the frequency-converted signals;
A plurality of power detection circuits for respectively detecting power values of the frequency-converted signals;
A comparison circuit for generating a phase control signal indicating a phase correction amount for each of the frequency-converted signals according to a power value detected by each of the plurality of power detection circuits;
A plurality of phase correction circuits that respectively perform phase correction on the frequency-converted signal according to the phase control signal;
A synthesis circuit that synthesizes signals corrected by each of the plurality of phase correction circuits,
The comparison circuit is
In accordance with the power values detected by the plurality of power detection circuits, a relationship between the power value and the phase correction amount is determined, and the phase correction amount for each of the frequency-converted signals is determined as the power value detected for the signal. The multi-antenna receiving circuit is characterized in that the phase control signal is obtained from the relationship using the relationship and indicates the obtained phase correction amount. The multi-antenna receiving circuit according to claim 1,
The comparison circuit is
The relationship between the maximum value and the minimum value of the power values detected by the plurality of power detection circuits is divided into a plurality of sections, and a phase correction amount is assigned to each of the plurality of sections, thereby defining the relationship. A multi-antenna receiving circuit. The multi-antenna receiving circuit according to claim 1,
The comparison circuit is
The relationship is determined so that a given power value corresponds to a phase correction amount according to a difference between the given power value and a maximum value of power values detected by the plurality of power detection circuits. A multi-antenna receiving circuit. The multi-antenna receiving circuit according to claim 1,
The comparison circuit is
The relationship is determined so that a given power value corresponds to a phase correction amount corresponding to a difference between the given power value and a minimum value of the power values detected by the plurality of power detection circuits. A multi-antenna receiving circuit. The multi-antenna receiving circuit according to claim 1,
The comparison circuit is
The given power value depends on a difference between the given power value and a power value closest to an average value of the power values detected by the plurality of power detection circuits. The multi-antenna receiving circuit, wherein the relationship is determined so as to correspond to a phase correction amount. The multi-antenna receiving circuit according to claim 1,
The comparison circuit is
The relationship is set so that a given power value corresponds to a phase correction amount according to a difference between the given power value and an average value of the power values detected by the plurality of power detection circuits. A multi-antenna receiving circuit characterized by defining. The multi-antenna receiving circuit according to claim 1,
The comparison circuit is
The phase control signal is generated so that a weak signal whose power value is a predetermined value or less is not given to the synthesis circuit,
Each of the plurality of phase correction circuits is
A multi-antenna receiving circuit, wherein the weak signal is not output according to the phase control signal. The multi-antenna receiving circuit according to claim 7,
The comparison circuit is
A multi-antenna receiving circuit, characterized by generating an antenna control signal for changing the direction of the antenna that has received the weak signal so that received power is increased. The multi-antenna receiving circuit according to claim 1,
A plurality of AD converters for AD (Analog to Digital) converting the signals converted by each of the plurality of down converters into digital signals;
The plurality of phase correction circuits include:
A multi-antenna receiving circuit, wherein the phases of the signals after AD conversion obtained by the plurality of AD converters are respectively corrected according to the phase control signal. The multi-antenna receiving circuit according to claim 1,
A plurality of AD converters for AD-converting signals converted by the plurality of down converters into digital signals, respectively;
A plurality of demodulation circuits that respectively demodulate the signals after the AD conversion obtained by the plurality of AD converters to obtain demodulation results;
The plurality of phase correction circuits include:
A multi-antenna receiving circuit, wherein the phases of the demodulation results obtained by the plurality of demodulation circuits are respectively corrected according to the phase control signal. The multi-antenna receiving circuit according to claim 1,
A plurality of demodulation circuits for demodulating signals corrected by each of the plurality of phase correction circuits to obtain respective demodulation results;
The synthesis circuit is:
A multi-antenna receiving circuit, wherein correct received data is obtained from the demodulation result. The multi-antenna receiving circuit according to claim 11,
The synthesis circuit is:
A multi-antenna receiving circuit characterized in that correct received data is obtained by majority decision from the demodulation result. The multi-antenna receiving circuit according to claim 1,
A plurality of demodulation circuits for demodulating signals corrected by each of the plurality of phase correction circuits to obtain respective demodulation results;
The synthesis circuit is:
A multi-antenna receiving circuit, wherein the demodulation results are combined at the same time. Multiple antennas,
A plurality of downconverters that respectively convert the frequency of the received signals output from each of the plurality of antennas and output the frequency-converted signals;
A plurality of power detection circuits for respectively detecting power values of the frequency-converted signals;
A comparison circuit for generating a phase control signal indicating a phase correction amount for each of the frequency-converted signals according to a power value detected by each of the plurality of power detection circuits;
A plurality of phase correction circuits that respectively perform phase correction on the frequency-converted signal according to the phase control signal;
A synthesis circuit that synthesizes signals corrected by each of the plurality of phase correction circuits,
The comparison circuit is
In accordance with the power values detected by the plurality of power detection circuits, a relationship between the power value and the phase correction amount is determined, and the phase correction amount for each of the frequency-converted signals is determined as the power value detected for the signal. The multi-antenna receiving apparatus is characterized in that the phase control signal is obtained by using the relationship and generating the phase control signal indicating the obtained phase correction amount. The multi-antenna reception apparatus according to claim 14,
The comparison circuit is
The relationship between the maximum value and the minimum value of the power values detected by the plurality of power detection circuits is divided into a plurality of sections, and a phase correction amount is assigned to each of the plurality of sections, thereby defining the relationship. Multi-antenna receiver. The multi-antenna receiving apparatus according to claim 14,
The comparison circuit is
The relationship is determined so that a given power value corresponds to a phase correction amount according to a difference between the given power value and a maximum value of power values detected by the plurality of power detection circuits. A multi-antenna receiving apparatus. The multi-antenna receiving apparatus according to claim 14,
The comparison circuit is
The relationship is determined so that a given power value corresponds to a phase correction amount corresponding to a difference between the given power value and a minimum value of the power values detected by the plurality of power detection circuits. A multi-antenna receiving apparatus. The multi-antenna reception apparatus according to claim 14,
The comparison circuit is
The given power value depends on a difference between the given power value and a power value closest to an average value of the power values detected by the plurality of power detection circuits. The multi-antenna receiving apparatus characterized in that the relationship is determined so as to correspond to a phase correction amount. The multi-antenna reception apparatus according to claim 14,
The comparison circuit is
The relationship is set so that a given power value corresponds to a phase correction amount according to a difference between the given power value and an average value of the power values detected by the plurality of power detection circuits. A multi-antenna receiving apparatus characterized by defining. A down-conversion step for frequency-converting the received signal output from each of the plurality of antennas;
A power detection step of detecting a power value of the frequency converted signal;
A comparison step of generating a phase control signal indicating a phase correction amount for each of the frequency-converted signals according to the power value detected in the power detection step;
A phase correction step for performing phase correction on the frequency-converted signal according to the phase control signal;
A synthesis step of synthesizing the signal corrected in the phase correction step,
The comparison step includes
According to the power value detected in the power detection step, a relationship between the power value and the phase correction amount is determined, and the phase correction amount for each of the frequency converted signals is determined from the power value detected for the signal. A multi-antenna reception method, characterized in that the phase control signal is obtained using a relationship and indicates the obtained phase correction amount. The multi-antenna reception method according to claim 20,
The comparison step includes
The relationship between the maximum value and the minimum value detected in the power detection step is divided into a plurality of sections, and the relationship is determined by assigning a phase correction amount for each of the plurality of sections. Multi-antenna reception method. The multi-antenna reception method according to claim 20,
The comparison step includes
Defining the relationship such that a given power value corresponds to a phase correction amount according to a difference between the given power value and a maximum value of the power value detected in the power detection step. A feature of a multi-antenna reception method. The multi-antenna reception method according to claim 20,
The comparison step includes
Defining the relationship such that a given power value corresponds to a phase correction amount according to a difference between the given power value and a minimum value of the power value detected in the power detection step. A feature of a multi-antenna reception method. The multi-antenna reception method according to claim 20,
The comparison step includes
The phase correction according to the difference between the given power value and the power value closest to the average value of the given power value and the power value detected in the power detection step. A multi-antenna reception method, wherein the relationship is determined so as to correspond to a quantity. The multi-antenna reception method according to claim 20,
The comparison step includes
Defining the relationship such that a given power value corresponds to a phase correction amount according to a difference between the given power value and an average value of the power values detected in the power detection step; A multi-antenna receiving method. The multi-antenna reception method according to claim 20,
The comparison step includes
Generating the phase control signal so that a weak signal whose power value is less than or equal to a predetermined value is not used in the combining step;
The phase correction step includes
A multi-antenna reception method, wherein the weak signal is not output according to the phase control signal. The multi-antenna reception method according to claim 26.
The comparison step includes
A multi-antenna reception method, comprising: generating an antenna control signal that changes a direction of the antenna that has received the weak signal so that reception power is increased. The multi-antenna reception method according to claim 20,
An AD conversion step of AD converting the signal converted in the down-conversion step into a digital signal;
The phase correction step includes
A multi-antenna reception method, comprising: correcting a phase of the signal after AD conversion obtained in the AD conversion step according to the phase control signal. The multi-antenna reception method according to claim 20,
An AD conversion step of AD converting the signal converted in the down-conversion step into a digital signal;
A demodulation step of demodulating the signal after AD conversion obtained in the AD conversion step to obtain a demodulation result;
The phase correction step includes
A multi-antenna reception method, wherein the phase of the demodulation result obtained in the demodulation step is corrected according to the phase control signal. The multi-antenna reception method according to claim 20,
Further comprising a demodulation step of demodulating the signal corrected in the phase correction step to obtain a demodulation result;
The synthesis step includes
A multi-antenna reception method characterized in that correct reception data is obtained from the demodulation result. The multi-antenna reception method according to claim 30,
The synthesis step includes
A multi-antenna reception method characterized in that correct reception data is obtained by majority decision from the demodulation result. The multi-antenna reception method according to claim 20,
Further comprising a demodulation step of demodulating the signal corrected in the phase correction step to obtain a demodulation result;
The synthesis step includes
A multi-antenna reception method comprising combining the demodulation results simultaneously.

Images