JP2009231593A - Hetero-junction bipolar transistor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an HBT capable of simultaneously improving both on-state resistance and a breakdown voltage in the state that a collector current is flowing. <P>SOLUTION: The hetero-junction bipolar transistor includes an n-type GaAs sub collector layer 101, an InGaP collector layer 102 formed on the GaAs sub collector layer 101, an n-type GaAs collector layer 103 formed on the InGaP collector layer 102, a p-type GaAs base layer 104 formed on the GaAs collector layer 103, and an n-type GaAs emitter layer 105 formed on the GaAs base layer 104. The carrier density of the GaAs sub collector layer 101 is higher than that of the GaAs collector layer 103, and a p-type GaAs spacer layer 110 is inserted between the InGaP collector layer 102 and the GaAs sub collector layer 101. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to heterojunction bipolar transistors.

  A compound semiconductor device such as a field effect transistor (hereinafter referred to as FET) or a heterojunction bipolar transistor (hereinafter referred to as HBT) is, for example, a high output power amplifier for transmission which is one of the components of a mobile phone. Etc. are used. In recent years, high output characteristics, high gain characteristics, and low distortion characteristics have been demanded for HBTs, and in order to realize these, it is required to realize HBTs having high breakdown voltage and low on-resistance. Yes.

  As a material used for the emitter layer of the HBT, InGaP is becoming mainstream in recent years instead of AlGaAs. Advantages of InGaP include lattice matching with GaAs near In composition 0.5, high selectivity of wet etching to GaAs, and valence band discontinuity when bonded to GaAs base layer compared to AlGaAs. For example, it is large, there is no deep impurity level like the DX center found in AlGaAs, and the surface recombination velocity is low.

  Next, a device structure of a conventional HBT will be described with reference to a cross-sectional view of FIG. 6 (see, for example, Patent Document 1).

On an GaAs substrate 400, an n-type GaAs subcollector layer 401 having an electron concentration of 5E18 cm ⁻³ and a thickness of 600 nm, an undoped InGaP collector layer 402 having a thickness of 100 nm, an n-type GaAs spacer layer having an electron concentration of 2E18 cm ⁻³ and a thickness of 10 nm 410, an n-type GaAs collector layer 403 having an electron concentration of 1E16 cm ⁻³ and a thickness of 500 nm, a p-type GaAs base layer 404 having a hole concentration of 4E19 cm ⁻³ and a thickness of 80 nm, an n-type InGaP emitter having an electron concentration of 3E17 cm ⁻³ and a thickness of 30 nm A layer 405, an n-type GaAs emitter cap layer 406 having an electron concentration of 3E18 cm ⁻³ and a thickness of 200 nm, and an n-type InGaAs emitter contact layer 407 having an electron concentration of 1E19 cm ⁻³ and a thickness of 100 nm are grown in this order. By etching these semiconductor layers and electrode deposition, a collector electrode 420 is formed on the GaAs subcollector layer 401, a base electrode 421 is formed on the GaAs base layer 404, and an emitter electrode 422 is formed on the InGaAs emitter contact layer 407 as ohmic electrodes. Has been.

  The reason for introducing the n-type GaAs spacer layer 410 is to effectively reduce ΔEc, which is generated between the InGaP collector layer 402 and the GaAs collector layer 403 and increases the on-resistance.

  The reason for introducing the InGaP collector layer 402 is to improve the emitter-collector breakdown voltage (BVcex) in a state where the collector current flows, as described in detail in Patent Document 1. The peak of the electric field strength at this time occurs between the collector layer and the subcollector layer, and the breakdown voltage is improved by introducing InGaP having a collision ionization coefficient smaller than GaAs at this position.

  InGaP has the property that the atomic arrangement state and band gap in the crystal change according to the growth conditions. When the growth temperature of InGaP is changed, the group III elements In and Ga are regularly arranged in the group III atomic layer surface to form a CuPt type natural superlattice structure or an ordered arrangement structure (order type). It is observed that a disordered arrangement structure (disorder type) is formed by arranging regularly. Accordingly, the band gap of InGaP changes in the range of approximately 1.84 to 1.90 eV.

  FIG. 7 shows a unit crystal lattice of a III-V mixed crystal semiconductor. The III-V mixed crystal semiconductor is formed of a IIIa-IIIb-V type mixed crystal, and in the III-V mixed crystal semiconductor, a crystal lattice (sublattice) in which two group III atoms of IIIa and IIIb are composed only of the same group atoms. It is known that they are arranged almost randomly. Referring to FIG. 7, in the group III-V mixed crystal semiconductor, two types of group III atoms different in IIIa or IIIb are randomly arranged at the sites from 3a to 3n, and at the sites from 5a to 5d. Group V atoms are arranged. However, it is known that the atoms of IIIa and IIIb form an order-type structure on the group III sublattice at a specific growth temperature. FIG. 8 is an example of a crystal structure of a group III-V mixed crystal semiconductor having an order type structure. FIG. 8 is a crystal structure of InGaP viewed perpendicularly to the growth direction, and represents a crystal structure viewed from the normal direction of the plane formed by the atoms 3a, 3b, 3c, and 3n in FIG. If the atoms at the sites 3a, 3e, 3g, 3h, 3i, and 3f in FIG. 7 are viewed as Ga atoms in FIG. 8, the atoms at the sites 3j, 3d, 3k, 3m, 3c, and 3l in FIG. It can be seen as an In atom. As can be seen from FIG. 8, in the order type, there are adjacent arrangements of IIIa-V (In-P) and IIIb-V (Ga-P). As described above, the band gap Eg of InGaP varies depending on the growth temperature. This state is shown in FIG. 9, and the band gap becomes smaller as the order type is set, and the band gap becomes larger as the order type is set.

If InGaP is grown in a disordered type, a conduction band discontinuity (ΔEc) of approximately 0.2 eV occurs between InGaP and GaAs. Therefore, the on-resistance (Ron) indicating the rise of the collector current with respect to the collector voltage increases. The InGaP collector layer 402 in the HBT of Patent Document 1 is assumed to be a disorder type. In order to prevent this problem, the HBT of Patent Document 1 introduces an n-type GaAs spacer layer 410 to reduce effective ΔEc and prevent an increase in Ron.
JP2007-103784A (FIG. 6)

  By the way, if InGaP is grown in order, there is no conduction band discontinuity between InGaP and GaAs, and no increase in on-resistance due to that occurs. However, it is known that when InGaP is sandwiched between GaAs and AlGaAs, polarization in a concentration distribution state occurs on the upper and lower surfaces of InGaP. This is considered to be caused by distortion of the atomic arrangement state at the interface. The greater the degree of ordering of InGaP, the greater the degree of polarization. An experimental result reproducing the phenomenon will be described with reference to FIGS.

FIG. 10 is a cross-sectional view of a measurement sample. As shown in FIG. 10, in the measurement sample, in order to GaAs substrate 500, n-type GaAs layer 501 concentration 3E17 cm ^-3 and the thickness 100 nm, concentration 3E17 cm ^-3 and a thickness of 100 nm n-type InGaP layer 502, and An n-type GaAs layer 503 having a concentration of 3E17 cm ⁻³ and a film thickness of 100 nm is grown. Further, an electrode for measurement (not shown) is formed. FIG. 11 shows the result of measuring the carrier concentration distribution by the CV method for the measurement sample having such a structure. In FIG. 11, the horizontal axis indicates the distance from the surface of the GaAs layer 503, and the vertical axis indicates the electron concentration. As can be seen from FIG. 11, carrier depletion occurs at the interface between the InGaP layer 502 and the upper GaAs layer 503, and carriers accumulate at the interface with the GaAs layer 501, which is the lower layer of the InGaP layer 502. . Due to such abnormal polarization, the flatness of the conduction band between InGaP and GaAs is impaired. This becomes an obstacle when the collector current is flowing, and causes an increase in on-resistance.

As one method for solving this problem, a high-concentration n ⁺ -type GaAs spacer layer is introduced between the order-type InGaP collector layer and the GaAs collector layer as in the HBT described in Japanese Patent No. 3573737. There is a way to do it. The HBT described in Japanese Patent No. 3573737 has the same structure as the HBT of FIG. 6 except that InGaP is an order type. According to Japanese Patent No. 3573737, carrier depletion occurs due to an interface state of about 2E12 cm ^{−2 at} the interface between the InGaP collector layer and the GaAs collector layer, and therefore, a potential peak occurs and the on-resistance increases. Yes. In order to compensate for this, an n ⁺ -type GaAs spacer layer having a concentration of 3E18 cm ⁻³ and a thickness of 5 nm is introduced. Free electrons from the n ⁺ -type GaAs spacer layer cancel out with a positive charge in the depletion region. The donor is positively charged due to electron shortage, but the electrons generated at the lower interface of the InGaP collector layer move to the n ⁺ -type GaAs spacer layer (donor region), and the positive charge of the donor Is solved. As a result, there is no concentration distribution abnormality occurring above and below the InGaP collector layer. As an example using such a technique, there is also Japanese Patent Laid-Open No. 2003-86603 which describes an HBT using an InGaP layer as an emitter.

In the HBT described in Japanese Patent No. 3573737, a carrier concentration (electron concentration) distribution and an electric field strength (absolute value) distribution when a collector current flows are shown in FIGS. 12 (a) and 12 (b), respectively. 12A, the horizontal axis represents the distance from the GaAs base layer surface, the vertical axis represents the carrier concentration, and in FIG. 12B, the horizontal axis represents the distance from the GaAs base layer surface, and the vertical axis represents the electric field. Indicates strength. FIGS. 12A and 12B show a case where the charge amount (surface density) of the n ⁺ -type GaAs spacer layer is made higher than the polarized charge amount.

In the HBT, after the polarization is eliminated, the n ⁺ -type GaAs spacer layer having a high electron concentration exists as it is. As can be seen in FIG. 12A, the actual electron concentration is higher than the set concentration (donor) inside the GaAs collector layer and is negatively charged. On the other hand, the n ⁺ -type GaAs spacer layer has a higher set concentration and is positively charged. The InGaP collector layer is negatively charged. Therefore, as shown in FIG. 12B, the electric field strength distribution is such that the electric field strength is greatly inclined in the n ⁺ -type GaAs spacer layer. Therefore, a slight electric field is applied to the InGaP collector layer, and it cannot be said that the high breakdown voltage property of InGaP is utilized. The breakdown voltage at this time is determined by the electric field strength generated on the n ⁺ -type GaAs spacer layer. When the n ⁺ -type GaAs spacer layer has a high concentration, breakdown occurs at a low critical electric field strength, and the breakdown voltage decreases. For this reason, if the electron concentration in the n ⁺ -type GaAs spacer layer is reduced, there is a problem that the electron concentration may be insufficient to cancel the polarization.

  Therefore, an object of the present invention is to provide an HBT that can simultaneously improve both the on-resistance and the breakdown voltage in a state where a collector current flows.

  In order to solve the above problems, a heterojunction bipolar transistor of the present invention is formed on an n-type GaAs subcollector layer, an InGaP collector layer formed on the GaAs subcollector layer, and the InGaP collector layer. An n-type GaAs collector layer, a p-type base layer formed on the GaAs collector layer, and an n-type emitter layer formed on the base layer, the carrier concentration of the GaAs subcollector layer Is higher than the carrier concentration of the GaAs collector layer, and a p-type GaAs spacer layer is inserted between the InGaP collector layer and the GaAs subcollector layer. Here, an n-type GaAs spacer layer may be inserted between the InGaP collector layer and the GaAs collector layer.

  With this structure, it is possible to eliminate anomalous polarization occurring at the interface contacting the upper and lower layers of the InGaP collector layer by a new method different from the HBT described in Japanese Patent No. 3573737. Therefore, both the on-resistance and the breakdown voltage in the state where the collector current flows can be improved at the same time.

  The carrier concentration of the GaAs collector layer may increase from a portion facing the base layer toward a portion facing the InGaP collector layer.

With this structure, the breakdown voltage can be further improved.
The crystal state of the InGaP collector layer may be a natural superlattice state.

  The greater the extent to which the InGaP collector layer is a (CuPt type) natural superlattice, the greater the degree of polarization on the upper and lower surfaces of the InGaP collector layer. Therefore, the effect of the technique of eliminating abnormal polarization by the p-type GaAs spacer layer is enhanced.

  As described above, the heterojunction bipolar transistor of the present invention can simultaneously improve both the on-resistance and the breakdown voltage in the state where the collector current flows.

  Hereinafter, heterojunction bipolar transistors according to embodiments of the present invention will be described with reference to the drawings.

(First embodiment)
FIG. 1 is a cross-sectional view showing the structure of the HBT of this embodiment.

As shown in FIG. 1, an n-type GaAs subcollector layer 101 having an electron concentration of 5E18 cm ⁻³ and a film thickness of 600 nm, a p-type GaAs spacer layer 110 having a hole concentration of 2E18 cm ⁻³ and a film thickness of 10 nm are undoped on a GaAs substrate 100. InGaP collector layer 102 having a thickness of 100 nm, n-type GaAs collector layer 103 having an electron concentration of 1.4E16 cm ⁻³ and 600 nm, p-type GaAs base layer 104 having a hole concentration of 4E19 cm ⁻³ and 80 nm, an electron concentration of 3E17 cm ⁻³ And an n-type InGaP emitter layer 105 having a thickness of 30 nm, an n-type GaAs emitter cap layer 106 having an electron concentration of 3E18 cm ⁻³ and a thickness of 200 nm, and an n-type InGaAs emitter contact layer 107 having an electron concentration of 1E19 cm ⁻³ and a thickness of 100 nm, respectively. In this order It is. By etching these semiconductor layers and depositing electrodes, a collector electrode 120 is formed on the GaAs subcollector layer 101, a base electrode 121 is formed on the GaAs base layer 104, and an emitter electrode 122 is formed on the InGaAs emitter contact layer 107 as ohmic electrodes. Has been.

At this time, the InGaP collector layer 102 is grown in order. Therefore, the crystal state of the InGaP collector layer 102 is a natural superlattice state, which is an order state. The p-type GaAs spacer layer 110 is inserted to eliminate accumulation of electrons (approximately 2E12 cm ⁻² ) generated on the lower surface of the InGaP collector layer 102. The mechanism is as follows. That is, free holes in the p-type GaAs spacer layer 110 and electrons accumulated on the lower surface of the InGaP collector layer 102 are combined and disappear. Although the acceptor is negatively charged by electrons, the electrons move to the carrier depletion region generated on the upper surface of the InGaP collector layer 102, and the depletion is eliminated. As a result, it is considered that the abnormal polarization above and below the InGaP collector layer 102 is eliminated, and the increase in on-resistance caused by the abnormal polarization does not occur.

  Next, the breakdown voltage of the HBT having the above structure will be considered. FIG. 2A and FIG. 2B are diagrams showing the distribution of carrier concentration (electron concentration) and electric field strength (absolute value) in the collector layer at the time of breakdown when a sufficiently high collector current flows. is there. 2A, the horizontal axis indicates the distance from the surface of the GaAs base layer 104, the vertical axis indicates the carrier concentration, and in FIG. 2B, the horizontal axis indicates the distance from the surface of the GaAs base layer 104, and the vertical axis. Indicates electric field strength.

  As shown in FIG. 2A, in the region of the GaAs collector layer 103 and the region of the InGaP collector layer 102, the actual electron concentration exceeds the set electron concentration (set concentration) and is negatively charged. . On the other hand, in the region of the GaAs subcollector layer 101, a slightly depleted positive region is generated. As a result, as shown in FIG. 2B, the electric field strength has a peak at the interface between the GaAs subcollector layer 101 and the p-type GaAs spacer layer 110. Since the region where the high electric field strength is generated is a region made of InGaP whose impact ionization coefficient is smaller than GaAs, a high breakdown voltage can be obtained.

  As described above, according to the HBT of the present embodiment, the p-type GaAs spacer layer 110 is inserted between the InGaP collector layer 102 and the GaAs subcollector layer 101 so as to be in contact with the lower surface of the InGaP collector layer 102. This eliminates carrier depletion and accumulation due to abnormal polarization in the upper and lower surfaces of InGaP. That is, carrier depletion and accumulation in the upper and lower surfaces of the InGaP layer are eliminated by a new method different from the HBT described in Japanese Patent No. 3573737. Therefore, both the on-resistance and the breakdown voltage in the state where the collector current flows can be improved at the same time.

In the present embodiment, the carrier concentration of the GaAs subcollector layer 101 is 5E18 cm ⁻³ , but is not limited thereto as long as it is higher than the carrier concentration of the GaAs collector layer 103.

(Second Embodiment)
FIG. 3 is a cross-sectional view showing the structure of the HBT of the present embodiment.

As shown in FIG. 3, an n-type GaAs subcollector layer 201 having an electron concentration of 5E18 cm ⁻³ and a film thickness of 600 nm, a p-type GaAs spacer layer 210 having a hole concentration of 1E18 cm ⁻³ and a film thickness of 10 nm, and undoped on a GaAs substrate 200. InGaP collector layer 202 with a thickness of 100 nm, electron concentration 1E18 cm ^-3 and the n-type GaAs spacer layer 211 having a thickness of 10 nm, electron concentration 1.4E16cm ^-3 and a thickness of 600 nm n-type GaAs collector layer 203, the hole concentration 4E19cm ^-3 A p-type GaAs base layer 204 having a thickness of 80 nm, an n-type InGaP emitter layer 205 having an electron concentration of 3E17 cm ⁻³ and a thickness of 30 nm, an n-type GaAs emitter cap layer 206 having an electron concentration of 3E18 cm ⁻³ and a thickness of 200 nm, and an electron concentration 1E19 cm ^-3 and film n-type InGaAs emitter contact layer 207 of 100nm are grown respectively in this order. By etching these semiconductor layers and depositing electrodes, a collector electrode 220 is formed on the GaAs subcollector layer 201, a base electrode 221 is formed on the GaAs base layer 204, and an emitter electrode 222 is formed on the InGaAs emitter contact layer 207 as ohmic electrodes. Has been.

  At this time, the InGaP collector layer 202 is grown in order. Therefore, the crystal state of the InGaP collector layer 202 is a natural superlattice state, which is an order state.

Thus, by introducing the n-type GaAs spacer layer 211 and the p-type GaAs spacer layer 210 above and below the InGaP collector layer 202, the abnormal polarization of the InGaP collector layer 202 can be eliminated. The idea is that the electron storage surface density 2E12 cm ⁻² on the lower side of the InGaP collector layer 202 is reduced to half 1E12 cm ⁻² by the surface density 1E12 cm ⁻² side of the holes of the newly introduced p-type GaAs spacer layer 210. . At this time, an electron depletion region of 1E12 cm ⁻² is generated above the InGaP collector layer 202. However, by introducing a new n-type GaAs spacer layer 211 having a carrier concentration higher than that of the n-type GaAs collector layer 203 and having a surface density of 1E12 cm ⁻² above the InGaP collector layer 202, all abnormal polarization is eliminated.

  As described above, according to the HBT of the present embodiment, the p-type GaAs spacer layer 210 is inserted between the InGaP collector layer 202 and the GaAs subcollector layer 201 in contact with the lower surface of the InGaP collector layer 202, and the InGaP By inserting the n-type GaAs spacer layer 211 in contact with the upper surface of the InGaP collector layer 202 between the collector layer 202 and the GaAs collector layer 203, carrier depletion and accumulation due to abnormal polarization in the upper and lower surfaces of InGaP are eliminated. To do. That is, carrier depletion and accumulation in the upper and lower surfaces of the InGaP layer are eliminated by a new method different from the HBT described in Japanese Patent No. 3573737. Therefore, both the on-resistance and the breakdown voltage in the state where the collector current flows can be improved at the same time.

In the present embodiment, the carrier concentration of the GaAs subcollector layer 201 is 5E18 cm ⁻³ , but is not limited thereto as long as it is higher than the carrier concentration of the GaAs collector layer 203.

(Third embodiment)
FIG. 4 is a cross-sectional view showing the structure of the HBT of the present embodiment.

As shown in FIG. 4, an n-type GaAs subcollector layer 301 having an electron concentration of 5E18 cm ⁻³ and a film thickness of 600 nm, a p-type GaAs spacer layer 310 having a hole concentration of 2E18 cm ⁻³ and a film thickness of 10 nm, and undoped on a GaAs substrate 300. InGaP collector layer 302 with a thickness of 100 nm, electron concentration 5.0E16cm ^-3 and the thickness 200nm of n-type GaAs third collector layer 303c, electron concentration 3.0E16cm ^-3 and a thickness of 200nm n-type GaAs second collector layer 303b An n-type GaAs first collector layer 303a having an electron concentration of 1.4E16 cm ⁻³ and a thickness of 200 nm, a p-type GaAs base layer 304 having a hole concentration of 4E19 cm ⁻³ and a thickness of 80 nm, an n concentration of 3E17 cm ⁻³ and a thickness of 30 nm. Type InGaP emitter layer 305, electron concentration 3E18c ³ and n-type GaAs emitter cap layer 306 having a thickness of 200nm and electron concentration 1E19 cm ^-3 and a thickness of 100 nm n-type InGaAs emitter contact layer 307, is grown respectively in this order. By etching these semiconductor layers and depositing electrodes, a collector electrode 320 is formed on the GaAs subcollector layer 301, a base electrode 321 is formed on the GaAs base layer 304, and an emitter electrode 322 is formed on the InGaAs emitter contact layer 307 as ohmic electrodes. Has been.

  At this time, the InGaP collector layer 302 is grown in order. Therefore, the crystal state of the InGaP collector layer 302 is a natural superlattice state, which is an order state.

  The advantage of the collector layer having a multilayer structure will be described with reference to FIGS. 5 (a) and 5 (b). 5 (a) and 5 (b) are diagrams showing the distribution of carrier concentration (electron concentration) and electric field strength (absolute value) in the collector layer at the time of breakdown when a sufficiently high collector current flows. is there. 5A, the horizontal axis indicates the distance from the surface of the GaAs base layer 304, the vertical axis indicates the carrier concentration, and in FIG. 5B, the horizontal axis indicates the distance from the surface of the GaAs base layer 304, and the vertical axis. Indicates electric field strength.

  Since the actual electron concentration and the set electron concentration (set concentration) are reversed at the interface between the GaAs first collector layer 303a and the GaAs second collector layer 303b, the peak of the electric field intensity is shown in FIG. As can be seen from FIG. 5A, the GaAs first collector layer 303a and the GaAs second collector layer 303b are generated at the interface. The position at which the withstand voltage is determined by the peak of the electric field strength depends on the concentration and film thickness of each layer. In the case of the HBTs of FIGS. 1 and 4, it is assumed that both are determined by the peak of the electric field strength at the interface between the GaAs subcollector layer and the p-type GaAs spacer layer, that is, the electric field strength at the interface is the same for both. Then, the area occupied by the electric field of the HBT of FIG. 4 (the value obtained by integrating the electric field strength in FIG. 5B) is clearly larger from both the diagrams of FIGS. 2B and 5B. Therefore, it can be said that the HBT in FIG. 4 has a higher breakdown voltage than the HBT in FIG.

  Such techniques for multilayering the collector layer have been introduced in Japanese Patent Application Laid-Open No. 2007-173624 and Japanese Patent Application Laid-Open No. 2006-60221, both of which introduce a p-type spacer layer as in the present invention. Is not touched on.

  As described above, according to the HBT of the present embodiment, the p-type GaAs spacer layer 310 is inserted between the InGaP collector layer 302 and the GaAs subcollector layer 301 so as to be in contact with the lower surface of the InGaP collector layer 302. This eliminates carrier depletion and accumulation due to abnormal polarization in the upper and lower surfaces of InGaP. That is, carrier depletion and accumulation on the upper and lower surfaces of InGaP are eliminated by a new method different from the HBT described in Japanese Patent No. 3573737. Therefore, both the on-resistance and the breakdown voltage in the state where the collector current flows can be improved at the same time.

  Further, according to the HBT of the present embodiment, the GaAs collector layer is composed of a plurality of semiconductor layers having different carrier concentrations, that is, a GaAs first collector layer 303a, a GaAs second collector layer 303b, and a GaAs third collector layer 303c. . Therefore, it is possible to realize a further higher breakdown voltage as compared with the HBT of the first embodiment.

In the present embodiment, the carrier concentration of the GaAs subcollector layer 301 is 5E18 cm ⁻³ , but from the carrier concentration of the GaAs first collector layer 303a, the GaAs second collector layer 303b, and the GaAs third collector layer 303c. If it is high, it is not limited to this.

  In the present embodiment, a portion facing the GaAs base layer 304 is formed by stacking three semiconductor layers having different carrier concentrations, ie, a GaAs first collector layer 303a, a GaAs second collector layer 303b, and a GaAs third collector layer 303c. It is assumed that a concentration distribution in which the carrier concentration increases toward the portion facing the InGaP collector layer 302 is formed in the GaAs collector layer. However, a concentration distribution in which only one GaAs layer is formed between the InGaP collector layer 302 and the GaAs base layer 304 and the carrier concentration increases from the GaAs base layer 304 side toward the InGaP collector layer 302 side. You may form in this one GaAs layer. In this case, a concentration distribution is formed by stepwise or continuous implantation of impurities into the semiconductor layer so that the impurity concentration increases from the GaAs base layer 304 side toward the InGaP collector layer 302 side. .

  The present invention can be used for heterojunction bipolar transistors, and in particular, can be used for transmission high-output power amplifiers and the like used for cellular phones and the like.

It is sectional drawing showing the device structure of HBT by the 1st Embodiment of this invention. (A) It is a figure showing the carrier concentration distribution of HBT by the 1st Embodiment of this invention. (B) It is a figure showing the electric field strength distribution of HBT by the 1st Embodiment of this invention. It is sectional drawing showing the device structure of HBT by the 2nd Embodiment of this invention. It is sectional drawing showing the device structure of HBT by the 3rd Embodiment of this invention. (A) It is a figure showing the carrier concentration distribution of HBT by the 3rd Embodiment of this invention. (B) It is a figure showing the electric field strength distribution of HBT by the 3rd Embodiment of this invention. It is sectional drawing showing the device structure of the conventional HBT. It is a figure showing the crystal structure of a III-V group mixed crystal semiconductor. It is the figure which looked at the crystal structure of InGaP perpendicularly | vertically from the growth direction. It is a figure showing the relationship between the growth temperature of InGaP, and a band gap. It is sectional drawing showing the structure of the sample used for the experiment showing that the depletion of a carrier has generate | occur | produced. It is a figure showing that the depletion of a carrier has occurred. (A) It is a figure showing the carrier concentration distribution of the conventional HBT. (B) It is a figure showing the electric field strength distribution of the conventional HBT.

Explanation of symbols

100, 200, 300, 400 GaAs substrate 101, 201, 301, 401 GaAs subcollector layer 102, 202, 302, 402 InGaP collector layer 103, 203, 403 GaAs collector layer 104, 204, 304, 404 GaAs base layer 105, 205, 305, 405 GaAs emitter layer 106, 206, 306, 406 GaAs emitter cap layer 107, 207, 307, 407 InGaAs emitter contact layer 110, 210, 310 p-type GaAs spacer layer 120, 220, 320, 420 Collector electrode 121 221, 321, 421 Base electrode 122, 222, 322, 422 Emitter electrode 211, 410 n-type GaAs spacer layer 303 a GaAs first collector layer 303 b GaAs Second collector layer 303c GaAs third collector layer

Claims (4)

an n-type GaAs subcollector layer;
An InGaP collector layer formed on the GaAs subcollector layer;
An n-type GaAs collector layer formed on the InGaP collector layer;
A p-type base layer formed on the GaAs collector layer;
An n-type emitter layer formed on the base layer,
The carrier concentration of the GaAs subcollector layer is higher than the carrier concentration of the GaAs collector layer,
A heterojunction bipolar transistor, wherein a p-type GaAs spacer layer is inserted between the InGaP collector layer and the GaAs subcollector layer. The heterojunction bipolar transistor according to claim 1, wherein an n-type GaAs spacer layer is inserted between the InGaP collector layer and the GaAs collector layer. 3. The heterojunction bipolar transistor according to claim 1, wherein a carrier concentration of the GaAs collector layer increases from a portion facing the base layer toward a portion facing the InGaP collector layer. The heterojunction bipolar transistor according to any one of claims 1 to 3, wherein the crystal state of the InGaP collector layer is a natural superlattice state.

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